1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Define to ensure that the "common" members always appear in the same 108 * order in different structs for back compat purposes 109 */ 110 #define COMMON_STREAM_STATIC_SUB_STATE \ 111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 113 struct dmub_fams2_cmd_drr_stream_static_state drr; 114 115 /* Maximum number of streams on any ASIC. */ 116 #define DMUB_MAX_STREAMS 6 117 118 /* Maximum number of planes on any ASIC. */ 119 #define DMUB_MAX_PLANES 6 120 121 /* Maximum number of phantom planes on any ASIC */ 122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 123 124 /* Trace buffer offset for entry */ 125 #define TRACE_BUFFER_ENTRY_OFFSET 16 126 127 /** 128 * Maximum number of dirty rects supported by FW. 129 */ 130 #define DMUB_MAX_DIRTY_RECTS 3 131 132 /** 133 * 134 * PSR control version legacy 135 */ 136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 137 /** 138 * PSR control version with multi edp support 139 */ 140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 142 143 /** 144 * ABM control version legacy 145 */ 146 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 147 148 /** 149 * ABM control version with multi edp support 150 */ 151 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 152 153 /** 154 * Physical framebuffer address location, 64-bit. 155 */ 156 #ifndef PHYSICAL_ADDRESS_LOC 157 #define PHYSICAL_ADDRESS_LOC union large_integer 158 #endif 159 160 /** 161 * OS/FW agnostic memcpy 162 */ 163 #ifndef dmub_memcpy 164 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 165 #endif 166 167 /** 168 * OS/FW agnostic memset 169 */ 170 #ifndef dmub_memset 171 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 172 #endif 173 174 /** 175 * OS/FW agnostic memcmp 176 */ 177 #ifndef dmub_memcmp 178 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 179 #endif 180 181 /** 182 * OS/FW agnostic udelay 183 */ 184 #ifndef dmub_udelay 185 #define dmub_udelay(microseconds) udelay(microseconds) 186 #endif 187 188 #pragma pack(push, 1) 189 #define ABM_NUM_OF_ACE_SEGMENTS 5 190 191 /** 192 * Debug FW state offset 193 */ 194 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 195 196 union abm_flags { 197 struct { 198 /** 199 * @abm_enabled: Indicates if ABM is enabled. 200 */ 201 unsigned int abm_enabled : 1; 202 203 /** 204 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 205 */ 206 unsigned int disable_abm_requested : 1; 207 208 /** 209 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 210 */ 211 unsigned int disable_abm_immediately : 1; 212 213 /** 214 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 215 * to be disabled immediately and keep gain. 216 */ 217 unsigned int disable_abm_immediate_keep_gain : 1; 218 219 /** 220 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 221 */ 222 unsigned int fractional_pwm : 1; 223 224 /** 225 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 226 * of user backlight level. 227 */ 228 unsigned int abm_gradual_bl_change : 1; 229 230 /** 231 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 232 */ 233 unsigned int abm_new_frame : 1; 234 235 /** 236 * @vb_scaling_enabled: Indicates variBright Scaling Enable 237 */ 238 unsigned int vb_scaling_enabled : 1; 239 } bitfields; 240 241 unsigned int u32All; 242 }; 243 244 struct abm_save_restore { 245 /** 246 * @flags: Misc. ABM flags. 247 */ 248 union abm_flags flags; 249 250 /** 251 * @pause: true: pause ABM and get state 252 * false: unpause ABM after setting state 253 */ 254 uint32_t pause; 255 256 /** 257 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 258 */ 259 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 260 261 /** 262 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 263 */ 264 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 265 266 /** 267 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 268 */ 269 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 270 271 272 /** 273 * @knee_threshold: Current x-position of ACE knee (u0.16). 274 */ 275 uint32_t knee_threshold; 276 /** 277 * @current_gain: Current backlight reduction (u16.16). 278 */ 279 uint32_t current_gain; 280 /** 281 * @curr_bl_level: Current actual backlight level converging to target backlight level. 282 */ 283 uint16_t curr_bl_level; 284 285 /** 286 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 287 */ 288 uint16_t curr_user_bl_level; 289 290 }; 291 292 /** 293 * union dmub_addr - DMUB physical/virtual 64-bit address. 294 */ 295 union dmub_addr { 296 struct { 297 uint32_t low_part; /**< Lower 32 bits */ 298 uint32_t high_part; /**< Upper 32 bits */ 299 } u; /*<< Low/high bit access */ 300 uint64_t quad_part; /*<< 64 bit address */ 301 }; 302 #pragma pack(pop) 303 304 /** 305 * Dirty rect definition. 306 */ 307 struct dmub_rect { 308 /** 309 * Dirty rect x offset. 310 */ 311 uint32_t x; 312 313 /** 314 * Dirty rect y offset. 315 */ 316 uint32_t y; 317 318 /** 319 * Dirty rect width. 320 */ 321 uint32_t width; 322 323 /** 324 * Dirty rect height. 325 */ 326 uint32_t height; 327 }; 328 329 /** 330 * Flags that can be set by driver to change some PSR behaviour. 331 */ 332 union dmub_psr_debug_flags { 333 /** 334 * Debug flags. 335 */ 336 struct { 337 /** 338 * Enable visual confirm in FW. 339 */ 340 uint32_t visual_confirm : 1; 341 342 /** 343 * Force all selective updates to bw full frame updates. 344 */ 345 uint32_t force_full_frame_update : 1; 346 347 /** 348 * Use HW Lock Mgr object to do HW locking in FW. 349 */ 350 uint32_t use_hw_lock_mgr : 1; 351 352 /** 353 * Use TPS3 signal when restore main link. 354 */ 355 uint32_t force_wakeup_by_tps3 : 1; 356 357 /** 358 * Back to back flip, therefore cannot power down PHY 359 */ 360 uint32_t back_to_back_flip : 1; 361 362 /** 363 * Enable visual confirm for IPS 364 */ 365 uint32_t enable_ips_visual_confirm : 1; 366 } bitfields; 367 368 /** 369 * Union for debug flags. 370 */ 371 uint32_t u32All; 372 }; 373 374 /** 375 * Flags that can be set by driver to change some Replay behaviour. 376 */ 377 union replay_debug_flags { 378 struct { 379 /** 380 * 0x1 (bit 0) 381 * Enable visual confirm in FW. 382 */ 383 uint32_t visual_confirm : 1; 384 385 /** 386 * 0x2 (bit 1) 387 * @skip_crc: Set if need to skip CRC. 388 */ 389 uint32_t skip_crc : 1; 390 391 /** 392 * 0x4 (bit 2) 393 * @force_link_power_on: Force disable ALPM control 394 */ 395 uint32_t force_link_power_on : 1; 396 397 /** 398 * 0x8 (bit 3) 399 * @force_phy_power_on: Force phy power on 400 */ 401 uint32_t force_phy_power_on : 1; 402 403 /** 404 * 0x10 (bit 4) 405 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 406 */ 407 uint32_t timing_resync_disabled : 1; 408 409 /** 410 * 0x20 (bit 5) 411 * @skip_crtc_disabled: CRTC disable skipped 412 */ 413 uint32_t skip_crtc_disabled : 1; 414 415 /** 416 * 0x40 (bit 6) 417 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 418 */ 419 uint32_t force_defer_one_frame_update : 1; 420 421 /** 422 * 0x80 (bit 7) 423 * @disable_delay_alpm_on: Force disable delay alpm on 424 */ 425 uint32_t disable_delay_alpm_on : 1; 426 427 /** 428 * 0x100 (bit 8) 429 * @disable_desync_error_check: Force disable desync error check 430 */ 431 uint32_t disable_desync_error_check : 1; 432 433 /** 434 * 0x200 (bit 9) 435 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 436 */ 437 uint32_t force_self_update_when_abm_non_steady : 1; 438 439 /** 440 * 0x400 (bit 10) 441 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 442 * If we enter IPS2, the Visual confirm bar will change to yellow 443 */ 444 uint32_t enable_ips_visual_confirm : 1; 445 446 /** 447 * 0x800 (bit 11) 448 * @enable_ips_residency_profiling: Enable IPS residency profiling 449 */ 450 uint32_t enable_ips_residency_profiling : 1; 451 452 /** 453 * 0x1000 (bit 12) 454 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 455 */ 456 uint32_t enable_coasting_vtotal_check : 1; 457 /** 458 * 0x2000 (bit 13) 459 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 460 */ 461 uint32_t enable_visual_confirm_debug : 1; 462 463 uint32_t reserved : 18; 464 } bitfields; 465 466 uint32_t u32All; 467 }; 468 469 /** 470 * Flags record error state. 471 */ 472 union replay_visual_confirm_error_state_flags { 473 struct { 474 /** 475 * 0x1 (bit 0) - Desync Error flag. 476 */ 477 uint32_t desync_error : 1; 478 479 /** 480 * 0x2 (bit 1) - State Transition Error flag. 481 */ 482 uint32_t state_transition_error : 1; 483 484 /** 485 * 0x4 (bit 2) - Crc Error flag 486 */ 487 uint32_t crc_error : 1; 488 489 /** 490 * 0x8 (bit 3) - Reserved 491 */ 492 uint32_t reserved_3 : 1; 493 494 /** 495 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 496 * Added new debug flag to control DPCD. 497 */ 498 uint32_t incorrect_vtotal_in_static_screen : 1; 499 500 /** 501 * 0x20 (bit 5) - No doubled Refresh Rate. 502 */ 503 uint32_t no_double_rr : 1; 504 505 /** 506 * Reserved bit 6-7 507 */ 508 uint32_t reserved_6_7 : 2; 509 510 /** 511 * Reserved bit 9-31 512 */ 513 uint32_t reserved_9_31 : 24; 514 } bitfields; 515 516 uint32_t u32All; 517 }; 518 519 union replay_hw_flags { 520 struct { 521 /** 522 * @allow_alpm_fw_standby_mode: To indicate whether the 523 * ALPM FW standby mode is allowed 524 */ 525 uint32_t allow_alpm_fw_standby_mode : 1; 526 527 /* 528 * @dsc_enable_status: DSC enable status in driver 529 */ 530 uint32_t dsc_enable_status : 1; 531 532 /** 533 * @fec_enable_status: receive fec enable/disable status from driver 534 */ 535 uint32_t fec_enable_status : 1; 536 537 /* 538 * @smu_optimizations_en: SMU power optimization. 539 * Only when active display is Replay capable and display enters Replay. 540 * Trigger interrupt to SMU to powerup/down. 541 */ 542 uint32_t smu_optimizations_en : 1; 543 544 /** 545 * @phy_power_state: Indicates current phy power state 546 */ 547 uint32_t phy_power_state : 1; 548 549 /** 550 * @link_power_state: Indicates current link power state 551 */ 552 uint32_t link_power_state : 1; 553 /** 554 * Use TPS3 signal when restore main link. 555 */ 556 uint32_t force_wakeup_by_tps3 : 1; 557 /** 558 * @is_alpm_initialized: Indicates whether ALPM is initialized 559 */ 560 uint32_t is_alpm_initialized : 1; 561 562 /** 563 * @alpm_mode: Indicates ALPM mode selected 564 */ 565 uint32_t alpm_mode : 2; 566 } bitfields; 567 568 uint32_t u32All; 569 }; 570 571 union fw_assisted_mclk_switch_version { 572 struct { 573 uint8_t minor : 5; 574 uint8_t major : 3; 575 }; 576 uint8_t ver; 577 }; 578 579 /** 580 * DMUB feature capabilities. 581 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 582 */ 583 struct dmub_feature_caps { 584 /** 585 * Max PSR version supported by FW. 586 */ 587 uint8_t psr; 588 uint8_t fw_assisted_mclk_switch_ver; 589 uint8_t reserved[4]; 590 uint8_t subvp_psr_support; 591 uint8_t gecc_enable; 592 uint8_t replay_supported; 593 uint8_t replay_reserved[3]; 594 uint8_t abm_aux_backlight_support; 595 }; 596 597 struct dmub_visual_confirm_color { 598 /** 599 * Maximum 10 bits color value 600 */ 601 uint16_t color_r_cr; 602 uint16_t color_g_y; 603 uint16_t color_b_cb; 604 uint16_t panel_inst; 605 }; 606 607 //============================================================================== 608 //</DMUB_TYPES>================================================================= 609 //============================================================================== 610 //< DMUB_META>================================================================== 611 //============================================================================== 612 #pragma pack(push, 1) 613 614 /* Magic value for identifying dmub_fw_meta_info */ 615 #define DMUB_FW_META_MAGIC 0x444D5542 616 617 /* Offset from the end of the file to the dmub_fw_meta_info */ 618 #define DMUB_FW_META_OFFSET 0x24 619 620 /** 621 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 622 */ 623 union dmub_fw_meta_feature_bits { 624 struct { 625 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 626 uint32_t reserved : 31; 627 } bits; /**< status bits */ 628 uint32_t all; /**< 32-bit access to status bits */ 629 }; 630 631 /** 632 * struct dmub_fw_meta_info - metadata associated with fw binary 633 * 634 * NOTE: This should be considered a stable API. Fields should 635 * not be repurposed or reordered. New fields should be 636 * added instead to extend the structure. 637 * 638 * @magic_value: magic value identifying DMUB firmware meta info 639 * @fw_region_size: size of the firmware state region 640 * @trace_buffer_size: size of the tracebuffer region 641 * @fw_version: the firmware version information 642 * @dal_fw: 1 if the firmware is DAL 643 * @shared_state_size: size of the shared state region in bytes 644 * @shared_state_features: number of shared state features 645 */ 646 struct dmub_fw_meta_info { 647 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 648 uint32_t fw_region_size; /**< size of the firmware state region */ 649 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 650 uint32_t fw_version; /**< the firmware version information */ 651 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 652 uint8_t reserved[3]; /**< padding bits */ 653 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 654 uint16_t shared_state_features; /**< number of shared state features */ 655 uint16_t reserved2; /**< padding bytes */ 656 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 657 }; 658 659 /** 660 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 661 */ 662 union dmub_fw_meta { 663 struct dmub_fw_meta_info info; /**< metadata info */ 664 uint8_t reserved[64]; /**< padding bits */ 665 }; 666 667 #pragma pack(pop) 668 669 //============================================================================== 670 //< DMUB Trace Buffer>================================================================ 671 //============================================================================== 672 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 673 /** 674 * dmub_trace_code_t - firmware trace code, 32-bits 675 */ 676 typedef uint32_t dmub_trace_code_t; 677 678 /** 679 * struct dmcub_trace_buf_entry - Firmware trace entry 680 */ 681 struct dmcub_trace_buf_entry { 682 dmub_trace_code_t trace_code; /**< trace code for the event */ 683 uint32_t tick_count; /**< the tick count at time of trace */ 684 uint32_t param0; /**< trace defined parameter 0 */ 685 uint32_t param1; /**< trace defined parameter 1 */ 686 }; 687 #endif 688 689 //============================================================================== 690 //< DMUB_STATUS>================================================================ 691 //============================================================================== 692 693 /** 694 * DMCUB scratch registers can be used to determine firmware status. 695 * Current scratch register usage is as follows: 696 * 697 * SCRATCH0: FW Boot Status register 698 * SCRATCH5: LVTMA Status Register 699 * SCRATCH15: FW Boot Options register 700 */ 701 702 /** 703 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 704 */ 705 union dmub_fw_boot_status { 706 struct { 707 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 708 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 709 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 710 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 711 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 712 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 713 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 714 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 715 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 716 } bits; /**< status bits */ 717 uint32_t all; /**< 32-bit access to status bits */ 718 }; 719 720 /** 721 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 722 */ 723 enum dmub_fw_boot_status_bit { 724 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 725 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 726 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 727 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 728 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 729 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 730 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 731 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 732 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 733 }; 734 735 /* Register bit definition for SCRATCH5 */ 736 union dmub_lvtma_status { 737 struct { 738 uint32_t psp_ok : 1; 739 uint32_t edp_on : 1; 740 uint32_t reserved : 30; 741 } bits; 742 uint32_t all; 743 }; 744 745 enum dmub_lvtma_status_bit { 746 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 747 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 748 }; 749 750 enum dmub_ips_disable_type { 751 DMUB_IPS_ENABLE = 0, 752 DMUB_IPS_DISABLE_ALL = 1, 753 DMUB_IPS_DISABLE_IPS1 = 2, 754 DMUB_IPS_DISABLE_IPS2 = 3, 755 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 756 DMUB_IPS_DISABLE_DYNAMIC = 5, 757 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 758 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 759 }; 760 761 enum dmub_ips_rcg_disable_type { 762 DMUB_IPS_RCG_ENABLE = 0, 763 DMUB_IPS0_RCG_DISABLE = 1, 764 DMUB_IPS1_RCG_DISABLE = 2, 765 DMUB_IPS_RCG_DISABLE = 3 766 }; 767 768 #define DMUB_IPS1_ALLOW_MASK 0x00000001 769 #define DMUB_IPS2_ALLOW_MASK 0x00000002 770 #define DMUB_IPS1_COMMIT_MASK 0x00000004 771 #define DMUB_IPS2_COMMIT_MASK 0x00000008 772 773 /** 774 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 775 */ 776 union dmub_fw_boot_options { 777 struct { 778 uint32_t pemu_env : 1; /**< 1 if PEMU */ 779 uint32_t fpga_env : 1; /**< 1 if FPGA */ 780 uint32_t optimized_init : 1; /**< 1 if optimized init */ 781 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 782 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 783 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 784 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 785 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 786 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 787 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 788 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 789 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 790 uint32_t power_optimization: 1; 791 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 792 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 793 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 794 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 795 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 796 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 797 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 798 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 799 uint32_t ips_disable: 3; /* options to disable ips support*/ 800 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 801 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 802 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 803 uint32_t reserved : 6; /**< reserved */ 804 } bits; /**< boot bits */ 805 uint32_t all; /**< 32-bit access to bits */ 806 }; 807 808 enum dmub_fw_boot_options_bit { 809 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 810 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 811 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 812 }; 813 814 //============================================================================== 815 //< DMUB_SHARED_STATE>========================================================== 816 //============================================================================== 817 818 /** 819 * Shared firmware state between driver and firmware for lockless communication 820 * in situations where the inbox/outbox may be unavailable. 821 * 822 * Each structure *must* be at most 256-bytes in size. The layout allocation is 823 * described below: 824 * 825 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 826 */ 827 828 /** 829 * enum dmub_shared_state_feature_id - List of shared state features. 830 */ 831 enum dmub_shared_state_feature_id { 832 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 833 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 834 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 835 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 836 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 837 }; 838 839 /** 840 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 841 */ 842 union dmub_shared_state_ips_fw_signals { 843 struct { 844 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 845 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 846 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 847 uint32_t detection_required : 1; /**< 1 if detection is required */ 848 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 849 uint32_t reserved_bits : 27; /**< Reversed */ 850 } bits; 851 uint32_t all; 852 }; 853 854 /** 855 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 856 */ 857 union dmub_shared_state_ips_driver_signals { 858 struct { 859 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 860 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 861 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 862 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 863 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 864 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 865 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 866 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 867 uint32_t reserved_bits : 24; /**< Reversed bits */ 868 } bits; 869 uint32_t all; 870 }; 871 872 /** 873 * IPS FW Version 874 */ 875 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 876 877 struct dmub_shared_state_debug_setup { 878 union { 879 struct { 880 uint32_t exclude_points[62]; 881 } profile_mode; 882 }; 883 }; 884 885 /** 886 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 887 */ 888 struct dmub_shared_state_ips_fw { 889 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 890 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 891 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 892 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 893 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 894 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 895 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 896 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 897 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 898 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 899 }; /* 248-bytes, fixed */ 900 901 /** 902 * IPS Driver Version 903 */ 904 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 905 906 /** 907 * struct dmub_shared_state_ips_driver - Driver state for IPS. 908 */ 909 struct dmub_shared_state_ips_driver { 910 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 911 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 912 }; /* 248-bytes, fixed */ 913 914 /** 915 * enum dmub_shared_state_feature_common - Generic payload. 916 */ 917 struct dmub_shared_state_feature_common { 918 uint32_t padding[62]; 919 }; /* 248-bytes, fixed */ 920 921 /** 922 * enum dmub_shared_state_feature_header - Feature description. 923 */ 924 struct dmub_shared_state_feature_header { 925 uint16_t id; /**< Feature ID */ 926 uint16_t version; /**< Feature version */ 927 uint32_t reserved; /**< Reserved bytes. */ 928 }; /* 8 bytes, fixed */ 929 930 /** 931 * struct dmub_shared_state_feature_block - Feature block. 932 */ 933 struct dmub_shared_state_feature_block { 934 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 935 union dmub_shared_feature_state_union { 936 struct dmub_shared_state_feature_common common; /**< Generic data */ 937 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 938 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 939 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 940 } data; /**< Shared state data. */ 941 }; /* 256-bytes, fixed */ 942 943 /** 944 * Shared state size in bytes. 945 */ 946 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 947 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 948 949 //============================================================================== 950 //</DMUB_STATUS>================================================================ 951 //============================================================================== 952 //< DMUB_VBIOS>================================================================= 953 //============================================================================== 954 955 /* 956 * enum dmub_cmd_vbios_type - VBIOS commands. 957 * 958 * Command IDs should be treated as stable ABI. 959 * Do not reuse or modify IDs. 960 */ 961 enum dmub_cmd_vbios_type { 962 /** 963 * Configures the DIG encoder. 964 */ 965 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 966 /** 967 * Controls the PHY. 968 */ 969 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 970 /** 971 * Sets the pixel clock/symbol clock. 972 */ 973 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 974 /** 975 * Enables or disables power gating. 976 */ 977 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 978 /** 979 * Controls embedded panels. 980 */ 981 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 982 /** 983 * Query DP alt status on a transmitter. 984 */ 985 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 986 /** 987 * Control PHY FSM 988 */ 989 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 990 /** 991 * Controls domain power gating 992 */ 993 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 994 }; 995 996 //============================================================================== 997 //</DMUB_VBIOS>================================================================= 998 //============================================================================== 999 //< DMUB_GPINT>================================================================= 1000 //============================================================================== 1001 1002 /** 1003 * The shifts and masks below may alternatively be used to format and read 1004 * the command register bits. 1005 */ 1006 1007 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1008 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1009 1010 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1011 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1012 1013 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1014 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1015 1016 /** 1017 * Command responses. 1018 */ 1019 1020 /** 1021 * Return response for DMUB_GPINT__STOP_FW command. 1022 */ 1023 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1024 1025 /** 1026 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1027 */ 1028 union dmub_gpint_data_register { 1029 struct { 1030 uint32_t param : 16; /**< 16-bit parameter */ 1031 uint32_t command_code : 12; /**< GPINT command */ 1032 uint32_t status : 4; /**< Command status bit */ 1033 } bits; /**< GPINT bit access */ 1034 uint32_t all; /**< GPINT 32-bit access */ 1035 }; 1036 1037 /* 1038 * enum dmub_gpint_command - GPINT command to DMCUB FW 1039 * 1040 * Command IDs should be treated as stable ABI. 1041 * Do not reuse or modify IDs. 1042 */ 1043 enum dmub_gpint_command { 1044 /** 1045 * Invalid command, ignored. 1046 */ 1047 DMUB_GPINT__INVALID_COMMAND = 0, 1048 /** 1049 * DESC: Queries the firmware version. 1050 * RETURN: Firmware version. 1051 */ 1052 DMUB_GPINT__GET_FW_VERSION = 1, 1053 /** 1054 * DESC: Halts the firmware. 1055 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1056 */ 1057 DMUB_GPINT__STOP_FW = 2, 1058 /** 1059 * DESC: Get PSR state from FW. 1060 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1061 */ 1062 DMUB_GPINT__GET_PSR_STATE = 7, 1063 /** 1064 * DESC: Notifies DMCUB of the currently active streams. 1065 * ARGS: Stream mask, 1 bit per active stream index. 1066 */ 1067 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1068 /** 1069 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1070 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1071 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1072 * RETURN: PSR residency in milli-percent. 1073 */ 1074 DMUB_GPINT__PSR_RESIDENCY = 9, 1075 1076 /** 1077 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1078 */ 1079 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1080 1081 /** 1082 * DESC: Get REPLAY state from FW. 1083 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1084 */ 1085 DMUB_GPINT__GET_REPLAY_STATE = 13, 1086 1087 /** 1088 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1089 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1090 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1091 * RETURN: REPLAY residency in milli-percent. 1092 */ 1093 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1094 1095 /** 1096 * DESC: Copy bounding box to the host. 1097 * ARGS: Version of bounding box to copy 1098 * RETURN: Result of copying bounding box 1099 */ 1100 DMUB_GPINT__BB_COPY = 96, 1101 1102 /** 1103 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1104 * ARGS: The word3 for the 64 bit address 1105 */ 1106 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1107 1108 /** 1109 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1110 * ARGS: The word2 for the 64 bit address 1111 */ 1112 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1113 1114 /** 1115 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1116 * ARGS: The word1 for the 64 bit address 1117 */ 1118 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1119 1120 /** 1121 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1122 * ARGS: The word0 for the 64 bit address 1123 */ 1124 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1125 1126 /** 1127 * DESC: Updates the trace buffer lower 32-bit mask. 1128 * ARGS: The new mask 1129 * RETURN: Lower 32-bit mask. 1130 */ 1131 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1132 1133 /** 1134 * DESC: Updates the trace buffer mask bit0~bit15. 1135 * ARGS: The new mask 1136 * RETURN: Lower 32-bit mask. 1137 */ 1138 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1139 1140 /** 1141 * DESC: Updates the trace buffer mask bit16~bit31. 1142 * ARGS: The new mask 1143 * RETURN: Lower 32-bit mask. 1144 */ 1145 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1146 1147 /** 1148 * DESC: Updates the trace buffer mask bit32~bit47. 1149 * ARGS: The new mask 1150 * RETURN: Lower 32-bit mask. 1151 */ 1152 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1153 1154 /** 1155 * DESC: Updates the trace buffer mask bit48~bit63. 1156 * ARGS: The new mask 1157 * RETURN: Lower 32-bit mask. 1158 */ 1159 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1160 1161 /** 1162 * DESC: Read the trace buffer mask bi0~bit15. 1163 */ 1164 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1165 1166 /** 1167 * DESC: Read the trace buffer mask bit16~bit31. 1168 */ 1169 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1170 1171 /** 1172 * DESC: Read the trace buffer mask bi32~bit47. 1173 */ 1174 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1175 1176 /** 1177 * DESC: Updates the trace buffer mask bit32~bit63. 1178 */ 1179 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1180 1181 /** 1182 * DESC: Set IPS residency measurement 1183 * ARGS: 0 - Disable ips measurement 1184 * 1 - Enable ips measurement 1185 */ 1186 DMUB_GPINT__IPS_RESIDENCY = 121, 1187 1188 /** 1189 * DESC: Enable measurements for various task duration 1190 * ARGS: 0 - Disable measurement 1191 * 1 - Enable measurement 1192 */ 1193 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1194 1195 /** 1196 * DESC: Gets IPS residency in microseconds 1197 * ARGS: 0 - Return IPS1 residency 1198 * 1 - Return IPS2 residency 1199 * 2 - Return IPS1_RCG residency 1200 * 3 - Return IPS1_ONO2_ON residency 1201 * RETURN: Total residency in microseconds - lower 32 bits 1202 */ 1203 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1204 1205 /** 1206 * DESC: Gets IPS1 histogram counts 1207 * ARGS: Bucket index 1208 * RETURN: Total count for the bucket 1209 */ 1210 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1211 1212 /** 1213 * DESC: Gets IPS2 histogram counts 1214 * ARGS: Bucket index 1215 * RETURN: Total count for the bucket 1216 */ 1217 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1218 1219 /** 1220 * DESC: Gets IPS residency 1221 * ARGS: 0 - Return IPS1 residency 1222 * 1 - Return IPS2 residency 1223 * 2 - Return IPS1_RCG residency 1224 * 3 - Return IPS1_ONO2_ON residency 1225 * RETURN: Total residency in milli-percent. 1226 */ 1227 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1228 1229 /** 1230 * DESC: Gets IPS1_RCG histogram counts 1231 * ARGS: Bucket index 1232 * RETURN: Total count for the bucket 1233 */ 1234 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1235 1236 /** 1237 * DESC: Gets IPS1_ONO2_ON histogram counts 1238 * ARGS: Bucket index 1239 * RETURN: Total count for the bucket 1240 */ 1241 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1242 1243 /** 1244 * DESC: Gets IPS entry counter during residency measurement 1245 * ARGS: 0 - Return IPS1 entry counts 1246 * 1 - Return IPS2 entry counts 1247 * 2 - Return IPS1_RCG entry counts 1248 * 3 - Return IPS2_ONO2_ON entry counts 1249 * RETURN: Entry counter for selected IPS mode 1250 */ 1251 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1252 1253 /** 1254 * DESC: Gets IPS inactive residency in microseconds 1255 * ARGS: 0 - Return IPS1_MAX residency 1256 * 1 - Return IPS2 residency 1257 * 2 - Return IPS1_RCG residency 1258 * 3 - Return IPS1_ONO2_ON residency 1259 * RETURN: Total inactive residency in microseconds - lower 32 bits 1260 */ 1261 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1262 1263 /** 1264 * DESC: Gets IPS inactive residency in microseconds 1265 * ARGS: 0 - Return IPS1_MAX residency 1266 * 1 - Return IPS2 residency 1267 * 2 - Return IPS1_RCG residency 1268 * 3 - Return IPS1_ONO2_ON residency 1269 * RETURN: Total inactive residency in microseconds - upper 32 bits 1270 */ 1271 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1272 1273 /** 1274 * DESC: Gets IPS residency in microseconds 1275 * ARGS: 0 - Return IPS1 residency 1276 * 1 - Return IPS2 residency 1277 * 2 - Return IPS1_RCG residency 1278 * 3 - Return IPS1_ONO2_ON residency 1279 * RETURN: Total residency in microseconds - upper 32 bits 1280 */ 1281 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1282 /** 1283 * DESC: Setup debug configs. 1284 */ 1285 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1286 /** 1287 * DESC: Initiates IPS wake sequence. 1288 */ 1289 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1290 }; 1291 1292 /** 1293 * INBOX0 generic command definition 1294 */ 1295 union dmub_inbox0_cmd_common { 1296 struct { 1297 uint32_t command_code: 8; /**< INBOX0 command code */ 1298 uint32_t param: 24; /**< 24-bit parameter */ 1299 } bits; 1300 uint32_t all; 1301 }; 1302 1303 /** 1304 * INBOX0 hw_lock command definition 1305 */ 1306 union dmub_inbox0_cmd_lock_hw { 1307 struct { 1308 uint32_t command_code: 8; 1309 1310 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1311 uint32_t hw_lock_client: 2; 1312 1313 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1314 uint32_t otg_inst: 3; 1315 uint32_t opp_inst: 3; 1316 uint32_t dig_inst: 3; 1317 1318 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1319 uint32_t lock_pipe: 1; 1320 uint32_t lock_cursor: 1; 1321 uint32_t lock_dig: 1; 1322 uint32_t triple_buffer_lock: 1; 1323 1324 uint32_t lock: 1; /**< Lock */ 1325 uint32_t should_release: 1; /**< Release */ 1326 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1327 } bits; 1328 uint32_t all; 1329 }; 1330 1331 union dmub_inbox0_data_register { 1332 union dmub_inbox0_cmd_common inbox0_cmd_common; 1333 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1334 }; 1335 1336 enum dmub_inbox0_command { 1337 /** 1338 * DESC: Invalid command, ignored. 1339 */ 1340 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1341 /** 1342 * DESC: Notification to acquire/release HW lock 1343 * ARGS: 1344 */ 1345 DMUB_INBOX0_CMD__HW_LOCK = 1, 1346 }; 1347 //============================================================================== 1348 //</DMUB_GPINT>================================================================= 1349 //============================================================================== 1350 //< DMUB_CMD>=================================================================== 1351 //============================================================================== 1352 1353 /** 1354 * Size in bytes of each DMUB command. 1355 */ 1356 #define DMUB_RB_CMD_SIZE 64 1357 1358 /** 1359 * Maximum number of items in the DMUB ringbuffer. 1360 */ 1361 #define DMUB_RB_MAX_ENTRY 128 1362 1363 /** 1364 * Ringbuffer size in bytes. 1365 */ 1366 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1367 1368 /** 1369 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1370 */ 1371 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1372 1373 /** 1374 * Ringbuffer size in bytes. 1375 */ 1376 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1377 1378 /** 1379 * REG_SET mask for reg offload. 1380 */ 1381 #define REG_SET_MASK 0xFFFF 1382 1383 /* 1384 * enum dmub_cmd_type - DMUB inbox command. 1385 * 1386 * Command IDs should be treated as stable ABI. 1387 * Do not reuse or modify IDs. 1388 */ 1389 enum dmub_cmd_type { 1390 /** 1391 * Invalid command. 1392 */ 1393 DMUB_CMD__NULL = 0, 1394 /** 1395 * Read modify write register sequence offload. 1396 */ 1397 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1398 /** 1399 * Field update register sequence offload. 1400 */ 1401 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1402 /** 1403 * Burst write sequence offload. 1404 */ 1405 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1406 /** 1407 * Reg wait sequence offload. 1408 */ 1409 DMUB_CMD__REG_REG_WAIT = 4, 1410 /** 1411 * Workaround to avoid HUBP underflow during NV12 playback. 1412 */ 1413 DMUB_CMD__PLAT_54186_WA = 5, 1414 /** 1415 * Command type used to query FW feature caps. 1416 */ 1417 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1418 /** 1419 * Command type used to get visual confirm color. 1420 */ 1421 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1422 /** 1423 * Command type used for all PSR commands. 1424 */ 1425 DMUB_CMD__PSR = 64, 1426 /** 1427 * Command type used for all MALL commands. 1428 */ 1429 DMUB_CMD__MALL = 65, 1430 /** 1431 * Command type used for all ABM commands. 1432 */ 1433 DMUB_CMD__ABM = 66, 1434 /** 1435 * Command type used to update dirty rects in FW. 1436 */ 1437 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1438 /** 1439 * Command type used to update cursor info in FW. 1440 */ 1441 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1442 /** 1443 * Command type used for HW locking in FW. 1444 */ 1445 DMUB_CMD__HW_LOCK = 69, 1446 /** 1447 * Command type used to access DP AUX. 1448 */ 1449 DMUB_CMD__DP_AUX_ACCESS = 70, 1450 /** 1451 * Command type used for OUTBOX1 notification enable 1452 */ 1453 DMUB_CMD__OUTBOX1_ENABLE = 71, 1454 1455 /** 1456 * Command type used for all idle optimization commands. 1457 */ 1458 DMUB_CMD__IDLE_OPT = 72, 1459 /** 1460 * Command type used for all clock manager commands. 1461 */ 1462 DMUB_CMD__CLK_MGR = 73, 1463 /** 1464 * Command type used for all panel control commands. 1465 */ 1466 DMUB_CMD__PANEL_CNTL = 74, 1467 1468 /** 1469 * Command type used for all CAB commands. 1470 */ 1471 DMUB_CMD__CAB_FOR_SS = 75, 1472 1473 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1474 1475 /** 1476 * Command type used for interfacing with DPIA. 1477 */ 1478 DMUB_CMD__DPIA = 77, 1479 /** 1480 * Command type used for EDID CEA parsing 1481 */ 1482 DMUB_CMD__EDID_CEA = 79, 1483 /** 1484 * Command type used for getting usbc cable ID 1485 */ 1486 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1487 /** 1488 * Command type used to query HPD state. 1489 */ 1490 DMUB_CMD__QUERY_HPD_STATE = 82, 1491 /** 1492 * Command type used for all VBIOS interface commands. 1493 */ 1494 /** 1495 * Command type used for all REPLAY commands. 1496 */ 1497 DMUB_CMD__REPLAY = 83, 1498 1499 /** 1500 * Command type used for all SECURE_DISPLAY commands. 1501 */ 1502 DMUB_CMD__SECURE_DISPLAY = 85, 1503 1504 /** 1505 * Command type used to set DPIA HPD interrupt state 1506 */ 1507 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1508 1509 /** 1510 * Command type used for all PSP commands. 1511 */ 1512 DMUB_CMD__PSP = 88, 1513 1514 /** 1515 * Command type used for all Fused IO commands. 1516 */ 1517 DMUB_CMD__FUSED_IO = 89, 1518 1519 /** 1520 * Command type used for all LSDMA commands. 1521 */ 1522 DMUB_CMD__LSDMA = 90, 1523 1524 DMUB_CMD__VBIOS = 128, 1525 }; 1526 1527 /** 1528 * enum dmub_out_cmd_type - DMUB outbox commands. 1529 */ 1530 enum dmub_out_cmd_type { 1531 /** 1532 * Invalid outbox command, ignored. 1533 */ 1534 DMUB_OUT_CMD__NULL = 0, 1535 /** 1536 * Command type used for DP AUX Reply data notification 1537 */ 1538 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1539 /** 1540 * Command type used for DP HPD event notification 1541 */ 1542 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1543 /** 1544 * Command type used for SET_CONFIG Reply notification 1545 */ 1546 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1547 /** 1548 * Command type used for USB4 DPIA notification 1549 */ 1550 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1551 /** 1552 * Command type used for HPD redetect notification 1553 */ 1554 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1555 /** 1556 * Command type used for Fused IO notification 1557 */ 1558 DMUB_OUT_CMD__FUSED_IO = 7, 1559 }; 1560 1561 /* DMUB_CMD__DPIA command sub-types. */ 1562 enum dmub_cmd_dpia_type { 1563 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1564 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1565 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1566 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1567 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1568 }; 1569 1570 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1571 enum dmub_cmd_dpia_notification_type { 1572 DPIA_NOTIFY__BW_ALLOCATION = 0, 1573 }; 1574 1575 #pragma pack(push, 1) 1576 1577 /** 1578 * struct dmub_cmd_header - Common command header fields. 1579 */ 1580 struct dmub_cmd_header { 1581 unsigned int type : 8; /**< command type */ 1582 unsigned int sub_type : 8; /**< command sub type */ 1583 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1584 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1585 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1586 unsigned int reserved0 : 5; /**< reserved bits */ 1587 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1588 unsigned int reserved1 : 2; /**< reserved bits */ 1589 }; 1590 1591 /* 1592 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1593 * 1594 * 60 payload bytes can hold up to 5 sets of read modify writes, 1595 * each take 3 dwords. 1596 * 1597 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1598 * 1599 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1600 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1601 */ 1602 struct dmub_cmd_read_modify_write_sequence { 1603 uint32_t addr; /**< register address */ 1604 uint32_t modify_mask; /**< modify mask */ 1605 uint32_t modify_value; /**< modify value */ 1606 }; 1607 1608 /** 1609 * Maximum number of ops in read modify write sequence. 1610 */ 1611 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1612 1613 /** 1614 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1615 */ 1616 struct dmub_rb_cmd_read_modify_write { 1617 struct dmub_cmd_header header; /**< command header */ 1618 /** 1619 * Read modify write sequence. 1620 */ 1621 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1622 }; 1623 1624 /* 1625 * Update a register with specified masks and values sequeunce 1626 * 1627 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1628 * 1629 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1630 * 1631 * 1632 * USE CASE: 1633 * 1. auto-increment register where additional read would update pointer and produce wrong result 1634 * 2. toggle a bit without read in the middle 1635 */ 1636 1637 struct dmub_cmd_reg_field_update_sequence { 1638 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1639 uint32_t modify_value; /**< value to update with */ 1640 }; 1641 1642 /** 1643 * Maximum number of ops in field update sequence. 1644 */ 1645 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1646 1647 /** 1648 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1649 */ 1650 struct dmub_rb_cmd_reg_field_update_sequence { 1651 struct dmub_cmd_header header; /**< command header */ 1652 uint32_t addr; /**< register address */ 1653 /** 1654 * Field update sequence. 1655 */ 1656 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1657 }; 1658 1659 1660 /** 1661 * Maximum number of burst write values. 1662 */ 1663 #define DMUB_BURST_WRITE_VALUES__MAX 14 1664 1665 /* 1666 * struct dmub_rb_cmd_burst_write - Burst write 1667 * 1668 * support use case such as writing out LUTs. 1669 * 1670 * 60 payload bytes can hold up to 14 values to write to given address 1671 * 1672 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1673 */ 1674 struct dmub_rb_cmd_burst_write { 1675 struct dmub_cmd_header header; /**< command header */ 1676 uint32_t addr; /**< register start address */ 1677 /** 1678 * Burst write register values. 1679 */ 1680 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1681 }; 1682 1683 /** 1684 * struct dmub_rb_cmd_common - Common command header 1685 */ 1686 struct dmub_rb_cmd_common { 1687 struct dmub_cmd_header header; /**< command header */ 1688 /** 1689 * Padding to RB_CMD_SIZE 1690 */ 1691 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1692 }; 1693 1694 /** 1695 * struct dmub_cmd_reg_wait_data - Register wait data 1696 */ 1697 struct dmub_cmd_reg_wait_data { 1698 uint32_t addr; /**< Register address */ 1699 uint32_t mask; /**< Mask for register bits */ 1700 uint32_t condition_field_value; /**< Value to wait for */ 1701 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1702 }; 1703 1704 /** 1705 * struct dmub_rb_cmd_reg_wait - Register wait command 1706 */ 1707 struct dmub_rb_cmd_reg_wait { 1708 struct dmub_cmd_header header; /**< Command header */ 1709 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1710 }; 1711 1712 /** 1713 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1714 * 1715 * Reprograms surface parameters to avoid underflow. 1716 */ 1717 struct dmub_cmd_PLAT_54186_wa { 1718 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1719 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1720 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1721 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1722 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1723 struct { 1724 uint32_t hubp_inst : 4; /**< HUBP instance */ 1725 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1726 uint32_t immediate :1; /**< Immediate flip */ 1727 uint32_t vmid : 4; /**< VMID */ 1728 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1729 uint32_t reserved : 21; /**< Reserved */ 1730 } flip_params; /**< Pageflip parameters */ 1731 uint32_t reserved[9]; /**< Reserved bits */ 1732 }; 1733 1734 /** 1735 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1736 */ 1737 struct dmub_rb_cmd_PLAT_54186_wa { 1738 struct dmub_cmd_header header; /**< Command header */ 1739 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1740 }; 1741 1742 /** 1743 * enum dmub_cmd_mall_type - MALL commands 1744 */ 1745 enum dmub_cmd_mall_type { 1746 /** 1747 * Allows display refresh from MALL. 1748 */ 1749 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1750 /** 1751 * Disallows display refresh from MALL. 1752 */ 1753 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1754 /** 1755 * Cursor copy for MALL. 1756 */ 1757 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1758 /** 1759 * Controls DF requests. 1760 */ 1761 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1762 }; 1763 1764 /** 1765 * struct dmub_rb_cmd_mall - MALL command data. 1766 */ 1767 struct dmub_rb_cmd_mall { 1768 struct dmub_cmd_header header; /**< Common command header */ 1769 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1770 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1771 uint32_t tmr_delay; /**< Timer delay */ 1772 uint32_t tmr_scale; /**< Timer scale */ 1773 uint16_t cursor_width; /**< Cursor width in pixels */ 1774 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1775 uint16_t cursor_height; /**< Cursor height in pixels */ 1776 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1777 uint8_t debug_bits; /**< Debug bits */ 1778 1779 uint8_t reserved1; /**< Reserved bits */ 1780 uint8_t reserved2; /**< Reserved bits */ 1781 }; 1782 1783 /** 1784 * enum dmub_cmd_cab_type - CAB command data. 1785 */ 1786 enum dmub_cmd_cab_type { 1787 /** 1788 * No idle optimizations (i.e. no CAB) 1789 */ 1790 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1791 /** 1792 * No DCN requests for memory 1793 */ 1794 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1795 /** 1796 * Fit surfaces in CAB (i.e. CAB enable) 1797 */ 1798 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1799 /** 1800 * Do not fit surfaces in CAB (i.e. no CAB) 1801 */ 1802 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1803 }; 1804 1805 /** 1806 * struct dmub_rb_cmd_cab - CAB command data. 1807 */ 1808 struct dmub_rb_cmd_cab_for_ss { 1809 struct dmub_cmd_header header; 1810 uint8_t cab_alloc_ways; /* total number of ways */ 1811 uint8_t debug_bits; /* debug bits */ 1812 }; 1813 1814 /** 1815 * Enum for indicating which MCLK switch mode per pipe 1816 */ 1817 enum mclk_switch_mode { 1818 NONE = 0, 1819 FPO = 1, 1820 SUBVP = 2, 1821 VBLANK = 3, 1822 }; 1823 1824 /* Per pipe struct which stores the MCLK switch mode 1825 * data to be sent to DMUB. 1826 * Named "v2" for now -- once FPO and SUBVP are fully merged 1827 * the type name can be updated 1828 */ 1829 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1830 union { 1831 struct { 1832 uint32_t pix_clk_100hz; 1833 uint16_t main_vblank_start; 1834 uint16_t main_vblank_end; 1835 uint16_t mall_region_lines; 1836 uint16_t prefetch_lines; 1837 uint16_t prefetch_to_mall_start_lines; 1838 uint16_t processing_delay_lines; 1839 uint16_t htotal; // required to calculate line time for multi-display cases 1840 uint16_t vtotal; 1841 uint8_t main_pipe_index; 1842 uint8_t phantom_pipe_index; 1843 /* Since the microschedule is calculated in terms of OTG lines, 1844 * include any scaling factors to make sure when we get accurate 1845 * conversion when programming MALL_START_LINE (which is in terms 1846 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1847 * is 1/2 (numerator = 1, denominator = 2). 1848 */ 1849 uint8_t scale_factor_numerator; 1850 uint8_t scale_factor_denominator; 1851 uint8_t is_drr; 1852 uint8_t main_split_pipe_index; 1853 uint8_t phantom_split_pipe_index; 1854 } subvp_data; 1855 1856 struct { 1857 uint32_t pix_clk_100hz; 1858 uint16_t vblank_start; 1859 uint16_t vblank_end; 1860 uint16_t vstartup_start; 1861 uint16_t vtotal; 1862 uint16_t htotal; 1863 uint8_t vblank_pipe_index; 1864 uint8_t padding[1]; 1865 struct { 1866 uint8_t drr_in_use; 1867 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1868 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1869 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1870 uint8_t use_ramping; // Use ramping or not 1871 uint8_t drr_vblank_start_margin; 1872 } drr_info; // DRR considered as part of SubVP + VBLANK case 1873 } vblank_data; 1874 } pipe_config; 1875 1876 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1877 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1878 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1879 */ 1880 uint8_t mode; // enum mclk_switch_mode 1881 }; 1882 1883 /** 1884 * Config data for Sub-VP and FPO 1885 * Named "v2" for now -- once FPO and SUBVP are fully merged 1886 * the type name can be updated 1887 */ 1888 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1889 uint16_t watermark_a_cache; 1890 uint8_t vertical_int_margin_us; 1891 uint8_t pstate_allow_width_us; 1892 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1893 }; 1894 1895 /** 1896 * DMUB rb command definition for Sub-VP and FPO 1897 * Named "v2" for now -- once FPO and SUBVP are fully merged 1898 * the type name can be updated 1899 */ 1900 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1901 struct dmub_cmd_header header; 1902 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1903 }; 1904 1905 struct dmub_flip_addr_info { 1906 uint32_t surf_addr_lo; 1907 uint32_t surf_addr_c_lo; 1908 uint32_t meta_addr_lo; 1909 uint32_t meta_addr_c_lo; 1910 uint16_t surf_addr_hi; 1911 uint16_t surf_addr_c_hi; 1912 uint16_t meta_addr_hi; 1913 uint16_t meta_addr_c_hi; 1914 }; 1915 1916 struct dmub_fams2_flip_info { 1917 union { 1918 struct { 1919 uint8_t is_immediate: 1; 1920 } bits; 1921 uint8_t all; 1922 } config; 1923 uint8_t otg_inst; 1924 uint8_t pipe_mask; 1925 uint8_t pad; 1926 struct dmub_flip_addr_info addr_info; 1927 }; 1928 1929 struct dmub_rb_cmd_fams2_flip { 1930 struct dmub_cmd_header header; 1931 struct dmub_fams2_flip_info flip_info; 1932 }; 1933 1934 struct dmub_cmd_lsdma_data { 1935 union { 1936 struct lsdma_init_data { 1937 union dmub_addr gpu_addr_base; 1938 uint32_t ring_size; 1939 } init_data; 1940 struct lsdma_tiled_copy_data { 1941 uint32_t src_addr_lo; 1942 uint32_t src_addr_hi; 1943 uint32_t dst_addr_lo; 1944 uint32_t dst_addr_hi; 1945 1946 uint32_t src_x : 16; 1947 uint32_t src_y : 16; 1948 1949 uint32_t src_width : 16; 1950 uint32_t src_height : 16; 1951 1952 uint32_t dst_x : 16; 1953 uint32_t dst_y : 16; 1954 1955 uint32_t dst_width : 16; 1956 uint32_t dst_height : 16; 1957 1958 uint32_t rect_x : 16; 1959 uint32_t rect_y : 16; 1960 1961 uint32_t src_swizzle_mode : 5; 1962 uint32_t src_mip_max : 5; 1963 uint32_t src_mip_id : 5; 1964 uint32_t dst_mip_max : 5; 1965 uint32_t dst_swizzle_mode : 5; 1966 uint32_t dst_mip_id : 5; 1967 uint32_t tmz : 1; 1968 uint32_t dcc : 1; 1969 1970 uint32_t data_format : 6; 1971 uint32_t padding1 : 4; 1972 uint32_t dst_element_size : 3; 1973 uint32_t num_type : 3; 1974 uint32_t src_element_size : 3; 1975 uint32_t write_compress : 2; 1976 uint32_t cache_policy_dst : 2; 1977 uint32_t cache_policy_src : 2; 1978 uint32_t read_compress : 2; 1979 uint32_t src_dim : 2; 1980 uint32_t dst_dim : 2; 1981 uint32_t max_uncom : 1; 1982 1983 uint32_t max_com : 2; 1984 uint32_t padding : 30; 1985 } tiled_copy_data; 1986 struct lsdma_linear_copy_data { 1987 uint32_t count : 30; 1988 uint32_t cache_policy_dst : 2; 1989 1990 uint32_t tmz : 1; 1991 uint32_t cache_policy_src : 2; 1992 uint32_t padding : 29; 1993 1994 uint32_t src_lo; 1995 uint32_t src_hi; 1996 uint32_t dst_lo; 1997 uint32_t dst_hi; 1998 } linear_copy_data; 1999 struct lsdma_reg_write_data { 2000 uint32_t reg_addr; 2001 uint32_t reg_data; 2002 } reg_write_data; 2003 struct lsdma_pio_copy_data { 2004 union { 2005 struct { 2006 uint32_t byte_count : 26; 2007 uint32_t src_loc : 1; 2008 uint32_t dst_loc : 1; 2009 uint32_t src_addr_inc : 1; 2010 uint32_t dst_addr_inc : 1; 2011 uint32_t overlap_disable : 1; 2012 uint32_t constant_fill : 1; 2013 } fields; 2014 uint32_t raw; 2015 } packet; 2016 uint32_t src_lo; 2017 uint32_t src_hi; 2018 uint32_t dst_lo; 2019 uint32_t dst_hi; 2020 } pio_copy_data; 2021 struct lsdma_pio_constfill_data { 2022 union { 2023 struct { 2024 uint32_t byte_count : 26; 2025 uint32_t src_loc : 1; 2026 uint32_t dst_loc : 1; 2027 uint32_t src_addr_inc : 1; 2028 uint32_t dst_addr_inc : 1; 2029 uint32_t overlap_disable : 1; 2030 uint32_t constant_fill : 1; 2031 } fields; 2032 uint32_t raw; 2033 } packet; 2034 uint32_t dst_lo; 2035 uint32_t dst_hi; 2036 uint32_t data; 2037 } pio_constfill_data; 2038 2039 uint32_t all[14]; 2040 } u; 2041 2042 }; 2043 2044 struct dmub_rb_cmd_lsdma { 2045 struct dmub_cmd_header header; 2046 struct dmub_cmd_lsdma_data lsdma_data; 2047 }; 2048 2049 struct dmub_optc_state_v2 { 2050 uint32_t v_total_min; 2051 uint32_t v_total_max; 2052 uint32_t v_total_mid; 2053 uint32_t v_total_mid_frame_num; 2054 uint8_t program_manual_trigger; 2055 uint8_t tg_inst; 2056 uint8_t pad[2]; 2057 }; 2058 2059 struct dmub_optc_position { 2060 uint32_t vpos; 2061 uint32_t hpos; 2062 uint32_t frame; 2063 }; 2064 2065 struct dmub_rb_cmd_fams2_drr_update { 2066 struct dmub_cmd_header header; 2067 struct dmub_optc_state_v2 dmub_optc_state_req; 2068 }; 2069 2070 /* HW and FW global configuration data for FAMS2 */ 2071 /* FAMS2 types and structs */ 2072 enum fams2_stream_type { 2073 FAMS2_STREAM_TYPE_NONE = 0, 2074 FAMS2_STREAM_TYPE_VBLANK = 1, 2075 FAMS2_STREAM_TYPE_VACTIVE = 2, 2076 FAMS2_STREAM_TYPE_DRR = 3, 2077 FAMS2_STREAM_TYPE_SUBVP = 4, 2078 }; 2079 2080 /* static stream state */ 2081 struct dmub_fams2_legacy_stream_static_state { 2082 uint8_t vactive_det_fill_delay_otg_vlines; 2083 uint8_t programming_delay_otg_vlines; 2084 }; //v0 2085 2086 struct dmub_fams2_subvp_stream_static_state { 2087 uint16_t vratio_numerator; 2088 uint16_t vratio_denominator; 2089 uint16_t phantom_vtotal; 2090 uint16_t phantom_vactive; 2091 union { 2092 struct { 2093 uint8_t is_multi_planar : 1; 2094 uint8_t is_yuv420 : 1; 2095 } bits; 2096 uint8_t all; 2097 } config; 2098 uint8_t programming_delay_otg_vlines; 2099 uint8_t prefetch_to_mall_otg_vlines; 2100 uint8_t phantom_otg_inst; 2101 uint8_t phantom_pipe_mask; 2102 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2103 }; //v0 2104 2105 struct dmub_fams2_drr_stream_static_state { 2106 uint16_t nom_stretched_vtotal; 2107 uint8_t programming_delay_otg_vlines; 2108 uint8_t only_stretch_if_required; 2109 uint8_t pad[2]; 2110 }; //v0 2111 2112 struct dmub_fams2_cmd_legacy_stream_static_state { 2113 uint16_t vactive_det_fill_delay_otg_vlines; 2114 uint16_t programming_delay_otg_vlines; 2115 }; //v1 2116 2117 struct dmub_fams2_cmd_subvp_stream_static_state { 2118 uint16_t vratio_numerator; 2119 uint16_t vratio_denominator; 2120 uint16_t phantom_vtotal; 2121 uint16_t phantom_vactive; 2122 uint16_t programming_delay_otg_vlines; 2123 uint16_t prefetch_to_mall_otg_vlines; 2124 union { 2125 struct { 2126 uint8_t is_multi_planar : 1; 2127 uint8_t is_yuv420 : 1; 2128 } bits; 2129 uint8_t all; 2130 } config; 2131 uint8_t phantom_otg_inst; 2132 uint8_t phantom_pipe_mask; 2133 uint8_t pad0; 2134 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2135 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2136 }; //v1 2137 2138 struct dmub_fams2_cmd_drr_stream_static_state { 2139 uint16_t nom_stretched_vtotal; 2140 uint16_t programming_delay_otg_vlines; 2141 uint8_t only_stretch_if_required; 2142 uint8_t pad[3]; 2143 }; //v1 2144 2145 union dmub_fams2_stream_static_sub_state { 2146 struct dmub_fams2_legacy_stream_static_state legacy; 2147 struct dmub_fams2_subvp_stream_static_state subvp; 2148 struct dmub_fams2_drr_stream_static_state drr; 2149 }; //v0 2150 2151 union dmub_fams2_cmd_stream_static_sub_state { 2152 COMMON_STREAM_STATIC_SUB_STATE 2153 }; //v1 2154 2155 union dmub_fams2_stream_static_sub_state_v2 { 2156 COMMON_STREAM_STATIC_SUB_STATE 2157 }; //v2 2158 2159 struct dmub_fams2_stream_static_state { 2160 enum fams2_stream_type type; 2161 uint32_t otg_vline_time_ns; 2162 uint32_t otg_vline_time_ticks; 2163 uint16_t htotal; 2164 uint16_t vtotal; // nominal vtotal 2165 uint16_t vblank_start; 2166 uint16_t vblank_end; 2167 uint16_t max_vtotal; 2168 uint16_t allow_start_otg_vline; 2169 uint16_t allow_end_otg_vline; 2170 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2171 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2172 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2173 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2174 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2175 union { 2176 struct { 2177 uint8_t is_drr: 1; // stream is DRR enabled 2178 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2179 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2180 } bits; 2181 uint8_t all; 2182 } config; 2183 uint8_t otg_inst; 2184 uint8_t pipe_mask; // pipe mask for the whole config 2185 uint8_t num_planes; 2186 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2187 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2188 union dmub_fams2_stream_static_sub_state sub_state; 2189 }; //v0 2190 2191 struct dmub_fams2_cmd_stream_static_base_state { 2192 enum fams2_stream_type type; 2193 uint32_t otg_vline_time_ns; 2194 uint32_t otg_vline_time_ticks; 2195 uint16_t htotal; 2196 uint16_t vtotal; // nominal vtotal 2197 uint16_t vblank_start; 2198 uint16_t vblank_end; 2199 uint16_t max_vtotal; 2200 uint16_t allow_start_otg_vline; 2201 uint16_t allow_end_otg_vline; 2202 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2203 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2204 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2205 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2206 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2207 union { 2208 struct { 2209 uint8_t is_drr : 1; // stream is DRR enabled 2210 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2211 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2212 } bits; 2213 uint8_t all; 2214 } config; 2215 uint8_t otg_inst; 2216 uint8_t pipe_mask; // pipe mask for the whole config 2217 uint8_t num_planes; 2218 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2219 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2220 }; //v1 2221 2222 struct dmub_fams2_stream_static_state_v1 { 2223 struct dmub_fams2_cmd_stream_static_base_state base; 2224 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2225 }; //v1 2226 2227 /** 2228 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2229 * p-state request to allow latency 2230 */ 2231 enum dmub_fams2_allow_delay_check_mode { 2232 /* No check for request to allow delay */ 2233 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2234 /* Check for request to allow delay */ 2235 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2236 /* Check for prepare to allow delay */ 2237 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2238 }; 2239 2240 union dmub_fams2_global_feature_config { 2241 struct { 2242 uint32_t enable: 1; 2243 uint32_t enable_ppt_check: 1; 2244 uint32_t enable_stall_recovery: 1; 2245 uint32_t enable_debug: 1; 2246 uint32_t enable_offload_flip: 1; 2247 uint32_t enable_visual_confirm: 1; 2248 uint32_t allow_delay_check_mode: 2; 2249 uint32_t reserved: 24; 2250 } bits; 2251 uint32_t all; 2252 }; 2253 2254 struct dmub_cmd_fams2_global_config { 2255 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2256 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2257 uint32_t num_streams; 2258 union dmub_fams2_global_feature_config features; 2259 uint32_t recovery_timeout_us; 2260 uint32_t hwfq_flip_programming_delay_us; 2261 }; 2262 2263 union dmub_cmd_fams2_config { 2264 struct dmub_cmd_fams2_global_config global; 2265 struct dmub_fams2_stream_static_state stream; //v0 2266 union { 2267 struct dmub_fams2_cmd_stream_static_base_state base; 2268 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2269 } stream_v1; //v1 2270 }; 2271 2272 struct dmub_fams2_config_v2 { 2273 struct dmub_cmd_fams2_global_config global; 2274 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2275 }; 2276 2277 /** 2278 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2279 */ 2280 struct dmub_rb_cmd_fams2 { 2281 struct dmub_cmd_header header; 2282 union dmub_cmd_fams2_config config; 2283 }; 2284 2285 /** 2286 * Indirect buffer descriptor 2287 */ 2288 struct dmub_ib_data { 2289 union dmub_addr src; // location of indirect buffer in memory 2290 uint16_t size; // indirect buffer size in bytes 2291 }; 2292 2293 /** 2294 * DMUB rb command definition for commands passed over indirect buffer 2295 */ 2296 struct dmub_rb_cmd_ib { 2297 struct dmub_cmd_header header; 2298 struct dmub_ib_data ib_data; 2299 }; 2300 2301 /** 2302 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2303 */ 2304 enum dmub_cmd_idle_opt_type { 2305 /** 2306 * DCN hardware restore. 2307 */ 2308 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2309 2310 /** 2311 * DCN hardware save. 2312 */ 2313 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2314 2315 /** 2316 * DCN hardware notify idle. 2317 */ 2318 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2319 2320 /** 2321 * DCN hardware notify power state. 2322 */ 2323 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2324 2325 /** 2326 * DCN notify to release HW. 2327 */ 2328 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2329 }; 2330 2331 /** 2332 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2333 */ 2334 struct dmub_rb_cmd_idle_opt_dcn_restore { 2335 struct dmub_cmd_header header; /**< header */ 2336 }; 2337 2338 /** 2339 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2340 */ 2341 struct dmub_dcn_notify_idle_cntl_data { 2342 uint8_t driver_idle; 2343 uint8_t skip_otg_disable; 2344 uint8_t reserved[58]; 2345 }; 2346 2347 /** 2348 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2349 */ 2350 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2351 struct dmub_cmd_header header; /**< header */ 2352 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2353 }; 2354 2355 /** 2356 * enum dmub_idle_opt_dc_power_state - DC power states. 2357 */ 2358 enum dmub_idle_opt_dc_power_state { 2359 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2360 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2361 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2362 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2363 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2364 }; 2365 2366 /** 2367 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2368 */ 2369 struct dmub_idle_opt_set_dc_power_state_data { 2370 uint8_t power_state; /**< power state */ 2371 uint8_t pad[3]; /**< padding */ 2372 }; 2373 2374 /** 2375 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2376 */ 2377 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2378 struct dmub_cmd_header header; /**< header */ 2379 struct dmub_idle_opt_set_dc_power_state_data data; 2380 }; 2381 2382 /** 2383 * struct dmub_clocks - Clock update notification. 2384 */ 2385 struct dmub_clocks { 2386 uint32_t dispclk_khz; /**< dispclk kHz */ 2387 uint32_t dppclk_khz; /**< dppclk kHz */ 2388 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2389 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2390 }; 2391 2392 /** 2393 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2394 */ 2395 enum dmub_cmd_clk_mgr_type { 2396 /** 2397 * Notify DMCUB of clock update. 2398 */ 2399 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2400 }; 2401 2402 /** 2403 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2404 */ 2405 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2406 struct dmub_cmd_header header; /**< header */ 2407 struct dmub_clocks clocks; /**< clock data */ 2408 }; 2409 2410 /** 2411 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2412 */ 2413 struct dmub_cmd_digx_encoder_control_data { 2414 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2415 }; 2416 2417 /** 2418 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2419 */ 2420 struct dmub_rb_cmd_digx_encoder_control { 2421 struct dmub_cmd_header header; /**< header */ 2422 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2423 }; 2424 2425 /** 2426 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2427 */ 2428 struct dmub_cmd_set_pixel_clock_data { 2429 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2430 }; 2431 2432 /** 2433 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2434 */ 2435 struct dmub_rb_cmd_set_pixel_clock { 2436 struct dmub_cmd_header header; /**< header */ 2437 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2438 }; 2439 2440 /** 2441 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2442 */ 2443 struct dmub_cmd_enable_disp_power_gating_data { 2444 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2445 }; 2446 2447 /** 2448 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2449 */ 2450 struct dmub_rb_cmd_enable_disp_power_gating { 2451 struct dmub_cmd_header header; /**< header */ 2452 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2453 }; 2454 2455 /** 2456 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2457 */ 2458 struct dmub_dig_transmitter_control_data_v1_7 { 2459 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2460 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2461 union { 2462 uint8_t digmode; /**< enum atom_encode_mode_def */ 2463 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2464 } mode_laneset; 2465 uint8_t lanenum; /**< Number of lanes */ 2466 union { 2467 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2468 } symclk_units; 2469 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2470 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2471 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2472 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2473 uint8_t reserved1; /**< For future use */ 2474 uint8_t reserved2[3]; /**< For future use */ 2475 uint32_t reserved3[11]; /**< For future use */ 2476 }; 2477 2478 /** 2479 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2480 */ 2481 union dmub_cmd_dig1_transmitter_control_data { 2482 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2483 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2484 }; 2485 2486 /** 2487 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2488 */ 2489 struct dmub_rb_cmd_dig1_transmitter_control { 2490 struct dmub_cmd_header header; /**< header */ 2491 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2492 }; 2493 2494 /** 2495 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2496 */ 2497 struct dmub_rb_cmd_domain_control_data { 2498 uint8_t inst : 6; /**< DOMAIN instance to control */ 2499 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2500 uint8_t reserved[3]; /**< Reserved for future use */ 2501 }; 2502 2503 /** 2504 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2505 */ 2506 struct dmub_rb_cmd_domain_control { 2507 struct dmub_cmd_header header; /**< header */ 2508 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2509 }; 2510 2511 /** 2512 * DPIA tunnel command parameters. 2513 */ 2514 struct dmub_cmd_dig_dpia_control_data { 2515 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2516 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2517 union { 2518 uint8_t digmode; /** enum atom_encode_mode_def */ 2519 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2520 } mode_laneset; 2521 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2522 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2523 uint8_t hpdsel; /** =0: HPD is not assigned */ 2524 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2525 uint8_t dpia_id; /** Index of DPIA */ 2526 uint8_t fec_rdy : 1; 2527 uint8_t reserved : 7; 2528 uint32_t reserved1; 2529 }; 2530 2531 /** 2532 * DMUB command for DPIA tunnel control. 2533 */ 2534 struct dmub_rb_cmd_dig1_dpia_control { 2535 struct dmub_cmd_header header; 2536 struct dmub_cmd_dig_dpia_control_data dpia_control; 2537 }; 2538 2539 /** 2540 * SET_CONFIG Command Payload (deprecated) 2541 */ 2542 struct set_config_cmd_payload { 2543 uint8_t msg_type; /* set config message type */ 2544 uint8_t msg_data; /* set config message data */ 2545 }; 2546 2547 /** 2548 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2549 */ 2550 struct dmub_cmd_set_config_control_data { 2551 struct set_config_cmd_payload cmd_pkt; 2552 uint8_t instance; /* DPIA instance */ 2553 uint8_t immed_status; /* Immediate status returned in case of error */ 2554 }; 2555 2556 /** 2557 * SET_CONFIG Request Command Payload 2558 */ 2559 struct set_config_request_cmd_payload { 2560 uint8_t instance; /* DPIA instance */ 2561 uint8_t immed_status; /* Immediate status returned in case of error */ 2562 uint8_t msg_type; /* set config message type */ 2563 uint8_t reserved; 2564 uint32_t msg_data; /* set config message data */ 2565 }; 2566 2567 /** 2568 * DMUB command structure for SET_CONFIG command. 2569 */ 2570 struct dmub_rb_cmd_set_config_access { 2571 struct dmub_cmd_header header; /* header */ 2572 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2573 }; 2574 2575 /** 2576 * DMUB command structure for SET_CONFIG request command. 2577 */ 2578 struct dmub_rb_cmd_set_config_request { 2579 struct dmub_cmd_header header; /* header */ 2580 struct set_config_request_cmd_payload payload; /* set config request payload */ 2581 }; 2582 2583 /** 2584 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2585 */ 2586 struct dmub_cmd_mst_alloc_slots_control_data { 2587 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2588 uint8_t instance; /* DPIA instance */ 2589 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2590 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2591 }; 2592 2593 /** 2594 * DMUB command structure for SET_ command. 2595 */ 2596 struct dmub_rb_cmd_set_mst_alloc_slots { 2597 struct dmub_cmd_header header; /* header */ 2598 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2599 }; 2600 2601 /** 2602 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2603 */ 2604 struct dmub_cmd_tps_notification_data { 2605 uint8_t instance; /* DPIA instance */ 2606 uint8_t tps; /* requested training pattern */ 2607 uint8_t reserved1; 2608 uint8_t reserved2; 2609 }; 2610 2611 /** 2612 * DMUB command structure for SET_TPS_NOTIFICATION command. 2613 */ 2614 struct dmub_rb_cmd_set_tps_notification { 2615 struct dmub_cmd_header header; /* header */ 2616 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2617 }; 2618 2619 /** 2620 * DMUB command structure for DPIA HPD int enable control. 2621 */ 2622 struct dmub_rb_cmd_dpia_hpd_int_enable { 2623 struct dmub_cmd_header header; /* header */ 2624 uint32_t enable; /* dpia hpd interrupt enable */ 2625 }; 2626 2627 /** 2628 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2629 */ 2630 struct dmub_rb_cmd_dpphy_init { 2631 struct dmub_cmd_header header; /**< header */ 2632 uint8_t reserved[60]; /**< reserved bits */ 2633 }; 2634 2635 /** 2636 * enum dp_aux_request_action - DP AUX request command listing. 2637 * 2638 * 4 AUX request command bits are shifted to high nibble. 2639 */ 2640 enum dp_aux_request_action { 2641 /** I2C-over-AUX write request */ 2642 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2643 /** I2C-over-AUX read request */ 2644 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2645 /** I2C-over-AUX write status request */ 2646 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2647 /** I2C-over-AUX write request with MOT=1 */ 2648 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2649 /** I2C-over-AUX read request with MOT=1 */ 2650 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2651 /** I2C-over-AUX write status request with MOT=1 */ 2652 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2653 /** Native AUX write request */ 2654 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2655 /** Native AUX read request */ 2656 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2657 }; 2658 2659 /** 2660 * enum aux_return_code_type - DP AUX process return code listing. 2661 */ 2662 enum aux_return_code_type { 2663 /** AUX process succeeded */ 2664 AUX_RET_SUCCESS = 0, 2665 /** AUX process failed with unknown reason */ 2666 AUX_RET_ERROR_UNKNOWN, 2667 /** AUX process completed with invalid reply */ 2668 AUX_RET_ERROR_INVALID_REPLY, 2669 /** AUX process timed out */ 2670 AUX_RET_ERROR_TIMEOUT, 2671 /** HPD was low during AUX process */ 2672 AUX_RET_ERROR_HPD_DISCON, 2673 /** Failed to acquire AUX engine */ 2674 AUX_RET_ERROR_ENGINE_ACQUIRE, 2675 /** AUX request not supported */ 2676 AUX_RET_ERROR_INVALID_OPERATION, 2677 /** AUX process not available */ 2678 AUX_RET_ERROR_PROTOCOL_ERROR, 2679 }; 2680 2681 /** 2682 * enum aux_channel_type - DP AUX channel type listing. 2683 */ 2684 enum aux_channel_type { 2685 /** AUX thru Legacy DP AUX */ 2686 AUX_CHANNEL_LEGACY_DDC, 2687 /** AUX thru DPIA DP tunneling */ 2688 AUX_CHANNEL_DPIA 2689 }; 2690 2691 /** 2692 * struct aux_transaction_parameters - DP AUX request transaction data 2693 */ 2694 struct aux_transaction_parameters { 2695 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2696 uint8_t action; /**< enum dp_aux_request_action */ 2697 uint8_t length; /**< DP AUX request data length */ 2698 uint8_t reserved; /**< For future use */ 2699 uint32_t address; /**< DP AUX address */ 2700 uint8_t data[16]; /**< DP AUX write data */ 2701 }; 2702 2703 /** 2704 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2705 */ 2706 struct dmub_cmd_dp_aux_control_data { 2707 uint8_t instance; /**< AUX instance or DPIA instance */ 2708 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2709 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2710 uint8_t reserved0; /**< For future use */ 2711 uint16_t timeout; /**< timeout time in us */ 2712 uint16_t reserved1; /**< For future use */ 2713 enum aux_channel_type type; /**< enum aux_channel_type */ 2714 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2715 }; 2716 2717 /** 2718 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2719 */ 2720 struct dmub_rb_cmd_dp_aux_access { 2721 /** 2722 * Command header. 2723 */ 2724 struct dmub_cmd_header header; 2725 /** 2726 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2727 */ 2728 struct dmub_cmd_dp_aux_control_data aux_control; 2729 }; 2730 2731 /** 2732 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2733 */ 2734 struct dmub_rb_cmd_outbox1_enable { 2735 /** 2736 * Command header. 2737 */ 2738 struct dmub_cmd_header header; 2739 /** 2740 * enable: 0x0 -> disable outbox1 notification (default value) 2741 * 0x1 -> enable outbox1 notification 2742 */ 2743 uint32_t enable; 2744 }; 2745 2746 /* DP AUX Reply command - OutBox Cmd */ 2747 /** 2748 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2749 */ 2750 struct aux_reply_data { 2751 /** 2752 * Aux cmd 2753 */ 2754 uint8_t command; 2755 /** 2756 * Aux reply data length (max: 16 bytes) 2757 */ 2758 uint8_t length; 2759 /** 2760 * Alignment only 2761 */ 2762 uint8_t pad[2]; 2763 /** 2764 * Aux reply data 2765 */ 2766 uint8_t data[16]; 2767 }; 2768 2769 /** 2770 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2771 */ 2772 struct aux_reply_control_data { 2773 /** 2774 * Reserved for future use 2775 */ 2776 uint32_t handle; 2777 /** 2778 * Aux Instance 2779 */ 2780 uint8_t instance; 2781 /** 2782 * Aux transaction result: definition in enum aux_return_code_type 2783 */ 2784 uint8_t result; 2785 /** 2786 * Alignment only 2787 */ 2788 uint16_t pad; 2789 }; 2790 2791 /** 2792 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2793 */ 2794 struct dmub_rb_cmd_dp_aux_reply { 2795 /** 2796 * Command header. 2797 */ 2798 struct dmub_cmd_header header; 2799 /** 2800 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2801 */ 2802 struct aux_reply_control_data control; 2803 /** 2804 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2805 */ 2806 struct aux_reply_data reply_data; 2807 }; 2808 2809 /* DP HPD Notify command - OutBox Cmd */ 2810 /** 2811 * DP HPD Type 2812 */ 2813 enum dp_hpd_type { 2814 /** 2815 * Normal DP HPD 2816 */ 2817 DP_HPD = 0, 2818 /** 2819 * DP HPD short pulse 2820 */ 2821 DP_IRQ = 1, 2822 /** 2823 * Failure to acquire DP HPD state 2824 */ 2825 DP_NONE_HPD = 2 2826 }; 2827 2828 /** 2829 * DP HPD Status 2830 */ 2831 enum dp_hpd_status { 2832 /** 2833 * DP_HPD status low 2834 */ 2835 DP_HPD_UNPLUG = 0, 2836 /** 2837 * DP_HPD status high 2838 */ 2839 DP_HPD_PLUG 2840 }; 2841 2842 /** 2843 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2844 */ 2845 struct dp_hpd_data { 2846 /** 2847 * DP HPD instance 2848 */ 2849 uint8_t instance; 2850 /** 2851 * HPD type 2852 */ 2853 uint8_t hpd_type; 2854 /** 2855 * HPD status: only for type: DP_HPD to indicate status 2856 */ 2857 uint8_t hpd_status; 2858 /** 2859 * Alignment only 2860 */ 2861 uint8_t pad; 2862 }; 2863 2864 /** 2865 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2866 */ 2867 struct dmub_rb_cmd_dp_hpd_notify { 2868 /** 2869 * Command header. 2870 */ 2871 struct dmub_cmd_header header; 2872 /** 2873 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2874 */ 2875 struct dp_hpd_data hpd_data; 2876 }; 2877 2878 /** 2879 * Definition of a SET_CONFIG reply from DPOA. 2880 */ 2881 enum set_config_status { 2882 SET_CONFIG_PENDING = 0, 2883 SET_CONFIG_ACK_RECEIVED, 2884 SET_CONFIG_RX_TIMEOUT, 2885 SET_CONFIG_UNKNOWN_ERROR, 2886 }; 2887 2888 /** 2889 * Definition of a set_config reply 2890 */ 2891 struct set_config_reply_control_data { 2892 uint8_t instance; /* DPIA Instance */ 2893 uint8_t status; /* Set Config reply */ 2894 uint16_t pad; /* Alignment */ 2895 }; 2896 2897 /** 2898 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2899 */ 2900 struct dmub_rb_cmd_dp_set_config_reply { 2901 struct dmub_cmd_header header; 2902 struct set_config_reply_control_data set_config_reply_control; 2903 }; 2904 2905 /** 2906 * Definition of a DPIA notification header 2907 */ 2908 struct dpia_notification_header { 2909 uint8_t instance; /**< DPIA Instance */ 2910 uint8_t reserved[3]; 2911 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2912 }; 2913 2914 /** 2915 * Definition of the common data struct of DPIA notification 2916 */ 2917 struct dpia_notification_common { 2918 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2919 - sizeof(struct dpia_notification_header)]; 2920 }; 2921 2922 /** 2923 * Definition of a DPIA notification data 2924 */ 2925 struct dpia_bw_allocation_notify_data { 2926 union { 2927 struct { 2928 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2929 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2930 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2931 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2932 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2933 uint16_t reserved: 11; /**< Reserved */ 2934 } bits; 2935 2936 uint16_t flags; 2937 }; 2938 2939 uint8_t cm_id; /**< CM ID */ 2940 uint8_t group_id; /**< Group ID */ 2941 uint8_t granularity; /**< BW Allocation Granularity */ 2942 uint8_t estimated_bw; /**< Estimated_BW */ 2943 uint8_t allocated_bw; /**< Allocated_BW */ 2944 uint8_t reserved; 2945 }; 2946 2947 /** 2948 * union dpia_notify_data_type - DPIA Notification in Outbox command 2949 */ 2950 union dpia_notification_data { 2951 /** 2952 * DPIA Notification for common data struct 2953 */ 2954 struct dpia_notification_common common_data; 2955 2956 /** 2957 * DPIA Notification for DP BW Allocation support 2958 */ 2959 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2960 }; 2961 2962 /** 2963 * Definition of a DPIA notification payload 2964 */ 2965 struct dpia_notification_payload { 2966 struct dpia_notification_header header; 2967 union dpia_notification_data data; /**< DPIA notification payload data */ 2968 }; 2969 2970 /** 2971 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2972 */ 2973 struct dmub_rb_cmd_dpia_notification { 2974 struct dmub_cmd_header header; /**< DPIA notification header */ 2975 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2976 }; 2977 2978 /** 2979 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2980 */ 2981 struct dmub_cmd_hpd_state_query_data { 2982 uint8_t instance; /**< HPD instance or DPIA instance */ 2983 uint8_t result; /**< For returning HPD state */ 2984 uint16_t pad; /** < Alignment */ 2985 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2986 enum aux_return_code_type status; /**< for returning the status of command */ 2987 }; 2988 2989 /** 2990 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2991 */ 2992 struct dmub_rb_cmd_query_hpd_state { 2993 /** 2994 * Command header. 2995 */ 2996 struct dmub_cmd_header header; 2997 /** 2998 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2999 */ 3000 struct dmub_cmd_hpd_state_query_data data; 3001 }; 3002 3003 /** 3004 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3005 */ 3006 struct dmub_rb_cmd_hpd_sense_notify_data { 3007 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3008 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3009 }; 3010 3011 /** 3012 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3013 */ 3014 struct dmub_rb_cmd_hpd_sense_notify { 3015 struct dmub_cmd_header header; /**< header */ 3016 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3017 }; 3018 3019 /* 3020 * Command IDs should be treated as stable ABI. 3021 * Do not reuse or modify IDs. 3022 */ 3023 3024 /** 3025 * PSR command sub-types. 3026 */ 3027 enum dmub_cmd_psr_type { 3028 /** 3029 * Set PSR version support. 3030 */ 3031 DMUB_CMD__PSR_SET_VERSION = 0, 3032 /** 3033 * Copy driver-calculated parameters to PSR state. 3034 */ 3035 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3036 /** 3037 * Enable PSR. 3038 */ 3039 DMUB_CMD__PSR_ENABLE = 2, 3040 3041 /** 3042 * Disable PSR. 3043 */ 3044 DMUB_CMD__PSR_DISABLE = 3, 3045 3046 /** 3047 * Set PSR level. 3048 * PSR level is a 16-bit value dicated by driver that 3049 * will enable/disable different functionality. 3050 */ 3051 DMUB_CMD__PSR_SET_LEVEL = 4, 3052 3053 /** 3054 * Forces PSR enabled until an explicit PSR disable call. 3055 */ 3056 DMUB_CMD__PSR_FORCE_STATIC = 5, 3057 /** 3058 * Set vtotal in psr active for FreeSync PSR. 3059 */ 3060 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3061 /** 3062 * Set PSR power option 3063 */ 3064 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3065 }; 3066 3067 /** 3068 * Different PSR residency modes. 3069 * Different modes change the definition of PSR residency. 3070 */ 3071 enum psr_residency_mode { 3072 PSR_RESIDENCY_MODE_PHY = 0, 3073 PSR_RESIDENCY_MODE_ALPM, 3074 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3075 /* Do not add below. */ 3076 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3077 }; 3078 3079 enum dmub_cmd_fams_type { 3080 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3081 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3082 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3083 /** 3084 * For SubVP set manual trigger in FW because it 3085 * triggers DRR_UPDATE_PENDING which SubVP relies 3086 * on (for any SubVP cases that use a DRR display) 3087 */ 3088 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3089 DMUB_CMD__FAMS2_CONFIG = 4, 3090 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3091 DMUB_CMD__FAMS2_FLIP = 6, 3092 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3093 }; 3094 3095 /** 3096 * PSR versions. 3097 */ 3098 enum psr_version { 3099 /** 3100 * PSR version 1. 3101 */ 3102 PSR_VERSION_1 = 0, 3103 /** 3104 * Freesync PSR SU. 3105 */ 3106 PSR_VERSION_SU_1 = 1, 3107 /** 3108 * PSR not supported. 3109 */ 3110 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3111 }; 3112 3113 /** 3114 * PHY Link rate for DP. 3115 */ 3116 enum phy_link_rate { 3117 /** 3118 * not supported. 3119 */ 3120 PHY_RATE_UNKNOWN = 0, 3121 /** 3122 * Rate_1 (RBR) - 1.62 Gbps/Lane 3123 */ 3124 PHY_RATE_162 = 1, 3125 /** 3126 * Rate_2 - 2.16 Gbps/Lane 3127 */ 3128 PHY_RATE_216 = 2, 3129 /** 3130 * Rate_3 - 2.43 Gbps/Lane 3131 */ 3132 PHY_RATE_243 = 3, 3133 /** 3134 * Rate_4 (HBR) - 2.70 Gbps/Lane 3135 */ 3136 PHY_RATE_270 = 4, 3137 /** 3138 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3139 */ 3140 PHY_RATE_324 = 5, 3141 /** 3142 * Rate_6 - 4.32 Gbps/Lane 3143 */ 3144 PHY_RATE_432 = 6, 3145 /** 3146 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3147 */ 3148 PHY_RATE_540 = 7, 3149 /** 3150 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3151 */ 3152 PHY_RATE_810 = 8, 3153 /** 3154 * UHBR10 - 10.0 Gbps/Lane 3155 */ 3156 PHY_RATE_1000 = 9, 3157 /** 3158 * UHBR13.5 - 13.5 Gbps/Lane 3159 */ 3160 PHY_RATE_1350 = 10, 3161 /** 3162 * UHBR10 - 20.0 Gbps/Lane 3163 */ 3164 PHY_RATE_2000 = 11, 3165 3166 PHY_RATE_675 = 12, 3167 /** 3168 * Rate 12 - 6.75 Gbps/Lane 3169 */ 3170 }; 3171 3172 /** 3173 * enum dmub_phy_fsm_state - PHY FSM states. 3174 * PHY FSM state to transit to during PSR enable/disable. 3175 */ 3176 enum dmub_phy_fsm_state { 3177 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3178 DMUB_PHY_FSM_RESET, 3179 DMUB_PHY_FSM_RESET_RELEASED, 3180 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3181 DMUB_PHY_FSM_INITIALIZED, 3182 DMUB_PHY_FSM_CALIBRATED, 3183 DMUB_PHY_FSM_CALIBRATED_LP, 3184 DMUB_PHY_FSM_CALIBRATED_PG, 3185 DMUB_PHY_FSM_POWER_DOWN, 3186 DMUB_PHY_FSM_PLL_EN, 3187 DMUB_PHY_FSM_TX_EN, 3188 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3189 DMUB_PHY_FSM_FAST_LP, 3190 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3191 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3192 DMUB_PHY_FSM_P2_PLL_OFF, 3193 DMUB_PHY_FSM_P2_PLL_ON, 3194 }; 3195 3196 /** 3197 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3198 */ 3199 struct dmub_cmd_psr_copy_settings_data { 3200 /** 3201 * Flags that can be set by driver to change some PSR behaviour. 3202 */ 3203 union dmub_psr_debug_flags debug; 3204 /** 3205 * 16-bit value dicated by driver that will enable/disable different functionality. 3206 */ 3207 uint16_t psr_level; 3208 /** 3209 * DPP HW instance. 3210 */ 3211 uint8_t dpp_inst; 3212 /** 3213 * MPCC HW instance. 3214 * Not used in dmub fw, 3215 * dmub fw will get active opp by reading odm registers. 3216 */ 3217 uint8_t mpcc_inst; 3218 /** 3219 * OPP HW instance. 3220 * Not used in dmub fw, 3221 * dmub fw will get active opp by reading odm registers. 3222 */ 3223 uint8_t opp_inst; 3224 /** 3225 * OTG HW instance. 3226 */ 3227 uint8_t otg_inst; 3228 /** 3229 * DIG FE HW instance. 3230 */ 3231 uint8_t digfe_inst; 3232 /** 3233 * DIG BE HW instance. 3234 */ 3235 uint8_t digbe_inst; 3236 /** 3237 * DP PHY HW instance. 3238 */ 3239 uint8_t dpphy_inst; 3240 /** 3241 * AUX HW instance. 3242 */ 3243 uint8_t aux_inst; 3244 /** 3245 * Determines if SMU optimzations are enabled/disabled. 3246 */ 3247 uint8_t smu_optimizations_en; 3248 /** 3249 * Unused. 3250 * TODO: Remove. 3251 */ 3252 uint8_t frame_delay; 3253 /** 3254 * If RFB setup time is greater than the total VBLANK time, 3255 * it is not possible for the sink to capture the video frame 3256 * in the same frame the SDP is sent. In this case, 3257 * the frame capture indication bit should be set and an extra 3258 * static frame should be transmitted to the sink. 3259 */ 3260 uint8_t frame_cap_ind; 3261 /** 3262 * Granularity of Y offset supported by sink. 3263 */ 3264 uint8_t su_y_granularity; 3265 /** 3266 * Indicates whether sink should start capturing 3267 * immediately following active scan line, 3268 * or starting with the 2nd active scan line. 3269 */ 3270 uint8_t line_capture_indication; 3271 /** 3272 * Multi-display optimizations are implemented on certain ASICs. 3273 */ 3274 uint8_t multi_disp_optimizations_en; 3275 /** 3276 * The last possible line SDP may be transmitted without violating 3277 * the RFB setup time or entering the active video frame. 3278 */ 3279 uint16_t init_sdp_deadline; 3280 /** 3281 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3282 */ 3283 uint8_t rate_control_caps ; 3284 /* 3285 * Force PSRSU always doing full frame update 3286 */ 3287 uint8_t force_ffu_mode; 3288 /** 3289 * Length of each horizontal line in us. 3290 */ 3291 uint32_t line_time_in_us; 3292 /** 3293 * FEC enable status in driver 3294 */ 3295 uint8_t fec_enable_status; 3296 /** 3297 * FEC re-enable delay when PSR exit. 3298 * unit is 100us, range form 0~255(0xFF). 3299 */ 3300 uint8_t fec_enable_delay_in100us; 3301 /** 3302 * PSR control version. 3303 */ 3304 uint8_t cmd_version; 3305 /** 3306 * Panel Instance. 3307 * Panel instance to identify which psr_state to use 3308 * Currently the support is only for 0 or 1 3309 */ 3310 uint8_t panel_inst; 3311 /* 3312 * DSC enable status in driver 3313 */ 3314 uint8_t dsc_enable_status; 3315 /* 3316 * Use FSM state for PSR power up/down 3317 */ 3318 uint8_t use_phy_fsm; 3319 /** 3320 * frame delay for frame re-lock 3321 */ 3322 uint8_t relock_delay_frame_cnt; 3323 /** 3324 * esd recovery indicate. 3325 */ 3326 uint8_t esd_recovery; 3327 /** 3328 * DSC Slice height. 3329 */ 3330 uint16_t dsc_slice_height; 3331 /** 3332 * Some panels request main link off before xth vertical line 3333 */ 3334 uint16_t poweroff_before_vertical_line; 3335 /** 3336 * Some panels cannot handle idle pattern during PSR entry. 3337 * To power down phy before disable stream to avoid sending 3338 * idle pattern. 3339 */ 3340 uint8_t power_down_phy_before_disable_stream; 3341 }; 3342 3343 /** 3344 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3345 */ 3346 struct dmub_rb_cmd_psr_copy_settings { 3347 /** 3348 * Command header. 3349 */ 3350 struct dmub_cmd_header header; 3351 /** 3352 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3353 */ 3354 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3355 }; 3356 3357 /** 3358 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3359 */ 3360 struct dmub_cmd_psr_set_level_data { 3361 /** 3362 * 16-bit value dicated by driver that will enable/disable different functionality. 3363 */ 3364 uint16_t psr_level; 3365 /** 3366 * PSR control version. 3367 */ 3368 uint8_t cmd_version; 3369 /** 3370 * Panel Instance. 3371 * Panel instance to identify which psr_state to use 3372 * Currently the support is only for 0 or 1 3373 */ 3374 uint8_t panel_inst; 3375 }; 3376 3377 /** 3378 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3379 */ 3380 struct dmub_rb_cmd_psr_set_level { 3381 /** 3382 * Command header. 3383 */ 3384 struct dmub_cmd_header header; 3385 /** 3386 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3387 */ 3388 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3389 }; 3390 3391 struct dmub_rb_cmd_psr_enable_data { 3392 /** 3393 * PSR control version. 3394 */ 3395 uint8_t cmd_version; 3396 /** 3397 * Panel Instance. 3398 * Panel instance to identify which psr_state to use 3399 * Currently the support is only for 0 or 1 3400 */ 3401 uint8_t panel_inst; 3402 /** 3403 * Phy state to enter. 3404 * Values to use are defined in dmub_phy_fsm_state 3405 */ 3406 uint8_t phy_fsm_state; 3407 /** 3408 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3409 * Set this using enum phy_link_rate. 3410 * This does not support HDMI/DP2 for now. 3411 */ 3412 uint8_t phy_rate; 3413 }; 3414 3415 /** 3416 * Definition of a DMUB_CMD__PSR_ENABLE command. 3417 * PSR enable/disable is controlled using the sub_type. 3418 */ 3419 struct dmub_rb_cmd_psr_enable { 3420 /** 3421 * Command header. 3422 */ 3423 struct dmub_cmd_header header; 3424 3425 struct dmub_rb_cmd_psr_enable_data data; 3426 }; 3427 3428 /** 3429 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3430 */ 3431 struct dmub_cmd_psr_set_version_data { 3432 /** 3433 * PSR version that FW should implement. 3434 */ 3435 enum psr_version version; 3436 /** 3437 * PSR control version. 3438 */ 3439 uint8_t cmd_version; 3440 /** 3441 * Panel Instance. 3442 * Panel instance to identify which psr_state to use 3443 * Currently the support is only for 0 or 1 3444 */ 3445 uint8_t panel_inst; 3446 /** 3447 * Explicit padding to 4 byte boundary. 3448 */ 3449 uint8_t pad[2]; 3450 }; 3451 3452 /** 3453 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3454 */ 3455 struct dmub_rb_cmd_psr_set_version { 3456 /** 3457 * Command header. 3458 */ 3459 struct dmub_cmd_header header; 3460 /** 3461 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3462 */ 3463 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3464 }; 3465 3466 struct dmub_cmd_psr_force_static_data { 3467 /** 3468 * PSR control version. 3469 */ 3470 uint8_t cmd_version; 3471 /** 3472 * Panel Instance. 3473 * Panel instance to identify which psr_state to use 3474 * Currently the support is only for 0 or 1 3475 */ 3476 uint8_t panel_inst; 3477 /** 3478 * Explicit padding to 4 byte boundary. 3479 */ 3480 uint8_t pad[2]; 3481 }; 3482 3483 /** 3484 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3485 */ 3486 struct dmub_rb_cmd_psr_force_static { 3487 /** 3488 * Command header. 3489 */ 3490 struct dmub_cmd_header header; 3491 /** 3492 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3493 */ 3494 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3495 }; 3496 3497 /** 3498 * PSR SU debug flags. 3499 */ 3500 union dmub_psr_su_debug_flags { 3501 /** 3502 * PSR SU debug flags. 3503 */ 3504 struct { 3505 /** 3506 * Update dirty rect in SW only. 3507 */ 3508 uint8_t update_dirty_rect_only : 1; 3509 /** 3510 * Reset the cursor/plane state before processing the call. 3511 */ 3512 uint8_t reset_state : 1; 3513 } bitfields; 3514 3515 /** 3516 * Union for debug flags. 3517 */ 3518 uint32_t u32All; 3519 }; 3520 3521 /** 3522 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3523 * This triggers a selective update for PSR SU. 3524 */ 3525 struct dmub_cmd_update_dirty_rect_data { 3526 /** 3527 * Dirty rects from OS. 3528 */ 3529 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3530 /** 3531 * PSR SU debug flags. 3532 */ 3533 union dmub_psr_su_debug_flags debug_flags; 3534 /** 3535 * OTG HW instance. 3536 */ 3537 uint8_t pipe_idx; 3538 /** 3539 * Number of dirty rects. 3540 */ 3541 uint8_t dirty_rect_count; 3542 /** 3543 * PSR control version. 3544 */ 3545 uint8_t cmd_version; 3546 /** 3547 * Panel Instance. 3548 * Panel instance to identify which psr_state to use 3549 * Currently the support is only for 0 or 1 3550 */ 3551 uint8_t panel_inst; 3552 }; 3553 3554 /** 3555 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3556 */ 3557 struct dmub_rb_cmd_update_dirty_rect { 3558 /** 3559 * Command header. 3560 */ 3561 struct dmub_cmd_header header; 3562 /** 3563 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3564 */ 3565 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3566 }; 3567 3568 /** 3569 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3570 */ 3571 union dmub_reg_cursor_control_cfg { 3572 struct { 3573 uint32_t cur_enable: 1; 3574 uint32_t reser0: 3; 3575 uint32_t cur_2x_magnify: 1; 3576 uint32_t reser1: 3; 3577 uint32_t mode: 3; 3578 uint32_t reser2: 5; 3579 uint32_t pitch: 2; 3580 uint32_t reser3: 6; 3581 uint32_t line_per_chunk: 5; 3582 uint32_t reser4: 3; 3583 } bits; 3584 uint32_t raw; 3585 }; 3586 struct dmub_cursor_position_cache_hubp { 3587 union dmub_reg_cursor_control_cfg cur_ctl; 3588 union dmub_reg_position_cfg { 3589 struct { 3590 uint32_t cur_x_pos: 16; 3591 uint32_t cur_y_pos: 16; 3592 } bits; 3593 uint32_t raw; 3594 } position; 3595 union dmub_reg_hot_spot_cfg { 3596 struct { 3597 uint32_t hot_x: 16; 3598 uint32_t hot_y: 16; 3599 } bits; 3600 uint32_t raw; 3601 } hot_spot; 3602 union dmub_reg_dst_offset_cfg { 3603 struct { 3604 uint32_t dst_x_offset: 13; 3605 uint32_t reserved: 19; 3606 } bits; 3607 uint32_t raw; 3608 } dst_offset; 3609 }; 3610 3611 union dmub_reg_cur0_control_cfg { 3612 struct { 3613 uint32_t cur0_enable: 1; 3614 uint32_t expansion_mode: 1; 3615 uint32_t reser0: 1; 3616 uint32_t cur0_rom_en: 1; 3617 uint32_t mode: 3; 3618 uint32_t reserved: 25; 3619 } bits; 3620 uint32_t raw; 3621 }; 3622 struct dmub_cursor_position_cache_dpp { 3623 union dmub_reg_cur0_control_cfg cur0_ctl; 3624 }; 3625 struct dmub_cursor_position_cfg { 3626 struct dmub_cursor_position_cache_hubp pHubp; 3627 struct dmub_cursor_position_cache_dpp pDpp; 3628 uint8_t pipe_idx; 3629 /* 3630 * Padding is required. To be 4 Bytes Aligned. 3631 */ 3632 uint8_t padding[3]; 3633 }; 3634 3635 struct dmub_cursor_attribute_cache_hubp { 3636 uint32_t SURFACE_ADDR_HIGH; 3637 uint32_t SURFACE_ADDR; 3638 union dmub_reg_cursor_control_cfg cur_ctl; 3639 union dmub_reg_cursor_size_cfg { 3640 struct { 3641 uint32_t width: 16; 3642 uint32_t height: 16; 3643 } bits; 3644 uint32_t raw; 3645 } size; 3646 union dmub_reg_cursor_settings_cfg { 3647 struct { 3648 uint32_t dst_y_offset: 8; 3649 uint32_t chunk_hdl_adjust: 2; 3650 uint32_t reserved: 22; 3651 } bits; 3652 uint32_t raw; 3653 } settings; 3654 }; 3655 struct dmub_cursor_attribute_cache_dpp { 3656 union dmub_reg_cur0_control_cfg cur0_ctl; 3657 }; 3658 struct dmub_cursor_attributes_cfg { 3659 struct dmub_cursor_attribute_cache_hubp aHubp; 3660 struct dmub_cursor_attribute_cache_dpp aDpp; 3661 }; 3662 3663 struct dmub_cmd_update_cursor_payload0 { 3664 /** 3665 * Cursor dirty rects. 3666 */ 3667 struct dmub_rect cursor_rect; 3668 /** 3669 * PSR SU debug flags. 3670 */ 3671 union dmub_psr_su_debug_flags debug_flags; 3672 /** 3673 * Cursor enable/disable. 3674 */ 3675 uint8_t enable; 3676 /** 3677 * OTG HW instance. 3678 */ 3679 uint8_t pipe_idx; 3680 /** 3681 * PSR control version. 3682 */ 3683 uint8_t cmd_version; 3684 /** 3685 * Panel Instance. 3686 * Panel instance to identify which psr_state to use 3687 * Currently the support is only for 0 or 1 3688 */ 3689 uint8_t panel_inst; 3690 /** 3691 * Cursor Position Register. 3692 * Registers contains Hubp & Dpp modules 3693 */ 3694 struct dmub_cursor_position_cfg position_cfg; 3695 }; 3696 3697 struct dmub_cmd_update_cursor_payload1 { 3698 struct dmub_cursor_attributes_cfg attribute_cfg; 3699 }; 3700 3701 union dmub_cmd_update_cursor_info_data { 3702 struct dmub_cmd_update_cursor_payload0 payload0; 3703 struct dmub_cmd_update_cursor_payload1 payload1; 3704 }; 3705 /** 3706 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3707 */ 3708 struct dmub_rb_cmd_update_cursor_info { 3709 /** 3710 * Command header. 3711 */ 3712 struct dmub_cmd_header header; 3713 /** 3714 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3715 */ 3716 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3717 }; 3718 3719 /** 3720 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3721 */ 3722 struct dmub_cmd_psr_set_vtotal_data { 3723 /** 3724 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3725 */ 3726 uint16_t psr_vtotal_idle; 3727 /** 3728 * PSR control version. 3729 */ 3730 uint8_t cmd_version; 3731 /** 3732 * Panel Instance. 3733 * Panel instance to identify which psr_state to use 3734 * Currently the support is only for 0 or 1 3735 */ 3736 uint8_t panel_inst; 3737 /* 3738 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3739 */ 3740 uint16_t psr_vtotal_su; 3741 /** 3742 * Explicit padding to 4 byte boundary. 3743 */ 3744 uint8_t pad2[2]; 3745 }; 3746 3747 /** 3748 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3749 */ 3750 struct dmub_rb_cmd_psr_set_vtotal { 3751 /** 3752 * Command header. 3753 */ 3754 struct dmub_cmd_header header; 3755 /** 3756 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3757 */ 3758 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3759 }; 3760 3761 /** 3762 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3763 */ 3764 struct dmub_cmd_psr_set_power_opt_data { 3765 /** 3766 * PSR control version. 3767 */ 3768 uint8_t cmd_version; 3769 /** 3770 * Panel Instance. 3771 * Panel instance to identify which psr_state to use 3772 * Currently the support is only for 0 or 1 3773 */ 3774 uint8_t panel_inst; 3775 /** 3776 * Explicit padding to 4 byte boundary. 3777 */ 3778 uint8_t pad[2]; 3779 /** 3780 * PSR power option 3781 */ 3782 uint32_t power_opt; 3783 }; 3784 3785 /** 3786 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3787 */ 3788 struct dmub_rb_cmd_psr_set_power_opt { 3789 /** 3790 * Command header. 3791 */ 3792 struct dmub_cmd_header header; 3793 /** 3794 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3795 */ 3796 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3797 }; 3798 3799 enum dmub_alpm_mode { 3800 ALPM_AUXWAKE = 0, 3801 ALPM_AUXLESS = 1, 3802 ALPM_UNSUPPORTED = 2, 3803 }; 3804 3805 /** 3806 * Definition of Replay Residency GPINT command. 3807 * Bit[0] - Residency mode for Revision 0 3808 * Bit[1] - Enable/Disable state 3809 * Bit[2-3] - Revision number 3810 * Bit[4-7] - Residency mode for Revision 1 3811 * Bit[8] - Panel instance 3812 * Bit[9-15] - Reserved 3813 */ 3814 3815 enum pr_residency_mode { 3816 PR_RESIDENCY_MODE_PHY = 0x0, 3817 PR_RESIDENCY_MODE_ALPM, 3818 PR_RESIDENCY_MODE_IPS2, 3819 PR_RESIDENCY_MODE_FRAME_CNT, 3820 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3821 }; 3822 3823 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3824 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3825 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3826 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3827 3828 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3829 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3830 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3831 3832 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3833 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3834 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3835 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3836 3837 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3838 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3839 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3840 3841 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3842 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3843 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3844 3845 /** 3846 * Definition of a replay_state. 3847 */ 3848 enum replay_state { 3849 REPLAY_STATE_0 = 0x0, 3850 REPLAY_STATE_1 = 0x10, 3851 REPLAY_STATE_1A = 0x11, 3852 REPLAY_STATE_2 = 0x20, 3853 REPLAY_STATE_2A = 0x21, 3854 REPLAY_STATE_3 = 0x30, 3855 REPLAY_STATE_3INIT = 0x31, 3856 REPLAY_STATE_4 = 0x40, 3857 REPLAY_STATE_4A = 0x41, 3858 REPLAY_STATE_4B = 0x42, 3859 REPLAY_STATE_4C = 0x43, 3860 REPLAY_STATE_4D = 0x44, 3861 REPLAY_STATE_4E = 0x45, 3862 REPLAY_STATE_4B_LOCKED = 0x4A, 3863 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3864 REPLAY_STATE_5 = 0x50, 3865 REPLAY_STATE_5A = 0x51, 3866 REPLAY_STATE_5B = 0x52, 3867 REPLAY_STATE_5A_LOCKED = 0x5A, 3868 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3869 REPLAY_STATE_6 = 0x60, 3870 REPLAY_STATE_6A = 0x61, 3871 REPLAY_STATE_6B = 0x62, 3872 REPLAY_STATE_INVALID = 0xFF, 3873 }; 3874 3875 /** 3876 * Replay command sub-types. 3877 */ 3878 enum dmub_cmd_replay_type { 3879 /** 3880 * Copy driver-calculated parameters to REPLAY state. 3881 */ 3882 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3883 /** 3884 * Enable REPLAY. 3885 */ 3886 DMUB_CMD__REPLAY_ENABLE = 1, 3887 /** 3888 * Set Replay power option. 3889 */ 3890 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3891 /** 3892 * Set coasting vtotal. 3893 */ 3894 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3895 /** 3896 * Set power opt and coasting vtotal. 3897 */ 3898 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3899 /** 3900 * Set disabled iiming sync. 3901 */ 3902 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3903 /** 3904 * Set Residency Frameupdate Timer. 3905 */ 3906 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3907 /** 3908 * Set pseudo vtotal 3909 */ 3910 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3911 /** 3912 * Set adaptive sync sdp enabled 3913 */ 3914 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3915 /** 3916 * Set Replay General command. 3917 */ 3918 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3919 }; 3920 3921 /** 3922 * Replay general command sub-types. 3923 */ 3924 enum dmub_cmd_replay_general_subtype { 3925 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3926 /** 3927 * TODO: For backward compatible, allow new command only. 3928 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3929 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3930 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3931 */ 3932 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3933 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3934 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 3935 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 3936 }; 3937 3938 struct dmub_alpm_auxless_data { 3939 uint16_t lfps_setup_ns; 3940 uint16_t lfps_period_ns; 3941 uint16_t lfps_silence_ns; 3942 uint16_t lfps_t1_t2_override_us; 3943 short lfps_t1_t2_offset_us; 3944 uint8_t lttpr_count; 3945 }; 3946 3947 /** 3948 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3949 */ 3950 struct dmub_cmd_replay_copy_settings_data { 3951 /** 3952 * Flags that can be set by driver to change some replay behaviour. 3953 */ 3954 union replay_debug_flags debug; 3955 3956 /** 3957 * @flags: Flags used to determine feature functionality. 3958 */ 3959 union replay_hw_flags flags; 3960 3961 /** 3962 * DPP HW instance. 3963 */ 3964 uint8_t dpp_inst; 3965 /** 3966 * OTG HW instance. 3967 */ 3968 uint8_t otg_inst; 3969 /** 3970 * DIG FE HW instance. 3971 */ 3972 uint8_t digfe_inst; 3973 /** 3974 * DIG BE HW instance. 3975 */ 3976 uint8_t digbe_inst; 3977 /** 3978 * AUX HW instance. 3979 */ 3980 uint8_t aux_inst; 3981 /** 3982 * Panel Instance. 3983 * Panel isntance to identify which psr_state to use 3984 * Currently the support is only for 0 or 1 3985 */ 3986 uint8_t panel_inst; 3987 /** 3988 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3989 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3990 */ 3991 uint8_t pixel_deviation_per_line; 3992 /** 3993 * @max_deviation_line: The max number of deviation line that can keep the timing 3994 * synchronized between the Source and Sink during Replay normal sleep mode. 3995 */ 3996 uint8_t max_deviation_line; 3997 /** 3998 * Length of each horizontal line in ns. 3999 */ 4000 uint32_t line_time_in_ns; 4001 /** 4002 * PHY instance. 4003 */ 4004 uint8_t dpphy_inst; 4005 /** 4006 * Determines if SMU optimzations are enabled/disabled. 4007 */ 4008 uint8_t smu_optimizations_en; 4009 /** 4010 * Determines if timing sync are enabled/disabled. 4011 */ 4012 uint8_t replay_timing_sync_supported; 4013 /* 4014 * Use FSM state for Replay power up/down 4015 */ 4016 uint8_t use_phy_fsm; 4017 /** 4018 * Use for AUX-less ALPM LFPS wake operation 4019 */ 4020 struct dmub_alpm_auxless_data auxless_alpm_data; 4021 }; 4022 4023 /** 4024 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4025 */ 4026 struct dmub_rb_cmd_replay_copy_settings { 4027 /** 4028 * Command header. 4029 */ 4030 struct dmub_cmd_header header; 4031 /** 4032 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4033 */ 4034 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4035 }; 4036 4037 /** 4038 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4039 */ 4040 enum replay_enable { 4041 /** 4042 * Disable REPLAY. 4043 */ 4044 REPLAY_DISABLE = 0, 4045 /** 4046 * Enable REPLAY. 4047 */ 4048 REPLAY_ENABLE = 1, 4049 }; 4050 4051 /** 4052 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4053 */ 4054 struct dmub_rb_cmd_replay_enable_data { 4055 /** 4056 * Replay enable or disable. 4057 */ 4058 uint8_t enable; 4059 /** 4060 * Panel Instance. 4061 * Panel isntance to identify which replay_state to use 4062 * Currently the support is only for 0 or 1 4063 */ 4064 uint8_t panel_inst; 4065 /** 4066 * Phy state to enter. 4067 * Values to use are defined in dmub_phy_fsm_state 4068 */ 4069 uint8_t phy_fsm_state; 4070 /** 4071 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4072 * Set this using enum phy_link_rate. 4073 * This does not support HDMI/DP2 for now. 4074 */ 4075 uint8_t phy_rate; 4076 }; 4077 4078 /** 4079 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4080 * Replay enable/disable is controlled using action in data. 4081 */ 4082 struct dmub_rb_cmd_replay_enable { 4083 /** 4084 * Command header. 4085 */ 4086 struct dmub_cmd_header header; 4087 4088 struct dmub_rb_cmd_replay_enable_data data; 4089 }; 4090 4091 /** 4092 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4093 */ 4094 struct dmub_cmd_replay_set_power_opt_data { 4095 /** 4096 * Panel Instance. 4097 * Panel isntance to identify which replay_state to use 4098 * Currently the support is only for 0 or 1 4099 */ 4100 uint8_t panel_inst; 4101 /** 4102 * Explicit padding to 4 byte boundary. 4103 */ 4104 uint8_t pad[3]; 4105 /** 4106 * REPLAY power option 4107 */ 4108 uint32_t power_opt; 4109 }; 4110 4111 /** 4112 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4113 */ 4114 struct dmub_cmd_replay_set_timing_sync_data { 4115 /** 4116 * Panel Instance. 4117 * Panel isntance to identify which replay_state to use 4118 * Currently the support is only for 0 or 1 4119 */ 4120 uint8_t panel_inst; 4121 /** 4122 * REPLAY set_timing_sync 4123 */ 4124 uint8_t timing_sync_supported; 4125 /** 4126 * Explicit padding to 4 byte boundary. 4127 */ 4128 uint8_t pad[2]; 4129 }; 4130 4131 /** 4132 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4133 */ 4134 struct dmub_cmd_replay_set_pseudo_vtotal { 4135 /** 4136 * Panel Instance. 4137 * Panel isntance to identify which replay_state to use 4138 * Currently the support is only for 0 or 1 4139 */ 4140 uint8_t panel_inst; 4141 /** 4142 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4143 */ 4144 uint16_t vtotal; 4145 /** 4146 * Explicit padding to 4 byte boundary. 4147 */ 4148 uint8_t pad; 4149 }; 4150 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4151 /** 4152 * Panel Instance. 4153 * Panel isntance to identify which replay_state to use 4154 * Currently the support is only for 0 or 1 4155 */ 4156 uint8_t panel_inst; 4157 /** 4158 * enabled: set adaptive sync sdp enabled 4159 */ 4160 uint8_t force_disabled; 4161 4162 uint8_t pad[2]; 4163 }; 4164 struct dmub_cmd_replay_set_general_cmd_data { 4165 /** 4166 * Panel Instance. 4167 * Panel isntance to identify which replay_state to use 4168 * Currently the support is only for 0 or 1 4169 */ 4170 uint8_t panel_inst; 4171 /** 4172 * subtype: replay general cmd sub type 4173 */ 4174 uint8_t subtype; 4175 4176 uint8_t pad[2]; 4177 /** 4178 * config data with param1 and param2 4179 */ 4180 uint32_t param1; 4181 4182 uint32_t param2; 4183 }; 4184 4185 /** 4186 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4187 */ 4188 struct dmub_rb_cmd_replay_set_power_opt { 4189 /** 4190 * Command header. 4191 */ 4192 struct dmub_cmd_header header; 4193 /** 4194 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4195 */ 4196 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4197 }; 4198 4199 /** 4200 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4201 */ 4202 struct dmub_cmd_replay_set_coasting_vtotal_data { 4203 /** 4204 * 16-bit value dicated by driver that indicates the coasting vtotal. 4205 */ 4206 uint16_t coasting_vtotal; 4207 /** 4208 * REPLAY control version. 4209 */ 4210 uint8_t cmd_version; 4211 /** 4212 * Panel Instance. 4213 * Panel isntance to identify which replay_state to use 4214 * Currently the support is only for 0 or 1 4215 */ 4216 uint8_t panel_inst; 4217 /** 4218 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4219 */ 4220 uint16_t coasting_vtotal_high; 4221 /** 4222 * Explicit padding to 4 byte boundary. 4223 */ 4224 uint8_t pad[2]; 4225 }; 4226 4227 /** 4228 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4229 */ 4230 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4231 /** 4232 * Command header. 4233 */ 4234 struct dmub_cmd_header header; 4235 /** 4236 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4237 */ 4238 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4239 }; 4240 4241 /** 4242 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4243 */ 4244 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4245 /** 4246 * Command header. 4247 */ 4248 struct dmub_cmd_header header; 4249 /** 4250 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4251 */ 4252 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4253 /** 4254 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4255 */ 4256 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4257 }; 4258 4259 /** 4260 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4261 */ 4262 struct dmub_rb_cmd_replay_set_timing_sync { 4263 /** 4264 * Command header. 4265 */ 4266 struct dmub_cmd_header header; 4267 /** 4268 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4269 */ 4270 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4271 }; 4272 4273 /** 4274 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4275 */ 4276 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4277 /** 4278 * Command header. 4279 */ 4280 struct dmub_cmd_header header; 4281 /** 4282 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4283 */ 4284 struct dmub_cmd_replay_set_pseudo_vtotal data; 4285 }; 4286 4287 /** 4288 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4289 */ 4290 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4291 /** 4292 * Command header. 4293 */ 4294 struct dmub_cmd_header header; 4295 /** 4296 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4297 */ 4298 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4299 }; 4300 4301 /** 4302 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4303 */ 4304 struct dmub_rb_cmd_replay_set_general_cmd { 4305 /** 4306 * Command header. 4307 */ 4308 struct dmub_cmd_header header; 4309 /** 4310 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4311 */ 4312 struct dmub_cmd_replay_set_general_cmd_data data; 4313 }; 4314 4315 /** 4316 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4317 */ 4318 struct dmub_cmd_replay_frameupdate_timer_data { 4319 /** 4320 * Panel Instance. 4321 * Panel isntance to identify which replay_state to use 4322 * Currently the support is only for 0 or 1 4323 */ 4324 uint8_t panel_inst; 4325 /** 4326 * Replay Frameupdate Timer Enable or not 4327 */ 4328 uint8_t enable; 4329 /** 4330 * REPLAY force reflash frame update number 4331 */ 4332 uint16_t frameupdate_count; 4333 }; 4334 /** 4335 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4336 */ 4337 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4338 /** 4339 * Command header. 4340 */ 4341 struct dmub_cmd_header header; 4342 /** 4343 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4344 */ 4345 struct dmub_cmd_replay_frameupdate_timer_data data; 4346 }; 4347 4348 /** 4349 * Definition union of replay command set 4350 */ 4351 union dmub_replay_cmd_set { 4352 /** 4353 * Panel Instance. 4354 * Panel isntance to identify which replay_state to use 4355 * Currently the support is only for 0 or 1 4356 */ 4357 uint8_t panel_inst; 4358 /** 4359 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4360 */ 4361 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4362 /** 4363 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4364 */ 4365 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4366 /** 4367 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4368 */ 4369 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4370 /** 4371 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4372 */ 4373 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4374 /** 4375 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4376 */ 4377 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4378 }; 4379 4380 /** 4381 * Set of HW components that can be locked. 4382 * 4383 * Note: If updating with more HW components, fields 4384 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4385 */ 4386 union dmub_hw_lock_flags { 4387 /** 4388 * Set of HW components that can be locked. 4389 */ 4390 struct { 4391 /** 4392 * Lock/unlock OTG master update lock. 4393 */ 4394 uint8_t lock_pipe : 1; 4395 /** 4396 * Lock/unlock cursor. 4397 */ 4398 uint8_t lock_cursor : 1; 4399 /** 4400 * Lock/unlock global update lock. 4401 */ 4402 uint8_t lock_dig : 1; 4403 /** 4404 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4405 */ 4406 uint8_t triple_buffer_lock : 1; 4407 } bits; 4408 4409 /** 4410 * Union for HW Lock flags. 4411 */ 4412 uint8_t u8All; 4413 }; 4414 4415 /** 4416 * Instances of HW to be locked. 4417 * 4418 * Note: If updating with more HW components, fields 4419 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4420 */ 4421 struct dmub_hw_lock_inst_flags { 4422 /** 4423 * OTG HW instance for OTG master update lock. 4424 */ 4425 uint8_t otg_inst; 4426 /** 4427 * OPP instance for cursor lock. 4428 */ 4429 uint8_t opp_inst; 4430 /** 4431 * OTG HW instance for global update lock. 4432 * TODO: Remove, and re-use otg_inst. 4433 */ 4434 uint8_t dig_inst; 4435 /** 4436 * Explicit pad to 4 byte boundary. 4437 */ 4438 uint8_t pad; 4439 }; 4440 4441 /** 4442 * Clients that can acquire the HW Lock Manager. 4443 * 4444 * Note: If updating with more clients, fields in 4445 * dmub_inbox0_cmd_lock_hw must be updated to match. 4446 */ 4447 enum hw_lock_client { 4448 /** 4449 * Driver is the client of HW Lock Manager. 4450 */ 4451 HW_LOCK_CLIENT_DRIVER = 0, 4452 /** 4453 * PSR SU is the client of HW Lock Manager. 4454 */ 4455 HW_LOCK_CLIENT_PSR_SU = 1, 4456 HW_LOCK_CLIENT_SUBVP = 3, 4457 /** 4458 * Replay is the client of HW Lock Manager. 4459 */ 4460 HW_LOCK_CLIENT_REPLAY = 4, 4461 HW_LOCK_CLIENT_FAMS2 = 5, 4462 /** 4463 * Invalid client. 4464 */ 4465 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4466 }; 4467 4468 /** 4469 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4470 */ 4471 struct dmub_cmd_lock_hw_data { 4472 /** 4473 * Specifies the client accessing HW Lock Manager. 4474 */ 4475 enum hw_lock_client client; 4476 /** 4477 * HW instances to be locked. 4478 */ 4479 struct dmub_hw_lock_inst_flags inst_flags; 4480 /** 4481 * Which components to be locked. 4482 */ 4483 union dmub_hw_lock_flags hw_locks; 4484 /** 4485 * Specifies lock/unlock. 4486 */ 4487 uint8_t lock; 4488 /** 4489 * HW can be unlocked separately from releasing the HW Lock Mgr. 4490 * This flag is set if the client wishes to release the object. 4491 */ 4492 uint8_t should_release; 4493 /** 4494 * Explicit padding to 4 byte boundary. 4495 */ 4496 uint8_t pad; 4497 }; 4498 4499 /** 4500 * Definition of a DMUB_CMD__HW_LOCK command. 4501 * Command is used by driver and FW. 4502 */ 4503 struct dmub_rb_cmd_lock_hw { 4504 /** 4505 * Command header. 4506 */ 4507 struct dmub_cmd_header header; 4508 /** 4509 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4510 */ 4511 struct dmub_cmd_lock_hw_data lock_hw_data; 4512 }; 4513 4514 /** 4515 * ABM command sub-types. 4516 */ 4517 enum dmub_cmd_abm_type { 4518 /** 4519 * Initialize parameters for ABM algorithm. 4520 * Data is passed through an indirect buffer. 4521 */ 4522 DMUB_CMD__ABM_INIT_CONFIG = 0, 4523 /** 4524 * Set OTG and panel HW instance. 4525 */ 4526 DMUB_CMD__ABM_SET_PIPE = 1, 4527 /** 4528 * Set user requested backklight level. 4529 */ 4530 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4531 /** 4532 * Set ABM operating/aggression level. 4533 */ 4534 DMUB_CMD__ABM_SET_LEVEL = 3, 4535 /** 4536 * Set ambient light level. 4537 */ 4538 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4539 /** 4540 * Enable/disable fractional duty cycle for backlight PWM. 4541 */ 4542 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4543 4544 /** 4545 * unregister vertical interrupt after steady state is reached 4546 */ 4547 DMUB_CMD__ABM_PAUSE = 6, 4548 4549 /** 4550 * Save and Restore ABM state. On save we save parameters, and 4551 * on restore we update state with passed in data. 4552 */ 4553 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4554 4555 /** 4556 * Query ABM caps. 4557 */ 4558 DMUB_CMD__ABM_QUERY_CAPS = 8, 4559 4560 /** 4561 * Set ABM Events 4562 */ 4563 DMUB_CMD__ABM_SET_EVENT = 9, 4564 4565 /** 4566 * Get the current ACE curve. 4567 */ 4568 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4569 4570 /** 4571 * Get current histogram data 4572 */ 4573 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 4574 }; 4575 4576 /** 4577 * LSDMA command sub-types. 4578 */ 4579 enum dmub_cmd_lsdma_type { 4580 /** 4581 * Initialize parameters for LSDMA. 4582 * Ring buffer is mapped to the ring buffer 4583 */ 4584 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 4585 /** 4586 * LSDMA copies data from source to destination linearly 4587 */ 4588 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 4589 /** 4590 * Send the tiled-to-tiled copy command 4591 */ 4592 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 2, 4593 /** 4594 * Send the poll reg write command 4595 */ 4596 DMUB_CMD__LSDMA_POLL_REG_WRITE = 3, 4597 /** 4598 * Send the pio copy command 4599 */ 4600 DMUB_CMD__LSDMA_PIO_COPY = 4, 4601 /** 4602 * Send the pio constfill command 4603 */ 4604 DMUB_CMD__LSDMA_PIO_CONSTFILL = 5, 4605 }; 4606 4607 struct abm_ace_curve { 4608 /** 4609 * @offsets: ACE curve offsets. 4610 */ 4611 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4612 4613 /** 4614 * @thresholds: ACE curve thresholds. 4615 */ 4616 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4617 4618 /** 4619 * @slopes: ACE curve slopes. 4620 */ 4621 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4622 }; 4623 4624 struct fixed_pt_format { 4625 /** 4626 * @sign_bit: Indicates whether one bit is reserved for the sign. 4627 */ 4628 bool sign_bit; 4629 4630 /** 4631 * @num_int_bits: Number of bits used for integer part. 4632 */ 4633 uint8_t num_int_bits; 4634 4635 /** 4636 * @num_frac_bits: Number of bits used for fractional part. 4637 */ 4638 uint8_t num_frac_bits; 4639 4640 /** 4641 * @pad: Explicit padding to 4 byte boundary. 4642 */ 4643 uint8_t pad; 4644 }; 4645 4646 struct abm_caps { 4647 /** 4648 * @num_hg_bins: Number of histogram bins. 4649 */ 4650 uint8_t num_hg_bins; 4651 4652 /** 4653 * @num_ace_segments: Number of ACE curve segments. 4654 */ 4655 uint8_t num_ace_segments; 4656 4657 /** 4658 * @pad: Explicit padding to 4 byte boundary. 4659 */ 4660 uint8_t pad[2]; 4661 4662 /** 4663 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4664 */ 4665 struct fixed_pt_format ace_thresholds_format; 4666 4667 /** 4668 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4669 */ 4670 struct fixed_pt_format ace_offsets_format; 4671 4672 /** 4673 * @ace_slopes_format: Format of the ACE slopes. 4674 */ 4675 struct fixed_pt_format ace_slopes_format; 4676 }; 4677 4678 /** 4679 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4680 * Requirements: 4681 * - Padded explicitly to 32-bit boundary. 4682 * - Must ensure this structure matches the one on driver-side, 4683 * otherwise it won't be aligned. 4684 */ 4685 struct abm_config_table { 4686 /** 4687 * Gamma curve thresholds, used for crgb conversion. 4688 */ 4689 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4690 /** 4691 * Gamma curve offsets, used for crgb conversion. 4692 */ 4693 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4694 /** 4695 * Gamma curve slopes, used for crgb conversion. 4696 */ 4697 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4698 /** 4699 * Custom backlight curve thresholds. 4700 */ 4701 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4702 /** 4703 * Custom backlight curve offsets. 4704 */ 4705 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4706 /** 4707 * Ambient light thresholds. 4708 */ 4709 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4710 /** 4711 * Minimum programmable backlight. 4712 */ 4713 uint16_t min_abm_backlight; // 122B 4714 /** 4715 * Minimum reduction values. 4716 */ 4717 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4718 /** 4719 * Maximum reduction values. 4720 */ 4721 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4722 /** 4723 * Bright positive gain. 4724 */ 4725 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4726 /** 4727 * Dark negative gain. 4728 */ 4729 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4730 /** 4731 * Hybrid factor. 4732 */ 4733 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4734 /** 4735 * Contrast factor. 4736 */ 4737 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4738 /** 4739 * Deviation gain. 4740 */ 4741 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4742 /** 4743 * Minimum knee. 4744 */ 4745 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4746 /** 4747 * Maximum knee. 4748 */ 4749 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4750 /** 4751 * Unused. 4752 */ 4753 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4754 /** 4755 * Explicit padding to 4 byte boundary. 4756 */ 4757 uint8_t pad3[3]; // 229B 4758 /** 4759 * Backlight ramp reduction. 4760 */ 4761 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4762 /** 4763 * Backlight ramp start. 4764 */ 4765 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4766 }; 4767 4768 /** 4769 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4770 */ 4771 struct dmub_cmd_abm_set_pipe_data { 4772 /** 4773 * OTG HW instance. 4774 */ 4775 uint8_t otg_inst; 4776 4777 /** 4778 * Panel Control HW instance. 4779 */ 4780 uint8_t panel_inst; 4781 4782 /** 4783 * Controls how ABM will interpret a set pipe or set level command. 4784 */ 4785 uint8_t set_pipe_option; 4786 4787 /** 4788 * Unused. 4789 * TODO: Remove. 4790 */ 4791 uint8_t ramping_boundary; 4792 4793 /** 4794 * PwrSeq HW Instance. 4795 */ 4796 uint8_t pwrseq_inst; 4797 4798 /** 4799 * Explicit padding to 4 byte boundary. 4800 */ 4801 uint8_t pad[3]; 4802 }; 4803 4804 /** 4805 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4806 */ 4807 struct dmub_rb_cmd_abm_set_pipe { 4808 /** 4809 * Command header. 4810 */ 4811 struct dmub_cmd_header header; 4812 4813 /** 4814 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4815 */ 4816 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4817 }; 4818 4819 /** 4820 * Type of backlight control method to be used by ABM module 4821 */ 4822 enum dmub_backlight_control_type { 4823 /** 4824 * PWM Backlight control 4825 */ 4826 DMU_BACKLIGHT_CONTROL_PWM = 0, 4827 /** 4828 * VESA Aux-based backlight control 4829 */ 4830 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 4831 /** 4832 * AMD DPCD Aux-based backlight control 4833 */ 4834 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 4835 }; 4836 4837 /** 4838 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4839 */ 4840 struct dmub_cmd_abm_set_backlight_data { 4841 /** 4842 * Number of frames to ramp to backlight user level. 4843 */ 4844 uint32_t frame_ramp; 4845 4846 /** 4847 * Requested backlight level from user. 4848 */ 4849 uint32_t backlight_user_level; 4850 4851 /** 4852 * ABM control version. 4853 */ 4854 uint8_t version; 4855 4856 /** 4857 * Panel Control HW instance mask. 4858 * Bit 0 is Panel Control HW instance 0. 4859 * Bit 1 is Panel Control HW instance 1. 4860 */ 4861 uint8_t panel_mask; 4862 4863 /** 4864 * AUX HW Instance. 4865 */ 4866 uint8_t aux_inst; 4867 4868 /** 4869 * Explicit padding to 4 byte boundary. 4870 */ 4871 uint8_t pad[1]; 4872 4873 /** 4874 * Backlight control type. 4875 * Value 0 is PWM backlight control. 4876 * Value 1 is VAUX backlight control. 4877 * Value 2 is AMD DPCD AUX backlight control. 4878 */ 4879 enum dmub_backlight_control_type backlight_control_type; 4880 4881 /** 4882 * Minimum luminance in nits. 4883 */ 4884 uint32_t min_luminance; 4885 4886 /** 4887 * Maximum luminance in nits. 4888 */ 4889 uint32_t max_luminance; 4890 4891 /** 4892 * Minimum backlight in pwm. 4893 */ 4894 uint32_t min_backlight_pwm; 4895 4896 /** 4897 * Maximum backlight in pwm. 4898 */ 4899 uint32_t max_backlight_pwm; 4900 }; 4901 4902 /** 4903 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4904 */ 4905 struct dmub_rb_cmd_abm_set_backlight { 4906 /** 4907 * Command header. 4908 */ 4909 struct dmub_cmd_header header; 4910 4911 /** 4912 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4913 */ 4914 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4915 }; 4916 4917 /** 4918 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4919 */ 4920 struct dmub_cmd_abm_set_level_data { 4921 /** 4922 * Set current ABM operating/aggression level. 4923 */ 4924 uint32_t level; 4925 4926 /** 4927 * ABM control version. 4928 */ 4929 uint8_t version; 4930 4931 /** 4932 * Panel Control HW instance mask. 4933 * Bit 0 is Panel Control HW instance 0. 4934 * Bit 1 is Panel Control HW instance 1. 4935 */ 4936 uint8_t panel_mask; 4937 4938 /** 4939 * Explicit padding to 4 byte boundary. 4940 */ 4941 uint8_t pad[2]; 4942 }; 4943 4944 /** 4945 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4946 */ 4947 struct dmub_rb_cmd_abm_set_level { 4948 /** 4949 * Command header. 4950 */ 4951 struct dmub_cmd_header header; 4952 4953 /** 4954 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4955 */ 4956 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4957 }; 4958 4959 /** 4960 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4961 */ 4962 struct dmub_cmd_abm_set_ambient_level_data { 4963 /** 4964 * Ambient light sensor reading from OS. 4965 */ 4966 uint32_t ambient_lux; 4967 4968 /** 4969 * ABM control version. 4970 */ 4971 uint8_t version; 4972 4973 /** 4974 * Panel Control HW instance mask. 4975 * Bit 0 is Panel Control HW instance 0. 4976 * Bit 1 is Panel Control HW instance 1. 4977 */ 4978 uint8_t panel_mask; 4979 4980 /** 4981 * Explicit padding to 4 byte boundary. 4982 */ 4983 uint8_t pad[2]; 4984 }; 4985 4986 /** 4987 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4988 */ 4989 struct dmub_rb_cmd_abm_set_ambient_level { 4990 /** 4991 * Command header. 4992 */ 4993 struct dmub_cmd_header header; 4994 4995 /** 4996 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4997 */ 4998 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 4999 }; 5000 5001 /** 5002 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5003 */ 5004 struct dmub_cmd_abm_set_pwm_frac_data { 5005 /** 5006 * Enable/disable fractional duty cycle for backlight PWM. 5007 * TODO: Convert to uint8_t. 5008 */ 5009 uint32_t fractional_pwm; 5010 5011 /** 5012 * ABM control version. 5013 */ 5014 uint8_t version; 5015 5016 /** 5017 * Panel Control HW instance mask. 5018 * Bit 0 is Panel Control HW instance 0. 5019 * Bit 1 is Panel Control HW instance 1. 5020 */ 5021 uint8_t panel_mask; 5022 5023 /** 5024 * Explicit padding to 4 byte boundary. 5025 */ 5026 uint8_t pad[2]; 5027 }; 5028 5029 /** 5030 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5031 */ 5032 struct dmub_rb_cmd_abm_set_pwm_frac { 5033 /** 5034 * Command header. 5035 */ 5036 struct dmub_cmd_header header; 5037 5038 /** 5039 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5040 */ 5041 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5042 }; 5043 5044 /** 5045 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5046 */ 5047 struct dmub_cmd_abm_init_config_data { 5048 /** 5049 * Location of indirect buffer used to pass init data to ABM. 5050 */ 5051 union dmub_addr src; 5052 5053 /** 5054 * Indirect buffer length. 5055 */ 5056 uint16_t bytes; 5057 5058 5059 /** 5060 * ABM control version. 5061 */ 5062 uint8_t version; 5063 5064 /** 5065 * Panel Control HW instance mask. 5066 * Bit 0 is Panel Control HW instance 0. 5067 * Bit 1 is Panel Control HW instance 1. 5068 */ 5069 uint8_t panel_mask; 5070 5071 /** 5072 * Explicit padding to 4 byte boundary. 5073 */ 5074 uint8_t pad[2]; 5075 }; 5076 5077 /** 5078 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5079 */ 5080 struct dmub_rb_cmd_abm_init_config { 5081 /** 5082 * Command header. 5083 */ 5084 struct dmub_cmd_header header; 5085 5086 /** 5087 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5088 */ 5089 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5090 }; 5091 5092 /** 5093 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5094 */ 5095 5096 struct dmub_cmd_abm_pause_data { 5097 5098 /** 5099 * Panel Control HW instance mask. 5100 * Bit 0 is Panel Control HW instance 0. 5101 * Bit 1 is Panel Control HW instance 1. 5102 */ 5103 uint8_t panel_mask; 5104 5105 /** 5106 * OTG hw instance 5107 */ 5108 uint8_t otg_inst; 5109 5110 /** 5111 * Enable or disable ABM pause 5112 */ 5113 uint8_t enable; 5114 5115 /** 5116 * Explicit padding to 4 byte boundary. 5117 */ 5118 uint8_t pad[1]; 5119 }; 5120 5121 /** 5122 * Definition of a DMUB_CMD__ABM_PAUSE command. 5123 */ 5124 struct dmub_rb_cmd_abm_pause { 5125 /** 5126 * Command header. 5127 */ 5128 struct dmub_cmd_header header; 5129 5130 /** 5131 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5132 */ 5133 struct dmub_cmd_abm_pause_data abm_pause_data; 5134 }; 5135 5136 /** 5137 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 5138 */ 5139 struct dmub_cmd_abm_query_caps_in { 5140 /** 5141 * Panel instance. 5142 */ 5143 uint8_t panel_inst; 5144 5145 /** 5146 * Explicit padding to 4 byte boundary. 5147 */ 5148 uint8_t pad[3]; 5149 }; 5150 5151 /** 5152 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5153 */ 5154 struct dmub_cmd_abm_query_caps_out { 5155 /** 5156 * SW Algorithm caps. 5157 */ 5158 struct abm_caps sw_caps; 5159 5160 /** 5161 * ABM HW caps. 5162 */ 5163 struct abm_caps hw_caps; 5164 }; 5165 5166 /** 5167 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5168 */ 5169 struct dmub_rb_cmd_abm_query_caps { 5170 /** 5171 * Command header. 5172 */ 5173 struct dmub_cmd_header header; 5174 5175 /** 5176 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5177 */ 5178 union { 5179 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5180 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5181 } data; 5182 }; 5183 5184 /** 5185 * enum dmub_abm_ace_curve_type - ACE curve type. 5186 */ 5187 enum dmub_abm_ace_curve_type { 5188 /** 5189 * ACE curve as defined by the SW layer. 5190 */ 5191 ABM_ACE_CURVE_TYPE__SW = 0, 5192 /** 5193 * ACE curve as defined by the SW to HW translation interface layer. 5194 */ 5195 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5196 }; 5197 5198 /** 5199 * enum dmub_abm_histogram_type - Histogram type. 5200 */ 5201 enum dmub_abm_histogram_type { 5202 /** 5203 * ACE curve as defined by the SW layer. 5204 */ 5205 ABM_HISTOGRAM_TYPE__SW = 0, 5206 /** 5207 * ACE curve as defined by the SW to HW translation interface layer. 5208 */ 5209 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5210 }; 5211 5212 /** 5213 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5214 */ 5215 struct dmub_rb_cmd_abm_get_ace_curve { 5216 /** 5217 * Command header. 5218 */ 5219 struct dmub_cmd_header header; 5220 5221 /** 5222 * Address where ACE curve should be copied. 5223 */ 5224 union dmub_addr dest; 5225 5226 /** 5227 * Type of ACE curve being queried. 5228 */ 5229 enum dmub_abm_ace_curve_type ace_type; 5230 5231 /** 5232 * Indirect buffer length. 5233 */ 5234 uint16_t bytes; 5235 5236 /** 5237 * eDP panel instance. 5238 */ 5239 uint8_t panel_inst; 5240 5241 /** 5242 * Explicit padding to 4 byte boundary. 5243 */ 5244 uint8_t pad; 5245 }; 5246 5247 /** 5248 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5249 */ 5250 struct dmub_rb_cmd_abm_get_histogram { 5251 /** 5252 * Command header. 5253 */ 5254 struct dmub_cmd_header header; 5255 5256 /** 5257 * Address where Histogram should be copied. 5258 */ 5259 union dmub_addr dest; 5260 5261 /** 5262 * Type of Histogram being queried. 5263 */ 5264 enum dmub_abm_histogram_type histogram_type; 5265 5266 /** 5267 * Indirect buffer length. 5268 */ 5269 uint16_t bytes; 5270 5271 /** 5272 * eDP panel instance. 5273 */ 5274 uint8_t panel_inst; 5275 5276 /** 5277 * Explicit padding to 4 byte boundary. 5278 */ 5279 uint8_t pad; 5280 }; 5281 5282 /** 5283 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5284 */ 5285 struct dmub_rb_cmd_abm_save_restore { 5286 /** 5287 * Command header. 5288 */ 5289 struct dmub_cmd_header header; 5290 5291 /** 5292 * OTG hw instance 5293 */ 5294 uint8_t otg_inst; 5295 5296 /** 5297 * Enable or disable ABM pause 5298 */ 5299 uint8_t freeze; 5300 5301 /** 5302 * Explicit padding to 4 byte boundary. 5303 */ 5304 uint8_t debug; 5305 5306 /** 5307 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5308 */ 5309 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5310 }; 5311 5312 /** 5313 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5314 */ 5315 5316 struct dmub_cmd_abm_set_event_data { 5317 5318 /** 5319 * VB Scaling Init. Strength Mapping 5320 * Byte 0: 0~255 for VB level 0 5321 * Byte 1: 0~255 for VB level 1 5322 * Byte 2: 0~255 for VB level 2 5323 * Byte 3: 0~255 for VB level 3 5324 */ 5325 uint32_t vb_scaling_strength_mapping; 5326 /** 5327 * VariBright Scaling Enable 5328 */ 5329 uint8_t vb_scaling_enable; 5330 /** 5331 * Panel Control HW instance mask. 5332 * Bit 0 is Panel Control HW instance 0. 5333 * Bit 1 is Panel Control HW instance 1. 5334 */ 5335 uint8_t panel_mask; 5336 5337 /** 5338 * Explicit padding to 4 byte boundary. 5339 */ 5340 uint8_t pad[2]; 5341 }; 5342 5343 /** 5344 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5345 */ 5346 struct dmub_rb_cmd_abm_set_event { 5347 /** 5348 * Command header. 5349 */ 5350 struct dmub_cmd_header header; 5351 5352 /** 5353 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5354 */ 5355 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5356 }; 5357 5358 /** 5359 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5360 */ 5361 struct dmub_cmd_query_feature_caps_data { 5362 /** 5363 * DMUB feature capabilities. 5364 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5365 */ 5366 struct dmub_feature_caps feature_caps; 5367 }; 5368 5369 /** 5370 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5371 */ 5372 struct dmub_rb_cmd_query_feature_caps { 5373 /** 5374 * Command header. 5375 */ 5376 struct dmub_cmd_header header; 5377 /** 5378 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5379 */ 5380 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5381 }; 5382 5383 /** 5384 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5385 */ 5386 struct dmub_cmd_visual_confirm_color_data { 5387 /** 5388 * DMUB visual confirm color 5389 */ 5390 struct dmub_visual_confirm_color visual_confirm_color; 5391 }; 5392 5393 /** 5394 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5395 */ 5396 struct dmub_rb_cmd_get_visual_confirm_color { 5397 /** 5398 * Command header. 5399 */ 5400 struct dmub_cmd_header header; 5401 /** 5402 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5403 */ 5404 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5405 }; 5406 5407 /** 5408 * enum dmub_cmd_panel_cntl_type - Panel control command. 5409 */ 5410 enum dmub_cmd_panel_cntl_type { 5411 /** 5412 * Initializes embedded panel hardware blocks. 5413 */ 5414 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5415 /** 5416 * Queries backlight info for the embedded panel. 5417 */ 5418 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5419 /** 5420 * Sets the PWM Freq as per user's requirement. 5421 */ 5422 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5423 }; 5424 5425 /** 5426 * struct dmub_cmd_panel_cntl_data - Panel control data. 5427 */ 5428 struct dmub_cmd_panel_cntl_data { 5429 uint32_t pwrseq_inst; /**< pwrseq instance */ 5430 uint32_t current_backlight; /* in/out */ 5431 uint32_t bl_pwm_cntl; /* in/out */ 5432 uint32_t bl_pwm_period_cntl; /* in/out */ 5433 uint32_t bl_pwm_ref_div1; /* in/out */ 5434 uint8_t is_backlight_on : 1; /* in/out */ 5435 uint8_t is_powered_on : 1; /* in/out */ 5436 uint8_t padding[3]; 5437 uint32_t bl_pwm_ref_div2; /* in/out */ 5438 uint8_t reserved[4]; 5439 }; 5440 5441 /** 5442 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5443 */ 5444 struct dmub_rb_cmd_panel_cntl { 5445 struct dmub_cmd_header header; /**< header */ 5446 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5447 }; 5448 5449 struct dmub_optc_state { 5450 uint32_t v_total_max; 5451 uint32_t v_total_min; 5452 uint32_t tg_inst; 5453 }; 5454 5455 struct dmub_rb_cmd_drr_update { 5456 struct dmub_cmd_header header; 5457 struct dmub_optc_state dmub_optc_state_req; 5458 }; 5459 5460 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5461 uint32_t pix_clk_100hz; 5462 uint8_t max_ramp_step; 5463 uint8_t pipes; 5464 uint8_t min_refresh_in_hz; 5465 uint8_t pipe_count; 5466 uint8_t pipe_index[4]; 5467 }; 5468 5469 struct dmub_cmd_fw_assisted_mclk_switch_config { 5470 uint8_t fams_enabled; 5471 uint8_t visual_confirm_enabled; 5472 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5473 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5474 }; 5475 5476 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5477 struct dmub_cmd_header header; 5478 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5479 }; 5480 5481 /** 5482 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5483 */ 5484 struct dmub_cmd_lvtma_control_data { 5485 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5486 uint8_t bypass_panel_control_wait; 5487 uint8_t reserved_0[2]; /**< For future use */ 5488 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5489 uint8_t reserved_1[3]; /**< For future use */ 5490 }; 5491 5492 /** 5493 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5494 */ 5495 struct dmub_rb_cmd_lvtma_control { 5496 /** 5497 * Command header. 5498 */ 5499 struct dmub_cmd_header header; 5500 /** 5501 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5502 */ 5503 struct dmub_cmd_lvtma_control_data data; 5504 }; 5505 5506 /** 5507 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5508 */ 5509 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5510 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5511 uint8_t is_usb; /**< is phy is usb */ 5512 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5513 uint8_t is_dp4; /**< is dp in 4 lane */ 5514 }; 5515 5516 /** 5517 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5518 */ 5519 struct dmub_rb_cmd_transmitter_query_dp_alt { 5520 struct dmub_cmd_header header; /**< header */ 5521 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5522 }; 5523 5524 struct phy_test_mode { 5525 uint8_t mode; 5526 uint8_t pat0; 5527 uint8_t pad[2]; 5528 }; 5529 5530 /** 5531 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5532 */ 5533 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5534 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5535 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5536 uint8_t lane_num; /**< Number of lanes */ 5537 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5538 struct phy_test_mode test_mode; 5539 enum dmub_phy_fsm_state state; 5540 uint32_t status; 5541 uint8_t pad; 5542 }; 5543 5544 /** 5545 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5546 */ 5547 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5548 struct dmub_cmd_header header; /**< header */ 5549 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5550 }; 5551 5552 /** 5553 * Maximum number of bytes a chunk sent to DMUB for parsing 5554 */ 5555 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5556 5557 /** 5558 * Represent a chunk of CEA blocks sent to DMUB for parsing 5559 */ 5560 struct dmub_cmd_send_edid_cea { 5561 uint16_t offset; /**< offset into the CEA block */ 5562 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5563 uint16_t cea_total_length; /**< total length of the CEA block */ 5564 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5565 uint8_t pad[3]; /**< padding and for future expansion */ 5566 }; 5567 5568 /** 5569 * Result of VSDB parsing from CEA block 5570 */ 5571 struct dmub_cmd_edid_cea_amd_vsdb { 5572 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5573 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5574 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5575 uint16_t min_frame_rate; /**< Maximum frame rate */ 5576 uint16_t max_frame_rate; /**< Minimum frame rate */ 5577 }; 5578 5579 /** 5580 * Result of sending a CEA chunk 5581 */ 5582 struct dmub_cmd_edid_cea_ack { 5583 uint16_t offset; /**< offset of the chunk into the CEA block */ 5584 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5585 uint8_t pad; /**< padding and for future expansion */ 5586 }; 5587 5588 /** 5589 * Specify whether the result is an ACK/NACK or the parsing has finished 5590 */ 5591 enum dmub_cmd_edid_cea_reply_type { 5592 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5593 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5594 }; 5595 5596 /** 5597 * Definition of a DMUB_CMD__EDID_CEA command. 5598 */ 5599 struct dmub_rb_cmd_edid_cea { 5600 struct dmub_cmd_header header; /**< Command header */ 5601 union dmub_cmd_edid_cea_data { 5602 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5603 struct dmub_cmd_edid_cea_output { /**< output with results */ 5604 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5605 union { 5606 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5607 struct dmub_cmd_edid_cea_ack ack; 5608 }; 5609 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5610 } data; /**< Command data */ 5611 5612 }; 5613 5614 /** 5615 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5616 */ 5617 struct dmub_cmd_cable_id_input { 5618 uint8_t phy_inst; /**< phy inst for cable id data */ 5619 }; 5620 5621 /** 5622 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5623 */ 5624 struct dmub_cmd_cable_id_output { 5625 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5626 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5627 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5628 uint8_t RESERVED :2; /**< reserved means not defined */ 5629 }; 5630 5631 /** 5632 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5633 */ 5634 struct dmub_rb_cmd_get_usbc_cable_id { 5635 struct dmub_cmd_header header; /**< Command header */ 5636 /** 5637 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5638 */ 5639 union dmub_cmd_cable_id_data { 5640 struct dmub_cmd_cable_id_input input; /**< Input */ 5641 struct dmub_cmd_cable_id_output output; /**< Output */ 5642 uint8_t output_raw; /**< Raw data output */ 5643 } data; 5644 }; 5645 5646 enum dmub_cmd_fused_io_sub_type { 5647 DMUB_CMD__FUSED_IO_EXECUTE = 0, 5648 DMUB_CMD__FUSED_IO_ABORT = 1, 5649 }; 5650 5651 enum dmub_cmd_fused_request_type { 5652 FUSED_REQUEST_READ, 5653 FUSED_REQUEST_WRITE, 5654 FUSED_REQUEST_POLL, 5655 }; 5656 5657 enum dmub_cmd_fused_request_status { 5658 FUSED_REQUEST_STATUS_SUCCESS, 5659 FUSED_REQUEST_STATUS_BEGIN, 5660 FUSED_REQUEST_STATUS_SUBMIT, 5661 FUSED_REQUEST_STATUS_REPLY, 5662 FUSED_REQUEST_STATUS_POLL, 5663 FUSED_REQUEST_STATUS_ABORTED, 5664 FUSED_REQUEST_STATUS_FAILED = 0x80, 5665 FUSED_REQUEST_STATUS_INVALID, 5666 FUSED_REQUEST_STATUS_BUSY, 5667 FUSED_REQUEST_STATUS_TIMEOUT, 5668 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 5669 }; 5670 5671 struct dmub_cmd_fused_request { 5672 uint8_t status; 5673 uint8_t type : 2; 5674 uint8_t _reserved0 : 3; 5675 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 5676 uint8_t identifier; 5677 uint8_t _reserved1; 5678 uint32_t timeout_us; 5679 union dmub_cmd_fused_request_location { 5680 struct dmub_cmd_fused_request_location_i2c { 5681 uint8_t is_aux : 1; // False 5682 uint8_t ddc_line : 3; 5683 uint8_t over_aux : 1; 5684 uint8_t _reserved0 : 3; 5685 uint8_t address; 5686 uint8_t offset; 5687 uint8_t length; 5688 } i2c; 5689 struct dmub_cmd_fused_request_location_aux { 5690 uint32_t is_aux : 1; // True 5691 uint32_t ddc_line : 3; 5692 uint32_t address : 20; 5693 uint32_t length : 8; // Automatically split into 16B transactions 5694 } aux; 5695 } u; 5696 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 5697 }; 5698 5699 struct dmub_rb_cmd_fused_io { 5700 struct dmub_cmd_header header; 5701 struct dmub_cmd_fused_request request; 5702 }; 5703 5704 /** 5705 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5706 */ 5707 enum dmub_cmd_secure_display_type { 5708 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5709 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5710 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5711 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5712 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5713 }; 5714 5715 #define MAX_ROI_NUM 2 5716 5717 struct dmub_cmd_roi_info { 5718 uint16_t x_start; 5719 uint16_t x_end; 5720 uint16_t y_start; 5721 uint16_t y_end; 5722 uint8_t otg_id; 5723 uint8_t phy_id; 5724 }; 5725 5726 struct dmub_cmd_roi_window_ctl { 5727 uint16_t x_start; 5728 uint16_t x_end; 5729 uint16_t y_start; 5730 uint16_t y_end; 5731 bool enable; 5732 }; 5733 5734 struct dmub_cmd_roi_ctl_info { 5735 uint8_t otg_id; 5736 uint8_t phy_id; 5737 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5738 }; 5739 5740 /** 5741 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5742 */ 5743 struct dmub_rb_cmd_secure_display { 5744 struct dmub_cmd_header header; 5745 /** 5746 * Data passed from driver to dmub firmware. 5747 */ 5748 struct dmub_cmd_roi_info roi_info; 5749 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5750 }; 5751 5752 /** 5753 * Command type of a DMUB_CMD__PSP command 5754 */ 5755 enum dmub_cmd_psp_type { 5756 DMUB_CMD__PSP_ASSR_ENABLE = 0 5757 }; 5758 5759 /** 5760 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5761 */ 5762 struct dmub_cmd_assr_enable_data { 5763 /** 5764 * ASSR enable or disable. 5765 */ 5766 uint8_t enable; 5767 /** 5768 * PHY port type. 5769 * Indicates eDP / non-eDP port type 5770 */ 5771 uint8_t phy_port_type; 5772 /** 5773 * PHY port ID. 5774 */ 5775 uint8_t phy_port_id; 5776 /** 5777 * Link encoder index. 5778 */ 5779 uint8_t link_enc_index; 5780 /** 5781 * HPO mode. 5782 */ 5783 uint8_t hpo_mode; 5784 5785 /** 5786 * Reserved field. 5787 */ 5788 uint8_t reserved[7]; 5789 }; 5790 5791 /** 5792 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5793 */ 5794 struct dmub_rb_cmd_assr_enable { 5795 /** 5796 * Command header. 5797 */ 5798 struct dmub_cmd_header header; 5799 5800 /** 5801 * Assr data. 5802 */ 5803 struct dmub_cmd_assr_enable_data assr_data; 5804 5805 /** 5806 * Reserved field. 5807 */ 5808 uint32_t reserved[3]; 5809 }; 5810 5811 /** 5812 * union dmub_rb_cmd - DMUB inbox command. 5813 */ 5814 union dmub_rb_cmd { 5815 /** 5816 * Elements shared with all commands. 5817 */ 5818 struct dmub_rb_cmd_common cmd_common; 5819 /** 5820 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5821 */ 5822 struct dmub_rb_cmd_read_modify_write read_modify_write; 5823 /** 5824 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5825 */ 5826 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5827 /** 5828 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5829 */ 5830 struct dmub_rb_cmd_burst_write burst_write; 5831 /** 5832 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5833 */ 5834 struct dmub_rb_cmd_reg_wait reg_wait; 5835 /** 5836 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5837 */ 5838 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5839 /** 5840 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5841 */ 5842 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5843 /** 5844 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5845 */ 5846 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5847 /** 5848 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5849 */ 5850 struct dmub_rb_cmd_dpphy_init dpphy_init; 5851 /** 5852 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5853 */ 5854 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5855 /** 5856 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5857 */ 5858 struct dmub_rb_cmd_domain_control domain_control; 5859 /** 5860 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5861 */ 5862 struct dmub_rb_cmd_psr_set_version psr_set_version; 5863 /** 5864 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5865 */ 5866 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5867 /** 5868 * Definition of a DMUB_CMD__PSR_ENABLE command. 5869 */ 5870 struct dmub_rb_cmd_psr_enable psr_enable; 5871 /** 5872 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5873 */ 5874 struct dmub_rb_cmd_psr_set_level psr_set_level; 5875 /** 5876 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5877 */ 5878 struct dmub_rb_cmd_psr_force_static psr_force_static; 5879 /** 5880 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5881 */ 5882 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5883 /** 5884 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5885 */ 5886 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5887 /** 5888 * Definition of a DMUB_CMD__HW_LOCK command. 5889 * Command is used by driver and FW. 5890 */ 5891 struct dmub_rb_cmd_lock_hw lock_hw; 5892 /** 5893 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5894 */ 5895 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5896 /** 5897 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5898 */ 5899 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5900 /** 5901 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5902 */ 5903 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5904 /** 5905 * Definition of a DMUB_CMD__MALL command. 5906 */ 5907 struct dmub_rb_cmd_mall mall; 5908 5909 /** 5910 * Definition of a DMUB_CMD__CAB command. 5911 */ 5912 struct dmub_rb_cmd_cab_for_ss cab; 5913 5914 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5915 5916 /** 5917 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5918 */ 5919 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5920 5921 /** 5922 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5923 */ 5924 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5925 5926 /** 5927 * Definition of DMUB_CMD__PANEL_CNTL commands. 5928 */ 5929 struct dmub_rb_cmd_panel_cntl panel_cntl; 5930 5931 /** 5932 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5933 */ 5934 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5935 5936 /** 5937 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5938 */ 5939 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5940 5941 /** 5942 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5943 */ 5944 struct dmub_rb_cmd_abm_set_level abm_set_level; 5945 5946 /** 5947 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5948 */ 5949 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5950 5951 /** 5952 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5953 */ 5954 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 5955 5956 /** 5957 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5958 */ 5959 struct dmub_rb_cmd_abm_init_config abm_init_config; 5960 5961 /** 5962 * Definition of a DMUB_CMD__ABM_PAUSE command. 5963 */ 5964 struct dmub_rb_cmd_abm_pause abm_pause; 5965 5966 /** 5967 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5968 */ 5969 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 5970 5971 /** 5972 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5973 */ 5974 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 5975 5976 /** 5977 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5978 */ 5979 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 5980 5981 /** 5982 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5983 */ 5984 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 5985 5986 /** 5987 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5988 */ 5989 struct dmub_rb_cmd_abm_set_event abm_set_event; 5990 5991 /** 5992 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 5993 */ 5994 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 5995 5996 /** 5997 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 5998 */ 5999 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 6000 6001 /** 6002 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6003 */ 6004 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 6005 6006 /** 6007 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6008 */ 6009 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 6010 struct dmub_rb_cmd_drr_update drr_update; 6011 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 6012 6013 /** 6014 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6015 */ 6016 struct dmub_rb_cmd_lvtma_control lvtma_control; 6017 /** 6018 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6019 */ 6020 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 6021 /** 6022 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6023 */ 6024 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 6025 /** 6026 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 6027 */ 6028 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 6029 /** 6030 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6031 */ 6032 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 6033 /** 6034 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6035 */ 6036 struct dmub_rb_cmd_set_config_request set_config_request; 6037 /** 6038 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 6039 */ 6040 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 6041 /** 6042 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 6043 */ 6044 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 6045 /** 6046 * Definition of a DMUB_CMD__EDID_CEA command. 6047 */ 6048 struct dmub_rb_cmd_edid_cea edid_cea; 6049 /** 6050 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 6051 */ 6052 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 6053 6054 /** 6055 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 6056 */ 6057 struct dmub_rb_cmd_query_hpd_state query_hpd; 6058 /** 6059 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 6060 */ 6061 struct dmub_rb_cmd_secure_display secure_display; 6062 6063 /** 6064 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 6065 */ 6066 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 6067 /** 6068 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 6069 */ 6070 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 6071 /** 6072 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 6073 */ 6074 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 6075 /* 6076 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 6077 */ 6078 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 6079 /** 6080 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 6081 */ 6082 struct dmub_rb_cmd_replay_enable replay_enable; 6083 /** 6084 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 6085 */ 6086 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 6087 /** 6088 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 6089 */ 6090 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 6091 /** 6092 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 6093 */ 6094 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 6095 6096 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 6097 /** 6098 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 6099 */ 6100 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 6101 /** 6102 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 6103 */ 6104 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 6105 /** 6106 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 6107 */ 6108 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 6109 /** 6110 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 6111 */ 6112 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 6113 /** 6114 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6115 */ 6116 struct dmub_rb_cmd_assr_enable assr_enable; 6117 6118 struct dmub_rb_cmd_fams2 fams2_config; 6119 6120 struct dmub_rb_cmd_ib ib_fams2_config; 6121 6122 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 6123 6124 struct dmub_rb_cmd_fams2_flip fams2_flip; 6125 6126 struct dmub_rb_cmd_fused_io fused_io; 6127 6128 /** 6129 * Definition of a DMUB_CMD__LSDMA command. 6130 */ 6131 struct dmub_rb_cmd_lsdma lsdma; 6132 }; 6133 6134 /** 6135 * union dmub_rb_out_cmd - Outbox command 6136 */ 6137 union dmub_rb_out_cmd { 6138 /** 6139 * Parameters common to every command. 6140 */ 6141 struct dmub_rb_cmd_common cmd_common; 6142 /** 6143 * AUX reply command. 6144 */ 6145 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 6146 /** 6147 * HPD notify command. 6148 */ 6149 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 6150 /** 6151 * SET_CONFIG reply command. 6152 */ 6153 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 6154 /** 6155 * DPIA notification command. 6156 */ 6157 struct dmub_rb_cmd_dpia_notification dpia_notification; 6158 /** 6159 * HPD sense notification command. 6160 */ 6161 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 6162 struct dmub_rb_cmd_fused_io fused_io; 6163 }; 6164 #pragma pack(pop) 6165 6166 6167 //============================================================================== 6168 //</DMUB_CMD>=================================================================== 6169 //============================================================================== 6170 //< DMUB_RB>==================================================================== 6171 //============================================================================== 6172 6173 /** 6174 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 6175 */ 6176 struct dmub_rb_init_params { 6177 void *ctx; /**< Caller provided context pointer */ 6178 void *base_address; /**< CPU base address for ring's data */ 6179 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6180 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 6181 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 6182 }; 6183 6184 /** 6185 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 6186 */ 6187 struct dmub_rb { 6188 void *base_address; /**< CPU address for the ring's data */ 6189 uint32_t rptr; /**< Read pointer for consumer in bytes */ 6190 uint32_t wrpt; /**< Write pointer for producer in bytes */ 6191 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6192 6193 void *ctx; /**< Caller provided context pointer */ 6194 void *dmub; /**< Pointer to the DMUB interface */ 6195 }; 6196 6197 /** 6198 * @brief Checks if the ringbuffer is empty. 6199 * 6200 * @param rb DMUB Ringbuffer 6201 * @return true if empty 6202 * @return false otherwise 6203 */ 6204 static inline bool dmub_rb_empty(struct dmub_rb *rb) 6205 { 6206 return (rb->wrpt == rb->rptr); 6207 } 6208 6209 /** 6210 * @brief gets number of outstanding requests in the RB 6211 * 6212 * @param rb DMUB Ringbuffer 6213 * @return true if full 6214 */ 6215 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 6216 { 6217 uint32_t data_count; 6218 6219 if (rb->wrpt >= rb->rptr) 6220 data_count = rb->wrpt - rb->rptr; 6221 else 6222 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6223 6224 return data_count / DMUB_RB_CMD_SIZE; 6225 } 6226 6227 /** 6228 * @brief gets number of free buffers in the RB 6229 * 6230 * @param rb DMUB Ringbuffer 6231 * @return true if full 6232 */ 6233 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 6234 { 6235 uint32_t data_count; 6236 6237 if (rb->wrpt >= rb->rptr) 6238 data_count = rb->wrpt - rb->rptr; 6239 else 6240 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6241 6242 /* +1 because 1 entry is always unusable */ 6243 data_count += DMUB_RB_CMD_SIZE; 6244 6245 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 6246 } 6247 6248 /** 6249 * @brief Checks if the ringbuffer is full 6250 * 6251 * @param rb DMUB Ringbuffer 6252 * @return true if full 6253 * @return false otherwise 6254 */ 6255 static inline bool dmub_rb_full(struct dmub_rb *rb) 6256 { 6257 uint32_t data_count; 6258 6259 if (rb->wrpt >= rb->rptr) 6260 data_count = rb->wrpt - rb->rptr; 6261 else 6262 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6263 6264 /* -1 because 1 entry is always unusable */ 6265 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 6266 } 6267 6268 /** 6269 * @brief Pushes a command into the ringbuffer 6270 * 6271 * @param rb DMUB ringbuffer 6272 * @param cmd The command to push 6273 * @return true if the ringbuffer was not full 6274 * @return false otherwise 6275 */ 6276 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 6277 const union dmub_rb_cmd *cmd) 6278 { 6279 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 6280 const uint64_t *src = (const uint64_t *)cmd; 6281 uint8_t i; 6282 6283 if (dmub_rb_full(rb)) 6284 return false; 6285 6286 // copying data 6287 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6288 *dst++ = *src++; 6289 6290 rb->wrpt += DMUB_RB_CMD_SIZE; 6291 6292 if (rb->wrpt >= rb->capacity) 6293 rb->wrpt %= rb->capacity; 6294 6295 return true; 6296 } 6297 6298 /** 6299 * @brief Pushes a command into the DMUB outbox ringbuffer 6300 * 6301 * @param rb DMUB outbox ringbuffer 6302 * @param cmd Outbox command 6303 * @return true if not full 6304 * @return false otherwise 6305 */ 6306 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 6307 const union dmub_rb_out_cmd *cmd) 6308 { 6309 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6310 const uint8_t *src = (const uint8_t *)cmd; 6311 6312 if (dmub_rb_full(rb)) 6313 return false; 6314 6315 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6316 6317 rb->wrpt += DMUB_RB_CMD_SIZE; 6318 6319 if (rb->wrpt >= rb->capacity) 6320 rb->wrpt %= rb->capacity; 6321 6322 return true; 6323 } 6324 6325 /** 6326 * @brief Returns the next unprocessed command in the ringbuffer. 6327 * 6328 * @param rb DMUB ringbuffer 6329 * @param cmd The command to return 6330 * @return true if not empty 6331 * @return false otherwise 6332 */ 6333 static inline bool dmub_rb_front(struct dmub_rb *rb, 6334 union dmub_rb_cmd **cmd) 6335 { 6336 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6337 6338 if (dmub_rb_empty(rb)) 6339 return false; 6340 6341 *cmd = (union dmub_rb_cmd *)rb_cmd; 6342 6343 return true; 6344 } 6345 6346 /** 6347 * @brief Determines the next ringbuffer offset. 6348 * 6349 * @param rb DMUB inbox ringbuffer 6350 * @param num_cmds Number of commands 6351 * @param next_rptr The next offset in the ringbuffer 6352 */ 6353 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6354 uint32_t num_cmds, 6355 uint32_t *next_rptr) 6356 { 6357 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6358 6359 if (*next_rptr >= rb->capacity) 6360 *next_rptr %= rb->capacity; 6361 } 6362 6363 /** 6364 * @brief Returns a pointer to a command in the inbox. 6365 * 6366 * @param rb DMUB inbox ringbuffer 6367 * @param cmd The inbox command to return 6368 * @param rptr The ringbuffer offset 6369 * @return true if not empty 6370 * @return false otherwise 6371 */ 6372 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6373 union dmub_rb_cmd **cmd, 6374 uint32_t rptr) 6375 { 6376 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6377 6378 if (dmub_rb_empty(rb)) 6379 return false; 6380 6381 *cmd = (union dmub_rb_cmd *)rb_cmd; 6382 6383 return true; 6384 } 6385 6386 /** 6387 * @brief Returns the next unprocessed command in the outbox. 6388 * 6389 * @param rb DMUB outbox ringbuffer 6390 * @param cmd The outbox command to return 6391 * @return true if not empty 6392 * @return false otherwise 6393 */ 6394 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6395 union dmub_rb_out_cmd *cmd) 6396 { 6397 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6398 uint64_t *dst = (uint64_t *)cmd; 6399 uint8_t i; 6400 6401 if (dmub_rb_empty(rb)) 6402 return false; 6403 6404 // copying data 6405 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6406 *dst++ = *src++; 6407 6408 return true; 6409 } 6410 6411 /** 6412 * @brief Removes the front entry in the ringbuffer. 6413 * 6414 * @param rb DMUB ringbuffer 6415 * @return true if the command was removed 6416 * @return false if there were no commands 6417 */ 6418 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 6419 { 6420 if (dmub_rb_empty(rb)) 6421 return false; 6422 6423 rb->rptr += DMUB_RB_CMD_SIZE; 6424 6425 if (rb->rptr >= rb->capacity) 6426 rb->rptr %= rb->capacity; 6427 6428 return true; 6429 } 6430 6431 /** 6432 * @brief Flushes commands in the ringbuffer to framebuffer memory. 6433 * 6434 * Avoids a race condition where DMCUB accesses memory while 6435 * there are still writes in flight to framebuffer. 6436 * 6437 * @param rb DMUB ringbuffer 6438 */ 6439 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 6440 { 6441 uint32_t rptr = rb->rptr; 6442 uint32_t wptr = rb->wrpt; 6443 6444 while (rptr != wptr) { 6445 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 6446 uint8_t i; 6447 6448 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6449 (void)READ_ONCE(*data++); 6450 6451 rptr += DMUB_RB_CMD_SIZE; 6452 if (rptr >= rb->capacity) 6453 rptr %= rb->capacity; 6454 } 6455 } 6456 6457 /** 6458 * @brief Initializes a DMCUB ringbuffer 6459 * 6460 * @param rb DMUB ringbuffer 6461 * @param init_params initial configuration for the ringbuffer 6462 */ 6463 static inline void dmub_rb_init(struct dmub_rb *rb, 6464 struct dmub_rb_init_params *init_params) 6465 { 6466 rb->base_address = init_params->base_address; 6467 rb->capacity = init_params->capacity; 6468 rb->rptr = init_params->read_ptr; 6469 rb->wrpt = init_params->write_ptr; 6470 } 6471 6472 /** 6473 * @brief Copies output data from in/out commands into the given command. 6474 * 6475 * @param rb DMUB ringbuffer 6476 * @param cmd Command to copy data into 6477 */ 6478 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 6479 union dmub_rb_cmd *cmd) 6480 { 6481 // Copy rb entry back into command 6482 uint8_t *rd_ptr = (rb->rptr == 0) ? 6483 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 6484 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 6485 6486 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 6487 } 6488 6489 //============================================================================== 6490 //</DMUB_RB>==================================================================== 6491 //============================================================================== 6492 #endif /* _DMUB_CMD_H_ */ 6493