162a37553SKen Wang /* 262a37553SKen Wang * Copyright 2015 Advanced Micro Devices, Inc. 362a37553SKen Wang * 462a37553SKen Wang * Permission is hereby granted, free of charge, to any person obtaining a 562a37553SKen Wang * copy of this software and associated documentation files (the "Software"), 662a37553SKen Wang * to deal in the Software without restriction, including without limitation 762a37553SKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 862a37553SKen Wang * and/or sell copies of the Software, and to permit persons to whom the 962a37553SKen Wang * Software is furnished to do so, subject to the following conditions: 1062a37553SKen Wang * 1162a37553SKen Wang * The above copyright notice and this permission notice shall be included in 1262a37553SKen Wang * all copies or substantial portions of the Software. 1362a37553SKen Wang * 1462a37553SKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1562a37553SKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1662a37553SKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1762a37553SKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1862a37553SKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1962a37553SKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2062a37553SKen Wang * OTHER DEALINGS IN THE SOFTWARE. 2162a37553SKen Wang * 2262a37553SKen Wang */ 2362a37553SKen Wang 2462a37553SKen Wang #include <linux/firmware.h> 2562a37553SKen Wang #include <linux/slab.h> 2662a37553SKen Wang #include <linux/module.h> 2762a37553SKen Wang #include "drmP.h" 2862a37553SKen Wang #include "amdgpu.h" 2962a37553SKen Wang #include "amdgpu_atombios.h" 3062a37553SKen Wang #include "amdgpu_ih.h" 3162a37553SKen Wang #include "amdgpu_uvd.h" 3262a37553SKen Wang #include "amdgpu_vce.h" 3362a37553SKen Wang #include "atom.h" 3462a37553SKen Wang #include "amdgpu_powerplay.h" 3562a37553SKen Wang #include "si/sid.h" 3662a37553SKen Wang #include "si_ih.h" 3762a37553SKen Wang #include "gfx_v6_0.h" 3862a37553SKen Wang #include "gmc_v6_0.h" 3962a37553SKen Wang #include "si_dma.h" 4062a37553SKen Wang #include "dce_v6_0.h" 4162a37553SKen Wang #include "si.h" 422120df47SAlex Deucher #include "dce_virtual.h" 43*78bbe771STom St Denis #include "gca/gfx_6_0_d.h" 44*78bbe771STom St Denis #include "oss/oss_1_0_d.h" 45*78bbe771STom St Denis #include "gmc/gmc_6_0_d.h" 46*78bbe771STom St Denis #include "dce/dce_6_0_d.h" 47*78bbe771STom St Denis #include "uvd/uvd_4_0_d.h" 4862a37553SKen Wang 4962a37553SKen Wang static const u32 tahiti_golden_registers[] = 5062a37553SKen Wang { 51*78bbe771STom St Denis mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 52*78bbe771STom St Denis mmCB_HW_CONTROL, 0x00010000, 0x00018208, 53*78bbe771STom St Denis mmDB_DEBUG, 0xffffffff, 0x00000000, 54*78bbe771STom St Denis mmDB_DEBUG2, 0xf00fffff, 0x00000400, 55*78bbe771STom St Denis mmDB_DEBUG3, 0x0002021c, 0x00020200, 56*78bbe771STom St Denis mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 577c0a705eSFlora Cui 0x340c, 0x000000c0, 0x00800040, 587c0a705eSFlora Cui 0x360c, 0x000000c0, 0x00800040, 59*78bbe771STom St Denis mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 60*78bbe771STom St Denis mmFBC_MISC, 0x00200000, 0x50100000, 61*78bbe771STom St Denis mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 62*78bbe771STom St Denis mmMC_ARB_WTM_CNTL_RD, 0x00000003, 0x000007ff, 63*78bbe771STom St Denis mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 64*78bbe771STom St Denis mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 65*78bbe771STom St Denis mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 66*78bbe771STom St Denis mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 67*78bbe771STom St Denis mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 68*78bbe771STom St Denis mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a, 697c0a705eSFlora Cui 0x000c, 0xffffffff, 0x0040, 7062a37553SKen Wang 0x000d, 0x00000040, 0x00004040, 71*78bbe771STom St Denis mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 72*78bbe771STom St Denis mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000, 73*78bbe771STom St Denis mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000, 74*78bbe771STom St Denis mmSX_DEBUG_1, 0x0000007f, 0x00000020, 75*78bbe771STom St Denis mmTA_CNTL_AUX, 0x00010000, 0x00010000, 76*78bbe771STom St Denis mmTCP_ADDR_CONFIG, 0x00000200, 0x000002fb, 77*78bbe771STom St Denis mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, 78*78bbe771STom St Denis mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, 79*78bbe771STom St Denis mmVGT_FIFO_DEPTHS, 0xffffffff, 0x000fff40, 80*78bbe771STom St Denis mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 81*78bbe771STom St Denis mmVM_CONTEXT0_CNTL, 0x20000000, 0x20fffed8, 82*78bbe771STom St Denis mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 83*78bbe771STom St Denis mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 84*78bbe771STom St Denis mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 85*78bbe771STom St Denis mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 86*78bbe771STom St Denis mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 8762a37553SKen Wang }; 8862a37553SKen Wang 8962a37553SKen Wang static const u32 tahiti_golden_registers2[] = 9062a37553SKen Wang { 91*78bbe771STom St Denis mmMCIF_MEM_CONTROL, 0x00000001, 0x00000001, 9262a37553SKen Wang }; 9362a37553SKen Wang 9462a37553SKen Wang static const u32 tahiti_golden_rlc_registers[] = 9562a37553SKen Wang { 96*78bbe771STom St Denis mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003, 97*78bbe771STom St Denis mmRLC_LB_PARAMS, 0xffffffff, 0x00601005, 9862a37553SKen Wang 0x311f, 0xffffffff, 0x10104040, 9962a37553SKen Wang 0x3122, 0xffffffff, 0x0100000a, 100*78bbe771STom St Denis mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 101*78bbe771STom St Denis mmRLC_LB_CNTL, 0xffffffff, 0x800000f4, 102*78bbe771STom St Denis mmUVD_CGC_GATE, 0x00000008, 0x00000000, 10362a37553SKen Wang }; 10462a37553SKen Wang 10562a37553SKen Wang static const u32 pitcairn_golden_registers[] = 10662a37553SKen Wang { 107*78bbe771STom St Denis mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 108*78bbe771STom St Denis mmCB_HW_CONTROL, 0x00010000, 0x00018208, 109*78bbe771STom St Denis mmDB_DEBUG, 0xffffffff, 0x00000000, 110*78bbe771STom St Denis mmDB_DEBUG2, 0xf00fffff, 0x00000400, 111*78bbe771STom St Denis mmDB_DEBUG3, 0x0002021c, 0x00020200, 112*78bbe771STom St Denis mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 11362a37553SKen Wang 0x340c, 0x000300c0, 0x00800040, 11462a37553SKen Wang 0x360c, 0x000300c0, 0x00800040, 115*78bbe771STom St Denis mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 116*78bbe771STom St Denis mmFBC_MISC, 0x00200000, 0x50100000, 117*78bbe771STom St Denis mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 118*78bbe771STom St Denis mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 119*78bbe771STom St Denis mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 120*78bbe771STom St Denis mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 121*78bbe771STom St Denis mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 122*78bbe771STom St Denis mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 123*78bbe771STom St Denis mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 124*78bbe771STom St Denis mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a, 1251245a694SFlora Cui 0x000c, 0xffffffff, 0x0040, 12662a37553SKen Wang 0x000d, 0x00000040, 0x00004040, 127*78bbe771STom St Denis mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 128*78bbe771STom St Denis mmSX_DEBUG_1, 0x0000007f, 0x00000020, 129*78bbe771STom St Denis mmTA_CNTL_AUX, 0x00010000, 0x00010000, 130*78bbe771STom St Denis mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7, 131*78bbe771STom St Denis mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 132*78bbe771STom St Denis mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054, 133*78bbe771STom St Denis mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 134*78bbe771STom St Denis mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 135*78bbe771STom St Denis mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 136*78bbe771STom St Denis mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 137*78bbe771STom St Denis mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 138*78bbe771STom St Denis mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 13962a37553SKen Wang }; 14062a37553SKen Wang 14162a37553SKen Wang static const u32 pitcairn_golden_rlc_registers[] = 14262a37553SKen Wang { 143*78bbe771STom St Denis mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003, 144*78bbe771STom St Denis mmRLC_LB_PARAMS, 0xffffffff, 0x00601004, 14562a37553SKen Wang 0x311f, 0xffffffff, 0x10102020, 14662a37553SKen Wang 0x3122, 0xffffffff, 0x01000020, 147*78bbe771STom St Denis mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 148*78bbe771STom St Denis mmRLC_LB_CNTL, 0xffffffff, 0x800000a4, 14962a37553SKen Wang }; 15062a37553SKen Wang 15162a37553SKen Wang static const u32 verde_pg_init[] = 15262a37553SKen Wang { 153*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x40000, 154*78bbe771STom St Denis mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x200010ff, 155*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 156*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 157*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 158*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 159*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 160*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x7007, 161*78bbe771STom St Denis mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x300010ff, 162*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 163*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 164*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 165*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 166*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 167*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x400000, 168*78bbe771STom St Denis mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x100010ff, 169*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 170*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 171*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 172*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 173*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 174*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x120200, 175*78bbe771STom St Denis mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x500010ff, 176*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 177*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 178*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 179*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 180*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 181*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x1e1e16, 182*78bbe771STom St Denis mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x600010ff, 183*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 184*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 185*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 186*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 187*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 188*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x171f1e, 189*78bbe771STom St Denis mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x700010ff, 190*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 191*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 192*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 193*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 194*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 195*78bbe771STom St Denis mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 196*78bbe771STom St Denis mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x9ff, 197*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x0, 198*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10000800, 199*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf, 200*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf, 201*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4, 202*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1000051e, 203*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff, 204*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff, 205*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x8, 206*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x80500, 207*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x12, 208*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x9050c, 209*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1d, 210*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xb052c, 211*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2a, 212*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1053e, 213*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2d, 214*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10546, 215*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x30, 216*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xa054e, 217*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3c, 218*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1055f, 219*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3f, 220*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10567, 221*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x42, 222*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1056f, 223*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x45, 224*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10572, 225*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x48, 226*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20575, 227*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4c, 228*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x190801, 229*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x67, 230*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1082a, 231*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x6a, 232*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1b082d, 233*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x87, 234*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x310851, 235*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xba, 236*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x891, 237*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbc, 238*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x893, 239*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbe, 240*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20895, 241*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc2, 242*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20899, 243*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc6, 244*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2089d, 245*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xca, 246*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a1, 247*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xcc, 248*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a3, 249*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xce, 250*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x308a5, 251*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xd3, 252*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x6d08cd, 253*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x142, 254*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2000095a, 255*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1, 256*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x144, 257*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x301f095b, 258*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x165, 259*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc094d, 260*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x173, 261*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf096d, 262*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x184, 263*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x15097f, 264*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x19b, 265*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc0998, 266*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1a9, 267*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x409a7, 268*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1af, 269*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xcdc, 270*78bbe771STom St Denis mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1b1, 271*78bbe771STom St Denis mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x800, 272*78bbe771STom St Denis mmGMCON_RENG_EXECUTE, 0xffffffff, 0x6c9b2000, 273*78bbe771STom St Denis mmGMCON_MISC2, 0xfc00, 0x2000, 274*78bbe771STom St Denis mmGMCON_MISC3, 0xffffffff, 0xfc0, 275*78bbe771STom St Denis mmMC_PMG_AUTO_CFG, 0x00000100, 0x100, 27662a37553SKen Wang }; 27762a37553SKen Wang 27862a37553SKen Wang static const u32 verde_golden_rlc_registers[] = 27962a37553SKen Wang { 280*78bbe771STom St Denis mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002, 281*78bbe771STom St Denis mmRLC_LB_PARAMS, 0xffffffff, 0x033f1005, 28262a37553SKen Wang 0x311f, 0xffffffff, 0x10808020, 28362a37553SKen Wang 0x3122, 0xffffffff, 0x00800008, 284*78bbe771STom St Denis mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00001000, 285*78bbe771STom St Denis mmRLC_LB_CNTL, 0xffffffff, 0x80010014, 28662a37553SKen Wang }; 28762a37553SKen Wang 28862a37553SKen Wang static const u32 verde_golden_registers[] = 28962a37553SKen Wang { 290*78bbe771STom St Denis mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 291*78bbe771STom St Denis mmCB_HW_CONTROL, 0x00010000, 0x00018208, 292*78bbe771STom St Denis mmDB_DEBUG, 0xffffffff, 0x00000000, 293*78bbe771STom St Denis mmDB_DEBUG2, 0xf00fffff, 0x00000400, 294*78bbe771STom St Denis mmDB_DEBUG3, 0x0002021c, 0x00020200, 295*78bbe771STom St Denis mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 29662a37553SKen Wang 0x340c, 0x000300c0, 0x00800040, 29762a37553SKen Wang 0x360c, 0x000300c0, 0x00800040, 298*78bbe771STom St Denis mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 299*78bbe771STom St Denis mmFBC_MISC, 0x00200000, 0x50100000, 300*78bbe771STom St Denis mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 301*78bbe771STom St Denis mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 302*78bbe771STom St Denis mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 303*78bbe771STom St Denis mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 304*78bbe771STom St Denis mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 305*78bbe771STom St Denis mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 306*78bbe771STom St Denis mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 307*78bbe771STom St Denis mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x0000124a, 308dae5c298SFlora Cui 0x000c, 0xffffffff, 0x0040, 30962a37553SKen Wang 0x000d, 0x00000040, 0x00004040, 310*78bbe771STom St Denis mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 311*78bbe771STom St Denis mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000, 312*78bbe771STom St Denis mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000, 313*78bbe771STom St Denis mmSX_DEBUG_1, 0x0000007f, 0x00000020, 314*78bbe771STom St Denis mmTA_CNTL_AUX, 0x00010000, 0x00010000, 315*78bbe771STom St Denis mmTCP_ADDR_CONFIG, 0x000003ff, 0x00000003, 316*78bbe771STom St Denis mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 317*78bbe771STom St Denis mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001032, 318*78bbe771STom St Denis mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 319*78bbe771STom St Denis mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 320*78bbe771STom St Denis mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 321*78bbe771STom St Denis mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 322*78bbe771STom St Denis mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 323*78bbe771STom St Denis mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 32462a37553SKen Wang }; 32562a37553SKen Wang 32662a37553SKen Wang static const u32 oland_golden_registers[] = 32762a37553SKen Wang { 328*78bbe771STom St Denis mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 329*78bbe771STom St Denis mmCB_HW_CONTROL, 0x00010000, 0x00018208, 330*78bbe771STom St Denis mmDB_DEBUG, 0xffffffff, 0x00000000, 331*78bbe771STom St Denis mmDB_DEBUG2, 0xf00fffff, 0x00000400, 332*78bbe771STom St Denis mmDB_DEBUG3, 0x0002021c, 0x00020200, 333*78bbe771STom St Denis mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 33462a37553SKen Wang 0x340c, 0x000300c0, 0x00800040, 33562a37553SKen Wang 0x360c, 0x000300c0, 0x00800040, 336*78bbe771STom St Denis mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 337*78bbe771STom St Denis mmFBC_MISC, 0x00200000, 0x50100000, 338*78bbe771STom St Denis mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 339*78bbe771STom St Denis mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 340*78bbe771STom St Denis mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 341*78bbe771STom St Denis mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 342*78bbe771STom St Denis mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 343*78bbe771STom St Denis mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 344*78bbe771STom St Denis mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 345*78bbe771STom St Denis mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000082, 3466b7985efSFlora Cui 0x000c, 0xffffffff, 0x0040, 34762a37553SKen Wang 0x000d, 0x00000040, 0x00004040, 348*78bbe771STom St Denis mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 349*78bbe771STom St Denis mmSX_DEBUG_1, 0x0000007f, 0x00000020, 350*78bbe771STom St Denis mmTA_CNTL_AUX, 0x00010000, 0x00010000, 351*78bbe771STom St Denis mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3, 352*78bbe771STom St Denis mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 353*78bbe771STom St Denis mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, 354*78bbe771STom St Denis mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 355*78bbe771STom St Denis mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 356*78bbe771STom St Denis mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 357*78bbe771STom St Denis mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 358*78bbe771STom St Denis mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 359*78bbe771STom St Denis mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 360*78bbe771STom St Denis 36162a37553SKen Wang }; 36262a37553SKen Wang 36362a37553SKen Wang static const u32 oland_golden_rlc_registers[] = 36462a37553SKen Wang { 365*78bbe771STom St Denis mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002, 366*78bbe771STom St Denis mmRLC_LB_PARAMS, 0xffffffff, 0x00601005, 36762a37553SKen Wang 0x311f, 0xffffffff, 0x10104040, 36862a37553SKen Wang 0x3122, 0xffffffff, 0x0100000a, 369*78bbe771STom St Denis mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 370*78bbe771STom St Denis mmRLC_LB_CNTL, 0xffffffff, 0x800000f4, 37162a37553SKen Wang }; 37262a37553SKen Wang 37362a37553SKen Wang static const u32 hainan_golden_registers[] = 37462a37553SKen Wang { 375bd27b678SFlora Cui 0x17bc, 0x00000030, 0x00000011, 376*78bbe771STom St Denis mmCB_HW_CONTROL, 0x00010000, 0x00018208, 377*78bbe771STom St Denis mmDB_DEBUG, 0xffffffff, 0x00000000, 378*78bbe771STom St Denis mmDB_DEBUG2, 0xf00fffff, 0x00000400, 379*78bbe771STom St Denis mmDB_DEBUG3, 0x0002021c, 0x00020200, 380bd27b678SFlora Cui 0x031e, 0x00000080, 0x00000000, 381bd27b678SFlora Cui 0x3430, 0xff000fff, 0x00000100, 38262a37553SKen Wang 0x340c, 0x000300c0, 0x00800040, 38362a37553SKen Wang 0x3630, 0xff000fff, 0x00000100, 38462a37553SKen Wang 0x360c, 0x000300c0, 0x00800040, 385bd27b678SFlora Cui 0x16ec, 0x000000f0, 0x00000070, 386bd27b678SFlora Cui 0x16f0, 0x00200000, 0x50100000, 387bd27b678SFlora Cui 0x1c0c, 0x31000311, 0x00000011, 388*78bbe771STom St Denis mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 389*78bbe771STom St Denis mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 390*78bbe771STom St Denis mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 391*78bbe771STom St Denis mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 392*78bbe771STom St Denis mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 393*78bbe771STom St Denis mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 394*78bbe771STom St Denis mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000000, 395bd27b678SFlora Cui 0x000c, 0xffffffff, 0x0040, 39662a37553SKen Wang 0x000d, 0x00000040, 0x00004040, 397*78bbe771STom St Denis mmSPI_CONFIG_CNTL, 0x03e00000, 0x03600000, 398*78bbe771STom St Denis mmSX_DEBUG_1, 0x0000007f, 0x00000020, 399*78bbe771STom St Denis mmTA_CNTL_AUX, 0x00010000, 0x00010000, 400*78bbe771STom St Denis mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, 401*78bbe771STom St Denis mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 402*78bbe771STom St Denis mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, 403*78bbe771STom St Denis mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 404*78bbe771STom St Denis mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 405*78bbe771STom St Denis mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 406*78bbe771STom St Denis mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 407*78bbe771STom St Denis mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 408*78bbe771STom St Denis mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 40962a37553SKen Wang }; 41062a37553SKen Wang 41162a37553SKen Wang static const u32 hainan_golden_registers2[] = 41262a37553SKen Wang { 413*78bbe771STom St Denis mmGB_ADDR_CONFIG, 0xffffffff, 0x2011003, 41462a37553SKen Wang }; 41562a37553SKen Wang 41662a37553SKen Wang static const u32 tahiti_mgcg_cgcg_init[] = 41762a37553SKen Wang { 418*78bbe771STom St Denis mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 419*78bbe771STom St Denis mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 420*78bbe771STom St Denis mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 421*78bbe771STom St Denis mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 422*78bbe771STom St Denis mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 423*78bbe771STom St Denis mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 424*78bbe771STom St Denis mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 425*78bbe771STom St Denis mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 426*78bbe771STom St Denis mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 427*78bbe771STom St Denis mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 428*78bbe771STom St Denis mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 429*78bbe771STom St Denis mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 430*78bbe771STom St Denis mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 431*78bbe771STom St Denis mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 432*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 433*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 434*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 435*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 436*78bbe771STom St Denis mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 437*78bbe771STom St Denis mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 438*78bbe771STom St Denis mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 439*78bbe771STom St Denis mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 440*78bbe771STom St Denis mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 441*78bbe771STom St Denis mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 442*78bbe771STom St Denis mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 443*78bbe771STom St Denis mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 444*78bbe771STom St Denis mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 44562a37553SKen Wang 0x2458, 0xffffffff, 0x00010000, 44662a37553SKen Wang 0x2459, 0xffffffff, 0x00030002, 44762a37553SKen Wang 0x245a, 0xffffffff, 0x00040007, 44862a37553SKen Wang 0x245b, 0xffffffff, 0x00060005, 44962a37553SKen Wang 0x245c, 0xffffffff, 0x00090008, 45062a37553SKen Wang 0x245d, 0xffffffff, 0x00020001, 45162a37553SKen Wang 0x245e, 0xffffffff, 0x00040003, 45262a37553SKen Wang 0x245f, 0xffffffff, 0x00000007, 45362a37553SKen Wang 0x2460, 0xffffffff, 0x00060005, 45462a37553SKen Wang 0x2461, 0xffffffff, 0x00090008, 45562a37553SKen Wang 0x2462, 0xffffffff, 0x00030002, 45662a37553SKen Wang 0x2463, 0xffffffff, 0x00050004, 45762a37553SKen Wang 0x2464, 0xffffffff, 0x00000008, 45862a37553SKen Wang 0x2465, 0xffffffff, 0x00070006, 45962a37553SKen Wang 0x2466, 0xffffffff, 0x000a0009, 46062a37553SKen Wang 0x2467, 0xffffffff, 0x00040003, 46162a37553SKen Wang 0x2468, 0xffffffff, 0x00060005, 46262a37553SKen Wang 0x2469, 0xffffffff, 0x00000009, 46362a37553SKen Wang 0x246a, 0xffffffff, 0x00080007, 46462a37553SKen Wang 0x246b, 0xffffffff, 0x000b000a, 46562a37553SKen Wang 0x246c, 0xffffffff, 0x00050004, 46662a37553SKen Wang 0x246d, 0xffffffff, 0x00070006, 46762a37553SKen Wang 0x246e, 0xffffffff, 0x0008000b, 46862a37553SKen Wang 0x246f, 0xffffffff, 0x000a0009, 46962a37553SKen Wang 0x2470, 0xffffffff, 0x000d000c, 47062a37553SKen Wang 0x2471, 0xffffffff, 0x00060005, 47162a37553SKen Wang 0x2472, 0xffffffff, 0x00080007, 47262a37553SKen Wang 0x2473, 0xffffffff, 0x0000000b, 47362a37553SKen Wang 0x2474, 0xffffffff, 0x000a0009, 47462a37553SKen Wang 0x2475, 0xffffffff, 0x000d000c, 47562a37553SKen Wang 0x2476, 0xffffffff, 0x00070006, 47662a37553SKen Wang 0x2477, 0xffffffff, 0x00090008, 47762a37553SKen Wang 0x2478, 0xffffffff, 0x0000000c, 47862a37553SKen Wang 0x2479, 0xffffffff, 0x000b000a, 47962a37553SKen Wang 0x247a, 0xffffffff, 0x000e000d, 48062a37553SKen Wang 0x247b, 0xffffffff, 0x00080007, 48162a37553SKen Wang 0x247c, 0xffffffff, 0x000a0009, 48262a37553SKen Wang 0x247d, 0xffffffff, 0x0000000d, 48362a37553SKen Wang 0x247e, 0xffffffff, 0x000c000b, 48462a37553SKen Wang 0x247f, 0xffffffff, 0x000f000e, 48562a37553SKen Wang 0x2480, 0xffffffff, 0x00090008, 48662a37553SKen Wang 0x2481, 0xffffffff, 0x000b000a, 48762a37553SKen Wang 0x2482, 0xffffffff, 0x000c000f, 48862a37553SKen Wang 0x2483, 0xffffffff, 0x000e000d, 48962a37553SKen Wang 0x2484, 0xffffffff, 0x00110010, 49062a37553SKen Wang 0x2485, 0xffffffff, 0x000a0009, 49162a37553SKen Wang 0x2486, 0xffffffff, 0x000c000b, 49262a37553SKen Wang 0x2487, 0xffffffff, 0x0000000f, 49362a37553SKen Wang 0x2488, 0xffffffff, 0x000e000d, 49462a37553SKen Wang 0x2489, 0xffffffff, 0x00110010, 49562a37553SKen Wang 0x248a, 0xffffffff, 0x000b000a, 49662a37553SKen Wang 0x248b, 0xffffffff, 0x000d000c, 49762a37553SKen Wang 0x248c, 0xffffffff, 0x00000010, 49862a37553SKen Wang 0x248d, 0xffffffff, 0x000f000e, 49962a37553SKen Wang 0x248e, 0xffffffff, 0x00120011, 50062a37553SKen Wang 0x248f, 0xffffffff, 0x000c000b, 50162a37553SKen Wang 0x2490, 0xffffffff, 0x000e000d, 50262a37553SKen Wang 0x2491, 0xffffffff, 0x00000011, 50362a37553SKen Wang 0x2492, 0xffffffff, 0x0010000f, 50462a37553SKen Wang 0x2493, 0xffffffff, 0x00130012, 50562a37553SKen Wang 0x2494, 0xffffffff, 0x000d000c, 50662a37553SKen Wang 0x2495, 0xffffffff, 0x000f000e, 50762a37553SKen Wang 0x2496, 0xffffffff, 0x00100013, 50862a37553SKen Wang 0x2497, 0xffffffff, 0x00120011, 50962a37553SKen Wang 0x2498, 0xffffffff, 0x00150014, 51062a37553SKen Wang 0x2499, 0xffffffff, 0x000e000d, 51162a37553SKen Wang 0x249a, 0xffffffff, 0x0010000f, 51262a37553SKen Wang 0x249b, 0xffffffff, 0x00000013, 51362a37553SKen Wang 0x249c, 0xffffffff, 0x00120011, 51462a37553SKen Wang 0x249d, 0xffffffff, 0x00150014, 51562a37553SKen Wang 0x249e, 0xffffffff, 0x000f000e, 51662a37553SKen Wang 0x249f, 0xffffffff, 0x00110010, 51762a37553SKen Wang 0x24a0, 0xffffffff, 0x00000014, 51862a37553SKen Wang 0x24a1, 0xffffffff, 0x00130012, 51962a37553SKen Wang 0x24a2, 0xffffffff, 0x00160015, 52062a37553SKen Wang 0x24a3, 0xffffffff, 0x0010000f, 52162a37553SKen Wang 0x24a4, 0xffffffff, 0x00120011, 52262a37553SKen Wang 0x24a5, 0xffffffff, 0x00000015, 52362a37553SKen Wang 0x24a6, 0xffffffff, 0x00140013, 52462a37553SKen Wang 0x24a7, 0xffffffff, 0x00170016, 525*78bbe771STom St Denis mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 526*78bbe771STom St Denis mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 527*78bbe771STom St Denis mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 528*78bbe771STom St Denis mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 5297c0a705eSFlora Cui 0x000c, 0xffffffff, 0x0000001c, 5307c0a705eSFlora Cui 0x000d, 0x000f0000, 0x000f0000, 5317c0a705eSFlora Cui 0x0583, 0xffffffff, 0x00000100, 532*78bbe771STom St Denis mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 533*78bbe771STom St Denis mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 534*78bbe771STom St Denis mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 535*78bbe771STom St Denis mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 536*78bbe771STom St Denis mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 537*78bbe771STom St Denis mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 53862a37553SKen Wang 0x157a, 0x00000001, 0x00000001, 539*78bbe771STom St Denis mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 540*78bbe771STom St Denis mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 541*78bbe771STom St Denis mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 54262a37553SKen Wang 0x3430, 0xfffffff0, 0x00000100, 543*78bbe771STom St Denis 0x3630, 0xfffffff0, 0x00000100, 54462a37553SKen Wang }; 54562a37553SKen Wang static const u32 pitcairn_mgcg_cgcg_init[] = 54662a37553SKen Wang { 547*78bbe771STom St Denis mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 548*78bbe771STom St Denis mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 549*78bbe771STom St Denis mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 550*78bbe771STom St Denis mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 551*78bbe771STom St Denis mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 552*78bbe771STom St Denis mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 553*78bbe771STom St Denis mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 554*78bbe771STom St Denis mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 555*78bbe771STom St Denis mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 556*78bbe771STom St Denis mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 557*78bbe771STom St Denis mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 558*78bbe771STom St Denis mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 559*78bbe771STom St Denis mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 560*78bbe771STom St Denis mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 561*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 562*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 563*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 564*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 565*78bbe771STom St Denis mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 566*78bbe771STom St Denis mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 567*78bbe771STom St Denis mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 568*78bbe771STom St Denis mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 569*78bbe771STom St Denis mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 570*78bbe771STom St Denis mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 571*78bbe771STom St Denis mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 572*78bbe771STom St Denis mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 573*78bbe771STom St Denis mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 57462a37553SKen Wang 0x2458, 0xffffffff, 0x00010000, 57562a37553SKen Wang 0x2459, 0xffffffff, 0x00030002, 57662a37553SKen Wang 0x245a, 0xffffffff, 0x00040007, 57762a37553SKen Wang 0x245b, 0xffffffff, 0x00060005, 57862a37553SKen Wang 0x245c, 0xffffffff, 0x00090008, 57962a37553SKen Wang 0x245d, 0xffffffff, 0x00020001, 58062a37553SKen Wang 0x245e, 0xffffffff, 0x00040003, 58162a37553SKen Wang 0x245f, 0xffffffff, 0x00000007, 58262a37553SKen Wang 0x2460, 0xffffffff, 0x00060005, 58362a37553SKen Wang 0x2461, 0xffffffff, 0x00090008, 58462a37553SKen Wang 0x2462, 0xffffffff, 0x00030002, 58562a37553SKen Wang 0x2463, 0xffffffff, 0x00050004, 58662a37553SKen Wang 0x2464, 0xffffffff, 0x00000008, 58762a37553SKen Wang 0x2465, 0xffffffff, 0x00070006, 58862a37553SKen Wang 0x2466, 0xffffffff, 0x000a0009, 58962a37553SKen Wang 0x2467, 0xffffffff, 0x00040003, 59062a37553SKen Wang 0x2468, 0xffffffff, 0x00060005, 59162a37553SKen Wang 0x2469, 0xffffffff, 0x00000009, 59262a37553SKen Wang 0x246a, 0xffffffff, 0x00080007, 59362a37553SKen Wang 0x246b, 0xffffffff, 0x000b000a, 59462a37553SKen Wang 0x246c, 0xffffffff, 0x00050004, 59562a37553SKen Wang 0x246d, 0xffffffff, 0x00070006, 59662a37553SKen Wang 0x246e, 0xffffffff, 0x0008000b, 59762a37553SKen Wang 0x246f, 0xffffffff, 0x000a0009, 59862a37553SKen Wang 0x2470, 0xffffffff, 0x000d000c, 59962a37553SKen Wang 0x2480, 0xffffffff, 0x00090008, 60062a37553SKen Wang 0x2481, 0xffffffff, 0x000b000a, 60162a37553SKen Wang 0x2482, 0xffffffff, 0x000c000f, 60262a37553SKen Wang 0x2483, 0xffffffff, 0x000e000d, 60362a37553SKen Wang 0x2484, 0xffffffff, 0x00110010, 60462a37553SKen Wang 0x2485, 0xffffffff, 0x000a0009, 60562a37553SKen Wang 0x2486, 0xffffffff, 0x000c000b, 60662a37553SKen Wang 0x2487, 0xffffffff, 0x0000000f, 60762a37553SKen Wang 0x2488, 0xffffffff, 0x000e000d, 60862a37553SKen Wang 0x2489, 0xffffffff, 0x00110010, 60962a37553SKen Wang 0x248a, 0xffffffff, 0x000b000a, 61062a37553SKen Wang 0x248b, 0xffffffff, 0x000d000c, 61162a37553SKen Wang 0x248c, 0xffffffff, 0x00000010, 61262a37553SKen Wang 0x248d, 0xffffffff, 0x000f000e, 61362a37553SKen Wang 0x248e, 0xffffffff, 0x00120011, 61462a37553SKen Wang 0x248f, 0xffffffff, 0x000c000b, 61562a37553SKen Wang 0x2490, 0xffffffff, 0x000e000d, 61662a37553SKen Wang 0x2491, 0xffffffff, 0x00000011, 61762a37553SKen Wang 0x2492, 0xffffffff, 0x0010000f, 61862a37553SKen Wang 0x2493, 0xffffffff, 0x00130012, 61962a37553SKen Wang 0x2494, 0xffffffff, 0x000d000c, 62062a37553SKen Wang 0x2495, 0xffffffff, 0x000f000e, 62162a37553SKen Wang 0x2496, 0xffffffff, 0x00100013, 62262a37553SKen Wang 0x2497, 0xffffffff, 0x00120011, 62362a37553SKen Wang 0x2498, 0xffffffff, 0x00150014, 624*78bbe771STom St Denis mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 625*78bbe771STom St Denis mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 626*78bbe771STom St Denis mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 627*78bbe771STom St Denis mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 6281245a694SFlora Cui 0x000c, 0xffffffff, 0x0000001c, 6291245a694SFlora Cui 0x000d, 0x000f0000, 0x000f0000, 6301245a694SFlora Cui 0x0583, 0xffffffff, 0x00000100, 631*78bbe771STom St Denis mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 632*78bbe771STom St Denis mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 633*78bbe771STom St Denis mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 634*78bbe771STom St Denis mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 63562a37553SKen Wang 0x157a, 0x00000001, 0x00000001, 636*78bbe771STom St Denis mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 637*78bbe771STom St Denis mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 638*78bbe771STom St Denis mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 63962a37553SKen Wang 0x3430, 0xfffffff0, 0x00000100, 640*78bbe771STom St Denis 0x3630, 0xfffffff0, 0x00000100, 64162a37553SKen Wang }; 642*78bbe771STom St Denis 64362a37553SKen Wang static const u32 verde_mgcg_cgcg_init[] = 64462a37553SKen Wang { 645*78bbe771STom St Denis mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 646*78bbe771STom St Denis mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 647*78bbe771STom St Denis mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 648*78bbe771STom St Denis mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 649*78bbe771STom St Denis mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 650*78bbe771STom St Denis mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 651*78bbe771STom St Denis mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 652*78bbe771STom St Denis mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 653*78bbe771STom St Denis mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 654*78bbe771STom St Denis mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 655*78bbe771STom St Denis mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 656*78bbe771STom St Denis mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 657*78bbe771STom St Denis mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 658*78bbe771STom St Denis mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 659*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 660*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 661*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 662*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 663*78bbe771STom St Denis mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 664*78bbe771STom St Denis mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 665*78bbe771STom St Denis mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 666*78bbe771STom St Denis mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 667*78bbe771STom St Denis mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 668*78bbe771STom St Denis mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 669*78bbe771STom St Denis mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 670*78bbe771STom St Denis mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 671*78bbe771STom St Denis mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 67262a37553SKen Wang 0x2458, 0xffffffff, 0x00010000, 67362a37553SKen Wang 0x2459, 0xffffffff, 0x00030002, 67462a37553SKen Wang 0x245a, 0xffffffff, 0x00040007, 67562a37553SKen Wang 0x245b, 0xffffffff, 0x00060005, 67662a37553SKen Wang 0x245c, 0xffffffff, 0x00090008, 67762a37553SKen Wang 0x245d, 0xffffffff, 0x00020001, 67862a37553SKen Wang 0x245e, 0xffffffff, 0x00040003, 67962a37553SKen Wang 0x245f, 0xffffffff, 0x00000007, 68062a37553SKen Wang 0x2460, 0xffffffff, 0x00060005, 68162a37553SKen Wang 0x2461, 0xffffffff, 0x00090008, 68262a37553SKen Wang 0x2462, 0xffffffff, 0x00030002, 68362a37553SKen Wang 0x2463, 0xffffffff, 0x00050004, 68462a37553SKen Wang 0x2464, 0xffffffff, 0x00000008, 68562a37553SKen Wang 0x2465, 0xffffffff, 0x00070006, 68662a37553SKen Wang 0x2466, 0xffffffff, 0x000a0009, 68762a37553SKen Wang 0x2467, 0xffffffff, 0x00040003, 68862a37553SKen Wang 0x2468, 0xffffffff, 0x00060005, 68962a37553SKen Wang 0x2469, 0xffffffff, 0x00000009, 69062a37553SKen Wang 0x246a, 0xffffffff, 0x00080007, 69162a37553SKen Wang 0x246b, 0xffffffff, 0x000b000a, 69262a37553SKen Wang 0x246c, 0xffffffff, 0x00050004, 69362a37553SKen Wang 0x246d, 0xffffffff, 0x00070006, 69462a37553SKen Wang 0x246e, 0xffffffff, 0x0008000b, 69562a37553SKen Wang 0x246f, 0xffffffff, 0x000a0009, 69662a37553SKen Wang 0x2470, 0xffffffff, 0x000d000c, 69762a37553SKen Wang 0x2480, 0xffffffff, 0x00090008, 69862a37553SKen Wang 0x2481, 0xffffffff, 0x000b000a, 69962a37553SKen Wang 0x2482, 0xffffffff, 0x000c000f, 70062a37553SKen Wang 0x2483, 0xffffffff, 0x000e000d, 70162a37553SKen Wang 0x2484, 0xffffffff, 0x00110010, 70262a37553SKen Wang 0x2485, 0xffffffff, 0x000a0009, 70362a37553SKen Wang 0x2486, 0xffffffff, 0x000c000b, 70462a37553SKen Wang 0x2487, 0xffffffff, 0x0000000f, 70562a37553SKen Wang 0x2488, 0xffffffff, 0x000e000d, 70662a37553SKen Wang 0x2489, 0xffffffff, 0x00110010, 70762a37553SKen Wang 0x248a, 0xffffffff, 0x000b000a, 70862a37553SKen Wang 0x248b, 0xffffffff, 0x000d000c, 70962a37553SKen Wang 0x248c, 0xffffffff, 0x00000010, 71062a37553SKen Wang 0x248d, 0xffffffff, 0x000f000e, 71162a37553SKen Wang 0x248e, 0xffffffff, 0x00120011, 71262a37553SKen Wang 0x248f, 0xffffffff, 0x000c000b, 71362a37553SKen Wang 0x2490, 0xffffffff, 0x000e000d, 71462a37553SKen Wang 0x2491, 0xffffffff, 0x00000011, 71562a37553SKen Wang 0x2492, 0xffffffff, 0x0010000f, 71662a37553SKen Wang 0x2493, 0xffffffff, 0x00130012, 71762a37553SKen Wang 0x2494, 0xffffffff, 0x000d000c, 71862a37553SKen Wang 0x2495, 0xffffffff, 0x000f000e, 71962a37553SKen Wang 0x2496, 0xffffffff, 0x00100013, 72062a37553SKen Wang 0x2497, 0xffffffff, 0x00120011, 72162a37553SKen Wang 0x2498, 0xffffffff, 0x00150014, 722*78bbe771STom St Denis mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 723*78bbe771STom St Denis mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 724*78bbe771STom St Denis mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 725*78bbe771STom St Denis mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 726dae5c298SFlora Cui 0x000c, 0xffffffff, 0x0000001c, 727dae5c298SFlora Cui 0x000d, 0x000f0000, 0x000f0000, 728dae5c298SFlora Cui 0x0583, 0xffffffff, 0x00000100, 729*78bbe771STom St Denis mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 730*78bbe771STom St Denis mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 731*78bbe771STom St Denis mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 732*78bbe771STom St Denis mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 733*78bbe771STom St Denis mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 734*78bbe771STom St Denis mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 73562a37553SKen Wang 0x157a, 0x00000001, 0x00000001, 736*78bbe771STom St Denis mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 737*78bbe771STom St Denis mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 738*78bbe771STom St Denis mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 73962a37553SKen Wang 0x3430, 0xfffffff0, 0x00000100, 740*78bbe771STom St Denis 0x3630, 0xfffffff0, 0x00000100, 74162a37553SKen Wang }; 742*78bbe771STom St Denis 74362a37553SKen Wang static const u32 oland_mgcg_cgcg_init[] = 74462a37553SKen Wang { 745*78bbe771STom St Denis mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 746*78bbe771STom St Denis mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 747*78bbe771STom St Denis mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 748*78bbe771STom St Denis mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 749*78bbe771STom St Denis mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 750*78bbe771STom St Denis mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 751*78bbe771STom St Denis mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 752*78bbe771STom St Denis mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 753*78bbe771STom St Denis mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 754*78bbe771STom St Denis mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 755*78bbe771STom St Denis mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 756*78bbe771STom St Denis mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 757*78bbe771STom St Denis mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 758*78bbe771STom St Denis mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 759*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 760*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 761*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 762*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 763*78bbe771STom St Denis mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 764*78bbe771STom St Denis mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 765*78bbe771STom St Denis mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 766*78bbe771STom St Denis mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 767*78bbe771STom St Denis mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 768*78bbe771STom St Denis mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 769*78bbe771STom St Denis mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 770*78bbe771STom St Denis mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 771*78bbe771STom St Denis mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 77262a37553SKen Wang 0x2458, 0xffffffff, 0x00010000, 77362a37553SKen Wang 0x2459, 0xffffffff, 0x00030002, 77462a37553SKen Wang 0x245a, 0xffffffff, 0x00040007, 77562a37553SKen Wang 0x245b, 0xffffffff, 0x00060005, 77662a37553SKen Wang 0x245c, 0xffffffff, 0x00090008, 77762a37553SKen Wang 0x245d, 0xffffffff, 0x00020001, 77862a37553SKen Wang 0x245e, 0xffffffff, 0x00040003, 77962a37553SKen Wang 0x245f, 0xffffffff, 0x00000007, 78062a37553SKen Wang 0x2460, 0xffffffff, 0x00060005, 78162a37553SKen Wang 0x2461, 0xffffffff, 0x00090008, 78262a37553SKen Wang 0x2462, 0xffffffff, 0x00030002, 78362a37553SKen Wang 0x2463, 0xffffffff, 0x00050004, 78462a37553SKen Wang 0x2464, 0xffffffff, 0x00000008, 78562a37553SKen Wang 0x2465, 0xffffffff, 0x00070006, 78662a37553SKen Wang 0x2466, 0xffffffff, 0x000a0009, 78762a37553SKen Wang 0x2467, 0xffffffff, 0x00040003, 78862a37553SKen Wang 0x2468, 0xffffffff, 0x00060005, 78962a37553SKen Wang 0x2469, 0xffffffff, 0x00000009, 79062a37553SKen Wang 0x246a, 0xffffffff, 0x00080007, 79162a37553SKen Wang 0x246b, 0xffffffff, 0x000b000a, 79262a37553SKen Wang 0x246c, 0xffffffff, 0x00050004, 79362a37553SKen Wang 0x246d, 0xffffffff, 0x00070006, 79462a37553SKen Wang 0x246e, 0xffffffff, 0x0008000b, 79562a37553SKen Wang 0x246f, 0xffffffff, 0x000a0009, 79662a37553SKen Wang 0x2470, 0xffffffff, 0x000d000c, 79762a37553SKen Wang 0x2471, 0xffffffff, 0x00060005, 79862a37553SKen Wang 0x2472, 0xffffffff, 0x00080007, 79962a37553SKen Wang 0x2473, 0xffffffff, 0x0000000b, 80062a37553SKen Wang 0x2474, 0xffffffff, 0x000a0009, 80162a37553SKen Wang 0x2475, 0xffffffff, 0x000d000c, 802*78bbe771STom St Denis mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 803*78bbe771STom St Denis mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 804*78bbe771STom St Denis mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 805*78bbe771STom St Denis mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 8066b7985efSFlora Cui 0x000c, 0xffffffff, 0x0000001c, 8076b7985efSFlora Cui 0x000d, 0x000f0000, 0x000f0000, 8086b7985efSFlora Cui 0x0583, 0xffffffff, 0x00000100, 809*78bbe771STom St Denis mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 810*78bbe771STom St Denis mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 811*78bbe771STom St Denis mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 812*78bbe771STom St Denis mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 813*78bbe771STom St Denis mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 814*78bbe771STom St Denis mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 81562a37553SKen Wang 0x157a, 0x00000001, 0x00000001, 816*78bbe771STom St Denis mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 817*78bbe771STom St Denis mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 818*78bbe771STom St Denis mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 81962a37553SKen Wang 0x3430, 0xfffffff0, 0x00000100, 820*78bbe771STom St Denis 0x3630, 0xfffffff0, 0x00000100, 82162a37553SKen Wang }; 822*78bbe771STom St Denis 82362a37553SKen Wang static const u32 hainan_mgcg_cgcg_init[] = 82462a37553SKen Wang { 825*78bbe771STom St Denis mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 826*78bbe771STom St Denis mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 827*78bbe771STom St Denis mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 828*78bbe771STom St Denis mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 829*78bbe771STom St Denis mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 830*78bbe771STom St Denis mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 831*78bbe771STom St Denis mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 832*78bbe771STom St Denis mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 833*78bbe771STom St Denis mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 834*78bbe771STom St Denis mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 835*78bbe771STom St Denis mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 836*78bbe771STom St Denis mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 837*78bbe771STom St Denis mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 838*78bbe771STom St Denis mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 839*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 840*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 841*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 842*78bbe771STom St Denis mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 843*78bbe771STom St Denis mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 844*78bbe771STom St Denis mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 845*78bbe771STom St Denis mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 846*78bbe771STom St Denis mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 847*78bbe771STom St Denis mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 848*78bbe771STom St Denis mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 849*78bbe771STom St Denis mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 850*78bbe771STom St Denis mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 851*78bbe771STom St Denis mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 85262a37553SKen Wang 0x2458, 0xffffffff, 0x00010000, 85362a37553SKen Wang 0x2459, 0xffffffff, 0x00030002, 85462a37553SKen Wang 0x245a, 0xffffffff, 0x00040007, 85562a37553SKen Wang 0x245b, 0xffffffff, 0x00060005, 85662a37553SKen Wang 0x245c, 0xffffffff, 0x00090008, 85762a37553SKen Wang 0x245d, 0xffffffff, 0x00020001, 85862a37553SKen Wang 0x245e, 0xffffffff, 0x00040003, 85962a37553SKen Wang 0x245f, 0xffffffff, 0x00000007, 86062a37553SKen Wang 0x2460, 0xffffffff, 0x00060005, 86162a37553SKen Wang 0x2461, 0xffffffff, 0x00090008, 86262a37553SKen Wang 0x2462, 0xffffffff, 0x00030002, 86362a37553SKen Wang 0x2463, 0xffffffff, 0x00050004, 86462a37553SKen Wang 0x2464, 0xffffffff, 0x00000008, 86562a37553SKen Wang 0x2465, 0xffffffff, 0x00070006, 86662a37553SKen Wang 0x2466, 0xffffffff, 0x000a0009, 86762a37553SKen Wang 0x2467, 0xffffffff, 0x00040003, 86862a37553SKen Wang 0x2468, 0xffffffff, 0x00060005, 86962a37553SKen Wang 0x2469, 0xffffffff, 0x00000009, 87062a37553SKen Wang 0x246a, 0xffffffff, 0x00080007, 87162a37553SKen Wang 0x246b, 0xffffffff, 0x000b000a, 87262a37553SKen Wang 0x246c, 0xffffffff, 0x00050004, 87362a37553SKen Wang 0x246d, 0xffffffff, 0x00070006, 87462a37553SKen Wang 0x246e, 0xffffffff, 0x0008000b, 87562a37553SKen Wang 0x246f, 0xffffffff, 0x000a0009, 87662a37553SKen Wang 0x2470, 0xffffffff, 0x000d000c, 87762a37553SKen Wang 0x2471, 0xffffffff, 0x00060005, 87862a37553SKen Wang 0x2472, 0xffffffff, 0x00080007, 87962a37553SKen Wang 0x2473, 0xffffffff, 0x0000000b, 88062a37553SKen Wang 0x2474, 0xffffffff, 0x000a0009, 88162a37553SKen Wang 0x2475, 0xffffffff, 0x000d000c, 882*78bbe771STom St Denis mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 883*78bbe771STom St Denis mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 884*78bbe771STom St Denis mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 885*78bbe771STom St Denis mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 886bd27b678SFlora Cui 0x000c, 0xffffffff, 0x0000001c, 887bd27b678SFlora Cui 0x000d, 0x000f0000, 0x000f0000, 888bd27b678SFlora Cui 0x0583, 0xffffffff, 0x00000100, 889bd27b678SFlora Cui 0x0409, 0xffffffff, 0x00000100, 890*78bbe771STom St Denis mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 891*78bbe771STom St Denis mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 892*78bbe771STom St Denis mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 893*78bbe771STom St Denis mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 894*78bbe771STom St Denis mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 895*78bbe771STom St Denis mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 89662a37553SKen Wang 0x3430, 0xfffffff0, 0x00000100, 897*78bbe771STom St Denis 0x3630, 0xfffffff0, 0x00000100, 89862a37553SKen Wang }; 89962a37553SKen Wang 90062a37553SKen Wang static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg) 90162a37553SKen Wang { 90262a37553SKen Wang unsigned long flags; 90362a37553SKen Wang u32 r; 90462a37553SKen Wang 90562a37553SKen Wang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 90662a37553SKen Wang WREG32(AMDGPU_PCIE_INDEX, reg); 90762a37553SKen Wang (void)RREG32(AMDGPU_PCIE_INDEX); 90862a37553SKen Wang r = RREG32(AMDGPU_PCIE_DATA); 90962a37553SKen Wang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 91062a37553SKen Wang return r; 91162a37553SKen Wang } 91262a37553SKen Wang 91362a37553SKen Wang static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 91462a37553SKen Wang { 91562a37553SKen Wang unsigned long flags; 91662a37553SKen Wang 91762a37553SKen Wang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 91862a37553SKen Wang WREG32(AMDGPU_PCIE_INDEX, reg); 91962a37553SKen Wang (void)RREG32(AMDGPU_PCIE_INDEX); 92062a37553SKen Wang WREG32(AMDGPU_PCIE_DATA, v); 92162a37553SKen Wang (void)RREG32(AMDGPU_PCIE_DATA); 92262a37553SKen Wang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 92362a37553SKen Wang } 92462a37553SKen Wang 925d1936cc2SBaoyou Xie static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) 92636b9a952SHuang Rui { 92736b9a952SHuang Rui unsigned long flags; 92836b9a952SHuang Rui u32 r; 92936b9a952SHuang Rui 93036b9a952SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 93136b9a952SHuang Rui WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 93236b9a952SHuang Rui (void)RREG32(PCIE_PORT_INDEX); 93336b9a952SHuang Rui r = RREG32(PCIE_PORT_DATA); 93436b9a952SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 93536b9a952SHuang Rui return r; 93636b9a952SHuang Rui } 93736b9a952SHuang Rui 938d1936cc2SBaoyou Xie static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 93936b9a952SHuang Rui { 94036b9a952SHuang Rui unsigned long flags; 94136b9a952SHuang Rui 94236b9a952SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 94336b9a952SHuang Rui WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 94436b9a952SHuang Rui (void)RREG32(PCIE_PORT_INDEX); 94536b9a952SHuang Rui WREG32(PCIE_PORT_DATA, (v)); 94636b9a952SHuang Rui (void)RREG32(PCIE_PORT_DATA); 94736b9a952SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 94836b9a952SHuang Rui } 94936b9a952SHuang Rui 95062a37553SKen Wang static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg) 95162a37553SKen Wang { 95262a37553SKen Wang unsigned long flags; 95362a37553SKen Wang u32 r; 95462a37553SKen Wang 95562a37553SKen Wang spin_lock_irqsave(&adev->smc_idx_lock, flags); 95662a37553SKen Wang WREG32(SMC_IND_INDEX_0, (reg)); 95762a37553SKen Wang r = RREG32(SMC_IND_DATA_0); 95862a37553SKen Wang spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 95962a37553SKen Wang return r; 96062a37553SKen Wang } 96162a37553SKen Wang 96262a37553SKen Wang static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 96362a37553SKen Wang { 96462a37553SKen Wang unsigned long flags; 96562a37553SKen Wang 96662a37553SKen Wang spin_lock_irqsave(&adev->smc_idx_lock, flags); 96762a37553SKen Wang WREG32(SMC_IND_INDEX_0, (reg)); 96862a37553SKen Wang WREG32(SMC_IND_DATA_0, (v)); 96962a37553SKen Wang spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 97062a37553SKen Wang } 97162a37553SKen Wang 97262a37553SKen Wang static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = { 97362a37553SKen Wang {GRBM_STATUS, false}, 97462a37553SKen Wang {GB_ADDR_CONFIG, false}, 97562a37553SKen Wang {MC_ARB_RAMCFG, false}, 97662a37553SKen Wang {GB_TILE_MODE0, false}, 97762a37553SKen Wang {GB_TILE_MODE1, false}, 97862a37553SKen Wang {GB_TILE_MODE2, false}, 97962a37553SKen Wang {GB_TILE_MODE3, false}, 98062a37553SKen Wang {GB_TILE_MODE4, false}, 98162a37553SKen Wang {GB_TILE_MODE5, false}, 98262a37553SKen Wang {GB_TILE_MODE6, false}, 98362a37553SKen Wang {GB_TILE_MODE7, false}, 98462a37553SKen Wang {GB_TILE_MODE8, false}, 98562a37553SKen Wang {GB_TILE_MODE9, false}, 98662a37553SKen Wang {GB_TILE_MODE10, false}, 98762a37553SKen Wang {GB_TILE_MODE11, false}, 98862a37553SKen Wang {GB_TILE_MODE12, false}, 98962a37553SKen Wang {GB_TILE_MODE13, false}, 99062a37553SKen Wang {GB_TILE_MODE14, false}, 99162a37553SKen Wang {GB_TILE_MODE15, false}, 99262a37553SKen Wang {GB_TILE_MODE16, false}, 99362a37553SKen Wang {GB_TILE_MODE17, false}, 99462a37553SKen Wang {GB_TILE_MODE18, false}, 99562a37553SKen Wang {GB_TILE_MODE19, false}, 99662a37553SKen Wang {GB_TILE_MODE20, false}, 99762a37553SKen Wang {GB_TILE_MODE21, false}, 99862a37553SKen Wang {GB_TILE_MODE22, false}, 99962a37553SKen Wang {GB_TILE_MODE23, false}, 100062a37553SKen Wang {GB_TILE_MODE24, false}, 100162a37553SKen Wang {GB_TILE_MODE25, false}, 100262a37553SKen Wang {GB_TILE_MODE26, false}, 100362a37553SKen Wang {GB_TILE_MODE27, false}, 100462a37553SKen Wang {GB_TILE_MODE28, false}, 100562a37553SKen Wang {GB_TILE_MODE29, false}, 100662a37553SKen Wang {GB_TILE_MODE30, false}, 100762a37553SKen Wang {GB_TILE_MODE31, false}, 100862a37553SKen Wang {CC_RB_BACKEND_DISABLE, false, true}, 100962a37553SKen Wang {GC_USER_RB_BACKEND_DISABLE, false, true}, 101062a37553SKen Wang {PA_SC_RASTER_CONFIG, false, true}, 101162a37553SKen Wang }; 101262a37553SKen Wang 101362a37553SKen Wang static uint32_t si_read_indexed_register(struct amdgpu_device *adev, 101462a37553SKen Wang u32 se_num, u32 sh_num, 101562a37553SKen Wang u32 reg_offset) 101662a37553SKen Wang { 101762a37553SKen Wang uint32_t val; 101862a37553SKen Wang 101962a37553SKen Wang mutex_lock(&adev->grbm_idx_mutex); 102062a37553SKen Wang if (se_num != 0xffffffff || sh_num != 0xffffffff) 102162a37553SKen Wang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 102262a37553SKen Wang 102362a37553SKen Wang val = RREG32(reg_offset); 102462a37553SKen Wang 102562a37553SKen Wang if (se_num != 0xffffffff || sh_num != 0xffffffff) 102662a37553SKen Wang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 102762a37553SKen Wang mutex_unlock(&adev->grbm_idx_mutex); 102862a37553SKen Wang return val; 102962a37553SKen Wang } 103062a37553SKen Wang 103162a37553SKen Wang static int si_read_register(struct amdgpu_device *adev, u32 se_num, 103262a37553SKen Wang u32 sh_num, u32 reg_offset, u32 *value) 103362a37553SKen Wang { 103462a37553SKen Wang uint32_t i; 103562a37553SKen Wang 103662a37553SKen Wang *value = 0; 103762a37553SKen Wang for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) { 103862a37553SKen Wang if (reg_offset != si_allowed_read_registers[i].reg_offset) 103962a37553SKen Wang continue; 104062a37553SKen Wang 104162a37553SKen Wang if (!si_allowed_read_registers[i].untouched) 104262a37553SKen Wang *value = si_allowed_read_registers[i].grbm_indexed ? 104362a37553SKen Wang si_read_indexed_register(adev, se_num, 104462a37553SKen Wang sh_num, reg_offset) : 104562a37553SKen Wang RREG32(reg_offset); 104662a37553SKen Wang return 0; 104762a37553SKen Wang } 104862a37553SKen Wang return -EINVAL; 104962a37553SKen Wang } 105062a37553SKen Wang 105162a37553SKen Wang static bool si_read_disabled_bios(struct amdgpu_device *adev) 105262a37553SKen Wang { 105362a37553SKen Wang u32 bus_cntl; 105462a37553SKen Wang u32 d1vga_control = 0; 105562a37553SKen Wang u32 d2vga_control = 0; 105662a37553SKen Wang u32 vga_render_control = 0; 105762a37553SKen Wang u32 rom_cntl; 105862a37553SKen Wang bool r; 105962a37553SKen Wang 106062a37553SKen Wang bus_cntl = RREG32(R600_BUS_CNTL); 106162a37553SKen Wang if (adev->mode_info.num_crtc) { 106262a37553SKen Wang d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 106362a37553SKen Wang d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 106462a37553SKen Wang vga_render_control = RREG32(VGA_RENDER_CONTROL); 106562a37553SKen Wang } 106662a37553SKen Wang rom_cntl = RREG32(R600_ROM_CNTL); 106762a37553SKen Wang 106862a37553SKen Wang /* enable the rom */ 106962a37553SKen Wang WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 107062a37553SKen Wang if (adev->mode_info.num_crtc) { 107162a37553SKen Wang /* Disable VGA mode */ 107262a37553SKen Wang WREG32(AVIVO_D1VGA_CONTROL, 107362a37553SKen Wang (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 107462a37553SKen Wang AVIVO_DVGA_CONTROL_TIMING_SELECT))); 107562a37553SKen Wang WREG32(AVIVO_D2VGA_CONTROL, 107662a37553SKen Wang (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 107762a37553SKen Wang AVIVO_DVGA_CONTROL_TIMING_SELECT))); 107862a37553SKen Wang WREG32(VGA_RENDER_CONTROL, 107962a37553SKen Wang (vga_render_control & C_000300_VGA_VSTATUS_CNTL)); 108062a37553SKen Wang } 108162a37553SKen Wang WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 108262a37553SKen Wang 108362a37553SKen Wang r = amdgpu_read_bios(adev); 108462a37553SKen Wang 108562a37553SKen Wang /* restore regs */ 108662a37553SKen Wang WREG32(R600_BUS_CNTL, bus_cntl); 108762a37553SKen Wang if (adev->mode_info.num_crtc) { 108862a37553SKen Wang WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 108962a37553SKen Wang WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 109062a37553SKen Wang WREG32(VGA_RENDER_CONTROL, vga_render_control); 109162a37553SKen Wang } 109262a37553SKen Wang WREG32(R600_ROM_CNTL, rom_cntl); 109362a37553SKen Wang return r; 109462a37553SKen Wang } 109562a37553SKen Wang 109662a37553SKen Wang //xxx: not implemented 109762a37553SKen Wang static int si_asic_reset(struct amdgpu_device *adev) 109862a37553SKen Wang { 109962a37553SKen Wang return 0; 110062a37553SKen Wang } 110162a37553SKen Wang 110262a37553SKen Wang static void si_vga_set_state(struct amdgpu_device *adev, bool state) 110362a37553SKen Wang { 110462a37553SKen Wang uint32_t temp; 110562a37553SKen Wang 110662a37553SKen Wang temp = RREG32(CONFIG_CNTL); 110762a37553SKen Wang if (state == false) { 110862a37553SKen Wang temp &= ~(1<<0); 110962a37553SKen Wang temp |= (1<<1); 111062a37553SKen Wang } else { 111162a37553SKen Wang temp &= ~(1<<1); 111262a37553SKen Wang } 111362a37553SKen Wang WREG32(CONFIG_CNTL, temp); 111462a37553SKen Wang } 111562a37553SKen Wang 111662a37553SKen Wang static u32 si_get_xclk(struct amdgpu_device *adev) 111762a37553SKen Wang { 111862a37553SKen Wang u32 reference_clock = adev->clock.spll.reference_freq; 111962a37553SKen Wang u32 tmp; 112062a37553SKen Wang 112162a37553SKen Wang tmp = RREG32(CG_CLKPIN_CNTL_2); 112262a37553SKen Wang if (tmp & MUX_TCLK_TO_XCLK) 112362a37553SKen Wang return TCLK; 112462a37553SKen Wang 112562a37553SKen Wang tmp = RREG32(CG_CLKPIN_CNTL); 112662a37553SKen Wang if (tmp & XTALIN_DIVIDE) 112762a37553SKen Wang return reference_clock / 4; 112862a37553SKen Wang 112962a37553SKen Wang return reference_clock; 113062a37553SKen Wang } 11311919696eSMaruthi Srinivas Bayyavarapu 113262a37553SKen Wang //xxx:not implemented 113362a37553SKen Wang static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 113462a37553SKen Wang { 113562a37553SKen Wang return 0; 113662a37553SKen Wang } 113762a37553SKen Wang 11384e99a44eSMonk Liu static void si_detect_hw_virtualization(struct amdgpu_device *adev) 11394e99a44eSMonk Liu { 11404e99a44eSMonk Liu if (is_virtual_machine()) /* passthrough mode */ 11414e99a44eSMonk Liu adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE; 11424e99a44eSMonk Liu } 11434e99a44eSMonk Liu 114462a37553SKen Wang static const struct amdgpu_asic_funcs si_asic_funcs = 114562a37553SKen Wang { 114662a37553SKen Wang .read_disabled_bios = &si_read_disabled_bios, 11474e99a44eSMonk Liu .detect_hw_virtualization = si_detect_hw_virtualization, 114862a37553SKen Wang .read_register = &si_read_register, 114962a37553SKen Wang .reset = &si_asic_reset, 115062a37553SKen Wang .set_vga_state = &si_vga_set_state, 115162a37553SKen Wang .get_xclk = &si_get_xclk, 115262a37553SKen Wang .set_uvd_clocks = &si_set_uvd_clocks, 115362a37553SKen Wang .set_vce_clocks = NULL, 115462a37553SKen Wang }; 115562a37553SKen Wang 115662a37553SKen Wang static uint32_t si_get_rev_id(struct amdgpu_device *adev) 115762a37553SKen Wang { 115862a37553SKen Wang return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) 115962a37553SKen Wang >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; 116062a37553SKen Wang } 116162a37553SKen Wang 116262a37553SKen Wang static int si_common_early_init(void *handle) 116362a37553SKen Wang { 116462a37553SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 116562a37553SKen Wang 116662a37553SKen Wang adev->smc_rreg = &si_smc_rreg; 116762a37553SKen Wang adev->smc_wreg = &si_smc_wreg; 116862a37553SKen Wang adev->pcie_rreg = &si_pcie_rreg; 116962a37553SKen Wang adev->pcie_wreg = &si_pcie_wreg; 117036b9a952SHuang Rui adev->pciep_rreg = &si_pciep_rreg; 117136b9a952SHuang Rui adev->pciep_wreg = &si_pciep_wreg; 117262a37553SKen Wang adev->uvd_ctx_rreg = NULL; 117362a37553SKen Wang adev->uvd_ctx_wreg = NULL; 117462a37553SKen Wang adev->didt_rreg = NULL; 117562a37553SKen Wang adev->didt_wreg = NULL; 117662a37553SKen Wang 117762a37553SKen Wang adev->asic_funcs = &si_asic_funcs; 117862a37553SKen Wang 117962a37553SKen Wang adev->rev_id = si_get_rev_id(adev); 118062a37553SKen Wang adev->external_rev_id = 0xFF; 118162a37553SKen Wang switch (adev->asic_type) { 118262a37553SKen Wang case CHIP_TAHITI: 118362a37553SKen Wang adev->cg_flags = 118462a37553SKen Wang AMD_CG_SUPPORT_GFX_MGCG | 118562a37553SKen Wang AMD_CG_SUPPORT_GFX_MGLS | 118662a37553SKen Wang /*AMD_CG_SUPPORT_GFX_CGCG |*/ 118762a37553SKen Wang AMD_CG_SUPPORT_GFX_CGLS | 118862a37553SKen Wang AMD_CG_SUPPORT_GFX_CGTS | 118962a37553SKen Wang AMD_CG_SUPPORT_GFX_CP_LS | 119062a37553SKen Wang AMD_CG_SUPPORT_MC_MGCG | 119162a37553SKen Wang AMD_CG_SUPPORT_SDMA_MGCG | 119262a37553SKen Wang AMD_CG_SUPPORT_BIF_LS | 119362a37553SKen Wang AMD_CG_SUPPORT_VCE_MGCG | 119462a37553SKen Wang AMD_CG_SUPPORT_UVD_MGCG | 119562a37553SKen Wang AMD_CG_SUPPORT_HDP_LS | 119662a37553SKen Wang AMD_CG_SUPPORT_HDP_MGCG; 119762a37553SKen Wang adev->pg_flags = 0; 11987c0a705eSFlora Cui adev->external_rev_id = (adev->rev_id == 0) ? 1 : 11997c0a705eSFlora Cui (adev->rev_id == 1) ? 5 : 6; 120062a37553SKen Wang break; 120162a37553SKen Wang case CHIP_PITCAIRN: 120262a37553SKen Wang adev->cg_flags = 120362a37553SKen Wang AMD_CG_SUPPORT_GFX_MGCG | 120462a37553SKen Wang AMD_CG_SUPPORT_GFX_MGLS | 120562a37553SKen Wang /*AMD_CG_SUPPORT_GFX_CGCG |*/ 120662a37553SKen Wang AMD_CG_SUPPORT_GFX_CGLS | 120762a37553SKen Wang AMD_CG_SUPPORT_GFX_CGTS | 120862a37553SKen Wang AMD_CG_SUPPORT_GFX_CP_LS | 120962a37553SKen Wang AMD_CG_SUPPORT_GFX_RLC_LS | 121062a37553SKen Wang AMD_CG_SUPPORT_MC_LS | 121162a37553SKen Wang AMD_CG_SUPPORT_MC_MGCG | 121262a37553SKen Wang AMD_CG_SUPPORT_SDMA_MGCG | 121362a37553SKen Wang AMD_CG_SUPPORT_BIF_LS | 121462a37553SKen Wang AMD_CG_SUPPORT_VCE_MGCG | 121562a37553SKen Wang AMD_CG_SUPPORT_UVD_MGCG | 121662a37553SKen Wang AMD_CG_SUPPORT_HDP_LS | 121762a37553SKen Wang AMD_CG_SUPPORT_HDP_MGCG; 121862a37553SKen Wang adev->pg_flags = 0; 1219e285a9a6SFlora Cui adev->external_rev_id = adev->rev_id + 20; 122062a37553SKen Wang break; 122162a37553SKen Wang 122262a37553SKen Wang case CHIP_VERDE: 122362a37553SKen Wang adev->cg_flags = 122462a37553SKen Wang AMD_CG_SUPPORT_GFX_MGCG | 122562a37553SKen Wang AMD_CG_SUPPORT_GFX_MGLS | 122662a37553SKen Wang AMD_CG_SUPPORT_GFX_CGLS | 122762a37553SKen Wang AMD_CG_SUPPORT_GFX_CGTS | 122862a37553SKen Wang AMD_CG_SUPPORT_GFX_CGTS_LS | 122962a37553SKen Wang AMD_CG_SUPPORT_GFX_CP_LS | 123062a37553SKen Wang AMD_CG_SUPPORT_MC_LS | 123162a37553SKen Wang AMD_CG_SUPPORT_MC_MGCG | 123262a37553SKen Wang AMD_CG_SUPPORT_SDMA_MGCG | 123362a37553SKen Wang AMD_CG_SUPPORT_SDMA_LS | 123462a37553SKen Wang AMD_CG_SUPPORT_BIF_LS | 123562a37553SKen Wang AMD_CG_SUPPORT_VCE_MGCG | 123662a37553SKen Wang AMD_CG_SUPPORT_UVD_MGCG | 123762a37553SKen Wang AMD_CG_SUPPORT_HDP_LS | 123862a37553SKen Wang AMD_CG_SUPPORT_HDP_MGCG; 123962a37553SKen Wang adev->pg_flags = 0; 124062a37553SKen Wang //??? 1241f815b29cSFlora Cui adev->external_rev_id = adev->rev_id + 40; 124262a37553SKen Wang break; 124362a37553SKen Wang case CHIP_OLAND: 124462a37553SKen Wang adev->cg_flags = 124562a37553SKen Wang AMD_CG_SUPPORT_GFX_MGCG | 124662a37553SKen Wang AMD_CG_SUPPORT_GFX_MGLS | 124762a37553SKen Wang /*AMD_CG_SUPPORT_GFX_CGCG |*/ 124862a37553SKen Wang AMD_CG_SUPPORT_GFX_CGLS | 124962a37553SKen Wang AMD_CG_SUPPORT_GFX_CGTS | 125062a37553SKen Wang AMD_CG_SUPPORT_GFX_CP_LS | 125162a37553SKen Wang AMD_CG_SUPPORT_GFX_RLC_LS | 125262a37553SKen Wang AMD_CG_SUPPORT_MC_LS | 125362a37553SKen Wang AMD_CG_SUPPORT_MC_MGCG | 125462a37553SKen Wang AMD_CG_SUPPORT_SDMA_MGCG | 125562a37553SKen Wang AMD_CG_SUPPORT_BIF_LS | 125662a37553SKen Wang AMD_CG_SUPPORT_UVD_MGCG | 125762a37553SKen Wang AMD_CG_SUPPORT_HDP_LS | 125862a37553SKen Wang AMD_CG_SUPPORT_HDP_MGCG; 125962a37553SKen Wang adev->pg_flags = 0; 12608fd74cb4SFlora Cui adev->external_rev_id = 60; 126162a37553SKen Wang break; 126262a37553SKen Wang case CHIP_HAINAN: 126362a37553SKen Wang adev->cg_flags = 126462a37553SKen Wang AMD_CG_SUPPORT_GFX_MGCG | 126562a37553SKen Wang AMD_CG_SUPPORT_GFX_MGLS | 126662a37553SKen Wang /*AMD_CG_SUPPORT_GFX_CGCG |*/ 126762a37553SKen Wang AMD_CG_SUPPORT_GFX_CGLS | 126862a37553SKen Wang AMD_CG_SUPPORT_GFX_CGTS | 126962a37553SKen Wang AMD_CG_SUPPORT_GFX_CP_LS | 127062a37553SKen Wang AMD_CG_SUPPORT_GFX_RLC_LS | 127162a37553SKen Wang AMD_CG_SUPPORT_MC_LS | 127262a37553SKen Wang AMD_CG_SUPPORT_MC_MGCG | 127362a37553SKen Wang AMD_CG_SUPPORT_SDMA_MGCG | 127462a37553SKen Wang AMD_CG_SUPPORT_BIF_LS | 127562a37553SKen Wang AMD_CG_SUPPORT_HDP_LS | 127662a37553SKen Wang AMD_CG_SUPPORT_HDP_MGCG; 127762a37553SKen Wang adev->pg_flags = 0; 127805319478SFlora Cui adev->external_rev_id = 70; 127962a37553SKen Wang break; 128062a37553SKen Wang 128162a37553SKen Wang default: 128262a37553SKen Wang return -EINVAL; 128362a37553SKen Wang } 128462a37553SKen Wang 128562a37553SKen Wang return 0; 128662a37553SKen Wang } 128762a37553SKen Wang 128862a37553SKen Wang static int si_common_sw_init(void *handle) 128962a37553SKen Wang { 129062a37553SKen Wang return 0; 129162a37553SKen Wang } 129262a37553SKen Wang 129362a37553SKen Wang static int si_common_sw_fini(void *handle) 129462a37553SKen Wang { 129562a37553SKen Wang return 0; 129662a37553SKen Wang } 129762a37553SKen Wang 129862a37553SKen Wang 129962a37553SKen Wang static void si_init_golden_registers(struct amdgpu_device *adev) 130062a37553SKen Wang { 130162a37553SKen Wang switch (adev->asic_type) { 130262a37553SKen Wang case CHIP_TAHITI: 130362a37553SKen Wang amdgpu_program_register_sequence(adev, 130462a37553SKen Wang tahiti_golden_registers, 130562a37553SKen Wang (const u32)ARRAY_SIZE(tahiti_golden_registers)); 130662a37553SKen Wang amdgpu_program_register_sequence(adev, 130762a37553SKen Wang tahiti_golden_rlc_registers, 130862a37553SKen Wang (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers)); 130962a37553SKen Wang amdgpu_program_register_sequence(adev, 131062a37553SKen Wang tahiti_mgcg_cgcg_init, 131162a37553SKen Wang (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init)); 131262a37553SKen Wang amdgpu_program_register_sequence(adev, 131362a37553SKen Wang tahiti_golden_registers2, 131462a37553SKen Wang (const u32)ARRAY_SIZE(tahiti_golden_registers2)); 131562a37553SKen Wang break; 131662a37553SKen Wang case CHIP_PITCAIRN: 131762a37553SKen Wang amdgpu_program_register_sequence(adev, 131862a37553SKen Wang pitcairn_golden_registers, 131962a37553SKen Wang (const u32)ARRAY_SIZE(pitcairn_golden_registers)); 132062a37553SKen Wang amdgpu_program_register_sequence(adev, 132162a37553SKen Wang pitcairn_golden_rlc_registers, 132262a37553SKen Wang (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers)); 132362a37553SKen Wang amdgpu_program_register_sequence(adev, 132462a37553SKen Wang pitcairn_mgcg_cgcg_init, 132562a37553SKen Wang (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); 132662a37553SKen Wang case CHIP_VERDE: 132762a37553SKen Wang amdgpu_program_register_sequence(adev, 132862a37553SKen Wang verde_golden_registers, 132962a37553SKen Wang (const u32)ARRAY_SIZE(verde_golden_registers)); 133062a37553SKen Wang amdgpu_program_register_sequence(adev, 133162a37553SKen Wang verde_golden_rlc_registers, 133262a37553SKen Wang (const u32)ARRAY_SIZE(verde_golden_rlc_registers)); 133362a37553SKen Wang amdgpu_program_register_sequence(adev, 133462a37553SKen Wang verde_mgcg_cgcg_init, 133562a37553SKen Wang (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init)); 133662a37553SKen Wang amdgpu_program_register_sequence(adev, 133762a37553SKen Wang verde_pg_init, 133862a37553SKen Wang (const u32)ARRAY_SIZE(verde_pg_init)); 133962a37553SKen Wang break; 134062a37553SKen Wang case CHIP_OLAND: 134162a37553SKen Wang amdgpu_program_register_sequence(adev, 134262a37553SKen Wang oland_golden_registers, 134362a37553SKen Wang (const u32)ARRAY_SIZE(oland_golden_registers)); 134462a37553SKen Wang amdgpu_program_register_sequence(adev, 134562a37553SKen Wang oland_golden_rlc_registers, 134662a37553SKen Wang (const u32)ARRAY_SIZE(oland_golden_rlc_registers)); 134762a37553SKen Wang amdgpu_program_register_sequence(adev, 134862a37553SKen Wang oland_mgcg_cgcg_init, 134962a37553SKen Wang (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init)); 135062a37553SKen Wang case CHIP_HAINAN: 135162a37553SKen Wang amdgpu_program_register_sequence(adev, 135262a37553SKen Wang hainan_golden_registers, 135362a37553SKen Wang (const u32)ARRAY_SIZE(hainan_golden_registers)); 135462a37553SKen Wang amdgpu_program_register_sequence(adev, 135562a37553SKen Wang hainan_golden_registers2, 135662a37553SKen Wang (const u32)ARRAY_SIZE(hainan_golden_registers2)); 135762a37553SKen Wang amdgpu_program_register_sequence(adev, 135862a37553SKen Wang hainan_mgcg_cgcg_init, 135962a37553SKen Wang (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init)); 136062a37553SKen Wang break; 136162a37553SKen Wang 136262a37553SKen Wang 136362a37553SKen Wang default: 136462a37553SKen Wang BUG(); 136562a37553SKen Wang } 136662a37553SKen Wang } 136762a37553SKen Wang 136862a37553SKen Wang static void si_pcie_gen3_enable(struct amdgpu_device *adev) 136962a37553SKen Wang { 137062a37553SKen Wang struct pci_dev *root = adev->pdev->bus->self; 137162a37553SKen Wang int bridge_pos, gpu_pos; 137262a37553SKen Wang u32 speed_cntl, mask, current_data_rate; 137362a37553SKen Wang int ret, i; 137462a37553SKen Wang u16 tmp16; 137562a37553SKen Wang 137662a37553SKen Wang if (pci_is_root_bus(adev->pdev->bus)) 137762a37553SKen Wang return; 137862a37553SKen Wang 137962a37553SKen Wang if (amdgpu_pcie_gen2 == 0) 138062a37553SKen Wang return; 138162a37553SKen Wang 138262a37553SKen Wang if (adev->flags & AMD_IS_APU) 138362a37553SKen Wang return; 138462a37553SKen Wang 138562a37553SKen Wang ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 138662a37553SKen Wang if (ret != 0) 138762a37553SKen Wang return; 138862a37553SKen Wang 138962a37553SKen Wang if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80))) 139062a37553SKen Wang return; 139162a37553SKen Wang 139236b9a952SHuang Rui speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 139362a37553SKen Wang current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> 139462a37553SKen Wang LC_CURRENT_DATA_RATE_SHIFT; 139562a37553SKen Wang if (mask & DRM_PCIE_SPEED_80) { 139662a37553SKen Wang if (current_data_rate == 2) { 139762a37553SKen Wang DRM_INFO("PCIE gen 3 link speeds already enabled\n"); 139862a37553SKen Wang return; 139962a37553SKen Wang } 140062a37553SKen Wang DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); 140162a37553SKen Wang } else if (mask & DRM_PCIE_SPEED_50) { 140262a37553SKen Wang if (current_data_rate == 1) { 140362a37553SKen Wang DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 140462a37553SKen Wang return; 140562a37553SKen Wang } 140662a37553SKen Wang DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); 140762a37553SKen Wang } 140862a37553SKen Wang 140962a37553SKen Wang bridge_pos = pci_pcie_cap(root); 141062a37553SKen Wang if (!bridge_pos) 141162a37553SKen Wang return; 141262a37553SKen Wang 141362a37553SKen Wang gpu_pos = pci_pcie_cap(adev->pdev); 141462a37553SKen Wang if (!gpu_pos) 141562a37553SKen Wang return; 141662a37553SKen Wang 141762a37553SKen Wang if (mask & DRM_PCIE_SPEED_80) { 141862a37553SKen Wang if (current_data_rate != 2) { 141962a37553SKen Wang u16 bridge_cfg, gpu_cfg; 142062a37553SKen Wang u16 bridge_cfg2, gpu_cfg2; 142162a37553SKen Wang u32 max_lw, current_lw, tmp; 142262a37553SKen Wang 142362a37553SKen Wang pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 142462a37553SKen Wang pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 142562a37553SKen Wang 142662a37553SKen Wang tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; 142762a37553SKen Wang pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 142862a37553SKen Wang 142962a37553SKen Wang tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; 143062a37553SKen Wang pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 143162a37553SKen Wang 143262a37553SKen Wang tmp = RREG32_PCIE(PCIE_LC_STATUS1); 143362a37553SKen Wang max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; 143462a37553SKen Wang current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT; 143562a37553SKen Wang 143662a37553SKen Wang if (current_lw < max_lw) { 143736b9a952SHuang Rui tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 143862a37553SKen Wang if (tmp & LC_RENEGOTIATION_SUPPORT) { 143962a37553SKen Wang tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS); 144062a37553SKen Wang tmp |= (max_lw << LC_LINK_WIDTH_SHIFT); 144162a37553SKen Wang tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW; 144236b9a952SHuang Rui WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp); 144362a37553SKen Wang } 144462a37553SKen Wang } 144562a37553SKen Wang 144662a37553SKen Wang for (i = 0; i < 10; i++) { 144762a37553SKen Wang pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); 144862a37553SKen Wang if (tmp16 & PCI_EXP_DEVSTA_TRPND) 144962a37553SKen Wang break; 145062a37553SKen Wang 145162a37553SKen Wang pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 145262a37553SKen Wang pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 145362a37553SKen Wang 145462a37553SKen Wang pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); 145562a37553SKen Wang pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); 145662a37553SKen Wang 145736b9a952SHuang Rui tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 145862a37553SKen Wang tmp |= LC_SET_QUIESCE; 145936b9a952SHuang Rui WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); 146062a37553SKen Wang 146136b9a952SHuang Rui tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 146262a37553SKen Wang tmp |= LC_REDO_EQ; 146336b9a952SHuang Rui WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); 146462a37553SKen Wang 146562a37553SKen Wang mdelay(100); 146662a37553SKen Wang 146762a37553SKen Wang pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); 146862a37553SKen Wang tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 146962a37553SKen Wang tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); 147062a37553SKen Wang pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 147162a37553SKen Wang 147262a37553SKen Wang pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); 147362a37553SKen Wang tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 147462a37553SKen Wang tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); 147562a37553SKen Wang pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 147662a37553SKen Wang 147762a37553SKen Wang pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); 147862a37553SKen Wang tmp16 &= ~((1 << 4) | (7 << 9)); 147962a37553SKen Wang tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); 148062a37553SKen Wang pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); 148162a37553SKen Wang 148262a37553SKen Wang pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 148362a37553SKen Wang tmp16 &= ~((1 << 4) | (7 << 9)); 148462a37553SKen Wang tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); 148562a37553SKen Wang pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 148662a37553SKen Wang 148736b9a952SHuang Rui tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 148862a37553SKen Wang tmp &= ~LC_SET_QUIESCE; 148936b9a952SHuang Rui WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); 149062a37553SKen Wang } 149162a37553SKen Wang } 149262a37553SKen Wang } 149362a37553SKen Wang 149462a37553SKen Wang speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE; 149562a37553SKen Wang speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; 149636b9a952SHuang Rui WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 149762a37553SKen Wang 149862a37553SKen Wang pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 149962a37553SKen Wang tmp16 &= ~0xf; 150062a37553SKen Wang if (mask & DRM_PCIE_SPEED_80) 150162a37553SKen Wang tmp16 |= 3; 150262a37553SKen Wang else if (mask & DRM_PCIE_SPEED_50) 150362a37553SKen Wang tmp16 |= 2; 150462a37553SKen Wang else 150562a37553SKen Wang tmp16 |= 1; 150662a37553SKen Wang pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 150762a37553SKen Wang 150836b9a952SHuang Rui speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 150962a37553SKen Wang speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; 151036b9a952SHuang Rui WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 151162a37553SKen Wang 151262a37553SKen Wang for (i = 0; i < adev->usec_timeout; i++) { 151336b9a952SHuang Rui speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 151462a37553SKen Wang if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0) 151562a37553SKen Wang break; 151662a37553SKen Wang udelay(1); 151762a37553SKen Wang } 151862a37553SKen Wang } 151962a37553SKen Wang 152062a37553SKen Wang static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg) 152162a37553SKen Wang { 152262a37553SKen Wang unsigned long flags; 152362a37553SKen Wang u32 r; 152462a37553SKen Wang 152562a37553SKen Wang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 152662a37553SKen Wang WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 152762a37553SKen Wang r = RREG32(EVERGREEN_PIF_PHY0_DATA); 152862a37553SKen Wang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 152962a37553SKen Wang return r; 153062a37553SKen Wang } 153162a37553SKen Wang 153262a37553SKen Wang static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 153362a37553SKen Wang { 153462a37553SKen Wang unsigned long flags; 153562a37553SKen Wang 153662a37553SKen Wang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 153762a37553SKen Wang WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 153862a37553SKen Wang WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 153962a37553SKen Wang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 154062a37553SKen Wang } 154162a37553SKen Wang 154262a37553SKen Wang static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg) 154362a37553SKen Wang { 154462a37553SKen Wang unsigned long flags; 154562a37553SKen Wang u32 r; 154662a37553SKen Wang 154762a37553SKen Wang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 154862a37553SKen Wang WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 154962a37553SKen Wang r = RREG32(EVERGREEN_PIF_PHY1_DATA); 155062a37553SKen Wang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 155162a37553SKen Wang return r; 155262a37553SKen Wang } 155362a37553SKen Wang 155462a37553SKen Wang static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 155562a37553SKen Wang { 155662a37553SKen Wang unsigned long flags; 155762a37553SKen Wang 155862a37553SKen Wang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 155962a37553SKen Wang WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 156062a37553SKen Wang WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 156162a37553SKen Wang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 156262a37553SKen Wang } 156362a37553SKen Wang static void si_program_aspm(struct amdgpu_device *adev) 156462a37553SKen Wang { 156562a37553SKen Wang u32 data, orig; 156662a37553SKen Wang bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false; 156762a37553SKen Wang bool disable_clkreq = false; 156862a37553SKen Wang 156962a37553SKen Wang if (amdgpu_aspm == 0) 157062a37553SKen Wang return; 157162a37553SKen Wang 157262a37553SKen Wang if (adev->flags & AMD_IS_APU) 157362a37553SKen Wang return; 157436b9a952SHuang Rui orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL); 157562a37553SKen Wang data &= ~LC_XMIT_N_FTS_MASK; 157662a37553SKen Wang data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN; 157762a37553SKen Wang if (orig != data) 157836b9a952SHuang Rui WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data); 157962a37553SKen Wang 158036b9a952SHuang Rui orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3); 158162a37553SKen Wang data |= LC_GO_TO_RECOVERY; 158262a37553SKen Wang if (orig != data) 158336b9a952SHuang Rui WREG32_PCIE_PORT(PCIE_LC_CNTL3, data); 158462a37553SKen Wang 158562a37553SKen Wang orig = data = RREG32_PCIE(PCIE_P_CNTL); 158662a37553SKen Wang data |= P_IGNORE_EDB_ERR; 158762a37553SKen Wang if (orig != data) 158862a37553SKen Wang WREG32_PCIE(PCIE_P_CNTL, data); 158962a37553SKen Wang 159036b9a952SHuang Rui orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL); 159162a37553SKen Wang data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK); 159262a37553SKen Wang data |= LC_PMI_TO_L1_DIS; 159362a37553SKen Wang if (!disable_l0s) 159462a37553SKen Wang data |= LC_L0S_INACTIVITY(7); 159562a37553SKen Wang 159662a37553SKen Wang if (!disable_l1) { 159762a37553SKen Wang data |= LC_L1_INACTIVITY(7); 159862a37553SKen Wang data &= ~LC_PMI_TO_L1_DIS; 159962a37553SKen Wang if (orig != data) 160036b9a952SHuang Rui WREG32_PCIE_PORT(PCIE_LC_CNTL, data); 160162a37553SKen Wang 160262a37553SKen Wang if (!disable_plloff_in_l1) { 160362a37553SKen Wang bool clk_req_support; 160462a37553SKen Wang 160562a37553SKen Wang orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0); 160662a37553SKen Wang data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK); 160762a37553SKen Wang data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7); 160862a37553SKen Wang if (orig != data) 160962a37553SKen Wang si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data); 161062a37553SKen Wang 161162a37553SKen Wang orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1); 161262a37553SKen Wang data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK); 161362a37553SKen Wang data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7); 161462a37553SKen Wang if (orig != data) 161562a37553SKen Wang si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data); 161662a37553SKen Wang 161762a37553SKen Wang orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0); 161862a37553SKen Wang data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK); 161962a37553SKen Wang data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7); 162062a37553SKen Wang if (orig != data) 162162a37553SKen Wang si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data); 162262a37553SKen Wang 162362a37553SKen Wang orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1); 162462a37553SKen Wang data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK); 162562a37553SKen Wang data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7); 162662a37553SKen Wang if (orig != data) 162762a37553SKen Wang si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data); 162862a37553SKen Wang 162962a37553SKen Wang if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) { 163062a37553SKen Wang orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0); 163162a37553SKen Wang data &= ~PLL_RAMP_UP_TIME_0_MASK; 163262a37553SKen Wang if (orig != data) 163362a37553SKen Wang si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data); 163462a37553SKen Wang 163562a37553SKen Wang orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1); 163662a37553SKen Wang data &= ~PLL_RAMP_UP_TIME_1_MASK; 163762a37553SKen Wang if (orig != data) 163862a37553SKen Wang si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data); 163962a37553SKen Wang 164062a37553SKen Wang orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2); 164162a37553SKen Wang data &= ~PLL_RAMP_UP_TIME_2_MASK; 164262a37553SKen Wang if (orig != data) 164362a37553SKen Wang si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data); 164462a37553SKen Wang 164562a37553SKen Wang orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3); 164662a37553SKen Wang data &= ~PLL_RAMP_UP_TIME_3_MASK; 164762a37553SKen Wang if (orig != data) 164862a37553SKen Wang si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data); 164962a37553SKen Wang 165062a37553SKen Wang orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0); 165162a37553SKen Wang data &= ~PLL_RAMP_UP_TIME_0_MASK; 165262a37553SKen Wang if (orig != data) 165362a37553SKen Wang si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data); 165462a37553SKen Wang 165562a37553SKen Wang orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1); 165662a37553SKen Wang data &= ~PLL_RAMP_UP_TIME_1_MASK; 165762a37553SKen Wang if (orig != data) 165862a37553SKen Wang si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data); 165962a37553SKen Wang 166062a37553SKen Wang orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2); 166162a37553SKen Wang data &= ~PLL_RAMP_UP_TIME_2_MASK; 166262a37553SKen Wang if (orig != data) 166362a37553SKen Wang si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data); 166462a37553SKen Wang 166562a37553SKen Wang orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3); 166662a37553SKen Wang data &= ~PLL_RAMP_UP_TIME_3_MASK; 166762a37553SKen Wang if (orig != data) 166862a37553SKen Wang si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data); 166962a37553SKen Wang } 167036b9a952SHuang Rui orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 167162a37553SKen Wang data &= ~LC_DYN_LANES_PWR_STATE_MASK; 167262a37553SKen Wang data |= LC_DYN_LANES_PWR_STATE(3); 167362a37553SKen Wang if (orig != data) 167436b9a952SHuang Rui WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data); 167562a37553SKen Wang 167662a37553SKen Wang orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL); 167762a37553SKen Wang data &= ~LS2_EXIT_TIME_MASK; 167862a37553SKen Wang if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN)) 167962a37553SKen Wang data |= LS2_EXIT_TIME(5); 168062a37553SKen Wang if (orig != data) 168162a37553SKen Wang si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data); 168262a37553SKen Wang 168362a37553SKen Wang orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL); 168462a37553SKen Wang data &= ~LS2_EXIT_TIME_MASK; 168562a37553SKen Wang if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN)) 168662a37553SKen Wang data |= LS2_EXIT_TIME(5); 168762a37553SKen Wang if (orig != data) 168862a37553SKen Wang si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data); 168962a37553SKen Wang 169062a37553SKen Wang if (!disable_clkreq && 169162a37553SKen Wang !pci_is_root_bus(adev->pdev->bus)) { 169262a37553SKen Wang struct pci_dev *root = adev->pdev->bus->self; 169362a37553SKen Wang u32 lnkcap; 169462a37553SKen Wang 169562a37553SKen Wang clk_req_support = false; 169662a37553SKen Wang pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap); 169762a37553SKen Wang if (lnkcap & PCI_EXP_LNKCAP_CLKPM) 169862a37553SKen Wang clk_req_support = true; 169962a37553SKen Wang } else { 170062a37553SKen Wang clk_req_support = false; 170162a37553SKen Wang } 170262a37553SKen Wang 170362a37553SKen Wang if (clk_req_support) { 170436b9a952SHuang Rui orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2); 170562a37553SKen Wang data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23; 170662a37553SKen Wang if (orig != data) 170736b9a952SHuang Rui WREG32_PCIE_PORT(PCIE_LC_CNTL2, data); 170862a37553SKen Wang 170962a37553SKen Wang orig = data = RREG32(THM_CLK_CNTL); 171062a37553SKen Wang data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK); 171162a37553SKen Wang data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1); 171262a37553SKen Wang if (orig != data) 171362a37553SKen Wang WREG32(THM_CLK_CNTL, data); 171462a37553SKen Wang 171562a37553SKen Wang orig = data = RREG32(MISC_CLK_CNTL); 171662a37553SKen Wang data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK); 171762a37553SKen Wang data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1); 171862a37553SKen Wang if (orig != data) 171962a37553SKen Wang WREG32(MISC_CLK_CNTL, data); 172062a37553SKen Wang 172162a37553SKen Wang orig = data = RREG32(CG_CLKPIN_CNTL); 172262a37553SKen Wang data &= ~BCLK_AS_XCLK; 172362a37553SKen Wang if (orig != data) 172462a37553SKen Wang WREG32(CG_CLKPIN_CNTL, data); 172562a37553SKen Wang 172662a37553SKen Wang orig = data = RREG32(CG_CLKPIN_CNTL_2); 172762a37553SKen Wang data &= ~FORCE_BIF_REFCLK_EN; 172862a37553SKen Wang if (orig != data) 172962a37553SKen Wang WREG32(CG_CLKPIN_CNTL_2, data); 173062a37553SKen Wang 173162a37553SKen Wang orig = data = RREG32(MPLL_BYPASSCLK_SEL); 173262a37553SKen Wang data &= ~MPLL_CLKOUT_SEL_MASK; 173362a37553SKen Wang data |= MPLL_CLKOUT_SEL(4); 173462a37553SKen Wang if (orig != data) 173562a37553SKen Wang WREG32(MPLL_BYPASSCLK_SEL, data); 173662a37553SKen Wang 173762a37553SKen Wang orig = data = RREG32(SPLL_CNTL_MODE); 173862a37553SKen Wang data &= ~SPLL_REFCLK_SEL_MASK; 173962a37553SKen Wang if (orig != data) 174062a37553SKen Wang WREG32(SPLL_CNTL_MODE, data); 174162a37553SKen Wang } 174262a37553SKen Wang } 174362a37553SKen Wang } else { 174462a37553SKen Wang if (orig != data) 174536b9a952SHuang Rui WREG32_PCIE_PORT(PCIE_LC_CNTL, data); 174662a37553SKen Wang } 174762a37553SKen Wang 174862a37553SKen Wang orig = data = RREG32_PCIE(PCIE_CNTL2); 174962a37553SKen Wang data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN; 175062a37553SKen Wang if (orig != data) 175162a37553SKen Wang WREG32_PCIE(PCIE_CNTL2, data); 175262a37553SKen Wang 175362a37553SKen Wang if (!disable_l0s) { 175436b9a952SHuang Rui data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL); 175562a37553SKen Wang if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) { 175662a37553SKen Wang data = RREG32_PCIE(PCIE_LC_STATUS1); 175762a37553SKen Wang if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) { 175836b9a952SHuang Rui orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL); 175962a37553SKen Wang data &= ~LC_L0S_INACTIVITY_MASK; 176062a37553SKen Wang if (orig != data) 176136b9a952SHuang Rui WREG32_PCIE_PORT(PCIE_LC_CNTL, data); 176262a37553SKen Wang } 176362a37553SKen Wang } 176462a37553SKen Wang } 176562a37553SKen Wang } 176662a37553SKen Wang 176762a37553SKen Wang static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev) 176862a37553SKen Wang { 176962a37553SKen Wang int readrq; 177062a37553SKen Wang u16 v; 177162a37553SKen Wang 177262a37553SKen Wang readrq = pcie_get_readrq(adev->pdev); 177362a37553SKen Wang v = ffs(readrq) - 8; 177462a37553SKen Wang if ((v == 0) || (v == 6) || (v == 7)) 177562a37553SKen Wang pcie_set_readrq(adev->pdev, 512); 177662a37553SKen Wang } 177762a37553SKen Wang 177862a37553SKen Wang static int si_common_hw_init(void *handle) 177962a37553SKen Wang { 178062a37553SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 178162a37553SKen Wang 178262a37553SKen Wang si_fix_pci_max_read_req_size(adev); 178362a37553SKen Wang si_init_golden_registers(adev); 178462a37553SKen Wang si_pcie_gen3_enable(adev); 178562a37553SKen Wang si_program_aspm(adev); 178662a37553SKen Wang 178762a37553SKen Wang return 0; 178862a37553SKen Wang } 178962a37553SKen Wang 179062a37553SKen Wang static int si_common_hw_fini(void *handle) 179162a37553SKen Wang { 179262a37553SKen Wang return 0; 179362a37553SKen Wang } 179462a37553SKen Wang 179562a37553SKen Wang static int si_common_suspend(void *handle) 179662a37553SKen Wang { 179762a37553SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 179862a37553SKen Wang 179962a37553SKen Wang return si_common_hw_fini(adev); 180062a37553SKen Wang } 180162a37553SKen Wang 180262a37553SKen Wang static int si_common_resume(void *handle) 180362a37553SKen Wang { 180462a37553SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 180562a37553SKen Wang 180662a37553SKen Wang return si_common_hw_init(adev); 180762a37553SKen Wang } 180862a37553SKen Wang 180962a37553SKen Wang static bool si_common_is_idle(void *handle) 181062a37553SKen Wang { 181162a37553SKen Wang return true; 181262a37553SKen Wang } 181362a37553SKen Wang 181462a37553SKen Wang static int si_common_wait_for_idle(void *handle) 181562a37553SKen Wang { 181662a37553SKen Wang return 0; 181762a37553SKen Wang } 181862a37553SKen Wang 181962a37553SKen Wang static int si_common_soft_reset(void *handle) 182062a37553SKen Wang { 182162a37553SKen Wang return 0; 182262a37553SKen Wang } 182362a37553SKen Wang 182462a37553SKen Wang static int si_common_set_clockgating_state(void *handle, 182562a37553SKen Wang enum amd_clockgating_state state) 182662a37553SKen Wang { 182762a37553SKen Wang return 0; 182862a37553SKen Wang } 182962a37553SKen Wang 183062a37553SKen Wang static int si_common_set_powergating_state(void *handle, 183162a37553SKen Wang enum amd_powergating_state state) 183262a37553SKen Wang { 183362a37553SKen Wang return 0; 183462a37553SKen Wang } 183562a37553SKen Wang 1836a1255107SAlex Deucher static const struct amd_ip_funcs si_common_ip_funcs = { 183762a37553SKen Wang .name = "si_common", 183862a37553SKen Wang .early_init = si_common_early_init, 183962a37553SKen Wang .late_init = NULL, 184062a37553SKen Wang .sw_init = si_common_sw_init, 184162a37553SKen Wang .sw_fini = si_common_sw_fini, 184262a37553SKen Wang .hw_init = si_common_hw_init, 184362a37553SKen Wang .hw_fini = si_common_hw_fini, 184462a37553SKen Wang .suspend = si_common_suspend, 184562a37553SKen Wang .resume = si_common_resume, 184662a37553SKen Wang .is_idle = si_common_is_idle, 184762a37553SKen Wang .wait_for_idle = si_common_wait_for_idle, 184862a37553SKen Wang .soft_reset = si_common_soft_reset, 184962a37553SKen Wang .set_clockgating_state = si_common_set_clockgating_state, 185062a37553SKen Wang .set_powergating_state = si_common_set_powergating_state, 185162a37553SKen Wang }; 185262a37553SKen Wang 1853a1255107SAlex Deucher static const struct amdgpu_ip_block_version si_common_ip_block = 185462a37553SKen Wang { 185562a37553SKen Wang .type = AMD_IP_BLOCK_TYPE_COMMON, 185662a37553SKen Wang .major = 1, 185762a37553SKen Wang .minor = 0, 185862a37553SKen Wang .rev = 0, 185962a37553SKen Wang .funcs = &si_common_ip_funcs, 18602120df47SAlex Deucher }; 18612120df47SAlex Deucher 186262a37553SKen Wang int si_set_ip_blocks(struct amdgpu_device *adev) 186362a37553SKen Wang { 186462a37553SKen Wang switch (adev->asic_type) { 186562a37553SKen Wang case CHIP_VERDE: 186662a37553SKen Wang case CHIP_TAHITI: 186762a37553SKen Wang case CHIP_PITCAIRN: 1868a1255107SAlex Deucher amdgpu_ip_block_add(adev, &si_common_ip_block); 1869a1255107SAlex Deucher amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); 1870a1255107SAlex Deucher amdgpu_ip_block_add(adev, &si_ih_ip_block); 1871a1255107SAlex Deucher amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1872a1255107SAlex Deucher if (adev->enable_virtual_display) 1873a1255107SAlex Deucher amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1874a1255107SAlex Deucher else 1875a1255107SAlex Deucher amdgpu_ip_block_add(adev, &dce_v6_0_ip_block); 1876a1255107SAlex Deucher amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); 1877a1255107SAlex Deucher amdgpu_ip_block_add(adev, &si_dma_ip_block); 1878a1255107SAlex Deucher /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */ 1879a1255107SAlex Deucher /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */ 1880a1255107SAlex Deucher break; 188162a37553SKen Wang case CHIP_OLAND: 1882a1255107SAlex Deucher amdgpu_ip_block_add(adev, &si_common_ip_block); 1883a1255107SAlex Deucher amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); 1884a1255107SAlex Deucher amdgpu_ip_block_add(adev, &si_ih_ip_block); 1885a1255107SAlex Deucher amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1886a1255107SAlex Deucher if (adev->enable_virtual_display) 1887a1255107SAlex Deucher amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1888a1255107SAlex Deucher else 1889a1255107SAlex Deucher amdgpu_ip_block_add(adev, &dce_v6_4_ip_block); 1890a1255107SAlex Deucher amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); 1891a1255107SAlex Deucher amdgpu_ip_block_add(adev, &si_dma_ip_block); 1892a1255107SAlex Deucher /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */ 1893a1255107SAlex Deucher /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */ 189462a37553SKen Wang break; 189562a37553SKen Wang case CHIP_HAINAN: 1896a1255107SAlex Deucher amdgpu_ip_block_add(adev, &si_common_ip_block); 1897a1255107SAlex Deucher amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); 1898a1255107SAlex Deucher amdgpu_ip_block_add(adev, &si_ih_ip_block); 1899a1255107SAlex Deucher amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1900a1255107SAlex Deucher if (adev->enable_virtual_display) 1901a1255107SAlex Deucher amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1902a1255107SAlex Deucher amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); 1903a1255107SAlex Deucher amdgpu_ip_block_add(adev, &si_dma_ip_block); 190462a37553SKen Wang break; 190562a37553SKen Wang default: 190662a37553SKen Wang BUG(); 190762a37553SKen Wang } 190862a37553SKen Wang return 0; 190962a37553SKen Wang } 191062a37553SKen Wang 1911