1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <drm/drm_drv.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_vpe.h" 29 #include "amdgpu_smu.h" 30 #include "soc15_common.h" 31 #include "vpe_v6_1.h" 32 33 #define AMDGPU_CSA_VPE_SIZE 64 34 /* VPE CSA resides in the 4th page of CSA */ 35 #define AMDGPU_CSA_VPE_OFFSET (4096 * 3) 36 37 /* 1 second timeout */ 38 #define VPE_IDLE_TIMEOUT msecs_to_jiffies(1000) 39 40 #define VPE_MAX_DPM_LEVEL 4 41 #define FIXED1_8_BITS_PER_FRACTIONAL_PART 8 42 #define GET_PRATIO_INTEGER_PART(x) ((x) >> FIXED1_8_BITS_PER_FRACTIONAL_PART) 43 44 static void vpe_set_ring_funcs(struct amdgpu_device *adev); 45 46 static inline uint16_t div16_u16_rem(uint16_t dividend, uint16_t divisor, uint16_t *remainder) 47 { 48 *remainder = dividend % divisor; 49 return dividend / divisor; 50 } 51 52 static inline uint16_t complete_integer_division_u16( 53 uint16_t dividend, 54 uint16_t divisor, 55 uint16_t *remainder) 56 { 57 return div16_u16_rem(dividend, divisor, (uint16_t *)remainder); 58 } 59 60 static uint16_t vpe_u1_8_from_fraction(uint16_t numerator, uint16_t denominator) 61 { 62 u16 arg1_value = numerator; 63 u16 arg2_value = denominator; 64 65 uint16_t remainder; 66 67 /* determine integer part */ 68 uint16_t res_value = complete_integer_division_u16( 69 arg1_value, arg2_value, &remainder); 70 71 if (res_value > 127 /* CHAR_MAX */) 72 return 0; 73 74 /* determine fractional part */ 75 { 76 unsigned int i = FIXED1_8_BITS_PER_FRACTIONAL_PART; 77 78 do { 79 remainder <<= 1; 80 81 res_value <<= 1; 82 83 if (remainder >= arg2_value) { 84 res_value |= 1; 85 remainder -= arg2_value; 86 } 87 } while (--i != 0); 88 } 89 90 /* round up LSB */ 91 { 92 uint16_t summand = (remainder << 1) >= arg2_value; 93 94 if ((res_value + summand) > 32767 /* SHRT_MAX */) 95 return 0; 96 97 res_value += summand; 98 } 99 100 return res_value; 101 } 102 103 static uint16_t vpe_internal_get_pratio(uint16_t from_frequency, uint16_t to_frequency) 104 { 105 uint16_t pratio = vpe_u1_8_from_fraction(from_frequency, to_frequency); 106 107 if (GET_PRATIO_INTEGER_PART(pratio) > 1) 108 pratio = 0; 109 110 return pratio; 111 } 112 113 /* 114 * VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest), 115 * VPE FW will dynamically decide which level should be used according to current loading. 116 * 117 * Get VPE and SOC clocks from PM, and select the appropriate four clock values, 118 * calculate the ratios of adjusting from one clock to another. 119 * The VPE FW can then request the appropriate frequency from the PMFW. 120 */ 121 int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe) 122 { 123 struct amdgpu_device *adev = vpe->ring.adev; 124 uint32_t dpm_ctl; 125 126 if (adev->pm.dpm_enabled) { 127 struct dpm_clocks clock_table = { 0 }; 128 struct dpm_clock *VPEClks; 129 struct dpm_clock *SOCClks; 130 uint32_t idx; 131 uint32_t vpeclk_enalbled_num = 0; 132 uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0; 133 uint16_t pratio_vmin_freq = 0, pratio_vmid_freq = 0, pratio_vnorm_freq = 0, pratio_vmax_freq = 0; 134 135 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable)); 136 dpm_ctl |= 1; /* DPM enablement */ 137 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl); 138 139 /* Get VPECLK and SOCCLK */ 140 if (amdgpu_dpm_get_dpm_clock_table(adev, &clock_table)) { 141 dev_dbg(adev->dev, "%s: get clock failed!\n", __func__); 142 goto disable_dpm; 143 } 144 145 SOCClks = clock_table.SocClocks; 146 VPEClks = clock_table.VPEClocks; 147 148 /* Comfirm enabled vpe clk num 149 * Enabled VPE clocks are ordered from low to high in VPEClks 150 * The highest valid clock index+1 is the number of VPEClks 151 */ 152 for (idx = PP_SMU_NUM_VPECLK_DPM_LEVELS; idx && !vpeclk_enalbled_num; idx--) 153 if (VPEClks[idx-1].Freq) 154 vpeclk_enalbled_num = idx; 155 156 /* vpe dpm only cares 4 levels. */ 157 for (idx = 0; idx < VPE_MAX_DPM_LEVEL; idx++) { 158 uint32_t soc_dpm_level; 159 uint32_t min_freq; 160 161 if (idx == 0) 162 soc_dpm_level = 0; 163 else 164 soc_dpm_level = (idx * 2) + 1; 165 166 /* clamp the max level */ 167 if (soc_dpm_level > vpeclk_enalbled_num - 1) 168 soc_dpm_level = vpeclk_enalbled_num - 1; 169 170 min_freq = (SOCClks[soc_dpm_level].Freq < VPEClks[soc_dpm_level].Freq) ? 171 SOCClks[soc_dpm_level].Freq : VPEClks[soc_dpm_level].Freq; 172 173 switch (idx) { 174 case 0: 175 pratio_vmin_freq = min_freq; 176 break; 177 case 1: 178 pratio_vmid_freq = min_freq; 179 break; 180 case 2: 181 pratio_vnorm_freq = min_freq; 182 break; 183 case 3: 184 pratio_vmax_freq = min_freq; 185 break; 186 default: 187 break; 188 } 189 } 190 191 if (pratio_vmin_freq && pratio_vmid_freq && pratio_vnorm_freq && pratio_vmax_freq) { 192 uint32_t pratio_ctl; 193 194 pratio_vmax_vnorm = (uint32_t)vpe_internal_get_pratio(pratio_vmax_freq, pratio_vnorm_freq); 195 pratio_vnorm_vmid = (uint32_t)vpe_internal_get_pratio(pratio_vnorm_freq, pratio_vmid_freq); 196 pratio_vmid_vmin = (uint32_t)vpe_internal_get_pratio(pratio_vmid_freq, pratio_vmin_freq); 197 198 pratio_ctl = pratio_vmax_vnorm | (pratio_vnorm_vmid << 9) | (pratio_vmid_vmin << 18); 199 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_pratio), pratio_ctl); /* PRatio */ 200 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_interval), 24000); /* 1ms, unit=1/24MHz */ 201 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_decision_threshold), 1200000); /* 50ms */ 202 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */ 203 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */ 204 dev_dbg(adev->dev, "%s: configure vpe dpm pratio done!\n", __func__); 205 } else { 206 dev_dbg(adev->dev, "%s: invalid pratio parameters!\n", __func__); 207 goto disable_dpm; 208 } 209 } 210 return 0; 211 212 disable_dpm: 213 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable)); 214 dpm_ctl &= 0xfffffffe; /* Disable DPM */ 215 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl); 216 dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__); 217 return -EINVAL; 218 } 219 220 int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev) 221 { 222 struct amdgpu_firmware_info ucode = { 223 .ucode_id = AMDGPU_UCODE_ID_VPE, 224 .mc_addr = adev->vpe.cmdbuf_gpu_addr, 225 .ucode_size = 8, 226 }; 227 228 return psp_execute_ip_fw_load(&adev->psp, &ucode); 229 } 230 231 int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe) 232 { 233 struct amdgpu_device *adev = vpe->ring.adev; 234 const struct vpe_firmware_header_v1_0 *vpe_hdr; 235 char fw_prefix[32]; 236 int ret; 237 238 amdgpu_ucode_ip_version_decode(adev, VPE_HWIP, fw_prefix, sizeof(fw_prefix)); 239 ret = amdgpu_ucode_request(adev, &adev->vpe.fw, AMDGPU_UCODE_REQUIRED, 240 "amdgpu/%s.bin", fw_prefix); 241 if (ret) 242 goto out; 243 244 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data; 245 adev->vpe.fw_version = le32_to_cpu(vpe_hdr->header.ucode_version); 246 adev->vpe.feature_version = le32_to_cpu(vpe_hdr->ucode_feature_version); 247 248 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 249 struct amdgpu_firmware_info *info; 250 251 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTX]; 252 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTX; 253 info->fw = adev->vpe.fw; 254 adev->firmware.fw_size += 255 ALIGN(le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes), PAGE_SIZE); 256 257 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTL]; 258 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTL; 259 info->fw = adev->vpe.fw; 260 adev->firmware.fw_size += 261 ALIGN(le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes), PAGE_SIZE); 262 } 263 264 return 0; 265 out: 266 dev_err(adev->dev, "fail to initialize vpe microcode\n"); 267 release_firmware(adev->vpe.fw); 268 adev->vpe.fw = NULL; 269 return ret; 270 } 271 272 int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe) 273 { 274 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe); 275 struct amdgpu_ring *ring = &vpe->ring; 276 int ret; 277 278 ring->ring_obj = NULL; 279 ring->use_doorbell = true; 280 ring->vm_hub = AMDGPU_MMHUB0(0); 281 ring->doorbell_index = (adev->doorbell_index.vpe_ring << 1); 282 snprintf(ring->name, 4, "vpe"); 283 284 ret = amdgpu_ring_init(adev, ring, 1024, &vpe->trap_irq, 0, 285 AMDGPU_RING_PRIO_DEFAULT, NULL); 286 if (ret) 287 return ret; 288 289 return 0; 290 } 291 292 int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe) 293 { 294 amdgpu_ring_fini(&vpe->ring); 295 296 return 0; 297 } 298 299 static int vpe_early_init(struct amdgpu_ip_block *ip_block) 300 { 301 struct amdgpu_device *adev = ip_block->adev; 302 struct amdgpu_vpe *vpe = &adev->vpe; 303 304 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 305 case IP_VERSION(6, 1, 0): 306 case IP_VERSION(6, 1, 3): 307 vpe_v6_1_set_funcs(vpe); 308 break; 309 case IP_VERSION(6, 1, 1): 310 vpe_v6_1_set_funcs(vpe); 311 vpe->collaborate_mode = true; 312 break; 313 default: 314 return -EINVAL; 315 } 316 317 vpe_set_ring_funcs(adev); 318 vpe_set_regs(vpe); 319 320 dev_info(adev->dev, "VPE: collaborate mode %s", vpe->collaborate_mode ? "true" : "false"); 321 322 return 0; 323 } 324 325 static void vpe_idle_work_handler(struct work_struct *work) 326 { 327 struct amdgpu_device *adev = 328 container_of(work, struct amdgpu_device, vpe.idle_work.work); 329 unsigned int fences = 0; 330 331 fences += amdgpu_fence_count_emitted(&adev->vpe.ring); 332 333 if (fences == 0) 334 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); 335 else 336 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); 337 } 338 339 static int vpe_common_init(struct amdgpu_vpe *vpe) 340 { 341 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe); 342 int r; 343 344 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 345 AMDGPU_GEM_DOMAIN_GTT, 346 &adev->vpe.cmdbuf_obj, 347 &adev->vpe.cmdbuf_gpu_addr, 348 (void **)&adev->vpe.cmdbuf_cpu_addr); 349 if (r) { 350 dev_err(adev->dev, "VPE: failed to allocate cmdbuf bo %d\n", r); 351 return r; 352 } 353 354 vpe->context_started = false; 355 INIT_DELAYED_WORK(&adev->vpe.idle_work, vpe_idle_work_handler); 356 357 return 0; 358 } 359 360 static int vpe_sw_init(struct amdgpu_ip_block *ip_block) 361 { 362 struct amdgpu_device *adev = ip_block->adev; 363 struct amdgpu_vpe *vpe = &adev->vpe; 364 int ret; 365 366 ret = vpe_common_init(vpe); 367 if (ret) 368 goto out; 369 370 ret = vpe_irq_init(vpe); 371 if (ret) 372 goto out; 373 374 ret = vpe_ring_init(vpe); 375 if (ret) 376 goto out; 377 378 ret = vpe_init_microcode(vpe); 379 if (ret) 380 goto out; 381 382 adev->vpe.supported_reset = 383 amdgpu_get_soft_full_reset_mask(&adev->vpe.ring); 384 if (!amdgpu_sriov_vf(adev)) 385 adev->vpe.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 386 ret = amdgpu_vpe_sysfs_reset_mask_init(adev); 387 if (ret) 388 goto out; 389 out: 390 return ret; 391 } 392 393 static int vpe_sw_fini(struct amdgpu_ip_block *ip_block) 394 { 395 struct amdgpu_device *adev = ip_block->adev; 396 struct amdgpu_vpe *vpe = &adev->vpe; 397 398 release_firmware(vpe->fw); 399 vpe->fw = NULL; 400 401 amdgpu_vpe_sysfs_reset_mask_fini(adev); 402 vpe_ring_fini(vpe); 403 404 amdgpu_bo_free_kernel(&adev->vpe.cmdbuf_obj, 405 &adev->vpe.cmdbuf_gpu_addr, 406 (void **)&adev->vpe.cmdbuf_cpu_addr); 407 408 return 0; 409 } 410 411 static int vpe_hw_init(struct amdgpu_ip_block *ip_block) 412 { 413 struct amdgpu_device *adev = ip_block->adev; 414 struct amdgpu_vpe *vpe = &adev->vpe; 415 int ret; 416 417 /* Power on VPE */ 418 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, 419 AMD_PG_STATE_UNGATE); 420 if (ret) 421 return ret; 422 423 ret = vpe_load_microcode(vpe); 424 if (ret) 425 return ret; 426 427 ret = vpe_ring_start(vpe); 428 if (ret) 429 return ret; 430 431 return 0; 432 } 433 434 static int vpe_hw_fini(struct amdgpu_ip_block *ip_block) 435 { 436 struct amdgpu_device *adev = ip_block->adev; 437 struct amdgpu_vpe *vpe = &adev->vpe; 438 439 vpe_ring_stop(vpe); 440 441 /* Power off VPE */ 442 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); 443 444 return 0; 445 } 446 447 static int vpe_suspend(struct amdgpu_ip_block *ip_block) 448 { 449 struct amdgpu_device *adev = ip_block->adev; 450 451 cancel_delayed_work_sync(&adev->vpe.idle_work); 452 453 return vpe_hw_fini(ip_block); 454 } 455 456 static int vpe_resume(struct amdgpu_ip_block *ip_block) 457 { 458 return vpe_hw_init(ip_block); 459 } 460 461 static void vpe_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 462 { 463 int i; 464 465 for (i = 0; i < count; i++) 466 if (i == 0) 467 amdgpu_ring_write(ring, ring->funcs->nop | 468 VPE_CMD_NOP_HEADER_COUNT(count - 1)); 469 else 470 amdgpu_ring_write(ring, ring->funcs->nop); 471 } 472 473 static uint64_t vpe_get_csa_mc_addr(struct amdgpu_ring *ring, uint32_t vmid) 474 { 475 struct amdgpu_device *adev = ring->adev; 476 uint32_t index = 0; 477 uint64_t csa_mc_addr; 478 479 if (amdgpu_sriov_vf(adev) || vmid == 0 || !adev->gfx.mcbp) 480 return 0; 481 482 csa_mc_addr = amdgpu_csa_vaddr(adev) + AMDGPU_CSA_VPE_OFFSET + 483 index * AMDGPU_CSA_VPE_SIZE; 484 485 return csa_mc_addr; 486 } 487 488 static void vpe_ring_emit_pred_exec(struct amdgpu_ring *ring, 489 uint32_t device_select, 490 uint32_t exec_count) 491 { 492 if (!ring->adev->vpe.collaborate_mode) 493 return; 494 495 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_PRED_EXE, 0) | 496 (device_select << 16)); 497 amdgpu_ring_write(ring, exec_count & 0x1fff); 498 } 499 500 static void vpe_ring_emit_ib(struct amdgpu_ring *ring, 501 struct amdgpu_job *job, 502 struct amdgpu_ib *ib, 503 uint32_t flags) 504 { 505 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); 506 uint64_t csa_mc_addr = vpe_get_csa_mc_addr(ring, vmid); 507 508 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0) | 509 VPE_CMD_INDIRECT_HEADER_VMID(vmid & 0xf)); 510 511 /* base must be 32 byte aligned */ 512 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); 513 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 514 amdgpu_ring_write(ring, ib->length_dw); 515 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 516 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 517 } 518 519 static void vpe_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, 520 uint64_t seq, unsigned int flags) 521 { 522 int i = 0; 523 524 do { 525 /* write the fence */ 526 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0)); 527 /* zero in first two bits */ 528 WARN_ON_ONCE(addr & 0x3); 529 amdgpu_ring_write(ring, lower_32_bits(addr)); 530 amdgpu_ring_write(ring, upper_32_bits(addr)); 531 amdgpu_ring_write(ring, i == 0 ? lower_32_bits(seq) : upper_32_bits(seq)); 532 addr += 4; 533 } while ((flags & AMDGPU_FENCE_FLAG_64BIT) && (i++ < 1)); 534 535 if (flags & AMDGPU_FENCE_FLAG_INT) { 536 /* generate an interrupt */ 537 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_TRAP, 0)); 538 amdgpu_ring_write(ring, 0); 539 } 540 541 } 542 543 static void vpe_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 544 { 545 uint32_t seq = ring->fence_drv.sync_seq; 546 uint64_t addr = ring->fence_drv.gpu_addr; 547 548 vpe_ring_emit_pred_exec(ring, 0, 6); 549 550 /* wait for idle */ 551 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM, 552 VPE_POLL_REGMEM_SUBOP_REGMEM) | 553 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 554 VPE_CMD_POLL_REGMEM_HEADER_MEM(1)); 555 amdgpu_ring_write(ring, addr & 0xfffffffc); 556 amdgpu_ring_write(ring, upper_32_bits(addr)); 557 amdgpu_ring_write(ring, seq); /* reference */ 558 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 559 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 560 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(4)); 561 } 562 563 static void vpe_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 564 { 565 vpe_ring_emit_pred_exec(ring, 0, 3); 566 567 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_REG_WRITE, 0)); 568 amdgpu_ring_write(ring, reg << 2); 569 amdgpu_ring_write(ring, val); 570 } 571 572 static void vpe_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 573 uint32_t val, uint32_t mask) 574 { 575 vpe_ring_emit_pred_exec(ring, 0, 6); 576 577 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM, 578 VPE_POLL_REGMEM_SUBOP_REGMEM) | 579 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 580 VPE_CMD_POLL_REGMEM_HEADER_MEM(0)); 581 amdgpu_ring_write(ring, reg << 2); 582 amdgpu_ring_write(ring, 0); 583 amdgpu_ring_write(ring, val); /* reference */ 584 amdgpu_ring_write(ring, mask); /* mask */ 585 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 586 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(10)); 587 } 588 589 static void vpe_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid, 590 uint64_t pd_addr) 591 { 592 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 593 } 594 595 static unsigned int vpe_ring_init_cond_exec(struct amdgpu_ring *ring, 596 uint64_t addr) 597 { 598 unsigned int ret; 599 600 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COND_EXE, 0)); 601 amdgpu_ring_write(ring, lower_32_bits(addr)); 602 amdgpu_ring_write(ring, upper_32_bits(addr)); 603 amdgpu_ring_write(ring, 1); 604 ret = ring->wptr & ring->buf_mask; 605 amdgpu_ring_write(ring, 0); 606 607 return ret; 608 } 609 610 static int vpe_ring_preempt_ib(struct amdgpu_ring *ring) 611 { 612 struct amdgpu_device *adev = ring->adev; 613 struct amdgpu_vpe *vpe = &adev->vpe; 614 uint32_t preempt_reg = vpe->regs.queue0_preempt; 615 int i, r = 0; 616 617 /* assert preemption condition */ 618 amdgpu_ring_set_preempt_cond_exec(ring, false); 619 620 /* emit the trailing fence */ 621 ring->trail_seq += 1; 622 amdgpu_ring_alloc(ring, 10); 623 vpe_ring_emit_fence(ring, ring->trail_fence_gpu_addr, ring->trail_seq, 0); 624 amdgpu_ring_commit(ring); 625 626 /* assert IB preemption */ 627 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 1); 628 629 /* poll the trailing fence */ 630 for (i = 0; i < adev->usec_timeout; i++) { 631 if (ring->trail_seq == 632 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 633 break; 634 udelay(1); 635 } 636 637 if (i >= adev->usec_timeout) { 638 r = -EINVAL; 639 dev_err(adev->dev, "ring %d failed to be preempted\n", ring->idx); 640 } 641 642 /* deassert IB preemption */ 643 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 0); 644 645 /* deassert the preemption condition */ 646 amdgpu_ring_set_preempt_cond_exec(ring, true); 647 648 return r; 649 } 650 651 static int vpe_set_clockgating_state(struct amdgpu_ip_block *ip_block, 652 enum amd_clockgating_state state) 653 { 654 return 0; 655 } 656 657 static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block, 658 enum amd_powergating_state state) 659 { 660 struct amdgpu_device *adev = ip_block->adev; 661 struct amdgpu_vpe *vpe = &adev->vpe; 662 663 if (!adev->pm.dpm_enabled) 664 dev_err(adev->dev, "Without PM, cannot support powergating\n"); 665 666 dev_dbg(adev->dev, "%s: %s!\n", __func__, (state == AMD_PG_STATE_GATE) ? "GATE":"UNGATE"); 667 668 if (state == AMD_PG_STATE_GATE) { 669 amdgpu_dpm_enable_vpe(adev, false); 670 vpe->context_started = false; 671 } else { 672 amdgpu_dpm_enable_vpe(adev, true); 673 } 674 675 return 0; 676 } 677 678 static uint64_t vpe_ring_get_rptr(struct amdgpu_ring *ring) 679 { 680 struct amdgpu_device *adev = ring->adev; 681 struct amdgpu_vpe *vpe = &adev->vpe; 682 uint64_t rptr; 683 684 if (ring->use_doorbell) { 685 rptr = atomic64_read((atomic64_t *)ring->rptr_cpu_addr); 686 dev_dbg(adev->dev, "rptr/doorbell before shift == 0x%016llx\n", rptr); 687 } else { 688 rptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_hi)); 689 rptr = rptr << 32; 690 rptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_lo)); 691 dev_dbg(adev->dev, "rptr before shift [%i] == 0x%016llx\n", ring->me, rptr); 692 } 693 694 return (rptr >> 2); 695 } 696 697 static uint64_t vpe_ring_get_wptr(struct amdgpu_ring *ring) 698 { 699 struct amdgpu_device *adev = ring->adev; 700 struct amdgpu_vpe *vpe = &adev->vpe; 701 uint64_t wptr; 702 703 if (ring->use_doorbell) { 704 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 705 dev_dbg(adev->dev, "wptr/doorbell before shift == 0x%016llx\n", wptr); 706 } else { 707 wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi)); 708 wptr = wptr << 32; 709 wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo)); 710 dev_dbg(adev->dev, "wptr before shift [%i] == 0x%016llx\n", ring->me, wptr); 711 } 712 713 return (wptr >> 2); 714 } 715 716 static void vpe_ring_set_wptr(struct amdgpu_ring *ring) 717 { 718 struct amdgpu_device *adev = ring->adev; 719 struct amdgpu_vpe *vpe = &adev->vpe; 720 721 if (ring->use_doorbell) { 722 dev_dbg(adev->dev, "Using doorbell, \ 723 wptr_offs == 0x%08x, \ 724 lower_32_bits(ring->wptr) << 2 == 0x%08x, \ 725 upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 726 ring->wptr_offs, 727 lower_32_bits(ring->wptr << 2), 728 upper_32_bits(ring->wptr << 2)); 729 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr << 2); 730 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 731 if (vpe->collaborate_mode) 732 WDOORBELL64(ring->doorbell_index + 4, ring->wptr << 2); 733 } else { 734 int i; 735 736 for (i = 0; i < vpe->num_instances; i++) { 737 dev_dbg(adev->dev, "Not using doorbell, \ 738 regVPEC_QUEUE0_RB_WPTR == 0x%08x, \ 739 regVPEC_QUEUE0_RB_WPTR_HI == 0x%08x\n", 740 lower_32_bits(ring->wptr << 2), 741 upper_32_bits(ring->wptr << 2)); 742 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_lo), 743 lower_32_bits(ring->wptr << 2)); 744 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_hi), 745 upper_32_bits(ring->wptr << 2)); 746 } 747 } 748 } 749 750 static int vpe_ring_test_ring(struct amdgpu_ring *ring) 751 { 752 struct amdgpu_device *adev = ring->adev; 753 const uint32_t test_pattern = 0xdeadbeef; 754 uint32_t index, i; 755 uint64_t wb_addr; 756 int ret; 757 758 ret = amdgpu_device_wb_get(adev, &index); 759 if (ret) { 760 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret); 761 return ret; 762 } 763 764 adev->wb.wb[index] = 0; 765 wb_addr = adev->wb.gpu_addr + (index * 4); 766 767 ret = amdgpu_ring_alloc(ring, 4); 768 if (ret) { 769 dev_err(adev->dev, "amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, ret); 770 goto out; 771 } 772 773 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0)); 774 amdgpu_ring_write(ring, lower_32_bits(wb_addr)); 775 amdgpu_ring_write(ring, upper_32_bits(wb_addr)); 776 amdgpu_ring_write(ring, test_pattern); 777 amdgpu_ring_commit(ring); 778 779 for (i = 0; i < adev->usec_timeout; i++) { 780 if (le32_to_cpu(adev->wb.wb[index]) == test_pattern) 781 goto out; 782 udelay(1); 783 } 784 785 ret = -ETIMEDOUT; 786 out: 787 amdgpu_device_wb_free(adev, index); 788 789 return ret; 790 } 791 792 static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout) 793 { 794 struct amdgpu_device *adev = ring->adev; 795 const uint32_t test_pattern = 0xdeadbeef; 796 struct amdgpu_ib ib = {}; 797 struct dma_fence *f = NULL; 798 uint32_t index; 799 uint64_t wb_addr; 800 int ret; 801 802 ret = amdgpu_device_wb_get(adev, &index); 803 if (ret) { 804 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret); 805 return ret; 806 } 807 808 adev->wb.wb[index] = 0; 809 wb_addr = adev->wb.gpu_addr + (index * 4); 810 811 ret = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 812 if (ret) 813 goto err0; 814 815 ib.ptr[0] = VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0); 816 ib.ptr[1] = lower_32_bits(wb_addr); 817 ib.ptr[2] = upper_32_bits(wb_addr); 818 ib.ptr[3] = test_pattern; 819 ib.ptr[4] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 820 ib.ptr[5] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 821 ib.ptr[6] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 822 ib.ptr[7] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0); 823 ib.length_dw = 8; 824 825 ret = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 826 if (ret) 827 goto err1; 828 829 ret = dma_fence_wait_timeout(f, false, timeout); 830 if (ret <= 0) { 831 ret = ret ? : -ETIMEDOUT; 832 goto err1; 833 } 834 835 ret = (le32_to_cpu(adev->wb.wb[index]) == test_pattern) ? 0 : -EINVAL; 836 837 err1: 838 amdgpu_ib_free(&ib, NULL); 839 dma_fence_put(f); 840 err0: 841 amdgpu_device_wb_free(adev, index); 842 843 return ret; 844 } 845 846 static void vpe_ring_begin_use(struct amdgpu_ring *ring) 847 { 848 struct amdgpu_device *adev = ring->adev; 849 struct amdgpu_vpe *vpe = &adev->vpe; 850 851 cancel_delayed_work_sync(&adev->vpe.idle_work); 852 853 /* Power on VPE and notify VPE of new context */ 854 if (!vpe->context_started) { 855 uint32_t context_notify; 856 857 /* Power on VPE */ 858 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_UNGATE); 859 860 /* Indicates that a job from a new context has been submitted. */ 861 context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator)); 862 if ((context_notify & 0x1) == 0) 863 context_notify |= 0x1; 864 else 865 context_notify &= ~(0x1); 866 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator), context_notify); 867 vpe->context_started = true; 868 } 869 } 870 871 static void vpe_ring_end_use(struct amdgpu_ring *ring) 872 { 873 struct amdgpu_device *adev = ring->adev; 874 875 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); 876 } 877 878 static int vpe_ring_reset(struct amdgpu_ring *ring, 879 unsigned int vmid, 880 struct amdgpu_fence *timedout_fence) 881 { 882 struct amdgpu_device *adev = ring->adev; 883 int r; 884 885 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 886 887 r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, 888 AMD_PG_STATE_GATE); 889 if (r) 890 return r; 891 r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, 892 AMD_PG_STATE_UNGATE); 893 if (r) 894 return r; 895 896 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 897 } 898 899 static ssize_t amdgpu_get_vpe_reset_mask(struct device *dev, 900 struct device_attribute *attr, 901 char *buf) 902 { 903 struct drm_device *ddev = dev_get_drvdata(dev); 904 struct amdgpu_device *adev = drm_to_adev(ddev); 905 906 if (!adev) 907 return -ENODEV; 908 909 return amdgpu_show_reset_mask(buf, adev->vpe.supported_reset); 910 } 911 912 static DEVICE_ATTR(vpe_reset_mask, 0444, 913 amdgpu_get_vpe_reset_mask, NULL); 914 915 int amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device *adev) 916 { 917 int r = 0; 918 919 if (adev->vpe.num_instances) { 920 r = device_create_file(adev->dev, &dev_attr_vpe_reset_mask); 921 if (r) 922 return r; 923 } 924 925 return r; 926 } 927 928 void amdgpu_vpe_sysfs_reset_mask_fini(struct amdgpu_device *adev) 929 { 930 if (adev->dev->kobj.sd) { 931 if (adev->vpe.num_instances) 932 device_remove_file(adev->dev, &dev_attr_vpe_reset_mask); 933 } 934 } 935 936 static const struct amdgpu_ring_funcs vpe_ring_funcs = { 937 .type = AMDGPU_RING_TYPE_VPE, 938 .align_mask = 0xf, 939 .nop = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0), 940 .support_64bit_ptrs = true, 941 .get_rptr = vpe_ring_get_rptr, 942 .get_wptr = vpe_ring_get_wptr, 943 .set_wptr = vpe_ring_set_wptr, 944 .emit_frame_size = 945 5 + /* vpe_ring_init_cond_exec */ 946 6 + /* vpe_ring_emit_pipeline_sync */ 947 10 + 10 + 10 + /* vpe_ring_emit_fence */ 948 /* vpe_ring_emit_vm_flush */ 949 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 950 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6, 951 .emit_ib_size = 7 + 6, 952 .emit_ib = vpe_ring_emit_ib, 953 .emit_pipeline_sync = vpe_ring_emit_pipeline_sync, 954 .emit_fence = vpe_ring_emit_fence, 955 .emit_vm_flush = vpe_ring_emit_vm_flush, 956 .emit_wreg = vpe_ring_emit_wreg, 957 .emit_reg_wait = vpe_ring_emit_reg_wait, 958 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 959 .insert_nop = vpe_ring_insert_nop, 960 .pad_ib = amdgpu_ring_generic_pad_ib, 961 .test_ring = vpe_ring_test_ring, 962 .test_ib = vpe_ring_test_ib, 963 .init_cond_exec = vpe_ring_init_cond_exec, 964 .preempt_ib = vpe_ring_preempt_ib, 965 .begin_use = vpe_ring_begin_use, 966 .end_use = vpe_ring_end_use, 967 .reset = vpe_ring_reset, 968 }; 969 970 static void vpe_set_ring_funcs(struct amdgpu_device *adev) 971 { 972 adev->vpe.ring.funcs = &vpe_ring_funcs; 973 } 974 975 const struct amd_ip_funcs vpe_ip_funcs = { 976 .name = "vpe_v6_1", 977 .early_init = vpe_early_init, 978 .sw_init = vpe_sw_init, 979 .sw_fini = vpe_sw_fini, 980 .hw_init = vpe_hw_init, 981 .hw_fini = vpe_hw_fini, 982 .suspend = vpe_suspend, 983 .resume = vpe_resume, 984 .set_clockgating_state = vpe_set_clockgating_state, 985 .set_powergating_state = vpe_set_powergating_state, 986 }; 987 988 const struct amdgpu_ip_block_version vpe_v6_1_ip_block = { 989 .type = AMD_IP_BLOCK_TYPE_VPE, 990 .major = 6, 991 .minor = 1, 992 .rev = 0, 993 .funcs = &vpe_ip_funcs, 994 }; 995