1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #include "amdgv_sriovmsg.h" 28 29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */ 35 36 /* flags for indirect register access path supported by rlcg for sriov */ 37 #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) 38 #define AMDGPU_RLCG_GC_WRITE (0x0 << 28) 39 #define AMDGPU_RLCG_GC_READ (0x1 << 28) 40 #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28) 41 42 /* error code for indirect register access path supported by rlcg for sriov */ 43 #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000 44 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000 45 #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000 46 47 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF 48 #define AMDGPU_RLCG_SCRATCH1_ERROR_MASK 0xF000000 49 50 /* all asic after AI use this offset */ 51 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 52 /* tonga/fiji use this offset */ 53 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 54 55 #define AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT 2 56 57 /* Signature used to validate the SR-IOV dynamic critical region init data header ("INDA") */ 58 #define AMDGPU_SRIOV_CRIT_DATA_SIGNATURE "INDA" 59 #define AMDGPU_SRIOV_CRIT_DATA_SIG_LEN 4 60 61 #define IS_SRIOV_CRIT_REGN_ENTRY_VALID(hdr, id) ((hdr)->valid_tables & (1 << (id))) 62 63 enum amdgpu_sriov_vf_mode { 64 SRIOV_VF_MODE_BARE_METAL = 0, 65 SRIOV_VF_MODE_ONE_VF, 66 SRIOV_VF_MODE_MULTI_VF, 67 }; 68 69 struct amdgpu_mm_table { 70 struct amdgpu_bo *bo; 71 uint32_t *cpu_addr; 72 uint64_t gpu_addr; 73 }; 74 75 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 76 77 /* struct error_entry - amdgpu VF error information. */ 78 struct amdgpu_vf_error_buffer { 79 struct mutex lock; 80 int read_count; 81 int write_count; 82 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 83 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 84 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 85 }; 86 87 enum idh_request; 88 89 /** 90 * struct amdgpu_virt_ops - amdgpu device virt operations 91 */ 92 struct amdgpu_virt_ops { 93 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 94 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 95 int (*req_init_data)(struct amdgpu_device *adev); 96 int (*reset_gpu)(struct amdgpu_device *adev); 97 void (*ready_to_reset)(struct amdgpu_device *adev); 98 int (*wait_reset)(struct amdgpu_device *adev); 99 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req, 100 u32 data1, u32 data2, u32 data3); 101 void (*ras_poison_handler)(struct amdgpu_device *adev, 102 enum amdgpu_ras_block block); 103 bool (*rcvd_ras_intr)(struct amdgpu_device *adev); 104 int (*req_ras_err_count)(struct amdgpu_device *adev); 105 int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr); 106 int (*req_bad_pages)(struct amdgpu_device *adev); 107 int (*req_ras_chk_criti)(struct amdgpu_device *adev, u64 addr); 108 }; 109 110 /* 111 * Firmware Reserve Frame buffer 112 */ 113 struct amdgpu_virt_fw_reserve { 114 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 115 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 116 void *ras_telemetry; 117 unsigned int checksum_key; 118 }; 119 120 /* 121 * Legacy GIM header 122 * 123 * Defination between PF and VF 124 * Structures forcibly aligned to 4 to keep the same style as PF. 125 */ 126 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 127 128 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 129 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 130 131 enum AMDGIM_FEATURE_FLAG { 132 /* GIM supports feature of Error log collecting */ 133 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 134 /* GIM supports feature of loading uCodes */ 135 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 136 /* VRAM LOST by GIM */ 137 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 138 /* MM bandwidth */ 139 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 140 /* PP ONE VF MODE in GIM */ 141 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 142 /* Indirect Reg Access enabled */ 143 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 144 /* AV1 Support MODE*/ 145 AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6), 146 /* VCN RB decouple */ 147 AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7), 148 /* MES info */ 149 AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8), 150 AMDGIM_FEATURE_RAS_CAPS = (1 << 9), 151 AMDGIM_FEATURE_RAS_TELEMETRY = (1 << 10), 152 AMDGIM_FEATURE_RAS_CPER = (1 << 11), 153 }; 154 155 enum AMDGIM_REG_ACCESS_FLAG { 156 /* Use PSP to program IH_RB_CNTL */ 157 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 158 /* Use RLC to program MMHUB regs */ 159 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 160 /* Use RLC to program GC regs */ 161 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 162 /* Use PSP to program L1_TLB_CNTL */ 163 AMDGIM_FEATURE_L1_TLB_CNTL_PSP_EN = (1 << 3), 164 /* Use RLCG to program SQ_CONFIG1 */ 165 AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG = (1 << 4), 166 }; 167 168 struct amdgim_pf2vf_info_v1 { 169 /* header contains size and version */ 170 struct amd_sriov_msg_pf2vf_info_header header; 171 /* max_width * max_height */ 172 unsigned int uvd_enc_max_pixels_count; 173 /* 16x16 pixels/sec, codec independent */ 174 unsigned int uvd_enc_max_bandwidth; 175 /* max_width * max_height */ 176 unsigned int vce_enc_max_pixels_count; 177 /* 16x16 pixels/sec, codec independent */ 178 unsigned int vce_enc_max_bandwidth; 179 /* MEC FW position in kb from the start of visible frame buffer */ 180 unsigned int mecfw_kboffset; 181 /* The features flags of the GIM driver supports. */ 182 unsigned int feature_flags; 183 /* use private key from mailbox 2 to create chueksum */ 184 unsigned int checksum; 185 } __aligned(4); 186 187 struct amdgim_vf2pf_info_v1 { 188 /* header contains size and version */ 189 struct amd_sriov_msg_vf2pf_info_header header; 190 /* driver version */ 191 char driver_version[64]; 192 /* driver certification, 1=WHQL, 0=None */ 193 unsigned int driver_cert; 194 /* guest OS type and version: need a define */ 195 unsigned int os_info; 196 /* in the unit of 1M */ 197 unsigned int fb_usage; 198 /* guest gfx engine usage percentage */ 199 unsigned int gfx_usage; 200 /* guest gfx engine health percentage */ 201 unsigned int gfx_health; 202 /* guest compute engine usage percentage */ 203 unsigned int compute_usage; 204 /* guest compute engine health percentage */ 205 unsigned int compute_health; 206 /* guest vce engine usage percentage. 0xffff means N/A. */ 207 unsigned int vce_enc_usage; 208 /* guest vce engine health percentage. 0xffff means N/A. */ 209 unsigned int vce_enc_health; 210 /* guest uvd engine usage percentage. 0xffff means N/A. */ 211 unsigned int uvd_enc_usage; 212 /* guest uvd engine usage percentage. 0xffff means N/A. */ 213 unsigned int uvd_enc_health; 214 unsigned int checksum; 215 } __aligned(4); 216 217 struct amdgim_vf2pf_info_v2 { 218 /* header contains size and version */ 219 struct amd_sriov_msg_vf2pf_info_header header; 220 uint32_t checksum; 221 /* driver version */ 222 uint8_t driver_version[64]; 223 /* driver certification, 1=WHQL, 0=None */ 224 uint32_t driver_cert; 225 /* guest OS type and version: need a define */ 226 uint32_t os_info; 227 /* in the unit of 1M */ 228 uint32_t fb_usage; 229 /* guest gfx engine usage percentage */ 230 uint32_t gfx_usage; 231 /* guest gfx engine health percentage */ 232 uint32_t gfx_health; 233 /* guest compute engine usage percentage */ 234 uint32_t compute_usage; 235 /* guest compute engine health percentage */ 236 uint32_t compute_health; 237 /* guest vce engine usage percentage. 0xffff means N/A. */ 238 uint32_t vce_enc_usage; 239 /* guest vce engine health percentage. 0xffff means N/A. */ 240 uint32_t vce_enc_health; 241 /* guest uvd engine usage percentage. 0xffff means N/A. */ 242 uint32_t uvd_enc_usage; 243 /* guest uvd engine usage percentage. 0xffff means N/A. */ 244 uint32_t uvd_enc_health; 245 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 246 } __aligned(4); 247 248 struct amdgpu_virt_ras_err_handler_data { 249 /* point to bad page records array */ 250 struct eeprom_table_record *bps; 251 /* point to reserved bo array */ 252 struct amdgpu_bo **bps_bo; 253 /* the count of entries */ 254 int count; 255 /* last reserved entry's index + 1 */ 256 int last_reserved; 257 }; 258 259 struct amdgpu_virt_ras { 260 struct ratelimit_state ras_error_cnt_rs; 261 struct ratelimit_state ras_cper_dump_rs; 262 struct ratelimit_state ras_chk_criti_rs; 263 struct mutex ras_telemetry_mutex; 264 uint64_t cper_rptr; 265 }; 266 267 #define AMDGPU_VIRT_CAPS_LIST(X) X(AMDGPU_VIRT_CAP_POWER_LIMIT) 268 269 DECLARE_ATTR_CAP_CLASS(amdgpu_virt, AMDGPU_VIRT_CAPS_LIST); 270 271 struct amdgpu_virt_region { 272 uint32_t offset; 273 uint32_t size_kb; 274 }; 275 276 /* GPU virtualization */ 277 struct amdgpu_virt { 278 uint32_t caps; 279 struct amdgpu_bo *csa_obj; 280 void *csa_cpu_addr; 281 bool chained_ib_support; 282 uint32_t reg_val_offs; 283 struct amdgpu_irq_src ack_irq; 284 struct amdgpu_irq_src rcv_irq; 285 286 struct work_struct flr_work; 287 struct work_struct req_bad_pages_work; 288 struct work_struct handle_bad_pages_work; 289 290 struct amdgpu_mm_table mm_table; 291 const struct amdgpu_virt_ops *ops; 292 struct amdgpu_vf_error_buffer vf_errors; 293 struct amdgpu_virt_fw_reserve fw_reserve; 294 struct amdgpu_virt_caps virt_caps; 295 uint32_t gim_feature; 296 uint32_t reg_access_mode; 297 int req_init_data_ver; 298 bool tdr_debug; 299 struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 300 bool ras_init_done; 301 uint32_t reg_access; 302 303 /* dynamic(v2) critical regions */ 304 struct amdgpu_virt_region init_data_header; 305 struct amdgpu_virt_region crit_regn; 306 struct amdgpu_virt_region crit_regn_tbl[AMD_SRIOV_MSG_MAX_TABLE_ID]; 307 bool is_dynamic_crit_regn_enabled; 308 309 /* vf2pf message */ 310 struct delayed_work vf2pf_work; 311 uint32_t vf2pf_update_interval_ms; 312 int vf2pf_update_retry_cnt; 313 314 /* multimedia bandwidth config */ 315 bool is_mm_bw_enabled; 316 uint32_t decode_max_dimension_pixels; 317 uint32_t decode_max_frame_pixels; 318 uint32_t encode_max_dimension_pixels; 319 uint32_t encode_max_frame_pixels; 320 321 /* the ucode id to signal the autoload */ 322 uint32_t autoload_ucode_id; 323 324 /* Spinlock to protect access to the RLCG register interface */ 325 spinlock_t rlcg_reg_lock; 326 327 union amd_sriov_ras_caps ras_en_caps; 328 union amd_sriov_ras_caps ras_telemetry_en_caps; 329 struct amdgpu_virt_ras ras; 330 struct amd_sriov_ras_telemetry_error_count count_cache; 331 332 /* hibernate and resume with different VF feature for xgmi enabled system */ 333 bool is_xgmi_node_migrate_enabled; 334 }; 335 336 struct amdgpu_video_codec_info; 337 338 #define amdgpu_sriov_enabled(adev) \ 339 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 340 341 #define amdgpu_sriov_vf(adev) \ 342 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 343 344 #define amdgpu_sriov_bios(adev) \ 345 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 346 347 #define amdgpu_sriov_runtime(adev) \ 348 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 349 350 #define amdgpu_sriov_fullaccess(adev) \ 351 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 352 353 #define amdgpu_sriov_reg_indirect_en(adev) \ 354 (amdgpu_sriov_vf((adev)) && \ 355 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 356 357 #define amdgpu_sriov_reg_indirect_ih(adev) \ 358 (amdgpu_sriov_vf((adev)) && \ 359 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 360 361 #define amdgpu_sriov_reg_indirect_mmhub(adev) \ 362 (amdgpu_sriov_vf((adev)) && \ 363 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 364 365 #define amdgpu_sriov_reg_indirect_gc(adev) \ 366 (amdgpu_sriov_vf((adev)) && \ 367 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 368 369 #define amdgpu_sriov_reg_indirect_l1_tlb_cntl(adev) \ 370 (amdgpu_sriov_vf((adev)) && \ 371 ((adev)->virt.reg_access & (AMDGIM_FEATURE_L1_TLB_CNTL_PSP_EN))) 372 373 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \ 374 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 375 376 #define amdgpu_sriov_reg_access_sq_config(adev) \ 377 (amdgpu_sriov_vf((adev)) && \ 378 ((adev)->virt.reg_access & (AMDGIM_FEATURE_REG_ACCESS_SQ_CONFIG))) 379 380 #define amdgpu_passthrough(adev) \ 381 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 382 383 #define amdgpu_sriov_vf_mmio_access_protection(adev) \ 384 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) 385 386 #define amdgpu_sriov_ras_caps_en(adev) \ 387 ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CAPS) 388 389 #define amdgpu_sriov_ras_telemetry_en(adev) \ 390 (((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_TELEMETRY) && (adev)->virt.fw_reserve.ras_telemetry) 391 392 #define amdgpu_sriov_ras_telemetry_block_en(adev, sriov_blk) \ 393 (amdgpu_sriov_ras_telemetry_en((adev)) && (adev)->virt.ras_telemetry_en_caps.all & BIT(sriov_blk)) 394 395 #define amdgpu_sriov_ras_cper_en(adev) \ 396 ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CPER) 397 398 static inline bool is_virtual_machine(void) 399 { 400 #if defined(CONFIG_X86) 401 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 402 #elif defined(CONFIG_ARM64) 403 return !is_kernel_in_hyp_mode(); 404 #else 405 return false; 406 #endif 407 } 408 409 #define amdgpu_sriov_is_pp_one_vf(adev) \ 410 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 411 #define amdgpu_sriov_multi_vf_mode(adev) \ 412 (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 413 #define amdgpu_sriov_is_debug(adev) \ 414 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 415 #define amdgpu_sriov_is_normal(adev) \ 416 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 417 #define amdgpu_sriov_is_av1_support(adev) \ 418 ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT) 419 #define amdgpu_sriov_is_vcn_rb_decouple(adev) \ 420 ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE) 421 #define amdgpu_sriov_is_mes_info_enable(adev) \ 422 ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE) 423 424 #define amdgpu_virt_xgmi_migrate_enabled(adev) \ 425 ((adev)->virt.is_xgmi_node_migrate_enabled && (adev)->gmc.xgmi.node_segment_size != 0) 426 427 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 428 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 429 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 430 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 431 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 432 void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 433 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev); 434 int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 435 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 436 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 437 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev); 438 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 439 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 440 void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 441 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 442 void amdgpu_virt_init(struct amdgpu_device *adev); 443 444 int amdgpu_virt_init_critical_region(struct amdgpu_device *adev); 445 int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev, 446 int data_id, uint8_t *binary, u32 *size); 447 448 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 449 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 450 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 451 452 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 453 454 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 455 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 456 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 457 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 458 u32 offset, u32 value, 459 u32 acc_flags, u32 hwip, u32 xcc_id); 460 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 461 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id); 462 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, 463 uint32_t ucode_id); 464 void amdgpu_virt_pre_reset(struct amdgpu_device *adev); 465 void amdgpu_virt_post_reset(struct amdgpu_device *adev); 466 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev); 467 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 468 u32 acc_flags, u32 hwip, 469 bool write, u32 *rlcg_flag); 470 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id); 471 bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev); 472 int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block, 473 struct ras_err_data *err_data); 474 int amdgpu_virt_req_ras_cper_dump(struct amdgpu_device *adev, bool force_update); 475 int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev); 476 bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev, 477 enum amdgpu_ras_block block); 478 void amdgpu_virt_request_bad_pages(struct amdgpu_device *adev); 479 int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit); 480 #endif 481