1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 * Authors: Christian König <christian.koenig@amd.com> 26 */ 27 28 #include <linux/firmware.h> 29 #include <linux/module.h> 30 #include <drm/drmP.h> 31 #include <drm/drm.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_pm.h" 35 #include "amdgpu_vce.h" 36 #include "cikd.h" 37 38 /* 1 second timeout */ 39 #define VCE_IDLE_TIMEOUT_MS 1000 40 41 /* Firmware Names */ 42 #ifdef CONFIG_DRM_AMDGPU_CIK 43 #define FIRMWARE_BONAIRE "radeon/bonaire_vce.bin" 44 #define FIRMWARE_KABINI "radeon/kabini_vce.bin" 45 #define FIRMWARE_KAVERI "radeon/kaveri_vce.bin" 46 #define FIRMWARE_HAWAII "radeon/hawaii_vce.bin" 47 #define FIRMWARE_MULLINS "radeon/mullins_vce.bin" 48 #endif 49 #define FIRMWARE_TONGA "amdgpu/tonga_vce.bin" 50 #define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin" 51 52 #ifdef CONFIG_DRM_AMDGPU_CIK 53 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 54 MODULE_FIRMWARE(FIRMWARE_KABINI); 55 MODULE_FIRMWARE(FIRMWARE_KAVERI); 56 MODULE_FIRMWARE(FIRMWARE_HAWAII); 57 MODULE_FIRMWARE(FIRMWARE_MULLINS); 58 #endif 59 MODULE_FIRMWARE(FIRMWARE_TONGA); 60 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 61 62 static void amdgpu_vce_idle_work_handler(struct work_struct *work); 63 64 /** 65 * amdgpu_vce_init - allocate memory, load vce firmware 66 * 67 * @adev: amdgpu_device pointer 68 * 69 * First step to get VCE online, allocate memory and load the firmware 70 */ 71 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) 72 { 73 const char *fw_name; 74 const struct common_firmware_header *hdr; 75 unsigned ucode_version, version_major, version_minor, binary_id; 76 int i, r; 77 78 INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler); 79 80 switch (adev->asic_type) { 81 #ifdef CONFIG_DRM_AMDGPU_CIK 82 case CHIP_BONAIRE: 83 fw_name = FIRMWARE_BONAIRE; 84 break; 85 case CHIP_KAVERI: 86 fw_name = FIRMWARE_KAVERI; 87 break; 88 case CHIP_KABINI: 89 fw_name = FIRMWARE_KABINI; 90 break; 91 case CHIP_HAWAII: 92 fw_name = FIRMWARE_HAWAII; 93 break; 94 case CHIP_MULLINS: 95 fw_name = FIRMWARE_MULLINS; 96 break; 97 #endif 98 case CHIP_TONGA: 99 fw_name = FIRMWARE_TONGA; 100 break; 101 case CHIP_CARRIZO: 102 fw_name = FIRMWARE_CARRIZO; 103 break; 104 105 default: 106 return -EINVAL; 107 } 108 109 r = request_firmware(&adev->vce.fw, fw_name, adev->dev); 110 if (r) { 111 dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n", 112 fw_name); 113 return r; 114 } 115 116 r = amdgpu_ucode_validate(adev->vce.fw); 117 if (r) { 118 dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n", 119 fw_name); 120 release_firmware(adev->vce.fw); 121 adev->vce.fw = NULL; 122 return r; 123 } 124 125 hdr = (const struct common_firmware_header *)adev->vce.fw->data; 126 127 ucode_version = le32_to_cpu(hdr->ucode_version); 128 version_major = (ucode_version >> 20) & 0xfff; 129 version_minor = (ucode_version >> 8) & 0xfff; 130 binary_id = ucode_version & 0xff; 131 DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n", 132 version_major, version_minor, binary_id); 133 adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) | 134 (binary_id << 8)); 135 136 /* allocate firmware, stack and heap BO */ 137 138 r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, 139 AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->vce.vcpu_bo); 140 if (r) { 141 dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r); 142 return r; 143 } 144 145 r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false); 146 if (r) { 147 amdgpu_bo_unref(&adev->vce.vcpu_bo); 148 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r); 149 return r; 150 } 151 152 r = amdgpu_bo_pin(adev->vce.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM, 153 &adev->vce.gpu_addr); 154 amdgpu_bo_unreserve(adev->vce.vcpu_bo); 155 if (r) { 156 amdgpu_bo_unref(&adev->vce.vcpu_bo); 157 dev_err(adev->dev, "(%d) VCE bo pin failed\n", r); 158 return r; 159 } 160 161 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) { 162 atomic_set(&adev->vce.handles[i], 0); 163 adev->vce.filp[i] = NULL; 164 } 165 166 return 0; 167 } 168 169 /** 170 * amdgpu_vce_fini - free memory 171 * 172 * @adev: amdgpu_device pointer 173 * 174 * Last step on VCE teardown, free firmware memory 175 */ 176 int amdgpu_vce_sw_fini(struct amdgpu_device *adev) 177 { 178 if (adev->vce.vcpu_bo == NULL) 179 return 0; 180 181 amdgpu_bo_unref(&adev->vce.vcpu_bo); 182 183 amdgpu_ring_fini(&adev->vce.ring[0]); 184 amdgpu_ring_fini(&adev->vce.ring[1]); 185 186 release_firmware(adev->vce.fw); 187 188 return 0; 189 } 190 191 /** 192 * amdgpu_vce_suspend - unpin VCE fw memory 193 * 194 * @adev: amdgpu_device pointer 195 * 196 */ 197 int amdgpu_vce_suspend(struct amdgpu_device *adev) 198 { 199 int i; 200 201 if (adev->vce.vcpu_bo == NULL) 202 return 0; 203 204 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) 205 if (atomic_read(&adev->vce.handles[i])) 206 break; 207 208 if (i == AMDGPU_MAX_VCE_HANDLES) 209 return 0; 210 211 /* TODO: suspending running encoding sessions isn't supported */ 212 return -EINVAL; 213 } 214 215 /** 216 * amdgpu_vce_resume - pin VCE fw memory 217 * 218 * @adev: amdgpu_device pointer 219 * 220 */ 221 int amdgpu_vce_resume(struct amdgpu_device *adev) 222 { 223 void *cpu_addr; 224 const struct common_firmware_header *hdr; 225 unsigned offset; 226 int r; 227 228 if (adev->vce.vcpu_bo == NULL) 229 return -EINVAL; 230 231 r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false); 232 if (r) { 233 dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r); 234 return r; 235 } 236 237 r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr); 238 if (r) { 239 amdgpu_bo_unreserve(adev->vce.vcpu_bo); 240 dev_err(adev->dev, "(%d) VCE map failed\n", r); 241 return r; 242 } 243 244 hdr = (const struct common_firmware_header *)adev->vce.fw->data; 245 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 246 memcpy(cpu_addr, (adev->vce.fw->data) + offset, 247 (adev->vce.fw->size) - offset); 248 249 amdgpu_bo_kunmap(adev->vce.vcpu_bo); 250 251 amdgpu_bo_unreserve(adev->vce.vcpu_bo); 252 253 return 0; 254 } 255 256 /** 257 * amdgpu_vce_idle_work_handler - power off VCE 258 * 259 * @work: pointer to work structure 260 * 261 * power of VCE when it's not used any more 262 */ 263 static void amdgpu_vce_idle_work_handler(struct work_struct *work) 264 { 265 struct amdgpu_device *adev = 266 container_of(work, struct amdgpu_device, vce.idle_work.work); 267 268 if ((amdgpu_fence_count_emitted(&adev->vce.ring[0]) == 0) && 269 (amdgpu_fence_count_emitted(&adev->vce.ring[1]) == 0)) { 270 if (adev->pm.dpm_enabled) { 271 amdgpu_dpm_enable_vce(adev, false); 272 } else { 273 amdgpu_asic_set_vce_clocks(adev, 0, 0); 274 } 275 } else { 276 schedule_delayed_work(&adev->vce.idle_work, 277 msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS)); 278 } 279 } 280 281 /** 282 * amdgpu_vce_note_usage - power up VCE 283 * 284 * @adev: amdgpu_device pointer 285 * 286 * Make sure VCE is powerd up when we want to use it 287 */ 288 static void amdgpu_vce_note_usage(struct amdgpu_device *adev) 289 { 290 bool streams_changed = false; 291 bool set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work); 292 set_clocks &= schedule_delayed_work(&adev->vce.idle_work, 293 msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS)); 294 295 if (adev->pm.dpm_enabled) { 296 /* XXX figure out if the streams changed */ 297 streams_changed = false; 298 } 299 300 if (set_clocks || streams_changed) { 301 if (adev->pm.dpm_enabled) { 302 amdgpu_dpm_enable_vce(adev, true); 303 } else { 304 amdgpu_asic_set_vce_clocks(adev, 53300, 40000); 305 } 306 } 307 } 308 309 /** 310 * amdgpu_vce_free_handles - free still open VCE handles 311 * 312 * @adev: amdgpu_device pointer 313 * @filp: drm file pointer 314 * 315 * Close all VCE handles still open by this file pointer 316 */ 317 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 318 { 319 struct amdgpu_ring *ring = &adev->vce.ring[0]; 320 int i, r; 321 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) { 322 uint32_t handle = atomic_read(&adev->vce.handles[i]); 323 if (!handle || adev->vce.filp[i] != filp) 324 continue; 325 326 amdgpu_vce_note_usage(adev); 327 328 r = amdgpu_vce_get_destroy_msg(ring, handle, NULL); 329 if (r) 330 DRM_ERROR("Error destroying VCE handle (%d)!\n", r); 331 332 adev->vce.filp[i] = NULL; 333 atomic_set(&adev->vce.handles[i], 0); 334 } 335 } 336 337 /** 338 * amdgpu_vce_get_create_msg - generate a VCE create msg 339 * 340 * @adev: amdgpu_device pointer 341 * @ring: ring we should submit the msg to 342 * @handle: VCE session handle to use 343 * @fence: optional fence to return 344 * 345 * Open up a stream for HW test 346 */ 347 int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 348 struct amdgpu_fence **fence) 349 { 350 const unsigned ib_size_dw = 1024; 351 struct amdgpu_ib ib; 352 uint64_t dummy; 353 int i, r; 354 355 r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, &ib); 356 if (r) { 357 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 358 return r; 359 } 360 361 dummy = ib.gpu_addr + 1024; 362 363 /* stitch together an VCE create msg */ 364 ib.length_dw = 0; 365 ib.ptr[ib.length_dw++] = 0x0000000c; /* len */ 366 ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */ 367 ib.ptr[ib.length_dw++] = handle; 368 369 ib.ptr[ib.length_dw++] = 0x00000030; /* len */ 370 ib.ptr[ib.length_dw++] = 0x01000001; /* create cmd */ 371 ib.ptr[ib.length_dw++] = 0x00000000; 372 ib.ptr[ib.length_dw++] = 0x00000042; 373 ib.ptr[ib.length_dw++] = 0x0000000a; 374 ib.ptr[ib.length_dw++] = 0x00000001; 375 ib.ptr[ib.length_dw++] = 0x00000080; 376 ib.ptr[ib.length_dw++] = 0x00000060; 377 ib.ptr[ib.length_dw++] = 0x00000100; 378 ib.ptr[ib.length_dw++] = 0x00000100; 379 ib.ptr[ib.length_dw++] = 0x0000000c; 380 ib.ptr[ib.length_dw++] = 0x00000000; 381 382 ib.ptr[ib.length_dw++] = 0x00000014; /* len */ 383 ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */ 384 ib.ptr[ib.length_dw++] = upper_32_bits(dummy); 385 ib.ptr[ib.length_dw++] = dummy; 386 ib.ptr[ib.length_dw++] = 0x00000001; 387 388 for (i = ib.length_dw; i < ib_size_dw; ++i) 389 ib.ptr[i] = 0x0; 390 391 r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); 392 if (r) { 393 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); 394 } 395 396 if (fence) 397 *fence = amdgpu_fence_ref(ib.fence); 398 399 amdgpu_ib_free(ring->adev, &ib); 400 401 return r; 402 } 403 404 /** 405 * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg 406 * 407 * @adev: amdgpu_device pointer 408 * @ring: ring we should submit the msg to 409 * @handle: VCE session handle to use 410 * @fence: optional fence to return 411 * 412 * Close up a stream for HW test or if userspace failed to do so 413 */ 414 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 415 struct amdgpu_fence **fence) 416 { 417 const unsigned ib_size_dw = 1024; 418 struct amdgpu_ib ib; 419 uint64_t dummy; 420 int i, r; 421 422 r = amdgpu_ib_get(ring, NULL, ib_size_dw * 4, &ib); 423 if (r) { 424 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 425 return r; 426 } 427 428 dummy = ib.gpu_addr + 1024; 429 430 /* stitch together an VCE destroy msg */ 431 ib.length_dw = 0; 432 ib.ptr[ib.length_dw++] = 0x0000000c; /* len */ 433 ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */ 434 ib.ptr[ib.length_dw++] = handle; 435 436 ib.ptr[ib.length_dw++] = 0x00000014; /* len */ 437 ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */ 438 ib.ptr[ib.length_dw++] = upper_32_bits(dummy); 439 ib.ptr[ib.length_dw++] = dummy; 440 ib.ptr[ib.length_dw++] = 0x00000001; 441 442 ib.ptr[ib.length_dw++] = 0x00000008; /* len */ 443 ib.ptr[ib.length_dw++] = 0x02000001; /* destroy cmd */ 444 445 for (i = ib.length_dw; i < ib_size_dw; ++i) 446 ib.ptr[i] = 0x0; 447 448 r = amdgpu_ib_schedule(ring->adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); 449 if (r) { 450 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); 451 } 452 453 if (fence) 454 *fence = amdgpu_fence_ref(ib.fence); 455 456 amdgpu_ib_free(ring->adev, &ib); 457 458 return r; 459 } 460 461 /** 462 * amdgpu_vce_cs_reloc - command submission relocation 463 * 464 * @p: parser context 465 * @lo: address of lower dword 466 * @hi: address of higher dword 467 * 468 * Patch relocation inside command stream with real buffer address 469 */ 470 int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx, int lo, int hi) 471 { 472 struct amdgpu_bo_va_mapping *mapping; 473 struct amdgpu_ib *ib = &p->ibs[ib_idx]; 474 struct amdgpu_bo *bo; 475 uint64_t addr; 476 477 addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) | 478 ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32; 479 480 mapping = amdgpu_cs_find_mapping(p, addr, &bo); 481 if (mapping == NULL) { 482 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d\n", 483 addr, lo, hi); 484 return -EINVAL; 485 } 486 487 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE; 488 addr += amdgpu_bo_gpu_offset(bo); 489 490 ib->ptr[lo] = addr & 0xFFFFFFFF; 491 ib->ptr[hi] = addr >> 32; 492 493 return 0; 494 } 495 496 /** 497 * amdgpu_vce_cs_parse - parse and validate the command stream 498 * 499 * @p: parser context 500 * 501 */ 502 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx) 503 { 504 uint32_t handle = 0; 505 bool destroy = false; 506 int i, r, idx = 0; 507 struct amdgpu_ib *ib = &p->ibs[ib_idx]; 508 509 amdgpu_vce_note_usage(p->adev); 510 511 while (idx < ib->length_dw) { 512 uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx); 513 uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1); 514 515 if ((len < 8) || (len & 3)) { 516 DRM_ERROR("invalid VCE command length (%d)!\n", len); 517 return -EINVAL; 518 } 519 520 switch (cmd) { 521 case 0x00000001: // session 522 handle = amdgpu_get_ib_value(p, ib_idx, idx + 2); 523 break; 524 525 case 0x00000002: // task info 526 case 0x01000001: // create 527 case 0x04000001: // config extension 528 case 0x04000002: // pic control 529 case 0x04000005: // rate control 530 case 0x04000007: // motion estimation 531 case 0x04000008: // rdo 532 case 0x04000009: // vui 533 case 0x05000002: // auxiliary buffer 534 break; 535 536 case 0x03000001: // encode 537 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 10, idx + 9); 538 if (r) 539 return r; 540 541 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 12, idx + 11); 542 if (r) 543 return r; 544 break; 545 546 case 0x02000001: // destroy 547 destroy = true; 548 break; 549 550 case 0x05000001: // context buffer 551 case 0x05000004: // video bitstream buffer 552 case 0x05000005: // feedback buffer 553 r = amdgpu_vce_cs_reloc(p, ib_idx, idx + 3, idx + 2); 554 if (r) 555 return r; 556 break; 557 558 default: 559 DRM_ERROR("invalid VCE command (0x%x)!\n", cmd); 560 return -EINVAL; 561 } 562 563 idx += len / 4; 564 } 565 566 if (destroy) { 567 /* IB contains a destroy msg, free the handle */ 568 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) 569 atomic_cmpxchg(&p->adev->vce.handles[i], handle, 0); 570 571 return 0; 572 } 573 574 /* create or encode, validate the handle */ 575 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) { 576 if (atomic_read(&p->adev->vce.handles[i]) == handle) 577 return 0; 578 } 579 580 /* handle not found try to alloc a new one */ 581 for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) { 582 if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) { 583 p->adev->vce.filp[i] = p->filp; 584 return 0; 585 } 586 } 587 588 DRM_ERROR("No more free VCE handles!\n"); 589 590 return -EINVAL; 591 } 592 593 /** 594 * amdgpu_vce_ring_emit_semaphore - emit a semaphore command 595 * 596 * @ring: engine to use 597 * @semaphore: address of semaphore 598 * @emit_wait: true=emit wait, false=emit signal 599 * 600 */ 601 bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring, 602 struct amdgpu_semaphore *semaphore, 603 bool emit_wait) 604 { 605 uint64_t addr = semaphore->gpu_addr; 606 607 amdgpu_ring_write(ring, VCE_CMD_SEMAPHORE); 608 amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF); 609 amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF); 610 amdgpu_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0)); 611 if (!emit_wait) 612 amdgpu_ring_write(ring, VCE_CMD_END); 613 614 return true; 615 } 616 617 /** 618 * amdgpu_vce_ring_emit_ib - execute indirect buffer 619 * 620 * @ring: engine to use 621 * @ib: the IB to execute 622 * 623 */ 624 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 625 { 626 amdgpu_ring_write(ring, VCE_CMD_IB); 627 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 628 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 629 amdgpu_ring_write(ring, ib->length_dw); 630 } 631 632 /** 633 * amdgpu_vce_ring_emit_fence - add a fence command to the ring 634 * 635 * @ring: engine to use 636 * @fence: the fence 637 * 638 */ 639 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 640 unsigned flags) 641 { 642 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 643 644 amdgpu_ring_write(ring, VCE_CMD_FENCE); 645 amdgpu_ring_write(ring, addr); 646 amdgpu_ring_write(ring, upper_32_bits(addr)); 647 amdgpu_ring_write(ring, seq); 648 amdgpu_ring_write(ring, VCE_CMD_TRAP); 649 amdgpu_ring_write(ring, VCE_CMD_END); 650 } 651 652 /** 653 * amdgpu_vce_ring_test_ring - test if VCE ring is working 654 * 655 * @ring: the engine to test on 656 * 657 */ 658 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring) 659 { 660 struct amdgpu_device *adev = ring->adev; 661 uint32_t rptr = amdgpu_ring_get_rptr(ring); 662 unsigned i; 663 int r; 664 665 r = amdgpu_ring_lock(ring, 16); 666 if (r) { 667 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n", 668 ring->idx, r); 669 return r; 670 } 671 amdgpu_ring_write(ring, VCE_CMD_END); 672 amdgpu_ring_unlock_commit(ring); 673 674 for (i = 0; i < adev->usec_timeout; i++) { 675 if (amdgpu_ring_get_rptr(ring) != rptr) 676 break; 677 DRM_UDELAY(1); 678 } 679 680 if (i < adev->usec_timeout) { 681 DRM_INFO("ring test on %d succeeded in %d usecs\n", 682 ring->idx, i); 683 } else { 684 DRM_ERROR("amdgpu: ring %d test failed\n", 685 ring->idx); 686 r = -ETIMEDOUT; 687 } 688 689 return r; 690 } 691 692 /** 693 * amdgpu_vce_ring_test_ib - test if VCE IBs are working 694 * 695 * @ring: the engine to test on 696 * 697 */ 698 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring) 699 { 700 struct amdgpu_fence *fence = NULL; 701 int r; 702 703 r = amdgpu_vce_get_create_msg(ring, 1, NULL); 704 if (r) { 705 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); 706 goto error; 707 } 708 709 r = amdgpu_vce_get_destroy_msg(ring, 1, &fence); 710 if (r) { 711 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); 712 goto error; 713 } 714 715 r = amdgpu_fence_wait(fence, false); 716 if (r) { 717 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 718 } else { 719 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 720 } 721 error: 722 amdgpu_fence_unref(&fence); 723 return r; 724 } 725