1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 * Christian König 28 */ 29 #include <linux/seq_file.h> 30 #include <linux/slab.h> 31 #include <linux/uaccess.h> 32 #include <linux/debugfs.h> 33 34 #include <drm/amdgpu_drm.h> 35 #include "amdgpu.h" 36 #include "amdgpu_ras_mgr.h" 37 #include "atom.h" 38 39 /* 40 * Rings 41 * Most engines on the GPU are fed via ring buffers. Ring 42 * buffers are areas of GPU accessible memory that the host 43 * writes commands into and the GPU reads commands out of. 44 * There is a rptr (read pointer) that determines where the 45 * GPU is currently reading, and a wptr (write pointer) 46 * which determines where the host has written. When the 47 * pointers are equal, the ring is idle. When the host 48 * writes commands to the ring buffer, it increments the 49 * wptr. The GPU then starts fetching commands and executes 50 * them until the pointers are equal again. 51 */ 52 53 /** 54 * amdgpu_ring_max_ibs - Return max IBs that fit in a single submission. 55 * 56 * @type: ring type for which to return the limit. 57 */ 58 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type) 59 { 60 switch (type) { 61 case AMDGPU_RING_TYPE_GFX: 62 /* Need to keep at least 192 on GFX7+ for old radv. */ 63 return 192; 64 case AMDGPU_RING_TYPE_COMPUTE: 65 return 125; 66 case AMDGPU_RING_TYPE_VCN_JPEG: 67 return 16; 68 default: 69 return 49; 70 } 71 } 72 73 /** 74 * amdgpu_ring_alloc - allocate space on the ring buffer 75 * 76 * @ring: amdgpu_ring structure holding ring information 77 * @ndw: number of dwords to allocate in the ring buffer 78 * 79 * Allocate @ndw dwords in the ring buffer (all asics). 80 * Returns 0 on success, error on failure. 81 */ 82 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) 83 { 84 /* Align requested size with padding so unlock_commit can 85 * pad safely */ 86 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; 87 88 /* Make sure we aren't trying to allocate more space 89 * than the maximum for one submission 90 */ 91 if (WARN_ON_ONCE(ndw > ring->max_dw)) 92 return -ENOMEM; 93 94 ring->count_dw = ndw; 95 ring->wptr_old = ring->wptr; 96 97 if (ring->funcs->begin_use) 98 ring->funcs->begin_use(ring); 99 100 return 0; 101 } 102 103 /** 104 * amdgpu_ring_alloc_reemit - allocate space on the ring buffer for reemit 105 * 106 * @ring: amdgpu_ring structure holding ring information 107 * @ndw: number of dwords to allocate in the ring buffer 108 * 109 * Allocate @ndw dwords in the ring buffer (all asics). 110 * doesn't check the max_dw limit as we may be reemitting 111 * several submissions. 112 */ 113 static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw) 114 { 115 /* Align requested size with padding so unlock_commit can 116 * pad safely */ 117 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; 118 119 ring->count_dw = ndw; 120 ring->wptr_old = ring->wptr; 121 122 if (ring->funcs->begin_use) 123 ring->funcs->begin_use(ring); 124 } 125 126 /** amdgpu_ring_insert_nop - insert NOP packets 127 * 128 * @ring: amdgpu_ring structure holding ring information 129 * @count: the number of NOP packets to insert 130 * 131 * This is the generic insert_nop function for rings except SDMA 132 */ 133 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 134 { 135 uint32_t occupied, chunk1, chunk2; 136 137 occupied = ring->wptr & ring->buf_mask; 138 chunk1 = ring->buf_mask + 1 - occupied; 139 chunk1 = (chunk1 >= count) ? count : chunk1; 140 chunk2 = count - chunk1; 141 142 if (chunk1) 143 memset32(&ring->ring[occupied], ring->funcs->nop, chunk1); 144 145 if (chunk2) 146 memset32(ring->ring, ring->funcs->nop, chunk2); 147 148 ring->wptr += count; 149 ring->wptr &= ring->ptr_mask; 150 ring->count_dw -= count; 151 } 152 153 /** 154 * amdgpu_ring_generic_pad_ib - pad IB with NOP packets 155 * 156 * @ring: amdgpu_ring structure holding ring information 157 * @ib: IB to add NOP packets to 158 * 159 * This is the generic pad_ib function for rings except SDMA 160 */ 161 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 162 { 163 u32 align_mask = ring->funcs->align_mask; 164 u32 count = ib->length_dw & align_mask; 165 166 if (count) { 167 count = align_mask + 1 - count; 168 169 memset32(&ib->ptr[ib->length_dw], ring->funcs->nop, count); 170 171 ib->length_dw += count; 172 } 173 } 174 175 /** 176 * amdgpu_ring_commit - tell the GPU to execute the new 177 * commands on the ring buffer 178 * 179 * @ring: amdgpu_ring structure holding ring information 180 * 181 * Update the wptr (write pointer) to tell the GPU to 182 * execute new commands on the ring buffer (all asics). 183 */ 184 void amdgpu_ring_commit(struct amdgpu_ring *ring) 185 { 186 uint32_t count; 187 188 if (ring->count_dw < 0) 189 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 190 191 /* We pad to match fetch size */ 192 count = ring->funcs->align_mask + 1 - 193 (ring->wptr & ring->funcs->align_mask); 194 count &= ring->funcs->align_mask; 195 196 if (count != 0) 197 ring->funcs->insert_nop(ring, count); 198 199 mb(); 200 amdgpu_ring_set_wptr(ring); 201 202 if (ring->funcs->end_use) 203 ring->funcs->end_use(ring); 204 } 205 206 /** 207 * amdgpu_ring_undo - reset the wptr 208 * 209 * @ring: amdgpu_ring structure holding ring information 210 * 211 * Reset the driver's copy of the wptr (all asics). 212 */ 213 void amdgpu_ring_undo(struct amdgpu_ring *ring) 214 { 215 ring->wptr = ring->wptr_old; 216 217 if (ring->funcs->end_use) 218 ring->funcs->end_use(ring); 219 } 220 221 #define amdgpu_ring_get_gpu_addr(ring, offset) \ 222 (ring->adev->wb.gpu_addr + offset * 4) 223 224 #define amdgpu_ring_get_cpu_addr(ring, offset) \ 225 (&ring->adev->wb.wb[offset]) 226 227 /** 228 * amdgpu_ring_init - init driver ring struct. 229 * 230 * @adev: amdgpu_device pointer 231 * @ring: amdgpu_ring structure holding ring information 232 * @max_dw: maximum number of dw for ring alloc 233 * @irq_src: interrupt source to use for this ring 234 * @irq_type: interrupt type to use for this ring 235 * @hw_prio: ring priority (NORMAL/HIGH) 236 * @sched_score: optional score atomic shared with other schedulers 237 * 238 * Initialize the driver information for the selected ring (all asics). 239 * Returns 0 on success, error on failure. 240 */ 241 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 242 unsigned int max_dw, struct amdgpu_irq_src *irq_src, 243 unsigned int irq_type, unsigned int hw_prio, 244 atomic_t *sched_score) 245 { 246 int r; 247 int sched_hw_submission = amdgpu_sched_hw_submission; 248 u32 *num_sched; 249 u32 hw_ip; 250 unsigned int max_ibs_dw; 251 252 /* Set the hw submission limit higher for KIQ because 253 * it's used for a number of gfx/compute tasks by both 254 * KFD and KGD which may have outstanding fences and 255 * it doesn't really use the gpu scheduler anyway; 256 * KIQ tasks get submitted directly to the ring. 257 */ 258 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 259 sched_hw_submission = max(sched_hw_submission, 256); 260 if (ring->funcs->type == AMDGPU_RING_TYPE_MES) 261 sched_hw_submission = 8; 262 else if (ring == &adev->sdma.instance[0].page) 263 sched_hw_submission = 256; 264 265 if (ring->adev == NULL) { 266 if (adev->num_rings >= AMDGPU_MAX_RINGS) 267 return -EINVAL; 268 269 ring->adev = adev; 270 ring->num_hw_submission = sched_hw_submission; 271 ring->sched_score = sched_score; 272 ring->vmid_wait = dma_fence_get_stub(); 273 274 ring->idx = adev->num_rings++; 275 adev->rings[ring->idx] = ring; 276 277 r = amdgpu_fence_driver_init_ring(ring); 278 if (r) 279 return r; 280 } 281 282 r = amdgpu_device_wb_get(adev, &ring->rptr_offs); 283 if (r) { 284 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); 285 return r; 286 } 287 288 r = amdgpu_device_wb_get(adev, &ring->wptr_offs); 289 if (r) { 290 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); 291 return r; 292 } 293 294 r = amdgpu_device_wb_get(adev, &ring->fence_offs); 295 if (r) { 296 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); 297 return r; 298 } 299 300 r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs); 301 if (r) { 302 dev_err(adev->dev, "(%d) ring trail_fence_offs wb alloc failed\n", r); 303 return r; 304 } 305 306 r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs); 307 if (r) { 308 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r); 309 return r; 310 } 311 312 ring->fence_gpu_addr = 313 amdgpu_ring_get_gpu_addr(ring, ring->fence_offs); 314 ring->fence_cpu_addr = 315 amdgpu_ring_get_cpu_addr(ring, ring->fence_offs); 316 317 ring->rptr_gpu_addr = 318 amdgpu_ring_get_gpu_addr(ring, ring->rptr_offs); 319 ring->rptr_cpu_addr = 320 amdgpu_ring_get_cpu_addr(ring, ring->rptr_offs); 321 322 ring->wptr_gpu_addr = 323 amdgpu_ring_get_gpu_addr(ring, ring->wptr_offs); 324 ring->wptr_cpu_addr = 325 amdgpu_ring_get_cpu_addr(ring, ring->wptr_offs); 326 327 ring->trail_fence_gpu_addr = 328 amdgpu_ring_get_gpu_addr(ring, ring->trail_fence_offs); 329 ring->trail_fence_cpu_addr = 330 amdgpu_ring_get_cpu_addr(ring, ring->trail_fence_offs); 331 332 ring->cond_exe_gpu_addr = 333 amdgpu_ring_get_gpu_addr(ring, ring->cond_exe_offs); 334 ring->cond_exe_cpu_addr = 335 amdgpu_ring_get_cpu_addr(ring, ring->cond_exe_offs); 336 337 /* always set cond_exec_polling to CONTINUE */ 338 *ring->cond_exe_cpu_addr = 1; 339 340 if (ring->funcs->type != AMDGPU_RING_TYPE_CPER) { 341 r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type); 342 if (r) { 343 dev_err(adev->dev, "failed initializing fences (%d).\n", r); 344 return r; 345 } 346 347 max_ibs_dw = ring->funcs->emit_frame_size + 348 amdgpu_ring_max_ibs(ring->funcs->type) * ring->funcs->emit_ib_size; 349 max_ibs_dw = (max_ibs_dw + ring->funcs->align_mask) & ~ring->funcs->align_mask; 350 351 if (WARN_ON(max_ibs_dw > max_dw)) 352 max_dw = max_ibs_dw; 353 354 ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission); 355 } else { 356 ring->ring_size = roundup_pow_of_two(max_dw * 4); 357 ring->count_dw = (ring->ring_size - 4) >> 2; 358 /* ring buffer is empty now */ 359 ring->wptr = *ring->rptr_cpu_addr = 0; 360 } 361 362 ring->buf_mask = (ring->ring_size / 4) - 1; 363 ring->ptr_mask = ring->funcs->support_64bit_ptrs ? 364 0xffffffffffffffff : ring->buf_mask; 365 /* Initialize cached_rptr to 0 */ 366 ring->cached_rptr = 0; 367 368 if (!ring->ring_backup) { 369 ring->ring_backup = kvzalloc(ring->ring_size, GFP_KERNEL); 370 if (!ring->ring_backup) 371 return -ENOMEM; 372 } 373 374 /* Allocate ring buffer */ 375 if (ring->ring_obj == NULL) { 376 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_bytes, 377 PAGE_SIZE, 378 AMDGPU_GEM_DOMAIN_GTT, 379 &ring->ring_obj, 380 &ring->gpu_addr, 381 (void **)&ring->ring); 382 if (r) { 383 dev_err(adev->dev, "(%d) ring create failed\n", r); 384 kvfree(ring->ring_backup); 385 return r; 386 } 387 amdgpu_ring_clear_ring(ring); 388 } 389 390 ring->max_dw = max_dw; 391 ring->hw_prio = hw_prio; 392 393 if (!ring->no_scheduler && ring->funcs->type < AMDGPU_HW_IP_NUM) { 394 hw_ip = ring->funcs->type; 395 num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds; 396 adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] = 397 &ring->sched; 398 } 399 400 return 0; 401 } 402 403 /** 404 * amdgpu_ring_fini - tear down the driver ring struct. 405 * 406 * @ring: amdgpu_ring structure holding ring information 407 * 408 * Tear down the driver information for the selected ring (all asics). 409 */ 410 void amdgpu_ring_fini(struct amdgpu_ring *ring) 411 { 412 413 /* Not to finish a ring which is not initialized */ 414 if (!(ring->adev) || !(ring->adev->rings[ring->idx])) 415 return; 416 417 ring->sched.ready = false; 418 419 amdgpu_device_wb_free(ring->adev, ring->rptr_offs); 420 amdgpu_device_wb_free(ring->adev, ring->wptr_offs); 421 422 amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs); 423 amdgpu_device_wb_free(ring->adev, ring->fence_offs); 424 425 amdgpu_bo_free_kernel(&ring->ring_obj, 426 &ring->gpu_addr, 427 (void **)&ring->ring); 428 kvfree(ring->ring_backup); 429 ring->ring_backup = NULL; 430 431 dma_fence_put(ring->vmid_wait); 432 ring->vmid_wait = NULL; 433 ring->me = 0; 434 } 435 436 /** 437 * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper 438 * 439 * @ring: ring to write to 440 * @reg0: register to write 441 * @reg1: register to wait on 442 * @ref: reference value to write/wait on 443 * @mask: mask to wait on 444 * 445 * Helper for rings that don't support write and wait in a 446 * single oneshot packet. 447 */ 448 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 449 uint32_t reg0, uint32_t reg1, 450 uint32_t ref, uint32_t mask) 451 { 452 amdgpu_ring_emit_wreg(ring, reg0, ref); 453 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 454 } 455 456 /** 457 * amdgpu_ring_soft_recovery - try to soft recover a ring lockup 458 * 459 * @ring: ring to try the recovery on 460 * @vmid: VMID we try to get going again 461 * @fence: timedout fence 462 * 463 * Tries to get a ring proceeding again when it is stuck. 464 */ 465 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 466 struct dma_fence *fence) 467 { 468 unsigned long flags; 469 ktime_t deadline; 470 bool ret; 471 472 deadline = ktime_add_us(ktime_get(), 10000); 473 474 if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence) 475 return false; 476 477 spin_lock_irqsave(fence->lock, flags); 478 if (!dma_fence_is_signaled_locked(fence)) 479 dma_fence_set_error(fence, -ENODATA); 480 spin_unlock_irqrestore(fence->lock, flags); 481 482 while (!dma_fence_is_signaled(fence) && 483 ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0) 484 ring->funcs->soft_recovery(ring, vmid); 485 486 ret = dma_fence_is_signaled(fence); 487 /* increment the counter only if soft reset worked */ 488 if (ret) 489 atomic_inc(&ring->adev->gpu_reset_counter); 490 491 return ret; 492 } 493 494 /* 495 * Debugfs info 496 */ 497 #if defined(CONFIG_DEBUG_FS) 498 499 static ssize_t amdgpu_ras_cper_debugfs_read(struct file *f, char __user *buf, 500 size_t size, loff_t *offset) 501 { 502 const uint8_t ring_header_size = 12; 503 struct amdgpu_ring *ring = file_inode(f)->i_private; 504 struct ras_cmd_cper_snapshot_req *snapshot_req __free(kfree) = 505 kzalloc(sizeof(struct ras_cmd_cper_snapshot_req), GFP_KERNEL); 506 struct ras_cmd_cper_snapshot_rsp *snapshot_rsp __free(kfree) = 507 kzalloc(sizeof(struct ras_cmd_cper_snapshot_rsp), GFP_KERNEL); 508 struct ras_cmd_cper_record_req *record_req __free(kfree) = 509 kzalloc(sizeof(struct ras_cmd_cper_record_req), GFP_KERNEL); 510 struct ras_cmd_cper_record_rsp *record_rsp __free(kfree) = 511 kzalloc(sizeof(struct ras_cmd_cper_record_rsp), GFP_KERNEL); 512 uint8_t *ring_header __free(kfree) = 513 kzalloc(ring_header_size, GFP_KERNEL); 514 uint32_t total_cper_num; 515 uint64_t start_cper_id; 516 int r; 517 518 if (!snapshot_req || !snapshot_rsp || !record_req || !record_rsp || 519 !ring_header) 520 return -ENOMEM; 521 522 if (!(*offset)) { 523 if (copy_to_user(buf, ring_header, ring_header_size)) 524 return -EFAULT; 525 buf += ring_header_size; 526 } 527 528 r = amdgpu_ras_mgr_handle_ras_cmd(ring->adev, 529 RAS_CMD__GET_CPER_SNAPSHOT, 530 snapshot_req, sizeof(struct ras_cmd_cper_snapshot_req), 531 snapshot_rsp, sizeof(struct ras_cmd_cper_snapshot_rsp)); 532 if (r || !snapshot_rsp->total_cper_num) 533 return r; 534 535 start_cper_id = snapshot_rsp->start_cper_id; 536 total_cper_num = snapshot_rsp->total_cper_num; 537 538 record_req->buf_ptr = (uint64_t)(uintptr_t)buf; 539 record_req->buf_size = size; 540 record_req->cper_start_id = start_cper_id + *offset; 541 record_req->cper_num = total_cper_num; 542 r = amdgpu_ras_mgr_handle_ras_cmd(ring->adev, RAS_CMD__GET_CPER_RECORD, 543 record_req, sizeof(struct ras_cmd_cper_record_req), 544 record_rsp, sizeof(struct ras_cmd_cper_record_rsp)); 545 if (r) 546 return r; 547 548 r = *offset ? record_rsp->real_data_size : record_rsp->real_data_size + ring_header_size; 549 (*offset) += record_rsp->real_cper_num; 550 551 return r; 552 } 553 554 /* Layout of file is 12 bytes consisting of 555 * - rptr 556 * - wptr 557 * - driver's copy of wptr 558 * 559 * followed by n-words of ring data 560 */ 561 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, 562 size_t size, loff_t *pos) 563 { 564 struct amdgpu_ring *ring = file_inode(f)->i_private; 565 uint32_t value, result, early[3]; 566 uint64_t p; 567 loff_t i; 568 int r; 569 570 if (ring->funcs->type == AMDGPU_RING_TYPE_CPER && amdgpu_uniras_enabled(ring->adev)) 571 return amdgpu_ras_cper_debugfs_read(f, buf, size, pos); 572 573 if (*pos & 3 || size & 3) 574 return -EINVAL; 575 576 result = 0; 577 578 if (*pos < 12) { 579 if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) 580 mutex_lock(&ring->adev->cper.ring_lock); 581 582 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; 583 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; 584 early[2] = ring->wptr & ring->buf_mask; 585 for (i = *pos / 4; i < 3 && size; i++) { 586 r = put_user(early[i], (uint32_t *)buf); 587 if (r) { 588 result = r; 589 goto out; 590 } 591 buf += 4; 592 result += 4; 593 size -= 4; 594 *pos += 4; 595 } 596 } 597 598 if (ring->funcs->type != AMDGPU_RING_TYPE_CPER) { 599 while (size) { 600 if (*pos >= (ring->ring_size + 12)) 601 return result; 602 603 value = ring->ring[(*pos - 12)/4]; 604 r = put_user(value, (uint32_t *)buf); 605 if (r) 606 return r; 607 buf += 4; 608 result += 4; 609 size -= 4; 610 *pos += 4; 611 } 612 } else { 613 p = early[0]; 614 if (early[0] <= early[1]) 615 size = (early[1] - early[0]); 616 else 617 size = ring->ring_size - (early[0] - early[1]); 618 619 while (size) { 620 if (p == early[1]) 621 goto out; 622 623 value = ring->ring[p]; 624 r = put_user(value, (uint32_t *)buf); 625 if (r) { 626 result = r; 627 goto out; 628 } 629 630 buf += 4; 631 result += 4; 632 size--; 633 p++; 634 p &= ring->ptr_mask; 635 } 636 } 637 638 out: 639 if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) 640 mutex_unlock(&ring->adev->cper.ring_lock); 641 642 return result; 643 } 644 645 static ssize_t amdgpu_debugfs_virt_ring_read(struct file *f, char __user *buf, 646 size_t size, loff_t *pos) 647 { 648 struct amdgpu_ring *ring = file_inode(f)->i_private; 649 650 if (*pos & 3 || size & 3) 651 return -EINVAL; 652 653 if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) 654 amdgpu_virt_req_ras_cper_dump(ring->adev, false); 655 656 return amdgpu_debugfs_ring_read(f, buf, size, pos); 657 } 658 659 static const struct file_operations amdgpu_debugfs_ring_fops = { 660 .owner = THIS_MODULE, 661 .read = amdgpu_debugfs_ring_read, 662 .llseek = default_llseek 663 }; 664 665 static const struct file_operations amdgpu_debugfs_virt_ring_fops = { 666 .owner = THIS_MODULE, 667 .read = amdgpu_debugfs_virt_ring_read, 668 .llseek = default_llseek 669 }; 670 671 static ssize_t amdgpu_debugfs_mqd_read(struct file *f, char __user *buf, 672 size_t size, loff_t *pos) 673 { 674 struct amdgpu_ring *ring = file_inode(f)->i_private; 675 ssize_t bytes = min_t(ssize_t, ring->mqd_size - *pos, size); 676 void *from = ((u8 *)ring->mqd_ptr) + *pos; 677 678 if (*pos > ring->mqd_size) 679 return 0; 680 681 if (copy_to_user(buf, from, bytes)) 682 return -EFAULT; 683 684 *pos += bytes; 685 return bytes; 686 } 687 688 static const struct file_operations amdgpu_debugfs_mqd_fops = { 689 .owner = THIS_MODULE, 690 .read = amdgpu_debugfs_mqd_read, 691 .llseek = default_llseek 692 }; 693 694 static int amdgpu_debugfs_ring_error(void *data, u64 val) 695 { 696 struct amdgpu_ring *ring = data; 697 698 amdgpu_fence_driver_set_error(ring, val); 699 return 0; 700 } 701 702 DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(amdgpu_debugfs_error_fops, NULL, 703 amdgpu_debugfs_ring_error, "%lld\n"); 704 705 #endif 706 707 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, 708 struct amdgpu_ring *ring) 709 { 710 #if defined(CONFIG_DEBUG_FS) 711 struct drm_minor *minor = adev_to_drm(adev)->primary; 712 struct dentry *root = minor->debugfs_root; 713 char name[32]; 714 715 sprintf(name, "amdgpu_ring_%s", ring->name); 716 if (amdgpu_sriov_vf(adev)) 717 debugfs_create_file_size(name, S_IFREG | 0444, root, ring, 718 &amdgpu_debugfs_virt_ring_fops, 719 ring->ring_size + 12); 720 else 721 debugfs_create_file_size(name, S_IFREG | 0444, root, ring, 722 &amdgpu_debugfs_ring_fops, 723 ring->ring_size + 12); 724 725 if (ring->mqd_obj) { 726 sprintf(name, "amdgpu_mqd_%s", ring->name); 727 debugfs_create_file_size(name, S_IFREG | 0444, root, ring, 728 &amdgpu_debugfs_mqd_fops, 729 ring->mqd_size); 730 } 731 732 sprintf(name, "amdgpu_error_%s", ring->name); 733 debugfs_create_file(name, 0200, root, ring, 734 &amdgpu_debugfs_error_fops); 735 736 #endif 737 } 738 739 /** 740 * amdgpu_ring_test_helper - tests ring and set sched readiness status 741 * 742 * @ring: ring to try the recovery on 743 * 744 * Tests ring and set sched readiness status 745 * 746 * Returns 0 on success, error on failure. 747 */ 748 int amdgpu_ring_test_helper(struct amdgpu_ring *ring) 749 { 750 struct amdgpu_device *adev = ring->adev; 751 int r; 752 753 r = amdgpu_ring_test_ring(ring); 754 if (r) 755 DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n", 756 ring->name, r); 757 else 758 DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n", 759 ring->name); 760 761 ring->sched.ready = !r; 762 763 return r; 764 } 765 766 static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring, 767 struct amdgpu_mqd_prop *prop) 768 { 769 struct amdgpu_device *adev = ring->adev; 770 bool is_high_prio_compute = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE && 771 amdgpu_gfx_is_high_priority_compute_queue(adev, ring); 772 bool is_high_prio_gfx = ring->funcs->type == AMDGPU_RING_TYPE_GFX && 773 amdgpu_gfx_is_high_priority_graphics_queue(adev, ring); 774 775 memset(prop, 0, sizeof(*prop)); 776 777 prop->mqd_gpu_addr = ring->mqd_gpu_addr; 778 prop->hqd_base_gpu_addr = ring->gpu_addr; 779 prop->rptr_gpu_addr = ring->rptr_gpu_addr; 780 prop->wptr_gpu_addr = ring->wptr_gpu_addr; 781 prop->queue_size = ring->ring_size; 782 prop->eop_gpu_addr = ring->eop_gpu_addr; 783 prop->use_doorbell = ring->use_doorbell; 784 prop->doorbell_index = ring->doorbell_index; 785 prop->kernel_queue = true; 786 787 /* map_queues packet doesn't need activate the queue, 788 * so only kiq need set this field. 789 */ 790 prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ; 791 792 prop->allow_tunneling = is_high_prio_compute; 793 if (is_high_prio_compute || is_high_prio_gfx) { 794 prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 795 prop->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 796 } 797 } 798 799 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring) 800 { 801 struct amdgpu_device *adev = ring->adev; 802 struct amdgpu_mqd *mqd_mgr; 803 struct amdgpu_mqd_prop prop; 804 805 amdgpu_ring_to_mqd_prop(ring, &prop); 806 807 ring->wptr = 0; 808 809 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 810 mqd_mgr = &adev->mqds[AMDGPU_HW_IP_COMPUTE]; 811 else 812 mqd_mgr = &adev->mqds[ring->funcs->type]; 813 814 return mqd_mgr->init_mqd(adev, ring->mqd_ptr, &prop); 815 } 816 817 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring) 818 { 819 if (ring->is_sw_ring) 820 amdgpu_sw_ring_ib_begin(ring); 821 } 822 823 void amdgpu_ring_ib_end(struct amdgpu_ring *ring) 824 { 825 if (ring->is_sw_ring) 826 amdgpu_sw_ring_ib_end(ring); 827 } 828 829 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring) 830 { 831 if (ring->is_sw_ring) 832 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CONTROL); 833 } 834 835 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring) 836 { 837 if (ring->is_sw_ring) 838 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CE); 839 } 840 841 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring) 842 { 843 if (ring->is_sw_ring) 844 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_DE); 845 } 846 847 bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring) 848 { 849 if (!ring) 850 return false; 851 852 if (ring->no_scheduler || !drm_sched_wqueue_ready(&ring->sched)) 853 return false; 854 855 return true; 856 } 857 858 void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, 859 struct amdgpu_fence *guilty_fence) 860 { 861 /* Stop the scheduler to prevent anybody else from touching the ring buffer. */ 862 drm_sched_wqueue_stop(&ring->sched); 863 /* back up the non-guilty commands */ 864 amdgpu_ring_backup_unprocessed_commands(ring, guilty_fence); 865 } 866 867 int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, 868 struct amdgpu_fence *guilty_fence) 869 { 870 unsigned int i; 871 int r; 872 873 /* verify that the ring is functional */ 874 r = amdgpu_ring_test_ring(ring); 875 if (r) 876 return r; 877 878 /* signal the guilty fence and set an error on all fences from the context */ 879 if (guilty_fence) 880 amdgpu_fence_driver_guilty_force_completion(guilty_fence); 881 /* Re-emit the non-guilty commands */ 882 if (ring->ring_backup_entries_to_copy) { 883 amdgpu_ring_alloc_reemit(ring, ring->ring_backup_entries_to_copy); 884 for (i = 0; i < ring->ring_backup_entries_to_copy; i++) 885 amdgpu_ring_write(ring, ring->ring_backup[i]); 886 amdgpu_ring_commit(ring); 887 } 888 /* Start the scheduler again */ 889 drm_sched_wqueue_start(&ring->sched); 890 return 0; 891 } 892 893 bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring, 894 u32 reset_type) 895 { 896 switch (ring->funcs->type) { 897 case AMDGPU_RING_TYPE_GFX: 898 if (ring->adev->gfx.gfx_supported_reset & reset_type) 899 return true; 900 break; 901 case AMDGPU_RING_TYPE_COMPUTE: 902 if (ring->adev->gfx.compute_supported_reset & reset_type) 903 return true; 904 break; 905 case AMDGPU_RING_TYPE_SDMA: 906 if (ring->adev->sdma.supported_reset & reset_type) 907 return true; 908 break; 909 case AMDGPU_RING_TYPE_VCN_DEC: 910 case AMDGPU_RING_TYPE_VCN_ENC: 911 if (ring->adev->vcn.supported_reset & reset_type) 912 return true; 913 break; 914 case AMDGPU_RING_TYPE_VCN_JPEG: 915 if (ring->adev->jpeg.supported_reset & reset_type) 916 return true; 917 break; 918 default: 919 break; 920 } 921 return false; 922 } 923