12bc956efSJack Xiao /* 22bc956efSJack Xiao * Copyright 2019 Advanced Micro Devices, Inc. 32bc956efSJack Xiao * 42bc956efSJack Xiao * Permission is hereby granted, free of charge, to any person obtaining a 52bc956efSJack Xiao * copy of this software and associated documentation files (the "Software"), 62bc956efSJack Xiao * to deal in the Software without restriction, including without limitation 72bc956efSJack Xiao * the rights to use, copy, modify, merge, publish, distribute, sublicense, 82bc956efSJack Xiao * and/or sell copies of the Software, and to permit persons to whom the 92bc956efSJack Xiao * Software is furnished to do so, subject to the following conditions: 102bc956efSJack Xiao * 112bc956efSJack Xiao * The above copyright notice and this permission notice shall be included in 122bc956efSJack Xiao * all copies or substantial portions of the Software. 132bc956efSJack Xiao * 142bc956efSJack Xiao * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 152bc956efSJack Xiao * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 162bc956efSJack Xiao * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 172bc956efSJack Xiao * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 182bc956efSJack Xiao * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 192bc956efSJack Xiao * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 202bc956efSJack Xiao * OTHER DEALINGS IN THE SOFTWARE. 212bc956efSJack Xiao * 222bc956efSJack Xiao */ 232bc956efSJack Xiao 242bc956efSJack Xiao #ifndef __AMDGPU_MES_CTX_H__ 252bc956efSJack Xiao #define __AMDGPU_MES_CTX_H__ 262bc956efSJack Xiao 272bc956efSJack Xiao #include "v10_structs.h" 282bc956efSJack Xiao 292bc956efSJack Xiao enum { 302bc956efSJack Xiao AMDGPU_MES_CTX_RPTR_OFFS = 0, 312bc956efSJack Xiao AMDGPU_MES_CTX_WPTR_OFFS, 322bc956efSJack Xiao AMDGPU_MES_CTX_FENCE_OFFS, 332bc956efSJack Xiao AMDGPU_MES_CTX_COND_EXE_OFFS, 342bc956efSJack Xiao AMDGPU_MES_CTX_TRAIL_FENCE_OFFS, 352bc956efSJack Xiao AMDGPU_MES_CTX_MAX_OFFS, 362bc956efSJack Xiao }; 372bc956efSJack Xiao 382bc956efSJack Xiao enum { 392bc956efSJack Xiao AMDGPU_MES_CTX_RING_OFFS = AMDGPU_MES_CTX_MAX_OFFS, 402bc956efSJack Xiao AMDGPU_MES_CTX_IB_OFFS, 412bc956efSJack Xiao AMDGPU_MES_CTX_PADDING_OFFS, 422bc956efSJack Xiao }; 432bc956efSJack Xiao 442bc956efSJack Xiao #define AMDGPU_MES_CTX_MAX_GFX_RINGS 1 452bc956efSJack Xiao #define AMDGPU_MES_CTX_MAX_COMPUTE_RINGS 4 462bc956efSJack Xiao #define AMDGPU_MES_CTX_MAX_SDMA_RINGS 2 472bc956efSJack Xiao #define AMDGPU_MES_CTX_MAX_RINGS \ 482bc956efSJack Xiao (AMDGPU_MES_CTX_MAX_GFX_RINGS + \ 492bc956efSJack Xiao AMDGPU_MES_CTX_MAX_COMPUTE_RINGS + \ 502bc956efSJack Xiao AMDGPU_MES_CTX_MAX_SDMA_RINGS) 512bc956efSJack Xiao 522bc956efSJack Xiao #define AMDGPU_CSA_SDMA_SIZE 64 532bc956efSJack Xiao #define GFX10_MEC_HPD_SIZE 2048 542bc956efSJack Xiao 552bc956efSJack Xiao struct amdgpu_wb_slot { 562bc956efSJack Xiao uint32_t data[8]; 572bc956efSJack Xiao }; 582bc956efSJack Xiao 592bc956efSJack Xiao struct amdgpu_mes_ctx_meta_data { 602bc956efSJack Xiao struct { 612bc956efSJack Xiao uint8_t ring[PAGE_SIZE * 4]; 622bc956efSJack Xiao 632bc956efSJack Xiao /* gfx csa */ 642bc956efSJack Xiao struct v10_gfx_meta_data gfx_meta_data; 652bc956efSJack Xiao 662bc956efSJack Xiao uint8_t gds_backup[64 * 1024]; 672bc956efSJack Xiao 682bc956efSJack Xiao struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS]; 692bc956efSJack Xiao 702bc956efSJack Xiao /* only for ib test */ 712bc956efSJack Xiao uint32_t ib[256] __aligned(256); 722bc956efSJack Xiao 732bc956efSJack Xiao uint32_t padding[64]; 742bc956efSJack Xiao 752bc956efSJack Xiao } __aligned(PAGE_SIZE) gfx[AMDGPU_MES_CTX_MAX_GFX_RINGS]; 762bc956efSJack Xiao 772bc956efSJack Xiao struct { 782bc956efSJack Xiao uint8_t ring[PAGE_SIZE * 4]; 792bc956efSJack Xiao 802bc956efSJack Xiao uint8_t mec_hpd[GFX10_MEC_HPD_SIZE]; 812bc956efSJack Xiao 822bc956efSJack Xiao struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS]; 832bc956efSJack Xiao 842bc956efSJack Xiao /* only for ib test */ 852bc956efSJack Xiao uint32_t ib[256] __aligned(256); 862bc956efSJack Xiao 872bc956efSJack Xiao uint32_t padding[64]; 882bc956efSJack Xiao 892bc956efSJack Xiao } __aligned(PAGE_SIZE) compute[AMDGPU_MES_CTX_MAX_COMPUTE_RINGS]; 902bc956efSJack Xiao 912bc956efSJack Xiao struct { 922bc956efSJack Xiao uint8_t ring[PAGE_SIZE * 4]; 932bc956efSJack Xiao 942bc956efSJack Xiao /* sdma csa for mcbp */ 952bc956efSJack Xiao uint8_t sdma_meta_data[AMDGPU_CSA_SDMA_SIZE]; 962bc956efSJack Xiao 972bc956efSJack Xiao struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS]; 982bc956efSJack Xiao 992bc956efSJack Xiao /* only for ib test */ 1002bc956efSJack Xiao uint32_t ib[256] __aligned(256); 1012bc956efSJack Xiao 1022bc956efSJack Xiao uint32_t padding[64]; 1032bc956efSJack Xiao 1042bc956efSJack Xiao } __aligned(PAGE_SIZE) sdma[AMDGPU_MES_CTX_MAX_SDMA_RINGS]; 1052bc956efSJack Xiao }; 1062bc956efSJack Xiao 1072bc956efSJack Xiao struct amdgpu_mes_ctx_data { 1082bc956efSJack Xiao struct amdgpu_bo *meta_data_obj; 1092bc956efSJack Xiao uint64_t meta_data_gpu_addr; 110*fe4e9ff9SJack Xiao uint64_t meta_data_mc_addr; 1112bc956efSJack Xiao struct amdgpu_bo_va *meta_data_va; 1122bc956efSJack Xiao void *meta_data_ptr; 1132bc956efSJack Xiao uint32_t gang_ids[AMDGPU_HW_IP_DMA+1]; 1142bc956efSJack Xiao }; 1152bc956efSJack Xiao 1162bc956efSJack Xiao #define AMDGPU_FENCE_MES_QUEUE_FLAG 0x1000000u 1172bc956efSJack Xiao #define AMDGPU_FENCE_MES_QUEUE_ID_MASK (AMDGPU_FENCE_MES_QUEUE_FLAG - 1) 1182bc956efSJack Xiao 11911f39576SJack Xiao #define AMDGPU_FENCE_MES_QUEUE_FLAG 0x1000000u 120534000c0SJack Xiao #define AMDGPU_FENCE_MES_QUEUE_ID_MASK (AMDGPU_FENCE_MES_QUEUE_FLAG - 1) 12111f39576SJack Xiao 1222bc956efSJack Xiao #endif 123