1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_modeset_helper_vtables.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 #include "atombios_encoders.h" 36 #include "atombios_dp.h" 37 #include "amdgpu_connectors.h" 38 #include "amdgpu_i2c.h" 39 #include "amdgpu_display.h" 40 41 #include <linux/pm_runtime.h> 42 43 void amdgpu_connector_hotplug(struct drm_connector *connector) 44 { 45 struct drm_device *dev = connector->dev; 46 struct amdgpu_device *adev = drm_to_adev(dev); 47 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 48 49 /* bail if the connector does not have hpd pin, e.g., 50 * VGA, TV, etc. 51 */ 52 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 53 return; 54 55 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 56 57 /* if the connector is already off, don't turn it back on */ 58 if (connector->dpms != DRM_MODE_DPMS_ON) 59 return; 60 61 /* just deal with DP (not eDP) here. */ 62 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 63 struct amdgpu_connector_atom_dig *dig_connector = 64 amdgpu_connector->con_priv; 65 66 /* if existing sink type was not DP no need to retrain */ 67 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 68 return; 69 70 /* first get sink type as it may be reset after (un)plug */ 71 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 72 /* don't do anything if sink is not display port, i.e., 73 * passive dp->(dvi|hdmi) adaptor 74 */ 75 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 76 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 77 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't start link training before we have the DPCD */ 79 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 80 return; 81 82 /* Turn the connector off and back on immediately, which 83 * will trigger link training 84 */ 85 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 86 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 87 } 88 } 89 } 90 91 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 92 { 93 struct drm_crtc *crtc = encoder->crtc; 94 95 if (crtc && crtc->enabled) { 96 drm_crtc_helper_set_mode(crtc, &crtc->mode, 97 crtc->x, crtc->y, crtc->primary->fb); 98 } 99 } 100 101 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 102 { 103 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 104 struct amdgpu_connector_atom_dig *dig_connector; 105 int bpc = 8; 106 unsigned int mode_clock, max_tmds_clock; 107 108 switch (connector->connector_type) { 109 case DRM_MODE_CONNECTOR_DVII: 110 case DRM_MODE_CONNECTOR_HDMIB: 111 if (amdgpu_connector->use_digital) { 112 if (connector->display_info.is_hdmi) { 113 if (connector->display_info.bpc) 114 bpc = connector->display_info.bpc; 115 } 116 } 117 break; 118 case DRM_MODE_CONNECTOR_DVID: 119 case DRM_MODE_CONNECTOR_HDMIA: 120 if (connector->display_info.is_hdmi) { 121 if (connector->display_info.bpc) 122 bpc = connector->display_info.bpc; 123 } 124 break; 125 case DRM_MODE_CONNECTOR_DisplayPort: 126 dig_connector = amdgpu_connector->con_priv; 127 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 128 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 129 connector->display_info.is_hdmi) { 130 if (connector->display_info.bpc) 131 bpc = connector->display_info.bpc; 132 } 133 break; 134 case DRM_MODE_CONNECTOR_eDP: 135 case DRM_MODE_CONNECTOR_LVDS: 136 if (connector->display_info.bpc) 137 bpc = connector->display_info.bpc; 138 else { 139 const struct drm_connector_helper_funcs *connector_funcs = 140 connector->helper_private; 141 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 142 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 143 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 144 145 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 146 bpc = 6; 147 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 148 bpc = 8; 149 } 150 break; 151 } 152 153 if (connector->display_info.is_hdmi) { 154 /* 155 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 156 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 157 * 12 bpc is always supported on hdmi deep color sinks, as this is 158 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 159 */ 160 if (bpc > 12) { 161 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 162 connector->name, bpc); 163 bpc = 12; 164 } 165 166 /* Any defined maximum tmds clock limit we must not exceed? */ 167 if (connector->display_info.max_tmds_clock > 0) { 168 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 169 mode_clock = amdgpu_connector->pixelclock_for_modeset; 170 171 /* Maximum allowable input clock in kHz */ 172 max_tmds_clock = connector->display_info.max_tmds_clock; 173 174 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 175 connector->name, mode_clock, max_tmds_clock); 176 177 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 178 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 179 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && 180 (mode_clock * 5/4 <= max_tmds_clock)) 181 bpc = 10; 182 else 183 bpc = 8; 184 185 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 186 connector->name, bpc); 187 } 188 189 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 190 bpc = 8; 191 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 192 connector->name, bpc); 193 } 194 } else if (bpc > 8) { 195 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 196 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 197 connector->name); 198 bpc = 8; 199 } 200 } 201 202 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 203 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 204 connector->name); 205 bpc = 8; 206 } 207 208 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 209 connector->name, connector->display_info.bpc, bpc); 210 211 return bpc; 212 } 213 214 static void 215 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 216 enum drm_connector_status status) 217 { 218 struct drm_encoder *best_encoder; 219 struct drm_encoder *encoder; 220 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 221 bool connected; 222 223 best_encoder = connector_funcs->best_encoder(connector); 224 225 drm_connector_for_each_possible_encoder(connector, encoder) { 226 if ((encoder == best_encoder) && (status == connector_status_connected)) 227 connected = true; 228 else 229 connected = false; 230 231 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 232 } 233 } 234 235 static struct drm_encoder * 236 amdgpu_connector_find_encoder(struct drm_connector *connector, 237 int encoder_type) 238 { 239 struct drm_encoder *encoder; 240 241 drm_connector_for_each_possible_encoder(connector, encoder) { 242 if (encoder->encoder_type == encoder_type) 243 return encoder; 244 } 245 246 return NULL; 247 } 248 249 static struct edid * 250 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 251 { 252 return drm_edid_duplicate(drm_edid_raw(adev->mode_info.bios_hardcoded_edid)); 253 } 254 255 static void amdgpu_connector_get_edid(struct drm_connector *connector) 256 { 257 struct drm_device *dev = connector->dev; 258 struct amdgpu_device *adev = drm_to_adev(dev); 259 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 260 261 if (amdgpu_connector->edid) 262 return; 263 264 /* on hw with routers, select right port */ 265 if (amdgpu_connector->router.ddc_valid) 266 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 267 268 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 269 ENCODER_OBJECT_ID_NONE) && 270 amdgpu_connector->ddc_bus->has_aux) { 271 amdgpu_connector->edid = drm_get_edid(connector, 272 &amdgpu_connector->ddc_bus->aux.ddc); 273 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 274 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 275 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 276 277 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 278 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 279 amdgpu_connector->ddc_bus->has_aux) 280 amdgpu_connector->edid = drm_get_edid(connector, 281 &amdgpu_connector->ddc_bus->aux.ddc); 282 else if (amdgpu_connector->ddc_bus) 283 amdgpu_connector->edid = drm_get_edid(connector, 284 &amdgpu_connector->ddc_bus->adapter); 285 } else if (amdgpu_connector->ddc_bus) { 286 amdgpu_connector->edid = drm_get_edid(connector, 287 &amdgpu_connector->ddc_bus->adapter); 288 } 289 290 if (!amdgpu_connector->edid) { 291 /* some laptops provide a hardcoded edid in rom for LCDs */ 292 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 293 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { 294 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 295 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 296 } 297 } 298 } 299 300 static void amdgpu_connector_free_edid(struct drm_connector *connector) 301 { 302 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 303 304 kfree(amdgpu_connector->edid); 305 amdgpu_connector->edid = NULL; 306 } 307 308 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 309 { 310 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 311 int ret; 312 313 if (amdgpu_connector->edid) { 314 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 315 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 316 return ret; 317 } 318 drm_connector_update_edid_property(connector, NULL); 319 return 0; 320 } 321 322 static struct drm_encoder * 323 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 324 { 325 struct drm_encoder *encoder; 326 327 /* pick the first one */ 328 drm_connector_for_each_possible_encoder(connector, encoder) 329 return encoder; 330 331 return NULL; 332 } 333 334 static void amdgpu_get_native_mode(struct drm_connector *connector) 335 { 336 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 337 struct amdgpu_encoder *amdgpu_encoder; 338 339 if (encoder == NULL) 340 return; 341 342 amdgpu_encoder = to_amdgpu_encoder(encoder); 343 344 if (!list_empty(&connector->probed_modes)) { 345 struct drm_display_mode *preferred_mode = 346 list_first_entry(&connector->probed_modes, 347 struct drm_display_mode, head); 348 349 amdgpu_encoder->native_mode = *preferred_mode; 350 } else { 351 amdgpu_encoder->native_mode.clock = 0; 352 } 353 } 354 355 static struct drm_display_mode * 356 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 357 { 358 struct drm_device *dev = encoder->dev; 359 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 360 struct drm_display_mode *mode = NULL; 361 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 362 363 if (native_mode->hdisplay != 0 && 364 native_mode->vdisplay != 0 && 365 native_mode->clock != 0) { 366 mode = drm_mode_duplicate(dev, native_mode); 367 if (!mode) 368 return NULL; 369 370 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 371 drm_mode_set_name(mode); 372 373 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 374 } else if (native_mode->hdisplay != 0 && 375 native_mode->vdisplay != 0) { 376 /* mac laptops without an edid */ 377 /* Note that this is not necessarily the exact panel mode, 378 * but an approximation based on the cvt formula. For these 379 * systems we should ideally read the mode info out of the 380 * registers or add a mode table, but this works and is much 381 * simpler. 382 */ 383 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 384 if (!mode) 385 return NULL; 386 387 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 388 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 389 } 390 return mode; 391 } 392 393 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 394 struct drm_connector *connector) 395 { 396 struct drm_device *dev = encoder->dev; 397 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 398 struct drm_display_mode *mode = NULL; 399 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 400 int i; 401 static const struct mode_size { 402 int w; 403 int h; 404 } common_modes[17] = { 405 { 640, 480}, 406 { 720, 480}, 407 { 800, 600}, 408 { 848, 480}, 409 {1024, 768}, 410 {1152, 768}, 411 {1280, 720}, 412 {1280, 800}, 413 {1280, 854}, 414 {1280, 960}, 415 {1280, 1024}, 416 {1440, 900}, 417 {1400, 1050}, 418 {1680, 1050}, 419 {1600, 1200}, 420 {1920, 1080}, 421 {1920, 1200} 422 }; 423 424 for (i = 0; i < 17; i++) { 425 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 426 if (common_modes[i].w > 1024 || 427 common_modes[i].h > 768) 428 continue; 429 } 430 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 431 if (common_modes[i].w > native_mode->hdisplay || 432 common_modes[i].h > native_mode->vdisplay || 433 (common_modes[i].w == native_mode->hdisplay && 434 common_modes[i].h == native_mode->vdisplay)) 435 continue; 436 } 437 if (common_modes[i].w < 320 || common_modes[i].h < 200) 438 continue; 439 440 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 441 if (!mode) 442 return; 443 444 drm_mode_probed_add(connector, mode); 445 } 446 } 447 448 static int amdgpu_connector_set_property(struct drm_connector *connector, 449 struct drm_property *property, 450 uint64_t val) 451 { 452 struct drm_device *dev = connector->dev; 453 struct amdgpu_device *adev = drm_to_adev(dev); 454 struct drm_encoder *encoder; 455 struct amdgpu_encoder *amdgpu_encoder; 456 457 if (property == adev->mode_info.coherent_mode_property) { 458 struct amdgpu_encoder_atom_dig *dig; 459 bool new_coherent_mode; 460 461 /* need to find digital encoder on connector */ 462 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 463 if (!encoder) 464 return 0; 465 466 amdgpu_encoder = to_amdgpu_encoder(encoder); 467 468 if (!amdgpu_encoder->enc_priv) 469 return 0; 470 471 dig = amdgpu_encoder->enc_priv; 472 new_coherent_mode = val ? true : false; 473 if (dig->coherent_mode != new_coherent_mode) { 474 dig->coherent_mode = new_coherent_mode; 475 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 476 } 477 } 478 479 if (property == adev->mode_info.audio_property) { 480 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 481 /* need to find digital encoder on connector */ 482 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 483 if (!encoder) 484 return 0; 485 486 amdgpu_encoder = to_amdgpu_encoder(encoder); 487 488 if (amdgpu_connector->audio != val) { 489 amdgpu_connector->audio = val; 490 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 491 } 492 } 493 494 if (property == adev->mode_info.dither_property) { 495 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 496 /* need to find digital encoder on connector */ 497 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 498 if (!encoder) 499 return 0; 500 501 amdgpu_encoder = to_amdgpu_encoder(encoder); 502 503 if (amdgpu_connector->dither != val) { 504 amdgpu_connector->dither = val; 505 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 506 } 507 } 508 509 if (property == adev->mode_info.underscan_property) { 510 /* need to find digital encoder on connector */ 511 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 512 if (!encoder) 513 return 0; 514 515 amdgpu_encoder = to_amdgpu_encoder(encoder); 516 517 if (amdgpu_encoder->underscan_type != val) { 518 amdgpu_encoder->underscan_type = val; 519 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 520 } 521 } 522 523 if (property == adev->mode_info.underscan_hborder_property) { 524 /* need to find digital encoder on connector */ 525 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 526 if (!encoder) 527 return 0; 528 529 amdgpu_encoder = to_amdgpu_encoder(encoder); 530 531 if (amdgpu_encoder->underscan_hborder != val) { 532 amdgpu_encoder->underscan_hborder = val; 533 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 534 } 535 } 536 537 if (property == adev->mode_info.underscan_vborder_property) { 538 /* need to find digital encoder on connector */ 539 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 540 if (!encoder) 541 return 0; 542 543 amdgpu_encoder = to_amdgpu_encoder(encoder); 544 545 if (amdgpu_encoder->underscan_vborder != val) { 546 amdgpu_encoder->underscan_vborder = val; 547 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 548 } 549 } 550 551 if (property == adev->mode_info.load_detect_property) { 552 struct amdgpu_connector *amdgpu_connector = 553 to_amdgpu_connector(connector); 554 555 if (val == 0) 556 amdgpu_connector->dac_load_detect = false; 557 else 558 amdgpu_connector->dac_load_detect = true; 559 } 560 561 if (property == dev->mode_config.scaling_mode_property) { 562 enum amdgpu_rmx_type rmx_type; 563 564 if (connector->encoder) { 565 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 566 } else { 567 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 568 569 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 570 } 571 572 switch (val) { 573 default: 574 case DRM_MODE_SCALE_NONE: 575 rmx_type = RMX_OFF; 576 break; 577 case DRM_MODE_SCALE_CENTER: 578 rmx_type = RMX_CENTER; 579 break; 580 case DRM_MODE_SCALE_ASPECT: 581 rmx_type = RMX_ASPECT; 582 break; 583 case DRM_MODE_SCALE_FULLSCREEN: 584 rmx_type = RMX_FULL; 585 break; 586 } 587 588 if (amdgpu_encoder->rmx_type == rmx_type) 589 return 0; 590 591 if ((rmx_type != DRM_MODE_SCALE_NONE) && 592 (amdgpu_encoder->native_mode.clock == 0)) 593 return 0; 594 595 amdgpu_encoder->rmx_type = rmx_type; 596 597 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 598 } 599 600 return 0; 601 } 602 603 static void 604 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 605 struct drm_connector *connector) 606 { 607 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 608 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 609 struct drm_display_mode *t, *mode; 610 611 /* If the EDID preferred mode doesn't match the native mode, use it */ 612 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 613 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 614 if (mode->hdisplay != native_mode->hdisplay || 615 mode->vdisplay != native_mode->vdisplay) 616 drm_mode_copy(native_mode, mode); 617 } 618 } 619 620 /* Try to get native mode details from EDID if necessary */ 621 if (!native_mode->clock) { 622 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 623 if (mode->hdisplay == native_mode->hdisplay && 624 mode->vdisplay == native_mode->vdisplay) { 625 drm_mode_copy(native_mode, mode); 626 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 627 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 628 break; 629 } 630 } 631 } 632 633 if (!native_mode->clock) { 634 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 635 amdgpu_encoder->rmx_type = RMX_OFF; 636 } 637 } 638 639 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 640 { 641 struct drm_encoder *encoder; 642 int ret = 0; 643 struct drm_display_mode *mode; 644 645 amdgpu_connector_get_edid(connector); 646 ret = amdgpu_connector_ddc_get_modes(connector); 647 if (ret > 0) { 648 encoder = amdgpu_connector_best_single_encoder(connector); 649 if (encoder) { 650 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 651 /* add scaled modes */ 652 amdgpu_connector_add_common_modes(encoder, connector); 653 } 654 return ret; 655 } 656 657 encoder = amdgpu_connector_best_single_encoder(connector); 658 if (!encoder) 659 return 0; 660 661 /* we have no EDID modes */ 662 mode = amdgpu_connector_lcd_native_mode(encoder); 663 if (mode) { 664 ret = 1; 665 drm_mode_probed_add(connector, mode); 666 /* add the width/height from vbios tables if available */ 667 connector->display_info.width_mm = mode->width_mm; 668 connector->display_info.height_mm = mode->height_mm; 669 /* add scaled modes */ 670 amdgpu_connector_add_common_modes(encoder, connector); 671 } 672 673 return ret; 674 } 675 676 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 677 const struct drm_display_mode *mode) 678 { 679 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 680 681 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 682 return MODE_PANEL; 683 684 if (encoder) { 685 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 686 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 687 688 /* AVIVO hardware supports downscaling modes larger than the panel 689 * to the panel size, but I'm not sure this is desirable. 690 */ 691 if ((mode->hdisplay > native_mode->hdisplay) || 692 (mode->vdisplay > native_mode->vdisplay)) 693 return MODE_PANEL; 694 695 /* if scaling is disabled, block non-native modes */ 696 if (amdgpu_encoder->rmx_type == RMX_OFF) { 697 if ((mode->hdisplay != native_mode->hdisplay) || 698 (mode->vdisplay != native_mode->vdisplay)) 699 return MODE_PANEL; 700 } 701 } 702 703 return MODE_OK; 704 } 705 706 static enum drm_connector_status 707 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 708 { 709 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 710 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 711 enum drm_connector_status ret = connector_status_disconnected; 712 int r; 713 714 if (!drm_kms_helper_is_poll_worker()) { 715 r = pm_runtime_get_sync(connector->dev->dev); 716 if (r < 0) { 717 pm_runtime_put_autosuspend(connector->dev->dev); 718 return connector_status_disconnected; 719 } 720 } 721 722 if (encoder) { 723 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 724 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 725 726 /* check if panel is valid */ 727 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 728 ret = connector_status_connected; 729 730 } 731 732 /* check for edid as well */ 733 amdgpu_connector_get_edid(connector); 734 if (amdgpu_connector->edid) 735 ret = connector_status_connected; 736 /* check acpi lid status ??? */ 737 738 amdgpu_connector_update_scratch_regs(connector, ret); 739 740 if (!drm_kms_helper_is_poll_worker()) { 741 pm_runtime_mark_last_busy(connector->dev->dev); 742 pm_runtime_put_autosuspend(connector->dev->dev); 743 } 744 745 return ret; 746 } 747 748 static void amdgpu_connector_unregister(struct drm_connector *connector) 749 { 750 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 751 752 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 753 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 754 amdgpu_connector->ddc_bus->has_aux = false; 755 } 756 } 757 758 static void amdgpu_connector_destroy(struct drm_connector *connector) 759 { 760 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 761 762 amdgpu_connector_free_edid(connector); 763 kfree(amdgpu_connector->con_priv); 764 drm_connector_unregister(connector); 765 drm_connector_cleanup(connector); 766 kfree(connector); 767 } 768 769 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 770 struct drm_property *property, 771 uint64_t value) 772 { 773 struct drm_device *dev = connector->dev; 774 struct amdgpu_encoder *amdgpu_encoder; 775 enum amdgpu_rmx_type rmx_type; 776 777 DRM_DEBUG_KMS("\n"); 778 if (property != dev->mode_config.scaling_mode_property) 779 return 0; 780 781 if (connector->encoder) 782 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 783 else { 784 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 785 786 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 787 } 788 789 switch (value) { 790 case DRM_MODE_SCALE_NONE: 791 rmx_type = RMX_OFF; 792 break; 793 case DRM_MODE_SCALE_CENTER: 794 rmx_type = RMX_CENTER; 795 break; 796 case DRM_MODE_SCALE_ASPECT: 797 rmx_type = RMX_ASPECT; 798 break; 799 default: 800 case DRM_MODE_SCALE_FULLSCREEN: 801 rmx_type = RMX_FULL; 802 break; 803 } 804 805 if (amdgpu_encoder->rmx_type == rmx_type) 806 return 0; 807 808 amdgpu_encoder->rmx_type = rmx_type; 809 810 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 811 return 0; 812 } 813 814 815 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 816 .get_modes = amdgpu_connector_lvds_get_modes, 817 .mode_valid = amdgpu_connector_lvds_mode_valid, 818 .best_encoder = amdgpu_connector_best_single_encoder, 819 }; 820 821 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 822 .dpms = drm_helper_connector_dpms, 823 .detect = amdgpu_connector_lvds_detect, 824 .fill_modes = drm_helper_probe_single_connector_modes, 825 .early_unregister = amdgpu_connector_unregister, 826 .destroy = amdgpu_connector_destroy, 827 .set_property = amdgpu_connector_set_lcd_property, 828 }; 829 830 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 831 { 832 int ret; 833 834 amdgpu_connector_get_edid(connector); 835 ret = amdgpu_connector_ddc_get_modes(connector); 836 amdgpu_get_native_mode(connector); 837 838 return ret; 839 } 840 841 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 842 const struct drm_display_mode *mode) 843 { 844 struct drm_device *dev = connector->dev; 845 struct amdgpu_device *adev = drm_to_adev(dev); 846 847 /* XXX check mode bandwidth */ 848 849 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 850 return MODE_CLOCK_HIGH; 851 852 return MODE_OK; 853 } 854 855 static enum drm_connector_status 856 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 857 { 858 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 859 struct drm_encoder *encoder; 860 const struct drm_encoder_helper_funcs *encoder_funcs; 861 bool dret = false; 862 enum drm_connector_status ret = connector_status_disconnected; 863 int r; 864 865 if (!drm_kms_helper_is_poll_worker()) { 866 r = pm_runtime_get_sync(connector->dev->dev); 867 if (r < 0) { 868 pm_runtime_put_autosuspend(connector->dev->dev); 869 return connector_status_disconnected; 870 } 871 } 872 873 encoder = amdgpu_connector_best_single_encoder(connector); 874 if (!encoder) 875 ret = connector_status_disconnected; 876 877 if (amdgpu_connector->ddc_bus) 878 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 879 if (dret) { 880 amdgpu_connector->detected_by_load = false; 881 amdgpu_connector_free_edid(connector); 882 amdgpu_connector_get_edid(connector); 883 884 if (!amdgpu_connector->edid) { 885 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 886 connector->name); 887 ret = connector_status_connected; 888 } else { 889 amdgpu_connector->use_digital = 890 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 891 892 /* some oems have boards with separate digital and analog connectors 893 * with a shared ddc line (often vga + hdmi) 894 */ 895 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 896 amdgpu_connector_free_edid(connector); 897 ret = connector_status_disconnected; 898 } else { 899 ret = connector_status_connected; 900 } 901 } 902 } else { 903 904 /* if we aren't forcing don't do destructive polling */ 905 if (!force) { 906 /* only return the previous status if we last 907 * detected a monitor via load. 908 */ 909 if (amdgpu_connector->detected_by_load) 910 ret = connector->status; 911 goto out; 912 } 913 914 if (amdgpu_connector->dac_load_detect && encoder) { 915 encoder_funcs = encoder->helper_private; 916 ret = encoder_funcs->detect(encoder, connector); 917 if (ret != connector_status_disconnected) 918 amdgpu_connector->detected_by_load = true; 919 } 920 } 921 922 amdgpu_connector_update_scratch_regs(connector, ret); 923 924 out: 925 if (!drm_kms_helper_is_poll_worker()) { 926 pm_runtime_mark_last_busy(connector->dev->dev); 927 pm_runtime_put_autosuspend(connector->dev->dev); 928 } 929 930 return ret; 931 } 932 933 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 934 .get_modes = amdgpu_connector_vga_get_modes, 935 .mode_valid = amdgpu_connector_vga_mode_valid, 936 .best_encoder = amdgpu_connector_best_single_encoder, 937 }; 938 939 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 940 .dpms = drm_helper_connector_dpms, 941 .detect = amdgpu_connector_vga_detect, 942 .fill_modes = drm_helper_probe_single_connector_modes, 943 .early_unregister = amdgpu_connector_unregister, 944 .destroy = amdgpu_connector_destroy, 945 .set_property = amdgpu_connector_set_property, 946 }; 947 948 static bool 949 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 950 { 951 struct drm_device *dev = connector->dev; 952 struct amdgpu_device *adev = drm_to_adev(dev); 953 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 954 enum drm_connector_status status; 955 956 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 957 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 958 status = connector_status_connected; 959 else 960 status = connector_status_disconnected; 961 if (connector->status == status) 962 return true; 963 } 964 965 return false; 966 } 967 968 static void amdgpu_connector_shared_ddc(enum drm_connector_status *status, 969 struct drm_connector *connector, 970 struct amdgpu_connector *amdgpu_connector) 971 { 972 struct drm_connector *list_connector; 973 struct drm_connector_list_iter iter; 974 struct amdgpu_connector *list_amdgpu_connector; 975 struct drm_device *dev = connector->dev; 976 struct amdgpu_device *adev = drm_to_adev(dev); 977 978 if (amdgpu_connector->shared_ddc && *status == connector_status_connected) { 979 drm_connector_list_iter_begin(dev, &iter); 980 drm_for_each_connector_iter(list_connector, 981 &iter) { 982 if (connector == list_connector) 983 continue; 984 list_amdgpu_connector = to_amdgpu_connector(list_connector); 985 if (list_amdgpu_connector->shared_ddc && 986 list_amdgpu_connector->ddc_bus->rec.i2c_id == 987 amdgpu_connector->ddc_bus->rec.i2c_id) { 988 /* cases where both connectors are digital */ 989 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 990 /* hpd is our only option in this case */ 991 if (!amdgpu_display_hpd_sense(adev, 992 amdgpu_connector->hpd.hpd)) { 993 amdgpu_connector_free_edid(connector); 994 *status = connector_status_disconnected; 995 } 996 } 997 } 998 } 999 drm_connector_list_iter_end(&iter); 1000 } 1001 } 1002 1003 /* 1004 * DVI is complicated 1005 * Do a DDC probe, if DDC probe passes, get the full EDID so 1006 * we can do analog/digital monitor detection at this point. 1007 * If the monitor is an analog monitor or we got no DDC, 1008 * we need to find the DAC encoder object for this connector. 1009 * If we got no DDC, we do load detection on the DAC encoder object. 1010 * If we got analog DDC or load detection passes on the DAC encoder 1011 * we have to check if this analog encoder is shared with anyone else (TV) 1012 * if its shared we have to set the other connector to disconnected. 1013 */ 1014 static enum drm_connector_status 1015 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 1016 { 1017 struct drm_device *dev = connector->dev; 1018 struct amdgpu_device *adev = drm_to_adev(dev); 1019 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1020 const struct drm_encoder_helper_funcs *encoder_funcs; 1021 int r; 1022 enum drm_connector_status ret = connector_status_disconnected; 1023 bool dret = false, broken_edid = false; 1024 1025 if (!drm_kms_helper_is_poll_worker()) { 1026 r = pm_runtime_get_sync(connector->dev->dev); 1027 if (r < 0) { 1028 pm_runtime_put_autosuspend(connector->dev->dev); 1029 return connector_status_disconnected; 1030 } 1031 } 1032 1033 if (amdgpu_connector->detected_hpd_without_ddc) { 1034 force = true; 1035 amdgpu_connector->detected_hpd_without_ddc = false; 1036 } 1037 1038 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1039 ret = connector->status; 1040 goto exit; 1041 } 1042 1043 if (amdgpu_connector->ddc_bus) { 1044 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 1045 1046 /* Sometimes the pins required for the DDC probe on DVI 1047 * connectors don't make contact at the same time that the ones 1048 * for HPD do. If the DDC probe fails even though we had an HPD 1049 * signal, try again later 1050 */ 1051 if (!dret && !force && 1052 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1053 DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n"); 1054 amdgpu_connector->detected_hpd_without_ddc = true; 1055 schedule_delayed_work(&adev->hotplug_work, 1056 msecs_to_jiffies(1000)); 1057 goto exit; 1058 } 1059 } 1060 if (dret) { 1061 amdgpu_connector->detected_by_load = false; 1062 amdgpu_connector_free_edid(connector); 1063 amdgpu_connector_get_edid(connector); 1064 1065 if (!amdgpu_connector->edid) { 1066 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1067 connector->name); 1068 ret = connector_status_connected; 1069 broken_edid = true; /* defer use_digital to later */ 1070 } else { 1071 amdgpu_connector->use_digital = 1072 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1073 1074 /* some oems have boards with separate digital and analog connectors 1075 * with a shared ddc line (often vga + hdmi) 1076 */ 1077 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1078 amdgpu_connector_free_edid(connector); 1079 ret = connector_status_disconnected; 1080 } else { 1081 ret = connector_status_connected; 1082 } 1083 1084 /* This gets complicated. We have boards with VGA + HDMI with a 1085 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1086 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1087 * you don't really know what's connected to which port as both are digital. 1088 */ 1089 amdgpu_connector_shared_ddc(&ret, connector, amdgpu_connector); 1090 } 1091 } 1092 1093 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1094 goto out; 1095 1096 /* DVI-D and HDMI-A are digital only */ 1097 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1098 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1099 goto out; 1100 1101 /* if we aren't forcing don't do destructive polling */ 1102 if (!force) { 1103 /* only return the previous status if we last 1104 * detected a monitor via load. 1105 */ 1106 if (amdgpu_connector->detected_by_load) 1107 ret = connector->status; 1108 goto out; 1109 } 1110 1111 /* find analog encoder */ 1112 if (amdgpu_connector->dac_load_detect) { 1113 struct drm_encoder *encoder; 1114 1115 drm_connector_for_each_possible_encoder(connector, encoder) { 1116 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1117 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1118 continue; 1119 1120 encoder_funcs = encoder->helper_private; 1121 if (encoder_funcs->detect) { 1122 if (!broken_edid) { 1123 if (ret != connector_status_connected) { 1124 /* deal with analog monitors without DDC */ 1125 ret = encoder_funcs->detect(encoder, connector); 1126 if (ret == connector_status_connected) { 1127 amdgpu_connector->use_digital = false; 1128 } 1129 if (ret != connector_status_disconnected) 1130 amdgpu_connector->detected_by_load = true; 1131 } 1132 } else { 1133 enum drm_connector_status lret; 1134 /* assume digital unless load detected otherwise */ 1135 amdgpu_connector->use_digital = true; 1136 lret = encoder_funcs->detect(encoder, connector); 1137 DRM_DEBUG_KMS("load_detect %x returned: %x\n", 1138 encoder->encoder_type, lret); 1139 if (lret == connector_status_connected) 1140 amdgpu_connector->use_digital = false; 1141 } 1142 break; 1143 } 1144 } 1145 } 1146 1147 out: 1148 /* updated in get modes as well since we need to know if it's analog or digital */ 1149 amdgpu_connector_update_scratch_regs(connector, ret); 1150 1151 exit: 1152 if (!drm_kms_helper_is_poll_worker()) { 1153 pm_runtime_mark_last_busy(connector->dev->dev); 1154 pm_runtime_put_autosuspend(connector->dev->dev); 1155 } 1156 1157 return ret; 1158 } 1159 1160 /* okay need to be smart in here about which encoder to pick */ 1161 static struct drm_encoder * 1162 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1163 { 1164 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1165 struct drm_encoder *encoder; 1166 1167 drm_connector_for_each_possible_encoder(connector, encoder) { 1168 if (amdgpu_connector->use_digital == true) { 1169 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1170 return encoder; 1171 } else { 1172 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1173 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1174 return encoder; 1175 } 1176 } 1177 1178 /* see if we have a default encoder TODO */ 1179 1180 /* then check use digitial */ 1181 /* pick the first one */ 1182 drm_connector_for_each_possible_encoder(connector, encoder) 1183 return encoder; 1184 1185 return NULL; 1186 } 1187 1188 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1189 { 1190 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1191 1192 if (connector->force == DRM_FORCE_ON) 1193 amdgpu_connector->use_digital = false; 1194 if (connector->force == DRM_FORCE_ON_DIGITAL) 1195 amdgpu_connector->use_digital = true; 1196 } 1197 1198 /** 1199 * Returns the maximum supported HDMI (TMDS) pixel clock in KHz. 1200 */ 1201 static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev) 1202 { 1203 if (adev->asic_type >= CHIP_POLARIS10) 1204 return 600000; 1205 else if (adev->asic_type >= CHIP_TONGA) 1206 return 300000; 1207 else 1208 return 297000; 1209 } 1210 1211 /** 1212 * Validates the given display mode on DVI and HDMI connectors, 1213 * including analog signals on DVI-I. 1214 */ 1215 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1216 const struct drm_display_mode *mode) 1217 { 1218 struct drm_device *dev = connector->dev; 1219 struct amdgpu_device *adev = drm_to_adev(dev); 1220 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1221 const int max_hdmi_pixel_clock = amdgpu_max_hdmi_pixel_clock(adev); 1222 const int max_dvi_single_link_pixel_clock = 165000; 1223 int max_digital_pixel_clock_khz; 1224 1225 /* XXX check mode bandwidth */ 1226 1227 if (amdgpu_connector->use_digital) { 1228 switch (amdgpu_connector->connector_object_id) { 1229 case CONNECTOR_OBJECT_ID_HDMI_TYPE_A: 1230 max_digital_pixel_clock_khz = max_hdmi_pixel_clock; 1231 break; 1232 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I: 1233 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D: 1234 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock; 1235 break; 1236 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I: 1237 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D: 1238 case CONNECTOR_OBJECT_ID_HDMI_TYPE_B: 1239 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock * 2; 1240 break; 1241 } 1242 1243 /* When the display EDID claims that it's an HDMI display, 1244 * we use the HDMI encoder mode of the display HW, 1245 * so we should verify against the max HDMI clock here. 1246 */ 1247 if (connector->display_info.is_hdmi) 1248 max_digital_pixel_clock_khz = max_hdmi_pixel_clock; 1249 1250 if (mode->clock > max_digital_pixel_clock_khz) 1251 return MODE_CLOCK_HIGH; 1252 } 1253 1254 /* check against the max pixel clock */ 1255 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1256 return MODE_CLOCK_HIGH; 1257 1258 return MODE_OK; 1259 } 1260 1261 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1262 .get_modes = amdgpu_connector_vga_get_modes, 1263 .mode_valid = amdgpu_connector_dvi_mode_valid, 1264 .best_encoder = amdgpu_connector_dvi_encoder, 1265 }; 1266 1267 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1268 .dpms = drm_helper_connector_dpms, 1269 .detect = amdgpu_connector_dvi_detect, 1270 .fill_modes = drm_helper_probe_single_connector_modes, 1271 .set_property = amdgpu_connector_set_property, 1272 .early_unregister = amdgpu_connector_unregister, 1273 .destroy = amdgpu_connector_destroy, 1274 .force = amdgpu_connector_dvi_force, 1275 }; 1276 1277 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1278 { 1279 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1280 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1281 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1282 int ret; 1283 1284 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1285 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1286 struct drm_display_mode *mode; 1287 1288 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1289 if (!amdgpu_dig_connector->edp_on) 1290 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1291 ATOM_TRANSMITTER_ACTION_POWER_ON); 1292 amdgpu_connector_get_edid(connector); 1293 ret = amdgpu_connector_ddc_get_modes(connector); 1294 if (!amdgpu_dig_connector->edp_on) 1295 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1296 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1297 } else { 1298 /* need to setup ddc on the bridge */ 1299 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1300 ENCODER_OBJECT_ID_NONE) { 1301 if (encoder) 1302 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1303 } 1304 amdgpu_connector_get_edid(connector); 1305 ret = amdgpu_connector_ddc_get_modes(connector); 1306 } 1307 1308 if (ret > 0) { 1309 if (encoder) { 1310 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1311 /* add scaled modes */ 1312 amdgpu_connector_add_common_modes(encoder, connector); 1313 } 1314 return ret; 1315 } 1316 1317 if (!encoder) 1318 return 0; 1319 1320 /* we have no EDID modes */ 1321 mode = amdgpu_connector_lcd_native_mode(encoder); 1322 if (mode) { 1323 ret = 1; 1324 drm_mode_probed_add(connector, mode); 1325 /* add the width/height from vbios tables if available */ 1326 connector->display_info.width_mm = mode->width_mm; 1327 connector->display_info.height_mm = mode->height_mm; 1328 /* add scaled modes */ 1329 amdgpu_connector_add_common_modes(encoder, connector); 1330 } 1331 } else { 1332 /* need to setup ddc on the bridge */ 1333 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1334 ENCODER_OBJECT_ID_NONE) { 1335 if (encoder) 1336 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1337 } 1338 amdgpu_connector_get_edid(connector); 1339 ret = amdgpu_connector_ddc_get_modes(connector); 1340 1341 amdgpu_get_native_mode(connector); 1342 } 1343 1344 return ret; 1345 } 1346 1347 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1348 { 1349 struct drm_encoder *encoder; 1350 struct amdgpu_encoder *amdgpu_encoder; 1351 1352 drm_connector_for_each_possible_encoder(connector, encoder) { 1353 amdgpu_encoder = to_amdgpu_encoder(encoder); 1354 1355 switch (amdgpu_encoder->encoder_id) { 1356 case ENCODER_OBJECT_ID_TRAVIS: 1357 case ENCODER_OBJECT_ID_NUTMEG: 1358 return amdgpu_encoder->encoder_id; 1359 default: 1360 break; 1361 } 1362 } 1363 1364 return ENCODER_OBJECT_ID_NONE; 1365 } 1366 1367 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1368 { 1369 struct drm_encoder *encoder; 1370 struct amdgpu_encoder *amdgpu_encoder; 1371 bool found = false; 1372 1373 drm_connector_for_each_possible_encoder(connector, encoder) { 1374 amdgpu_encoder = to_amdgpu_encoder(encoder); 1375 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1376 found = true; 1377 } 1378 1379 return found; 1380 } 1381 1382 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1383 { 1384 struct drm_device *dev = connector->dev; 1385 struct amdgpu_device *adev = drm_to_adev(dev); 1386 1387 if ((adev->clock.default_dispclk >= 53900) && 1388 amdgpu_connector_encoder_is_hbr2(connector)) { 1389 return true; 1390 } 1391 1392 return false; 1393 } 1394 1395 static enum drm_connector_status 1396 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1397 { 1398 struct drm_device *dev = connector->dev; 1399 struct amdgpu_device *adev = drm_to_adev(dev); 1400 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1401 enum drm_connector_status ret = connector_status_disconnected; 1402 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1403 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1404 int r; 1405 1406 if (!drm_kms_helper_is_poll_worker()) { 1407 r = pm_runtime_get_sync(connector->dev->dev); 1408 if (r < 0) { 1409 pm_runtime_put_autosuspend(connector->dev->dev); 1410 return connector_status_disconnected; 1411 } 1412 } 1413 1414 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1415 ret = connector->status; 1416 goto out; 1417 } 1418 1419 amdgpu_connector_free_edid(connector); 1420 1421 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1422 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1423 if (encoder) { 1424 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1425 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1426 1427 /* check if panel is valid */ 1428 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1429 ret = connector_status_connected; 1430 } 1431 /* eDP is always DP */ 1432 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1433 if (!amdgpu_dig_connector->edp_on) 1434 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1435 ATOM_TRANSMITTER_ACTION_POWER_ON); 1436 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1437 ret = connector_status_connected; 1438 if (!amdgpu_dig_connector->edp_on) 1439 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1440 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1441 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1442 ENCODER_OBJECT_ID_NONE) { 1443 /* DP bridges are always DP */ 1444 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1445 /* get the DPCD from the bridge */ 1446 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1447 1448 if (encoder) { 1449 /* setup ddc on the bridge */ 1450 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1451 /* bridge chips are always aux */ 1452 /* try DDC */ 1453 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1454 ret = connector_status_connected; 1455 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1456 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1457 1458 ret = encoder_funcs->detect(encoder, connector); 1459 } 1460 } 1461 } else { 1462 amdgpu_dig_connector->dp_sink_type = 1463 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1464 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1465 ret = connector_status_connected; 1466 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1467 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1468 } else { 1469 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1470 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1471 ret = connector_status_connected; 1472 } else { 1473 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1474 if (amdgpu_display_ddc_probe(amdgpu_connector, 1475 false)) 1476 ret = connector_status_connected; 1477 } 1478 } 1479 } 1480 1481 amdgpu_connector_update_scratch_regs(connector, ret); 1482 out: 1483 if (!drm_kms_helper_is_poll_worker()) { 1484 pm_runtime_mark_last_busy(connector->dev->dev); 1485 pm_runtime_put_autosuspend(connector->dev->dev); 1486 } 1487 1488 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1489 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 1490 drm_dp_set_subconnector_property(&amdgpu_connector->base, 1491 ret, 1492 amdgpu_dig_connector->dpcd, 1493 amdgpu_dig_connector->downstream_ports); 1494 return ret; 1495 } 1496 1497 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1498 const struct drm_display_mode *mode) 1499 { 1500 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1501 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1502 1503 /* XXX check mode bandwidth */ 1504 1505 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1506 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1507 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1508 1509 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1510 return MODE_PANEL; 1511 1512 if (encoder) { 1513 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1514 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1515 1516 /* AVIVO hardware supports downscaling modes larger than the panel 1517 * to the panel size, but I'm not sure this is desirable. 1518 */ 1519 if ((mode->hdisplay > native_mode->hdisplay) || 1520 (mode->vdisplay > native_mode->vdisplay)) 1521 return MODE_PANEL; 1522 1523 /* if scaling is disabled, block non-native modes */ 1524 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1525 if ((mode->hdisplay != native_mode->hdisplay) || 1526 (mode->vdisplay != native_mode->vdisplay)) 1527 return MODE_PANEL; 1528 } 1529 } 1530 return MODE_OK; 1531 } else { 1532 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1533 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1534 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1535 } else { 1536 if (connector->display_info.is_hdmi) { 1537 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1538 if (mode->clock > 340000) 1539 return MODE_CLOCK_HIGH; 1540 } else { 1541 if (mode->clock > 165000) 1542 return MODE_CLOCK_HIGH; 1543 } 1544 } 1545 } 1546 1547 return MODE_OK; 1548 } 1549 1550 static int 1551 amdgpu_connector_late_register(struct drm_connector *connector) 1552 { 1553 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1554 int r = 0; 1555 1556 if (amdgpu_connector->ddc_bus->has_aux) { 1557 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1558 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1559 } 1560 1561 return r; 1562 } 1563 1564 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1565 .get_modes = amdgpu_connector_dp_get_modes, 1566 .mode_valid = amdgpu_connector_dp_mode_valid, 1567 .best_encoder = amdgpu_connector_dvi_encoder, 1568 }; 1569 1570 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1571 .dpms = drm_helper_connector_dpms, 1572 .detect = amdgpu_connector_dp_detect, 1573 .fill_modes = drm_helper_probe_single_connector_modes, 1574 .set_property = amdgpu_connector_set_property, 1575 .early_unregister = amdgpu_connector_unregister, 1576 .destroy = amdgpu_connector_destroy, 1577 .force = amdgpu_connector_dvi_force, 1578 .late_register = amdgpu_connector_late_register, 1579 }; 1580 1581 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1582 .dpms = drm_helper_connector_dpms, 1583 .detect = amdgpu_connector_dp_detect, 1584 .fill_modes = drm_helper_probe_single_connector_modes, 1585 .set_property = amdgpu_connector_set_lcd_property, 1586 .early_unregister = amdgpu_connector_unregister, 1587 .destroy = amdgpu_connector_destroy, 1588 .force = amdgpu_connector_dvi_force, 1589 .late_register = amdgpu_connector_late_register, 1590 }; 1591 1592 void 1593 amdgpu_connector_add(struct amdgpu_device *adev, 1594 uint32_t connector_id, 1595 uint32_t supported_device, 1596 int connector_type, 1597 struct amdgpu_i2c_bus_rec *i2c_bus, 1598 uint16_t connector_object_id, 1599 struct amdgpu_hpd *hpd, 1600 struct amdgpu_router *router) 1601 { 1602 struct drm_device *dev = adev_to_drm(adev); 1603 struct drm_connector *connector; 1604 struct drm_connector_list_iter iter; 1605 struct amdgpu_connector *amdgpu_connector; 1606 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1607 struct drm_encoder *encoder; 1608 struct amdgpu_encoder *amdgpu_encoder; 1609 struct i2c_adapter *ddc = NULL; 1610 uint32_t subpixel_order = SubPixelNone; 1611 bool shared_ddc = false; 1612 bool is_dp_bridge = false; 1613 bool has_aux = false; 1614 1615 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1616 return; 1617 1618 /* see if we already added it */ 1619 drm_connector_list_iter_begin(dev, &iter); 1620 drm_for_each_connector_iter(connector, &iter) { 1621 amdgpu_connector = to_amdgpu_connector(connector); 1622 if (amdgpu_connector->connector_id == connector_id) { 1623 amdgpu_connector->devices |= supported_device; 1624 drm_connector_list_iter_end(&iter); 1625 return; 1626 } 1627 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1628 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1629 amdgpu_connector->shared_ddc = true; 1630 shared_ddc = true; 1631 } 1632 if (amdgpu_connector->router_bus && router->ddc_valid && 1633 (amdgpu_connector->router.router_id == router->router_id)) { 1634 amdgpu_connector->shared_ddc = false; 1635 shared_ddc = false; 1636 } 1637 } 1638 } 1639 drm_connector_list_iter_end(&iter); 1640 1641 /* check if it's a dp bridge */ 1642 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1643 amdgpu_encoder = to_amdgpu_encoder(encoder); 1644 if (amdgpu_encoder->devices & supported_device) { 1645 switch (amdgpu_encoder->encoder_id) { 1646 case ENCODER_OBJECT_ID_TRAVIS: 1647 case ENCODER_OBJECT_ID_NUTMEG: 1648 is_dp_bridge = true; 1649 break; 1650 default: 1651 break; 1652 } 1653 } 1654 } 1655 1656 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1657 if (!amdgpu_connector) 1658 return; 1659 1660 connector = &amdgpu_connector->base; 1661 1662 amdgpu_connector->connector_id = connector_id; 1663 amdgpu_connector->devices = supported_device; 1664 amdgpu_connector->shared_ddc = shared_ddc; 1665 amdgpu_connector->connector_object_id = connector_object_id; 1666 amdgpu_connector->hpd = *hpd; 1667 1668 amdgpu_connector->router = *router; 1669 if (router->ddc_valid || router->cd_valid) { 1670 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1671 if (!amdgpu_connector->router_bus) 1672 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1673 } 1674 1675 if (is_dp_bridge) { 1676 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1677 if (!amdgpu_dig_connector) 1678 goto failed; 1679 amdgpu_connector->con_priv = amdgpu_dig_connector; 1680 if (i2c_bus->valid) { 1681 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1682 if (amdgpu_connector->ddc_bus) { 1683 has_aux = true; 1684 ddc = &amdgpu_connector->ddc_bus->adapter; 1685 } else { 1686 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1687 } 1688 } 1689 switch (connector_type) { 1690 case DRM_MODE_CONNECTOR_VGA: 1691 case DRM_MODE_CONNECTOR_DVIA: 1692 default: 1693 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1694 &amdgpu_connector_dp_funcs, 1695 connector_type, 1696 ddc); 1697 drm_connector_helper_add(&amdgpu_connector->base, 1698 &amdgpu_connector_dp_helper_funcs); 1699 connector->interlace_allowed = true; 1700 connector->doublescan_allowed = true; 1701 amdgpu_connector->dac_load_detect = true; 1702 drm_object_attach_property(&amdgpu_connector->base.base, 1703 adev->mode_info.load_detect_property, 1704 1); 1705 drm_object_attach_property(&amdgpu_connector->base.base, 1706 dev->mode_config.scaling_mode_property, 1707 DRM_MODE_SCALE_NONE); 1708 break; 1709 case DRM_MODE_CONNECTOR_DVII: 1710 case DRM_MODE_CONNECTOR_DVID: 1711 case DRM_MODE_CONNECTOR_HDMIA: 1712 case DRM_MODE_CONNECTOR_HDMIB: 1713 case DRM_MODE_CONNECTOR_DisplayPort: 1714 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1715 &amdgpu_connector_dp_funcs, 1716 connector_type, 1717 ddc); 1718 drm_connector_helper_add(&amdgpu_connector->base, 1719 &amdgpu_connector_dp_helper_funcs); 1720 drm_object_attach_property(&amdgpu_connector->base.base, 1721 adev->mode_info.underscan_property, 1722 UNDERSCAN_OFF); 1723 drm_object_attach_property(&amdgpu_connector->base.base, 1724 adev->mode_info.underscan_hborder_property, 1725 0); 1726 drm_object_attach_property(&amdgpu_connector->base.base, 1727 adev->mode_info.underscan_vborder_property, 1728 0); 1729 1730 drm_object_attach_property(&amdgpu_connector->base.base, 1731 dev->mode_config.scaling_mode_property, 1732 DRM_MODE_SCALE_NONE); 1733 1734 drm_object_attach_property(&amdgpu_connector->base.base, 1735 adev->mode_info.dither_property, 1736 AMDGPU_FMT_DITHER_DISABLE); 1737 1738 if (amdgpu_audio != 0) { 1739 drm_object_attach_property(&amdgpu_connector->base.base, 1740 adev->mode_info.audio_property, 1741 AMDGPU_AUDIO_AUTO); 1742 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1743 } 1744 1745 subpixel_order = SubPixelHorizontalRGB; 1746 connector->interlace_allowed = true; 1747 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1748 connector->doublescan_allowed = true; 1749 else 1750 connector->doublescan_allowed = false; 1751 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1752 amdgpu_connector->dac_load_detect = true; 1753 drm_object_attach_property(&amdgpu_connector->base.base, 1754 adev->mode_info.load_detect_property, 1755 1); 1756 } 1757 break; 1758 case DRM_MODE_CONNECTOR_LVDS: 1759 case DRM_MODE_CONNECTOR_eDP: 1760 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1761 &amdgpu_connector_edp_funcs, 1762 connector_type, 1763 ddc); 1764 drm_connector_helper_add(&amdgpu_connector->base, 1765 &amdgpu_connector_dp_helper_funcs); 1766 drm_object_attach_property(&amdgpu_connector->base.base, 1767 dev->mode_config.scaling_mode_property, 1768 DRM_MODE_SCALE_FULLSCREEN); 1769 subpixel_order = SubPixelHorizontalRGB; 1770 connector->interlace_allowed = false; 1771 connector->doublescan_allowed = false; 1772 break; 1773 } 1774 } else { 1775 switch (connector_type) { 1776 case DRM_MODE_CONNECTOR_VGA: 1777 if (i2c_bus->valid) { 1778 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1779 if (!amdgpu_connector->ddc_bus) 1780 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1781 else 1782 ddc = &amdgpu_connector->ddc_bus->adapter; 1783 } 1784 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1785 &amdgpu_connector_vga_funcs, 1786 connector_type, 1787 ddc); 1788 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1789 amdgpu_connector->dac_load_detect = true; 1790 drm_object_attach_property(&amdgpu_connector->base.base, 1791 adev->mode_info.load_detect_property, 1792 1); 1793 drm_object_attach_property(&amdgpu_connector->base.base, 1794 dev->mode_config.scaling_mode_property, 1795 DRM_MODE_SCALE_NONE); 1796 /* no HPD on analog connectors */ 1797 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1798 connector->interlace_allowed = true; 1799 connector->doublescan_allowed = true; 1800 break; 1801 case DRM_MODE_CONNECTOR_DVIA: 1802 if (i2c_bus->valid) { 1803 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1804 if (!amdgpu_connector->ddc_bus) 1805 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1806 else 1807 ddc = &amdgpu_connector->ddc_bus->adapter; 1808 } 1809 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1810 &amdgpu_connector_vga_funcs, 1811 connector_type, 1812 ddc); 1813 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1814 amdgpu_connector->dac_load_detect = true; 1815 drm_object_attach_property(&amdgpu_connector->base.base, 1816 adev->mode_info.load_detect_property, 1817 1); 1818 drm_object_attach_property(&amdgpu_connector->base.base, 1819 dev->mode_config.scaling_mode_property, 1820 DRM_MODE_SCALE_NONE); 1821 /* no HPD on analog connectors */ 1822 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1823 connector->interlace_allowed = true; 1824 connector->doublescan_allowed = true; 1825 break; 1826 case DRM_MODE_CONNECTOR_DVII: 1827 case DRM_MODE_CONNECTOR_DVID: 1828 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1829 if (!amdgpu_dig_connector) 1830 goto failed; 1831 amdgpu_connector->con_priv = amdgpu_dig_connector; 1832 if (i2c_bus->valid) { 1833 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1834 if (!amdgpu_connector->ddc_bus) 1835 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1836 else 1837 ddc = &amdgpu_connector->ddc_bus->adapter; 1838 } 1839 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1840 &amdgpu_connector_dvi_funcs, 1841 connector_type, 1842 ddc); 1843 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1844 subpixel_order = SubPixelHorizontalRGB; 1845 drm_object_attach_property(&amdgpu_connector->base.base, 1846 adev->mode_info.coherent_mode_property, 1847 1); 1848 drm_object_attach_property(&amdgpu_connector->base.base, 1849 adev->mode_info.underscan_property, 1850 UNDERSCAN_OFF); 1851 drm_object_attach_property(&amdgpu_connector->base.base, 1852 adev->mode_info.underscan_hborder_property, 1853 0); 1854 drm_object_attach_property(&amdgpu_connector->base.base, 1855 adev->mode_info.underscan_vborder_property, 1856 0); 1857 drm_object_attach_property(&amdgpu_connector->base.base, 1858 dev->mode_config.scaling_mode_property, 1859 DRM_MODE_SCALE_NONE); 1860 1861 if (amdgpu_audio != 0) { 1862 drm_object_attach_property(&amdgpu_connector->base.base, 1863 adev->mode_info.audio_property, 1864 AMDGPU_AUDIO_AUTO); 1865 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1866 } 1867 drm_object_attach_property(&amdgpu_connector->base.base, 1868 adev->mode_info.dither_property, 1869 AMDGPU_FMT_DITHER_DISABLE); 1870 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1871 amdgpu_connector->dac_load_detect = true; 1872 drm_object_attach_property(&amdgpu_connector->base.base, 1873 adev->mode_info.load_detect_property, 1874 1); 1875 } 1876 connector->interlace_allowed = true; 1877 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1878 connector->doublescan_allowed = true; 1879 else 1880 connector->doublescan_allowed = false; 1881 break; 1882 case DRM_MODE_CONNECTOR_HDMIA: 1883 case DRM_MODE_CONNECTOR_HDMIB: 1884 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1885 if (!amdgpu_dig_connector) 1886 goto failed; 1887 amdgpu_connector->con_priv = amdgpu_dig_connector; 1888 if (i2c_bus->valid) { 1889 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1890 if (!amdgpu_connector->ddc_bus) 1891 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1892 else 1893 ddc = &amdgpu_connector->ddc_bus->adapter; 1894 } 1895 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1896 &amdgpu_connector_dvi_funcs, 1897 connector_type, 1898 ddc); 1899 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1900 drm_object_attach_property(&amdgpu_connector->base.base, 1901 adev->mode_info.coherent_mode_property, 1902 1); 1903 drm_object_attach_property(&amdgpu_connector->base.base, 1904 adev->mode_info.underscan_property, 1905 UNDERSCAN_OFF); 1906 drm_object_attach_property(&amdgpu_connector->base.base, 1907 adev->mode_info.underscan_hborder_property, 1908 0); 1909 drm_object_attach_property(&amdgpu_connector->base.base, 1910 adev->mode_info.underscan_vborder_property, 1911 0); 1912 drm_object_attach_property(&amdgpu_connector->base.base, 1913 dev->mode_config.scaling_mode_property, 1914 DRM_MODE_SCALE_NONE); 1915 if (amdgpu_audio != 0) { 1916 drm_object_attach_property(&amdgpu_connector->base.base, 1917 adev->mode_info.audio_property, 1918 AMDGPU_AUDIO_AUTO); 1919 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1920 } 1921 drm_object_attach_property(&amdgpu_connector->base.base, 1922 adev->mode_info.dither_property, 1923 AMDGPU_FMT_DITHER_DISABLE); 1924 subpixel_order = SubPixelHorizontalRGB; 1925 connector->interlace_allowed = true; 1926 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1927 connector->doublescan_allowed = true; 1928 else 1929 connector->doublescan_allowed = false; 1930 break; 1931 case DRM_MODE_CONNECTOR_DisplayPort: 1932 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1933 if (!amdgpu_dig_connector) 1934 goto failed; 1935 amdgpu_connector->con_priv = amdgpu_dig_connector; 1936 if (i2c_bus->valid) { 1937 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1938 if (amdgpu_connector->ddc_bus) { 1939 has_aux = true; 1940 ddc = &amdgpu_connector->ddc_bus->adapter; 1941 } else { 1942 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1943 } 1944 } 1945 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1946 &amdgpu_connector_dp_funcs, 1947 connector_type, 1948 ddc); 1949 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1950 subpixel_order = SubPixelHorizontalRGB; 1951 drm_object_attach_property(&amdgpu_connector->base.base, 1952 adev->mode_info.coherent_mode_property, 1953 1); 1954 drm_object_attach_property(&amdgpu_connector->base.base, 1955 adev->mode_info.underscan_property, 1956 UNDERSCAN_OFF); 1957 drm_object_attach_property(&amdgpu_connector->base.base, 1958 adev->mode_info.underscan_hborder_property, 1959 0); 1960 drm_object_attach_property(&amdgpu_connector->base.base, 1961 adev->mode_info.underscan_vborder_property, 1962 0); 1963 drm_object_attach_property(&amdgpu_connector->base.base, 1964 dev->mode_config.scaling_mode_property, 1965 DRM_MODE_SCALE_NONE); 1966 if (amdgpu_audio != 0) { 1967 drm_object_attach_property(&amdgpu_connector->base.base, 1968 adev->mode_info.audio_property, 1969 AMDGPU_AUDIO_AUTO); 1970 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1971 } 1972 drm_object_attach_property(&amdgpu_connector->base.base, 1973 adev->mode_info.dither_property, 1974 AMDGPU_FMT_DITHER_DISABLE); 1975 connector->interlace_allowed = true; 1976 /* in theory with a DP to VGA converter... */ 1977 connector->doublescan_allowed = false; 1978 break; 1979 case DRM_MODE_CONNECTOR_eDP: 1980 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1981 if (!amdgpu_dig_connector) 1982 goto failed; 1983 amdgpu_connector->con_priv = amdgpu_dig_connector; 1984 if (i2c_bus->valid) { 1985 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1986 if (amdgpu_connector->ddc_bus) { 1987 has_aux = true; 1988 ddc = &amdgpu_connector->ddc_bus->adapter; 1989 } else { 1990 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1991 } 1992 } 1993 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1994 &amdgpu_connector_edp_funcs, 1995 connector_type, 1996 ddc); 1997 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1998 drm_object_attach_property(&amdgpu_connector->base.base, 1999 dev->mode_config.scaling_mode_property, 2000 DRM_MODE_SCALE_FULLSCREEN); 2001 subpixel_order = SubPixelHorizontalRGB; 2002 connector->interlace_allowed = false; 2003 connector->doublescan_allowed = false; 2004 break; 2005 case DRM_MODE_CONNECTOR_LVDS: 2006 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 2007 if (!amdgpu_dig_connector) 2008 goto failed; 2009 amdgpu_connector->con_priv = amdgpu_dig_connector; 2010 if (i2c_bus->valid) { 2011 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 2012 if (!amdgpu_connector->ddc_bus) 2013 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 2014 else 2015 ddc = &amdgpu_connector->ddc_bus->adapter; 2016 } 2017 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 2018 &amdgpu_connector_lvds_funcs, 2019 connector_type, 2020 ddc); 2021 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 2022 drm_object_attach_property(&amdgpu_connector->base.base, 2023 dev->mode_config.scaling_mode_property, 2024 DRM_MODE_SCALE_FULLSCREEN); 2025 subpixel_order = SubPixelHorizontalRGB; 2026 connector->interlace_allowed = false; 2027 connector->doublescan_allowed = false; 2028 break; 2029 } 2030 } 2031 2032 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 2033 if (i2c_bus->valid) { 2034 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 2035 DRM_CONNECTOR_POLL_DISCONNECT; 2036 } 2037 } else 2038 connector->polled = DRM_CONNECTOR_POLL_HPD; 2039 2040 connector->display_info.subpixel_order = subpixel_order; 2041 2042 if (has_aux) 2043 amdgpu_atombios_dp_aux_init(amdgpu_connector); 2044 2045 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2046 connector_type == DRM_MODE_CONNECTOR_eDP) { 2047 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base); 2048 } 2049 2050 return; 2051 2052 failed: 2053 drm_connector_cleanup(connector); 2054 kfree(connector); 2055 } 2056