1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_modeset_helper_vtables.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "atom.h" 35 #include "atombios_encoders.h" 36 #include "atombios_dp.h" 37 #include "amdgpu_connectors.h" 38 #include "amdgpu_i2c.h" 39 #include "amdgpu_display.h" 40 41 #include <linux/pm_runtime.h> 42 43 void amdgpu_connector_hotplug(struct drm_connector *connector) 44 { 45 struct drm_device *dev = connector->dev; 46 struct amdgpu_device *adev = drm_to_adev(dev); 47 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 48 49 /* bail if the connector does not have hpd pin, e.g., 50 * VGA, TV, etc. 51 */ 52 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 53 return; 54 55 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 56 57 /* if the connector is already off, don't turn it back on */ 58 if (connector->dpms != DRM_MODE_DPMS_ON) 59 return; 60 61 /* just deal with DP (not eDP) here. */ 62 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 63 struct amdgpu_connector_atom_dig *dig_connector = 64 amdgpu_connector->con_priv; 65 66 /* if existing sink type was not DP no need to retrain */ 67 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 68 return; 69 70 /* first get sink type as it may be reset after (un)plug */ 71 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 72 /* don't do anything if sink is not display port, i.e., 73 * passive dp->(dvi|hdmi) adaptor 74 */ 75 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 76 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 77 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 /* Don't start link training before we have the DPCD */ 79 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 80 return; 81 82 /* Turn the connector off and back on immediately, which 83 * will trigger link training 84 */ 85 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 86 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 87 } 88 } 89 } 90 91 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 92 { 93 struct drm_crtc *crtc = encoder->crtc; 94 95 if (crtc && crtc->enabled) { 96 drm_crtc_helper_set_mode(crtc, &crtc->mode, 97 crtc->x, crtc->y, crtc->primary->fb); 98 } 99 } 100 101 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 102 { 103 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 104 struct amdgpu_connector_atom_dig *dig_connector; 105 int bpc = 8; 106 unsigned int mode_clock, max_tmds_clock; 107 108 switch (connector->connector_type) { 109 case DRM_MODE_CONNECTOR_DVII: 110 case DRM_MODE_CONNECTOR_HDMIB: 111 if (amdgpu_connector->use_digital) { 112 if (connector->display_info.is_hdmi) { 113 if (connector->display_info.bpc) 114 bpc = connector->display_info.bpc; 115 } 116 } 117 break; 118 case DRM_MODE_CONNECTOR_DVID: 119 case DRM_MODE_CONNECTOR_HDMIA: 120 if (connector->display_info.is_hdmi) { 121 if (connector->display_info.bpc) 122 bpc = connector->display_info.bpc; 123 } 124 break; 125 case DRM_MODE_CONNECTOR_DisplayPort: 126 dig_connector = amdgpu_connector->con_priv; 127 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 128 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 129 connector->display_info.is_hdmi) { 130 if (connector->display_info.bpc) 131 bpc = connector->display_info.bpc; 132 } 133 break; 134 case DRM_MODE_CONNECTOR_eDP: 135 case DRM_MODE_CONNECTOR_LVDS: 136 if (connector->display_info.bpc) 137 bpc = connector->display_info.bpc; 138 else { 139 const struct drm_connector_helper_funcs *connector_funcs = 140 connector->helper_private; 141 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 142 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 143 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 144 145 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 146 bpc = 6; 147 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 148 bpc = 8; 149 } 150 break; 151 } 152 153 if (connector->display_info.is_hdmi) { 154 /* 155 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 156 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 157 * 12 bpc is always supported on hdmi deep color sinks, as this is 158 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 159 */ 160 if (bpc > 12) { 161 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 162 connector->name, bpc); 163 bpc = 12; 164 } 165 166 /* Any defined maximum tmds clock limit we must not exceed? */ 167 if (connector->display_info.max_tmds_clock > 0) { 168 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 169 mode_clock = amdgpu_connector->pixelclock_for_modeset; 170 171 /* Maximum allowable input clock in kHz */ 172 max_tmds_clock = connector->display_info.max_tmds_clock; 173 174 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 175 connector->name, mode_clock, max_tmds_clock); 176 177 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 178 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 179 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && 180 (mode_clock * 5/4 <= max_tmds_clock)) 181 bpc = 10; 182 else 183 bpc = 8; 184 185 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 186 connector->name, bpc); 187 } 188 189 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 190 bpc = 8; 191 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 192 connector->name, bpc); 193 } 194 } else if (bpc > 8) { 195 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 196 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 197 connector->name); 198 bpc = 8; 199 } 200 } 201 202 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 203 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 204 connector->name); 205 bpc = 8; 206 } 207 208 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 209 connector->name, connector->display_info.bpc, bpc); 210 211 return bpc; 212 } 213 214 static void 215 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 216 enum drm_connector_status status) 217 { 218 struct drm_encoder *best_encoder; 219 struct drm_encoder *encoder; 220 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 221 bool connected; 222 223 best_encoder = connector_funcs->best_encoder(connector); 224 225 drm_connector_for_each_possible_encoder(connector, encoder) { 226 if ((encoder == best_encoder) && (status == connector_status_connected)) 227 connected = true; 228 else 229 connected = false; 230 231 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 232 } 233 } 234 235 static struct drm_encoder * 236 amdgpu_connector_find_encoder(struct drm_connector *connector, 237 int encoder_type) 238 { 239 struct drm_encoder *encoder; 240 241 drm_connector_for_each_possible_encoder(connector, encoder) { 242 if (encoder->encoder_type == encoder_type) 243 return encoder; 244 } 245 246 return NULL; 247 } 248 249 static struct edid * 250 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 251 { 252 return drm_edid_duplicate(drm_edid_raw(adev->mode_info.bios_hardcoded_edid)); 253 } 254 255 static void amdgpu_connector_get_edid(struct drm_connector *connector) 256 { 257 struct drm_device *dev = connector->dev; 258 struct amdgpu_device *adev = drm_to_adev(dev); 259 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 260 261 if (amdgpu_connector->edid) 262 return; 263 264 /* on hw with routers, select right port */ 265 if (amdgpu_connector->router.ddc_valid) 266 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 267 268 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 269 ENCODER_OBJECT_ID_NONE) && 270 amdgpu_connector->ddc_bus->has_aux) { 271 amdgpu_connector->edid = drm_get_edid(connector, 272 &amdgpu_connector->ddc_bus->aux.ddc); 273 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 274 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 275 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 276 277 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 278 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 279 amdgpu_connector->ddc_bus->has_aux) 280 amdgpu_connector->edid = drm_get_edid(connector, 281 &amdgpu_connector->ddc_bus->aux.ddc); 282 else if (amdgpu_connector->ddc_bus) 283 amdgpu_connector->edid = drm_get_edid(connector, 284 &amdgpu_connector->ddc_bus->adapter); 285 } else if (amdgpu_connector->ddc_bus) { 286 amdgpu_connector->edid = drm_get_edid(connector, 287 &amdgpu_connector->ddc_bus->adapter); 288 } 289 290 if (!amdgpu_connector->edid) { 291 /* some laptops provide a hardcoded edid in rom for LCDs */ 292 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 293 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { 294 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 295 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 296 } 297 } 298 } 299 300 static void amdgpu_connector_free_edid(struct drm_connector *connector) 301 { 302 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 303 304 kfree(amdgpu_connector->edid); 305 amdgpu_connector->edid = NULL; 306 } 307 308 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 309 { 310 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 311 int ret; 312 313 if (amdgpu_connector->edid) { 314 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 315 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 316 return ret; 317 } 318 drm_connector_update_edid_property(connector, NULL); 319 return 0; 320 } 321 322 static struct drm_encoder * 323 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 324 { 325 struct drm_encoder *encoder; 326 327 /* pick the first one */ 328 drm_connector_for_each_possible_encoder(connector, encoder) 329 return encoder; 330 331 return NULL; 332 } 333 334 static void amdgpu_get_native_mode(struct drm_connector *connector) 335 { 336 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 337 struct amdgpu_encoder *amdgpu_encoder; 338 339 if (encoder == NULL) 340 return; 341 342 amdgpu_encoder = to_amdgpu_encoder(encoder); 343 344 if (!list_empty(&connector->probed_modes)) { 345 struct drm_display_mode *preferred_mode = 346 list_first_entry(&connector->probed_modes, 347 struct drm_display_mode, head); 348 349 amdgpu_encoder->native_mode = *preferred_mode; 350 } else { 351 amdgpu_encoder->native_mode.clock = 0; 352 } 353 } 354 355 static struct drm_display_mode * 356 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 357 { 358 struct drm_device *dev = encoder->dev; 359 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 360 struct drm_display_mode *mode = NULL; 361 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 362 363 if (native_mode->hdisplay != 0 && 364 native_mode->vdisplay != 0 && 365 native_mode->clock != 0) { 366 mode = drm_mode_duplicate(dev, native_mode); 367 if (!mode) 368 return NULL; 369 370 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 371 drm_mode_set_name(mode); 372 373 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 374 } else if (native_mode->hdisplay != 0 && 375 native_mode->vdisplay != 0) { 376 /* mac laptops without an edid */ 377 /* Note that this is not necessarily the exact panel mode, 378 * but an approximation based on the cvt formula. For these 379 * systems we should ideally read the mode info out of the 380 * registers or add a mode table, but this works and is much 381 * simpler. 382 */ 383 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 384 if (!mode) 385 return NULL; 386 387 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 388 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 389 } 390 return mode; 391 } 392 393 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 394 struct drm_connector *connector) 395 { 396 struct drm_device *dev = encoder->dev; 397 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 398 struct drm_display_mode *mode = NULL; 399 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 400 int i; 401 static const struct mode_size { 402 int w; 403 int h; 404 } common_modes[17] = { 405 { 640, 480}, 406 { 720, 480}, 407 { 800, 600}, 408 { 848, 480}, 409 {1024, 768}, 410 {1152, 768}, 411 {1280, 720}, 412 {1280, 800}, 413 {1280, 854}, 414 {1280, 960}, 415 {1280, 1024}, 416 {1440, 900}, 417 {1400, 1050}, 418 {1680, 1050}, 419 {1600, 1200}, 420 {1920, 1080}, 421 {1920, 1200} 422 }; 423 424 for (i = 0; i < 17; i++) { 425 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 426 if (common_modes[i].w > 1024 || 427 common_modes[i].h > 768) 428 continue; 429 } 430 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 431 if (common_modes[i].w > native_mode->hdisplay || 432 common_modes[i].h > native_mode->vdisplay || 433 (common_modes[i].w == native_mode->hdisplay && 434 common_modes[i].h == native_mode->vdisplay)) 435 continue; 436 } 437 438 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 439 if (!mode) 440 return; 441 442 drm_mode_probed_add(connector, mode); 443 } 444 } 445 446 static int amdgpu_connector_set_property(struct drm_connector *connector, 447 struct drm_property *property, 448 uint64_t val) 449 { 450 struct drm_device *dev = connector->dev; 451 struct amdgpu_device *adev = drm_to_adev(dev); 452 struct drm_encoder *encoder; 453 struct amdgpu_encoder *amdgpu_encoder; 454 455 if (property == adev->mode_info.coherent_mode_property) { 456 struct amdgpu_encoder_atom_dig *dig; 457 bool new_coherent_mode; 458 459 /* need to find digital encoder on connector */ 460 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 461 if (!encoder) 462 return 0; 463 464 amdgpu_encoder = to_amdgpu_encoder(encoder); 465 466 if (!amdgpu_encoder->enc_priv) 467 return 0; 468 469 dig = amdgpu_encoder->enc_priv; 470 new_coherent_mode = val ? true : false; 471 if (dig->coherent_mode != new_coherent_mode) { 472 dig->coherent_mode = new_coherent_mode; 473 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 474 } 475 } 476 477 if (property == adev->mode_info.audio_property) { 478 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 479 /* need to find digital encoder on connector */ 480 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 481 if (!encoder) 482 return 0; 483 484 amdgpu_encoder = to_amdgpu_encoder(encoder); 485 486 if (amdgpu_connector->audio != val) { 487 amdgpu_connector->audio = val; 488 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 489 } 490 } 491 492 if (property == adev->mode_info.dither_property) { 493 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 494 /* need to find digital encoder on connector */ 495 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 496 if (!encoder) 497 return 0; 498 499 amdgpu_encoder = to_amdgpu_encoder(encoder); 500 501 if (amdgpu_connector->dither != val) { 502 amdgpu_connector->dither = val; 503 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 504 } 505 } 506 507 if (property == adev->mode_info.underscan_property) { 508 /* need to find digital encoder on connector */ 509 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 510 if (!encoder) 511 return 0; 512 513 amdgpu_encoder = to_amdgpu_encoder(encoder); 514 515 if (amdgpu_encoder->underscan_type != val) { 516 amdgpu_encoder->underscan_type = val; 517 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 518 } 519 } 520 521 if (property == adev->mode_info.underscan_hborder_property) { 522 /* need to find digital encoder on connector */ 523 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 524 if (!encoder) 525 return 0; 526 527 amdgpu_encoder = to_amdgpu_encoder(encoder); 528 529 if (amdgpu_encoder->underscan_hborder != val) { 530 amdgpu_encoder->underscan_hborder = val; 531 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 532 } 533 } 534 535 if (property == adev->mode_info.underscan_vborder_property) { 536 /* need to find digital encoder on connector */ 537 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 538 if (!encoder) 539 return 0; 540 541 amdgpu_encoder = to_amdgpu_encoder(encoder); 542 543 if (amdgpu_encoder->underscan_vborder != val) { 544 amdgpu_encoder->underscan_vborder = val; 545 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 546 } 547 } 548 549 if (property == adev->mode_info.load_detect_property) { 550 struct amdgpu_connector *amdgpu_connector = 551 to_amdgpu_connector(connector); 552 553 if (val == 0) 554 amdgpu_connector->dac_load_detect = false; 555 else 556 amdgpu_connector->dac_load_detect = true; 557 } 558 559 if (property == dev->mode_config.scaling_mode_property) { 560 enum amdgpu_rmx_type rmx_type; 561 562 if (connector->encoder) { 563 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 564 } else { 565 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 566 567 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 568 } 569 570 switch (val) { 571 default: 572 case DRM_MODE_SCALE_NONE: 573 rmx_type = RMX_OFF; 574 break; 575 case DRM_MODE_SCALE_CENTER: 576 rmx_type = RMX_CENTER; 577 break; 578 case DRM_MODE_SCALE_ASPECT: 579 rmx_type = RMX_ASPECT; 580 break; 581 case DRM_MODE_SCALE_FULLSCREEN: 582 rmx_type = RMX_FULL; 583 break; 584 } 585 586 if (amdgpu_encoder->rmx_type == rmx_type) 587 return 0; 588 589 if ((rmx_type != DRM_MODE_SCALE_NONE) && 590 (amdgpu_encoder->native_mode.clock == 0)) 591 return 0; 592 593 amdgpu_encoder->rmx_type = rmx_type; 594 595 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 596 } 597 598 return 0; 599 } 600 601 static void 602 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 603 struct drm_connector *connector) 604 { 605 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 606 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 607 struct drm_display_mode *t, *mode; 608 609 /* If the EDID preferred mode doesn't match the native mode, use it */ 610 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 611 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 612 if (mode->hdisplay != native_mode->hdisplay || 613 mode->vdisplay != native_mode->vdisplay) 614 drm_mode_copy(native_mode, mode); 615 } 616 } 617 618 /* Try to get native mode details from EDID if necessary */ 619 if (!native_mode->clock) { 620 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 621 if (mode->hdisplay == native_mode->hdisplay && 622 mode->vdisplay == native_mode->vdisplay) { 623 drm_mode_copy(native_mode, mode); 624 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 625 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 626 break; 627 } 628 } 629 } 630 631 if (!native_mode->clock) { 632 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 633 amdgpu_encoder->rmx_type = RMX_OFF; 634 } 635 } 636 637 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 638 { 639 struct drm_encoder *encoder; 640 int ret = 0; 641 struct drm_display_mode *mode; 642 643 amdgpu_connector_get_edid(connector); 644 ret = amdgpu_connector_ddc_get_modes(connector); 645 if (ret > 0) { 646 encoder = amdgpu_connector_best_single_encoder(connector); 647 if (encoder) { 648 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 649 /* add scaled modes */ 650 amdgpu_connector_add_common_modes(encoder, connector); 651 } 652 return ret; 653 } 654 655 encoder = amdgpu_connector_best_single_encoder(connector); 656 if (!encoder) 657 return 0; 658 659 /* we have no EDID modes */ 660 mode = amdgpu_connector_lcd_native_mode(encoder); 661 if (mode) { 662 ret = 1; 663 drm_mode_probed_add(connector, mode); 664 /* add the width/height from vbios tables if available */ 665 connector->display_info.width_mm = mode->width_mm; 666 connector->display_info.height_mm = mode->height_mm; 667 /* add scaled modes */ 668 amdgpu_connector_add_common_modes(encoder, connector); 669 } 670 671 return ret; 672 } 673 674 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 675 const struct drm_display_mode *mode) 676 { 677 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 678 679 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 680 return MODE_PANEL; 681 682 if (encoder) { 683 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 684 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 685 686 /* AVIVO hardware supports downscaling modes larger than the panel 687 * to the panel size, but I'm not sure this is desirable. 688 */ 689 if ((mode->hdisplay > native_mode->hdisplay) || 690 (mode->vdisplay > native_mode->vdisplay)) 691 return MODE_PANEL; 692 693 /* if scaling is disabled, block non-native modes */ 694 if (amdgpu_encoder->rmx_type == RMX_OFF) { 695 if ((mode->hdisplay != native_mode->hdisplay) || 696 (mode->vdisplay != native_mode->vdisplay)) 697 return MODE_PANEL; 698 } 699 } 700 701 return MODE_OK; 702 } 703 704 static enum drm_connector_status 705 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 706 { 707 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 708 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 709 enum drm_connector_status ret = connector_status_disconnected; 710 int r; 711 712 if (!drm_kms_helper_is_poll_worker()) { 713 r = pm_runtime_get_sync(connector->dev->dev); 714 if (r < 0) { 715 pm_runtime_put_autosuspend(connector->dev->dev); 716 return connector_status_disconnected; 717 } 718 } 719 720 if (encoder) { 721 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 722 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 723 724 /* check if panel is valid */ 725 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 726 ret = connector_status_connected; 727 728 } 729 730 /* check for edid as well */ 731 amdgpu_connector_get_edid(connector); 732 if (amdgpu_connector->edid) 733 ret = connector_status_connected; 734 /* check acpi lid status ??? */ 735 736 amdgpu_connector_update_scratch_regs(connector, ret); 737 738 if (!drm_kms_helper_is_poll_worker()) { 739 pm_runtime_mark_last_busy(connector->dev->dev); 740 pm_runtime_put_autosuspend(connector->dev->dev); 741 } 742 743 return ret; 744 } 745 746 static void amdgpu_connector_unregister(struct drm_connector *connector) 747 { 748 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 749 750 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 751 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 752 amdgpu_connector->ddc_bus->has_aux = false; 753 } 754 } 755 756 static void amdgpu_connector_destroy(struct drm_connector *connector) 757 { 758 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 759 760 amdgpu_connector_free_edid(connector); 761 kfree(amdgpu_connector->con_priv); 762 drm_connector_unregister(connector); 763 drm_connector_cleanup(connector); 764 kfree(connector); 765 } 766 767 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 768 struct drm_property *property, 769 uint64_t value) 770 { 771 struct drm_device *dev = connector->dev; 772 struct amdgpu_encoder *amdgpu_encoder; 773 enum amdgpu_rmx_type rmx_type; 774 775 DRM_DEBUG_KMS("\n"); 776 if (property != dev->mode_config.scaling_mode_property) 777 return 0; 778 779 if (connector->encoder) 780 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 781 else { 782 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 783 784 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 785 } 786 787 switch (value) { 788 case DRM_MODE_SCALE_NONE: 789 rmx_type = RMX_OFF; 790 break; 791 case DRM_MODE_SCALE_CENTER: 792 rmx_type = RMX_CENTER; 793 break; 794 case DRM_MODE_SCALE_ASPECT: 795 rmx_type = RMX_ASPECT; 796 break; 797 default: 798 case DRM_MODE_SCALE_FULLSCREEN: 799 rmx_type = RMX_FULL; 800 break; 801 } 802 803 if (amdgpu_encoder->rmx_type == rmx_type) 804 return 0; 805 806 amdgpu_encoder->rmx_type = rmx_type; 807 808 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 809 return 0; 810 } 811 812 813 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 814 .get_modes = amdgpu_connector_lvds_get_modes, 815 .mode_valid = amdgpu_connector_lvds_mode_valid, 816 .best_encoder = amdgpu_connector_best_single_encoder, 817 }; 818 819 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 820 .dpms = drm_helper_connector_dpms, 821 .detect = amdgpu_connector_lvds_detect, 822 .fill_modes = drm_helper_probe_single_connector_modes, 823 .early_unregister = amdgpu_connector_unregister, 824 .destroy = amdgpu_connector_destroy, 825 .set_property = amdgpu_connector_set_lcd_property, 826 }; 827 828 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 829 { 830 int ret; 831 832 amdgpu_connector_get_edid(connector); 833 ret = amdgpu_connector_ddc_get_modes(connector); 834 amdgpu_get_native_mode(connector); 835 836 return ret; 837 } 838 839 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 840 const struct drm_display_mode *mode) 841 { 842 struct drm_device *dev = connector->dev; 843 struct amdgpu_device *adev = drm_to_adev(dev); 844 845 /* XXX check mode bandwidth */ 846 847 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 848 return MODE_CLOCK_HIGH; 849 850 return MODE_OK; 851 } 852 853 static enum drm_connector_status 854 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 855 { 856 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 857 struct drm_encoder *encoder; 858 const struct drm_encoder_helper_funcs *encoder_funcs; 859 bool dret = false; 860 enum drm_connector_status ret = connector_status_disconnected; 861 int r; 862 863 if (!drm_kms_helper_is_poll_worker()) { 864 r = pm_runtime_get_sync(connector->dev->dev); 865 if (r < 0) { 866 pm_runtime_put_autosuspend(connector->dev->dev); 867 return connector_status_disconnected; 868 } 869 } 870 871 encoder = amdgpu_connector_best_single_encoder(connector); 872 if (!encoder) 873 ret = connector_status_disconnected; 874 875 if (amdgpu_connector->ddc_bus) 876 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 877 if (dret) { 878 amdgpu_connector->detected_by_load = false; 879 amdgpu_connector_free_edid(connector); 880 amdgpu_connector_get_edid(connector); 881 882 if (!amdgpu_connector->edid) { 883 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 884 connector->name); 885 ret = connector_status_connected; 886 } else { 887 amdgpu_connector->use_digital = 888 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 889 890 /* some oems have boards with separate digital and analog connectors 891 * with a shared ddc line (often vga + hdmi) 892 */ 893 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 894 amdgpu_connector_free_edid(connector); 895 ret = connector_status_disconnected; 896 } else { 897 ret = connector_status_connected; 898 } 899 } 900 } else { 901 902 /* if we aren't forcing don't do destructive polling */ 903 if (!force) { 904 /* only return the previous status if we last 905 * detected a monitor via load. 906 */ 907 if (amdgpu_connector->detected_by_load) 908 ret = connector->status; 909 goto out; 910 } 911 912 if (amdgpu_connector->dac_load_detect && encoder) { 913 encoder_funcs = encoder->helper_private; 914 ret = encoder_funcs->detect(encoder, connector); 915 if (ret != connector_status_disconnected) 916 amdgpu_connector->detected_by_load = true; 917 } 918 } 919 920 amdgpu_connector_update_scratch_regs(connector, ret); 921 922 out: 923 if (!drm_kms_helper_is_poll_worker()) { 924 pm_runtime_mark_last_busy(connector->dev->dev); 925 pm_runtime_put_autosuspend(connector->dev->dev); 926 } 927 928 return ret; 929 } 930 931 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 932 .get_modes = amdgpu_connector_vga_get_modes, 933 .mode_valid = amdgpu_connector_vga_mode_valid, 934 .best_encoder = amdgpu_connector_best_single_encoder, 935 }; 936 937 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 938 .dpms = drm_helper_connector_dpms, 939 .detect = amdgpu_connector_vga_detect, 940 .fill_modes = drm_helper_probe_single_connector_modes, 941 .early_unregister = amdgpu_connector_unregister, 942 .destroy = amdgpu_connector_destroy, 943 .set_property = amdgpu_connector_set_property, 944 }; 945 946 static bool 947 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 948 { 949 struct drm_device *dev = connector->dev; 950 struct amdgpu_device *adev = drm_to_adev(dev); 951 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 952 enum drm_connector_status status; 953 954 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 955 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 956 status = connector_status_connected; 957 else 958 status = connector_status_disconnected; 959 if (connector->status == status) 960 return true; 961 } 962 963 return false; 964 } 965 966 static void amdgpu_connector_shared_ddc(enum drm_connector_status *status, 967 struct drm_connector *connector, 968 struct amdgpu_connector *amdgpu_connector) 969 { 970 struct drm_connector *list_connector; 971 struct drm_connector_list_iter iter; 972 struct amdgpu_connector *list_amdgpu_connector; 973 struct drm_device *dev = connector->dev; 974 struct amdgpu_device *adev = drm_to_adev(dev); 975 976 if (amdgpu_connector->shared_ddc && *status == connector_status_connected) { 977 drm_connector_list_iter_begin(dev, &iter); 978 drm_for_each_connector_iter(list_connector, 979 &iter) { 980 if (connector == list_connector) 981 continue; 982 list_amdgpu_connector = to_amdgpu_connector(list_connector); 983 if (list_amdgpu_connector->shared_ddc && 984 list_amdgpu_connector->ddc_bus->rec.i2c_id == 985 amdgpu_connector->ddc_bus->rec.i2c_id) { 986 /* cases where both connectors are digital */ 987 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 988 /* hpd is our only option in this case */ 989 if (!amdgpu_display_hpd_sense(adev, 990 amdgpu_connector->hpd.hpd)) { 991 amdgpu_connector_free_edid(connector); 992 *status = connector_status_disconnected; 993 } 994 } 995 } 996 } 997 drm_connector_list_iter_end(&iter); 998 } 999 } 1000 1001 /* 1002 * DVI is complicated 1003 * Do a DDC probe, if DDC probe passes, get the full EDID so 1004 * we can do analog/digital monitor detection at this point. 1005 * If the monitor is an analog monitor or we got no DDC, 1006 * we need to find the DAC encoder object for this connector. 1007 * If we got no DDC, we do load detection on the DAC encoder object. 1008 * If we got analog DDC or load detection passes on the DAC encoder 1009 * we have to check if this analog encoder is shared with anyone else (TV) 1010 * if its shared we have to set the other connector to disconnected. 1011 */ 1012 static enum drm_connector_status 1013 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 1014 { 1015 struct drm_device *dev = connector->dev; 1016 struct amdgpu_device *adev = drm_to_adev(dev); 1017 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1018 const struct drm_encoder_helper_funcs *encoder_funcs; 1019 int r; 1020 enum drm_connector_status ret = connector_status_disconnected; 1021 bool dret = false, broken_edid = false; 1022 1023 if (!drm_kms_helper_is_poll_worker()) { 1024 r = pm_runtime_get_sync(connector->dev->dev); 1025 if (r < 0) { 1026 pm_runtime_put_autosuspend(connector->dev->dev); 1027 return connector_status_disconnected; 1028 } 1029 } 1030 1031 if (amdgpu_connector->detected_hpd_without_ddc) { 1032 force = true; 1033 amdgpu_connector->detected_hpd_without_ddc = false; 1034 } 1035 1036 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1037 ret = connector->status; 1038 goto exit; 1039 } 1040 1041 if (amdgpu_connector->ddc_bus) { 1042 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 1043 1044 /* Sometimes the pins required for the DDC probe on DVI 1045 * connectors don't make contact at the same time that the ones 1046 * for HPD do. If the DDC probe fails even though we had an HPD 1047 * signal, try again later 1048 */ 1049 if (!dret && !force && 1050 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1051 DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n"); 1052 amdgpu_connector->detected_hpd_without_ddc = true; 1053 schedule_delayed_work(&adev->hotplug_work, 1054 msecs_to_jiffies(1000)); 1055 goto exit; 1056 } 1057 } 1058 if (dret) { 1059 amdgpu_connector->detected_by_load = false; 1060 amdgpu_connector_free_edid(connector); 1061 amdgpu_connector_get_edid(connector); 1062 1063 if (!amdgpu_connector->edid) { 1064 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1065 connector->name); 1066 ret = connector_status_connected; 1067 broken_edid = true; /* defer use_digital to later */ 1068 } else { 1069 amdgpu_connector->use_digital = 1070 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1071 1072 /* some oems have boards with separate digital and analog connectors 1073 * with a shared ddc line (often vga + hdmi) 1074 */ 1075 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1076 amdgpu_connector_free_edid(connector); 1077 ret = connector_status_disconnected; 1078 } else { 1079 ret = connector_status_connected; 1080 } 1081 1082 /* This gets complicated. We have boards with VGA + HDMI with a 1083 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1084 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1085 * you don't really know what's connected to which port as both are digital. 1086 */ 1087 amdgpu_connector_shared_ddc(&ret, connector, amdgpu_connector); 1088 } 1089 } 1090 1091 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1092 goto out; 1093 1094 /* DVI-D and HDMI-A are digital only */ 1095 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1096 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1097 goto out; 1098 1099 /* if we aren't forcing don't do destructive polling */ 1100 if (!force) { 1101 /* only return the previous status if we last 1102 * detected a monitor via load. 1103 */ 1104 if (amdgpu_connector->detected_by_load) 1105 ret = connector->status; 1106 goto out; 1107 } 1108 1109 /* find analog encoder */ 1110 if (amdgpu_connector->dac_load_detect) { 1111 struct drm_encoder *encoder; 1112 1113 drm_connector_for_each_possible_encoder(connector, encoder) { 1114 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1115 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1116 continue; 1117 1118 encoder_funcs = encoder->helper_private; 1119 if (encoder_funcs->detect) { 1120 if (!broken_edid) { 1121 if (ret != connector_status_connected) { 1122 /* deal with analog monitors without DDC */ 1123 ret = encoder_funcs->detect(encoder, connector); 1124 if (ret == connector_status_connected) { 1125 amdgpu_connector->use_digital = false; 1126 } 1127 if (ret != connector_status_disconnected) 1128 amdgpu_connector->detected_by_load = true; 1129 } 1130 } else { 1131 enum drm_connector_status lret; 1132 /* assume digital unless load detected otherwise */ 1133 amdgpu_connector->use_digital = true; 1134 lret = encoder_funcs->detect(encoder, connector); 1135 DRM_DEBUG_KMS("load_detect %x returned: %x\n", 1136 encoder->encoder_type, lret); 1137 if (lret == connector_status_connected) 1138 amdgpu_connector->use_digital = false; 1139 } 1140 break; 1141 } 1142 } 1143 } 1144 1145 out: 1146 /* updated in get modes as well since we need to know if it's analog or digital */ 1147 amdgpu_connector_update_scratch_regs(connector, ret); 1148 1149 exit: 1150 if (!drm_kms_helper_is_poll_worker()) { 1151 pm_runtime_mark_last_busy(connector->dev->dev); 1152 pm_runtime_put_autosuspend(connector->dev->dev); 1153 } 1154 1155 return ret; 1156 } 1157 1158 /* okay need to be smart in here about which encoder to pick */ 1159 static struct drm_encoder * 1160 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1161 { 1162 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1163 struct drm_encoder *encoder; 1164 1165 drm_connector_for_each_possible_encoder(connector, encoder) { 1166 if (amdgpu_connector->use_digital == true) { 1167 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1168 return encoder; 1169 } else { 1170 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1171 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1172 return encoder; 1173 } 1174 } 1175 1176 /* see if we have a default encoder TODO */ 1177 1178 /* then check use digitial */ 1179 /* pick the first one */ 1180 drm_connector_for_each_possible_encoder(connector, encoder) 1181 return encoder; 1182 1183 return NULL; 1184 } 1185 1186 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1187 { 1188 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1189 1190 if (connector->force == DRM_FORCE_ON) 1191 amdgpu_connector->use_digital = false; 1192 if (connector->force == DRM_FORCE_ON_DIGITAL) 1193 amdgpu_connector->use_digital = true; 1194 } 1195 1196 /** 1197 * amdgpu_max_hdmi_pixel_clock - Return max supported HDMI (TMDS) pixel clock 1198 * @adev: pointer to amdgpu_device 1199 * 1200 * Return: maximum supported HDMI (TMDS) pixel clock in KHz. 1201 */ 1202 static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev) 1203 { 1204 if (adev->asic_type >= CHIP_POLARIS10) 1205 return 600000; 1206 else if (adev->asic_type >= CHIP_TONGA) 1207 return 300000; 1208 else 1209 return 297000; 1210 } 1211 1212 /** 1213 * amdgpu_connector_dvi_mode_valid - Validate a mode on DVI/HDMI connectors 1214 * @connector: DRM connector to validate the mode on 1215 * @mode: display mode to validate 1216 * 1217 * Validate the given display mode on DVI and HDMI connectors, including 1218 * analog signals on DVI-I. 1219 * 1220 * Return: drm_mode_status indicating whether the mode is valid. 1221 */ 1222 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1223 const struct drm_display_mode *mode) 1224 { 1225 struct drm_device *dev = connector->dev; 1226 struct amdgpu_device *adev = drm_to_adev(dev); 1227 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1228 const int max_hdmi_pixel_clock = amdgpu_max_hdmi_pixel_clock(adev); 1229 const int max_dvi_single_link_pixel_clock = 165000; 1230 int max_digital_pixel_clock_khz; 1231 1232 /* XXX check mode bandwidth */ 1233 1234 if (amdgpu_connector->use_digital) { 1235 switch (amdgpu_connector->connector_object_id) { 1236 case CONNECTOR_OBJECT_ID_HDMI_TYPE_A: 1237 max_digital_pixel_clock_khz = max_hdmi_pixel_clock; 1238 break; 1239 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I: 1240 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D: 1241 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock; 1242 break; 1243 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I: 1244 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D: 1245 case CONNECTOR_OBJECT_ID_HDMI_TYPE_B: 1246 max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock * 2; 1247 break; 1248 } 1249 1250 /* When the display EDID claims that it's an HDMI display, 1251 * we use the HDMI encoder mode of the display HW, 1252 * so we should verify against the max HDMI clock here. 1253 */ 1254 if (connector->display_info.is_hdmi) 1255 max_digital_pixel_clock_khz = max_hdmi_pixel_clock; 1256 1257 if (mode->clock > max_digital_pixel_clock_khz) 1258 return MODE_CLOCK_HIGH; 1259 } 1260 1261 /* check against the max pixel clock */ 1262 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1263 return MODE_CLOCK_HIGH; 1264 1265 return MODE_OK; 1266 } 1267 1268 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1269 .get_modes = amdgpu_connector_vga_get_modes, 1270 .mode_valid = amdgpu_connector_dvi_mode_valid, 1271 .best_encoder = amdgpu_connector_dvi_encoder, 1272 }; 1273 1274 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1275 .dpms = drm_helper_connector_dpms, 1276 .detect = amdgpu_connector_dvi_detect, 1277 .fill_modes = drm_helper_probe_single_connector_modes, 1278 .set_property = amdgpu_connector_set_property, 1279 .early_unregister = amdgpu_connector_unregister, 1280 .destroy = amdgpu_connector_destroy, 1281 .force = amdgpu_connector_dvi_force, 1282 }; 1283 1284 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1285 { 1286 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1287 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1288 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1289 int ret; 1290 1291 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1292 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1293 struct drm_display_mode *mode; 1294 1295 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1296 if (!amdgpu_dig_connector->edp_on) 1297 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1298 ATOM_TRANSMITTER_ACTION_POWER_ON); 1299 amdgpu_connector_get_edid(connector); 1300 ret = amdgpu_connector_ddc_get_modes(connector); 1301 if (!amdgpu_dig_connector->edp_on) 1302 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1303 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1304 } else { 1305 /* need to setup ddc on the bridge */ 1306 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1307 ENCODER_OBJECT_ID_NONE) { 1308 if (encoder) 1309 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1310 } 1311 amdgpu_connector_get_edid(connector); 1312 ret = amdgpu_connector_ddc_get_modes(connector); 1313 } 1314 1315 if (ret > 0) { 1316 if (encoder) { 1317 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1318 /* add scaled modes */ 1319 amdgpu_connector_add_common_modes(encoder, connector); 1320 } 1321 return ret; 1322 } 1323 1324 if (!encoder) 1325 return 0; 1326 1327 /* we have no EDID modes */ 1328 mode = amdgpu_connector_lcd_native_mode(encoder); 1329 if (mode) { 1330 ret = 1; 1331 drm_mode_probed_add(connector, mode); 1332 /* add the width/height from vbios tables if available */ 1333 connector->display_info.width_mm = mode->width_mm; 1334 connector->display_info.height_mm = mode->height_mm; 1335 /* add scaled modes */ 1336 amdgpu_connector_add_common_modes(encoder, connector); 1337 } 1338 } else { 1339 /* need to setup ddc on the bridge */ 1340 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1341 ENCODER_OBJECT_ID_NONE) { 1342 if (encoder) 1343 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1344 } 1345 amdgpu_connector_get_edid(connector); 1346 ret = amdgpu_connector_ddc_get_modes(connector); 1347 1348 amdgpu_get_native_mode(connector); 1349 } 1350 1351 return ret; 1352 } 1353 1354 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1355 { 1356 struct drm_encoder *encoder; 1357 struct amdgpu_encoder *amdgpu_encoder; 1358 1359 drm_connector_for_each_possible_encoder(connector, encoder) { 1360 amdgpu_encoder = to_amdgpu_encoder(encoder); 1361 1362 switch (amdgpu_encoder->encoder_id) { 1363 case ENCODER_OBJECT_ID_TRAVIS: 1364 case ENCODER_OBJECT_ID_NUTMEG: 1365 return amdgpu_encoder->encoder_id; 1366 default: 1367 break; 1368 } 1369 } 1370 1371 return ENCODER_OBJECT_ID_NONE; 1372 } 1373 1374 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1375 { 1376 struct drm_encoder *encoder; 1377 struct amdgpu_encoder *amdgpu_encoder; 1378 bool found = false; 1379 1380 drm_connector_for_each_possible_encoder(connector, encoder) { 1381 amdgpu_encoder = to_amdgpu_encoder(encoder); 1382 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1383 found = true; 1384 } 1385 1386 return found; 1387 } 1388 1389 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1390 { 1391 struct drm_device *dev = connector->dev; 1392 struct amdgpu_device *adev = drm_to_adev(dev); 1393 1394 if ((adev->clock.default_dispclk >= 53900) && 1395 amdgpu_connector_encoder_is_hbr2(connector)) { 1396 return true; 1397 } 1398 1399 return false; 1400 } 1401 1402 static enum drm_connector_status 1403 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1404 { 1405 struct drm_device *dev = connector->dev; 1406 struct amdgpu_device *adev = drm_to_adev(dev); 1407 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1408 enum drm_connector_status ret = connector_status_disconnected; 1409 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1410 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1411 int r; 1412 1413 if (!drm_kms_helper_is_poll_worker()) { 1414 r = pm_runtime_get_sync(connector->dev->dev); 1415 if (r < 0) { 1416 pm_runtime_put_autosuspend(connector->dev->dev); 1417 return connector_status_disconnected; 1418 } 1419 } 1420 1421 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1422 ret = connector->status; 1423 goto out; 1424 } 1425 1426 amdgpu_connector_free_edid(connector); 1427 1428 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1429 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1430 if (encoder) { 1431 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1432 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1433 1434 /* check if panel is valid */ 1435 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1436 ret = connector_status_connected; 1437 } 1438 /* eDP is always DP */ 1439 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1440 if (!amdgpu_dig_connector->edp_on) 1441 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1442 ATOM_TRANSMITTER_ACTION_POWER_ON); 1443 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1444 ret = connector_status_connected; 1445 if (!amdgpu_dig_connector->edp_on) 1446 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1447 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1448 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1449 ENCODER_OBJECT_ID_NONE) { 1450 /* DP bridges are always DP */ 1451 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1452 /* get the DPCD from the bridge */ 1453 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1454 1455 if (encoder) { 1456 /* setup ddc on the bridge */ 1457 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1458 /* bridge chips are always aux */ 1459 /* try DDC */ 1460 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1461 ret = connector_status_connected; 1462 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1463 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1464 1465 ret = encoder_funcs->detect(encoder, connector); 1466 } 1467 } 1468 } else { 1469 amdgpu_dig_connector->dp_sink_type = 1470 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1471 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1472 ret = connector_status_connected; 1473 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1474 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1475 } else { 1476 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1477 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1478 ret = connector_status_connected; 1479 } else { 1480 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1481 if (amdgpu_display_ddc_probe(amdgpu_connector, 1482 false)) 1483 ret = connector_status_connected; 1484 } 1485 } 1486 } 1487 1488 amdgpu_connector_update_scratch_regs(connector, ret); 1489 out: 1490 if (!drm_kms_helper_is_poll_worker()) { 1491 pm_runtime_mark_last_busy(connector->dev->dev); 1492 pm_runtime_put_autosuspend(connector->dev->dev); 1493 } 1494 1495 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 1496 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 1497 drm_dp_set_subconnector_property(&amdgpu_connector->base, 1498 ret, 1499 amdgpu_dig_connector->dpcd, 1500 amdgpu_dig_connector->downstream_ports); 1501 return ret; 1502 } 1503 1504 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1505 const struct drm_display_mode *mode) 1506 { 1507 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1508 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1509 1510 /* XXX check mode bandwidth */ 1511 1512 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1513 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1514 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1515 1516 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1517 return MODE_PANEL; 1518 1519 if (encoder) { 1520 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1521 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1522 1523 /* AVIVO hardware supports downscaling modes larger than the panel 1524 * to the panel size, but I'm not sure this is desirable. 1525 */ 1526 if ((mode->hdisplay > native_mode->hdisplay) || 1527 (mode->vdisplay > native_mode->vdisplay)) 1528 return MODE_PANEL; 1529 1530 /* if scaling is disabled, block non-native modes */ 1531 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1532 if ((mode->hdisplay != native_mode->hdisplay) || 1533 (mode->vdisplay != native_mode->vdisplay)) 1534 return MODE_PANEL; 1535 } 1536 } 1537 return MODE_OK; 1538 } else { 1539 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1540 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1541 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1542 } else { 1543 if (connector->display_info.is_hdmi) { 1544 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1545 if (mode->clock > 340000) 1546 return MODE_CLOCK_HIGH; 1547 } else { 1548 if (mode->clock > 165000) 1549 return MODE_CLOCK_HIGH; 1550 } 1551 } 1552 } 1553 1554 return MODE_OK; 1555 } 1556 1557 static int 1558 amdgpu_connector_late_register(struct drm_connector *connector) 1559 { 1560 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1561 int r = 0; 1562 1563 if (amdgpu_connector->ddc_bus->has_aux) { 1564 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 1565 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 1566 } 1567 1568 return r; 1569 } 1570 1571 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1572 .get_modes = amdgpu_connector_dp_get_modes, 1573 .mode_valid = amdgpu_connector_dp_mode_valid, 1574 .best_encoder = amdgpu_connector_dvi_encoder, 1575 }; 1576 1577 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1578 .dpms = drm_helper_connector_dpms, 1579 .detect = amdgpu_connector_dp_detect, 1580 .fill_modes = drm_helper_probe_single_connector_modes, 1581 .set_property = amdgpu_connector_set_property, 1582 .early_unregister = amdgpu_connector_unregister, 1583 .destroy = amdgpu_connector_destroy, 1584 .force = amdgpu_connector_dvi_force, 1585 .late_register = amdgpu_connector_late_register, 1586 }; 1587 1588 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1589 .dpms = drm_helper_connector_dpms, 1590 .detect = amdgpu_connector_dp_detect, 1591 .fill_modes = drm_helper_probe_single_connector_modes, 1592 .set_property = amdgpu_connector_set_lcd_property, 1593 .early_unregister = amdgpu_connector_unregister, 1594 .destroy = amdgpu_connector_destroy, 1595 .force = amdgpu_connector_dvi_force, 1596 .late_register = amdgpu_connector_late_register, 1597 }; 1598 1599 void 1600 amdgpu_connector_add(struct amdgpu_device *adev, 1601 uint32_t connector_id, 1602 uint32_t supported_device, 1603 int connector_type, 1604 struct amdgpu_i2c_bus_rec *i2c_bus, 1605 uint16_t connector_object_id, 1606 struct amdgpu_hpd *hpd, 1607 struct amdgpu_router *router) 1608 { 1609 struct drm_device *dev = adev_to_drm(adev); 1610 struct drm_connector *connector; 1611 struct drm_connector_list_iter iter; 1612 struct amdgpu_connector *amdgpu_connector; 1613 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1614 struct drm_encoder *encoder; 1615 struct amdgpu_encoder *amdgpu_encoder; 1616 struct i2c_adapter *ddc = NULL; 1617 uint32_t subpixel_order = SubPixelNone; 1618 bool shared_ddc = false; 1619 bool is_dp_bridge = false; 1620 bool has_aux = false; 1621 1622 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1623 return; 1624 1625 /* see if we already added it */ 1626 drm_connector_list_iter_begin(dev, &iter); 1627 drm_for_each_connector_iter(connector, &iter) { 1628 amdgpu_connector = to_amdgpu_connector(connector); 1629 if (amdgpu_connector->connector_id == connector_id) { 1630 amdgpu_connector->devices |= supported_device; 1631 drm_connector_list_iter_end(&iter); 1632 return; 1633 } 1634 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1635 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1636 amdgpu_connector->shared_ddc = true; 1637 shared_ddc = true; 1638 } 1639 if (amdgpu_connector->router_bus && router->ddc_valid && 1640 (amdgpu_connector->router.router_id == router->router_id)) { 1641 amdgpu_connector->shared_ddc = false; 1642 shared_ddc = false; 1643 } 1644 } 1645 } 1646 drm_connector_list_iter_end(&iter); 1647 1648 /* check if it's a dp bridge */ 1649 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1650 amdgpu_encoder = to_amdgpu_encoder(encoder); 1651 if (amdgpu_encoder->devices & supported_device) { 1652 switch (amdgpu_encoder->encoder_id) { 1653 case ENCODER_OBJECT_ID_TRAVIS: 1654 case ENCODER_OBJECT_ID_NUTMEG: 1655 is_dp_bridge = true; 1656 break; 1657 default: 1658 break; 1659 } 1660 } 1661 } 1662 1663 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1664 if (!amdgpu_connector) 1665 return; 1666 1667 connector = &amdgpu_connector->base; 1668 1669 amdgpu_connector->connector_id = connector_id; 1670 amdgpu_connector->devices = supported_device; 1671 amdgpu_connector->shared_ddc = shared_ddc; 1672 amdgpu_connector->connector_object_id = connector_object_id; 1673 amdgpu_connector->hpd = *hpd; 1674 1675 amdgpu_connector->router = *router; 1676 if (router->ddc_valid || router->cd_valid) { 1677 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1678 if (!amdgpu_connector->router_bus) 1679 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1680 } 1681 1682 if (is_dp_bridge) { 1683 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1684 if (!amdgpu_dig_connector) 1685 goto failed; 1686 amdgpu_connector->con_priv = amdgpu_dig_connector; 1687 if (i2c_bus->valid) { 1688 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1689 if (amdgpu_connector->ddc_bus) { 1690 has_aux = true; 1691 ddc = &amdgpu_connector->ddc_bus->adapter; 1692 } else { 1693 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1694 } 1695 } 1696 switch (connector_type) { 1697 case DRM_MODE_CONNECTOR_VGA: 1698 case DRM_MODE_CONNECTOR_DVIA: 1699 default: 1700 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1701 &amdgpu_connector_dp_funcs, 1702 connector_type, 1703 ddc); 1704 drm_connector_helper_add(&amdgpu_connector->base, 1705 &amdgpu_connector_dp_helper_funcs); 1706 connector->interlace_allowed = true; 1707 connector->doublescan_allowed = true; 1708 amdgpu_connector->dac_load_detect = true; 1709 drm_object_attach_property(&amdgpu_connector->base.base, 1710 adev->mode_info.load_detect_property, 1711 1); 1712 drm_object_attach_property(&amdgpu_connector->base.base, 1713 dev->mode_config.scaling_mode_property, 1714 DRM_MODE_SCALE_NONE); 1715 break; 1716 case DRM_MODE_CONNECTOR_DVII: 1717 case DRM_MODE_CONNECTOR_DVID: 1718 case DRM_MODE_CONNECTOR_HDMIA: 1719 case DRM_MODE_CONNECTOR_HDMIB: 1720 case DRM_MODE_CONNECTOR_DisplayPort: 1721 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1722 &amdgpu_connector_dp_funcs, 1723 connector_type, 1724 ddc); 1725 drm_connector_helper_add(&amdgpu_connector->base, 1726 &amdgpu_connector_dp_helper_funcs); 1727 drm_object_attach_property(&amdgpu_connector->base.base, 1728 adev->mode_info.underscan_property, 1729 UNDERSCAN_OFF); 1730 drm_object_attach_property(&amdgpu_connector->base.base, 1731 adev->mode_info.underscan_hborder_property, 1732 0); 1733 drm_object_attach_property(&amdgpu_connector->base.base, 1734 adev->mode_info.underscan_vborder_property, 1735 0); 1736 1737 drm_object_attach_property(&amdgpu_connector->base.base, 1738 dev->mode_config.scaling_mode_property, 1739 DRM_MODE_SCALE_NONE); 1740 1741 drm_object_attach_property(&amdgpu_connector->base.base, 1742 adev->mode_info.dither_property, 1743 AMDGPU_FMT_DITHER_DISABLE); 1744 1745 if (amdgpu_audio != 0) { 1746 drm_object_attach_property(&amdgpu_connector->base.base, 1747 adev->mode_info.audio_property, 1748 AMDGPU_AUDIO_AUTO); 1749 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1750 } 1751 1752 subpixel_order = SubPixelHorizontalRGB; 1753 connector->interlace_allowed = true; 1754 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1755 connector->doublescan_allowed = true; 1756 else 1757 connector->doublescan_allowed = false; 1758 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1759 amdgpu_connector->dac_load_detect = true; 1760 drm_object_attach_property(&amdgpu_connector->base.base, 1761 adev->mode_info.load_detect_property, 1762 1); 1763 } 1764 break; 1765 case DRM_MODE_CONNECTOR_LVDS: 1766 case DRM_MODE_CONNECTOR_eDP: 1767 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1768 &amdgpu_connector_edp_funcs, 1769 connector_type, 1770 ddc); 1771 drm_connector_helper_add(&amdgpu_connector->base, 1772 &amdgpu_connector_dp_helper_funcs); 1773 drm_object_attach_property(&amdgpu_connector->base.base, 1774 dev->mode_config.scaling_mode_property, 1775 DRM_MODE_SCALE_FULLSCREEN); 1776 subpixel_order = SubPixelHorizontalRGB; 1777 connector->interlace_allowed = false; 1778 connector->doublescan_allowed = false; 1779 break; 1780 } 1781 } else { 1782 switch (connector_type) { 1783 case DRM_MODE_CONNECTOR_VGA: 1784 if (i2c_bus->valid) { 1785 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1786 if (!amdgpu_connector->ddc_bus) 1787 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1788 else 1789 ddc = &amdgpu_connector->ddc_bus->adapter; 1790 } 1791 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1792 &amdgpu_connector_vga_funcs, 1793 connector_type, 1794 ddc); 1795 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1796 amdgpu_connector->dac_load_detect = true; 1797 drm_object_attach_property(&amdgpu_connector->base.base, 1798 adev->mode_info.load_detect_property, 1799 1); 1800 drm_object_attach_property(&amdgpu_connector->base.base, 1801 dev->mode_config.scaling_mode_property, 1802 DRM_MODE_SCALE_NONE); 1803 /* no HPD on analog connectors */ 1804 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1805 connector->interlace_allowed = true; 1806 connector->doublescan_allowed = true; 1807 break; 1808 case DRM_MODE_CONNECTOR_DVIA: 1809 if (i2c_bus->valid) { 1810 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1811 if (!amdgpu_connector->ddc_bus) 1812 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1813 else 1814 ddc = &amdgpu_connector->ddc_bus->adapter; 1815 } 1816 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1817 &amdgpu_connector_vga_funcs, 1818 connector_type, 1819 ddc); 1820 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1821 amdgpu_connector->dac_load_detect = true; 1822 drm_object_attach_property(&amdgpu_connector->base.base, 1823 adev->mode_info.load_detect_property, 1824 1); 1825 drm_object_attach_property(&amdgpu_connector->base.base, 1826 dev->mode_config.scaling_mode_property, 1827 DRM_MODE_SCALE_NONE); 1828 /* no HPD on analog connectors */ 1829 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1830 connector->interlace_allowed = true; 1831 connector->doublescan_allowed = true; 1832 break; 1833 case DRM_MODE_CONNECTOR_DVII: 1834 case DRM_MODE_CONNECTOR_DVID: 1835 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1836 if (!amdgpu_dig_connector) 1837 goto failed; 1838 amdgpu_connector->con_priv = amdgpu_dig_connector; 1839 if (i2c_bus->valid) { 1840 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1841 if (!amdgpu_connector->ddc_bus) 1842 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1843 else 1844 ddc = &amdgpu_connector->ddc_bus->adapter; 1845 } 1846 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1847 &amdgpu_connector_dvi_funcs, 1848 connector_type, 1849 ddc); 1850 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1851 subpixel_order = SubPixelHorizontalRGB; 1852 drm_object_attach_property(&amdgpu_connector->base.base, 1853 adev->mode_info.coherent_mode_property, 1854 1); 1855 drm_object_attach_property(&amdgpu_connector->base.base, 1856 adev->mode_info.underscan_property, 1857 UNDERSCAN_OFF); 1858 drm_object_attach_property(&amdgpu_connector->base.base, 1859 adev->mode_info.underscan_hborder_property, 1860 0); 1861 drm_object_attach_property(&amdgpu_connector->base.base, 1862 adev->mode_info.underscan_vborder_property, 1863 0); 1864 drm_object_attach_property(&amdgpu_connector->base.base, 1865 dev->mode_config.scaling_mode_property, 1866 DRM_MODE_SCALE_NONE); 1867 1868 if (amdgpu_audio != 0) { 1869 drm_object_attach_property(&amdgpu_connector->base.base, 1870 adev->mode_info.audio_property, 1871 AMDGPU_AUDIO_AUTO); 1872 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1873 } 1874 drm_object_attach_property(&amdgpu_connector->base.base, 1875 adev->mode_info.dither_property, 1876 AMDGPU_FMT_DITHER_DISABLE); 1877 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1878 amdgpu_connector->dac_load_detect = true; 1879 drm_object_attach_property(&amdgpu_connector->base.base, 1880 adev->mode_info.load_detect_property, 1881 1); 1882 } 1883 connector->interlace_allowed = true; 1884 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1885 connector->doublescan_allowed = true; 1886 else 1887 connector->doublescan_allowed = false; 1888 break; 1889 case DRM_MODE_CONNECTOR_HDMIA: 1890 case DRM_MODE_CONNECTOR_HDMIB: 1891 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1892 if (!amdgpu_dig_connector) 1893 goto failed; 1894 amdgpu_connector->con_priv = amdgpu_dig_connector; 1895 if (i2c_bus->valid) { 1896 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1897 if (!amdgpu_connector->ddc_bus) 1898 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1899 else 1900 ddc = &amdgpu_connector->ddc_bus->adapter; 1901 } 1902 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1903 &amdgpu_connector_dvi_funcs, 1904 connector_type, 1905 ddc); 1906 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1907 drm_object_attach_property(&amdgpu_connector->base.base, 1908 adev->mode_info.coherent_mode_property, 1909 1); 1910 drm_object_attach_property(&amdgpu_connector->base.base, 1911 adev->mode_info.underscan_property, 1912 UNDERSCAN_OFF); 1913 drm_object_attach_property(&amdgpu_connector->base.base, 1914 adev->mode_info.underscan_hborder_property, 1915 0); 1916 drm_object_attach_property(&amdgpu_connector->base.base, 1917 adev->mode_info.underscan_vborder_property, 1918 0); 1919 drm_object_attach_property(&amdgpu_connector->base.base, 1920 dev->mode_config.scaling_mode_property, 1921 DRM_MODE_SCALE_NONE); 1922 if (amdgpu_audio != 0) { 1923 drm_object_attach_property(&amdgpu_connector->base.base, 1924 adev->mode_info.audio_property, 1925 AMDGPU_AUDIO_AUTO); 1926 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1927 } 1928 drm_object_attach_property(&amdgpu_connector->base.base, 1929 adev->mode_info.dither_property, 1930 AMDGPU_FMT_DITHER_DISABLE); 1931 subpixel_order = SubPixelHorizontalRGB; 1932 connector->interlace_allowed = true; 1933 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1934 connector->doublescan_allowed = true; 1935 else 1936 connector->doublescan_allowed = false; 1937 break; 1938 case DRM_MODE_CONNECTOR_DisplayPort: 1939 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1940 if (!amdgpu_dig_connector) 1941 goto failed; 1942 amdgpu_connector->con_priv = amdgpu_dig_connector; 1943 if (i2c_bus->valid) { 1944 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1945 if (amdgpu_connector->ddc_bus) { 1946 has_aux = true; 1947 ddc = &amdgpu_connector->ddc_bus->adapter; 1948 } else { 1949 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1950 } 1951 } 1952 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 1953 &amdgpu_connector_dp_funcs, 1954 connector_type, 1955 ddc); 1956 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1957 subpixel_order = SubPixelHorizontalRGB; 1958 drm_object_attach_property(&amdgpu_connector->base.base, 1959 adev->mode_info.coherent_mode_property, 1960 1); 1961 drm_object_attach_property(&amdgpu_connector->base.base, 1962 adev->mode_info.underscan_property, 1963 UNDERSCAN_OFF); 1964 drm_object_attach_property(&amdgpu_connector->base.base, 1965 adev->mode_info.underscan_hborder_property, 1966 0); 1967 drm_object_attach_property(&amdgpu_connector->base.base, 1968 adev->mode_info.underscan_vborder_property, 1969 0); 1970 drm_object_attach_property(&amdgpu_connector->base.base, 1971 dev->mode_config.scaling_mode_property, 1972 DRM_MODE_SCALE_NONE); 1973 if (amdgpu_audio != 0) { 1974 drm_object_attach_property(&amdgpu_connector->base.base, 1975 adev->mode_info.audio_property, 1976 AMDGPU_AUDIO_AUTO); 1977 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO; 1978 } 1979 drm_object_attach_property(&amdgpu_connector->base.base, 1980 adev->mode_info.dither_property, 1981 AMDGPU_FMT_DITHER_DISABLE); 1982 connector->interlace_allowed = true; 1983 /* in theory with a DP to VGA converter... */ 1984 connector->doublescan_allowed = false; 1985 break; 1986 case DRM_MODE_CONNECTOR_eDP: 1987 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1988 if (!amdgpu_dig_connector) 1989 goto failed; 1990 amdgpu_connector->con_priv = amdgpu_dig_connector; 1991 if (i2c_bus->valid) { 1992 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1993 if (amdgpu_connector->ddc_bus) { 1994 has_aux = true; 1995 ddc = &amdgpu_connector->ddc_bus->adapter; 1996 } else { 1997 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1998 } 1999 } 2000 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 2001 &amdgpu_connector_edp_funcs, 2002 connector_type, 2003 ddc); 2004 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 2005 drm_object_attach_property(&amdgpu_connector->base.base, 2006 dev->mode_config.scaling_mode_property, 2007 DRM_MODE_SCALE_FULLSCREEN); 2008 subpixel_order = SubPixelHorizontalRGB; 2009 connector->interlace_allowed = false; 2010 connector->doublescan_allowed = false; 2011 break; 2012 case DRM_MODE_CONNECTOR_LVDS: 2013 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 2014 if (!amdgpu_dig_connector) 2015 goto failed; 2016 amdgpu_connector->con_priv = amdgpu_dig_connector; 2017 if (i2c_bus->valid) { 2018 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 2019 if (!amdgpu_connector->ddc_bus) 2020 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 2021 else 2022 ddc = &amdgpu_connector->ddc_bus->adapter; 2023 } 2024 drm_connector_init_with_ddc(dev, &amdgpu_connector->base, 2025 &amdgpu_connector_lvds_funcs, 2026 connector_type, 2027 ddc); 2028 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 2029 drm_object_attach_property(&amdgpu_connector->base.base, 2030 dev->mode_config.scaling_mode_property, 2031 DRM_MODE_SCALE_FULLSCREEN); 2032 subpixel_order = SubPixelHorizontalRGB; 2033 connector->interlace_allowed = false; 2034 connector->doublescan_allowed = false; 2035 break; 2036 } 2037 } 2038 2039 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 2040 if (i2c_bus->valid) { 2041 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 2042 DRM_CONNECTOR_POLL_DISCONNECT; 2043 } 2044 } else 2045 connector->polled = DRM_CONNECTOR_POLL_HPD; 2046 2047 connector->display_info.subpixel_order = subpixel_order; 2048 2049 if (has_aux) 2050 amdgpu_atombios_dp_aux_init(amdgpu_connector); 2051 2052 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2053 connector_type == DRM_MODE_CONNECTOR_eDP) { 2054 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base); 2055 } 2056 2057 return; 2058 2059 failed: 2060 drm_connector_cleanup(connector); 2061 kfree(connector); 2062 } 2063