1 /* 2 * Intel e7xxx Memory Controller kernel module 3 * (C) 2003 Linux Networx (http://lnxi.com) 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * See "enum e7xxx_chips" below for supported chipsets 8 * 9 * Written by Thayne Harbaugh 10 * Based on work by Dan Hollis <goemon at anime dot net> and others. 11 * http://www.anime.net/~goemon/linux-ecc/ 12 * 13 * Contributors: 14 * Eric Biederman (Linux Networx) 15 * Tom Zimmerman (Linux Networx) 16 * Jim Garlick (Lawrence Livermore National Labs) 17 * Dave Peterson (Lawrence Livermore National Labs) 18 * That One Guy (Some other place) 19 * Wang Zhenyu (intel.com) 20 * 21 * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $ 22 * 23 */ 24 25 #include <linux/config.h> 26 #include <linux/module.h> 27 #include <linux/init.h> 28 #include <linux/pci.h> 29 #include <linux/pci_ids.h> 30 #include <linux/slab.h> 31 #include "edac_mc.h" 32 33 #define e7xxx_printk(level, fmt, arg...) \ 34 edac_printk(level, "e7xxx", fmt, ##arg) 35 36 #define e7xxx_mc_printk(mci, level, fmt, arg...) \ 37 edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg) 38 39 #ifndef PCI_DEVICE_ID_INTEL_7205_0 40 #define PCI_DEVICE_ID_INTEL_7205_0 0x255d 41 #endif /* PCI_DEVICE_ID_INTEL_7205_0 */ 42 43 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR 44 #define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551 45 #endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */ 46 47 #ifndef PCI_DEVICE_ID_INTEL_7500_0 48 #define PCI_DEVICE_ID_INTEL_7500_0 0x2540 49 #endif /* PCI_DEVICE_ID_INTEL_7500_0 */ 50 51 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR 52 #define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541 53 #endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */ 54 55 #ifndef PCI_DEVICE_ID_INTEL_7501_0 56 #define PCI_DEVICE_ID_INTEL_7501_0 0x254c 57 #endif /* PCI_DEVICE_ID_INTEL_7501_0 */ 58 59 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR 60 #define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541 61 #endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */ 62 63 #ifndef PCI_DEVICE_ID_INTEL_7505_0 64 #define PCI_DEVICE_ID_INTEL_7505_0 0x2550 65 #endif /* PCI_DEVICE_ID_INTEL_7505_0 */ 66 67 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR 68 #define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551 69 #endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */ 70 71 #define E7XXX_NR_CSROWS 8 /* number of csrows */ 72 #define E7XXX_NR_DIMMS 8 /* FIXME - is this correct? */ 73 74 /* E7XXX register addresses - device 0 function 0 */ 75 #define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */ 76 #define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */ 77 /* 78 * 31 Device width row 7 0=x8 1=x4 79 * 27 Device width row 6 80 * 23 Device width row 5 81 * 19 Device width row 4 82 * 15 Device width row 3 83 * 11 Device width row 2 84 * 7 Device width row 1 85 * 3 Device width row 0 86 */ 87 #define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */ 88 /* 89 * 22 Number channels 0=1,1=2 90 * 19:18 DRB Granularity 32/64MB 91 */ 92 #define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ 93 #define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ 94 #define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ 95 96 /* E7XXX register addresses - device 0 function 1 */ 97 #define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */ 98 #define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */ 99 #define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */ 100 /* error address register (32b) */ 101 /* 102 * 31:28 Reserved 103 * 27:6 CE address (4k block 33:12) 104 * 5:0 Reserved 105 */ 106 #define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */ 107 /* error address register (32b) */ 108 /* 109 * 31:28 Reserved 110 * 27:6 CE address (4k block 33:12) 111 * 5:0 Reserved 112 */ 113 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */ 114 /* error syndrome register (16b) */ 115 116 enum e7xxx_chips { 117 E7500 = 0, 118 E7501, 119 E7505, 120 E7205, 121 }; 122 123 struct e7xxx_pvt { 124 struct pci_dev *bridge_ck; 125 u32 tolm; 126 u32 remapbase; 127 u32 remaplimit; 128 const struct e7xxx_dev_info *dev_info; 129 }; 130 131 struct e7xxx_dev_info { 132 u16 err_dev; 133 const char *ctl_name; 134 }; 135 136 struct e7xxx_error_info { 137 u8 dram_ferr; 138 u8 dram_nerr; 139 u32 dram_celog_add; 140 u16 dram_celog_syndrome; 141 u32 dram_uelog_add; 142 }; 143 144 static const struct e7xxx_dev_info e7xxx_devs[] = { 145 [E7500] = { 146 .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR, 147 .ctl_name = "E7500" 148 }, 149 [E7501] = { 150 .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR, 151 .ctl_name = "E7501" 152 }, 153 [E7505] = { 154 .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR, 155 .ctl_name = "E7505" 156 }, 157 [E7205] = { 158 .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR, 159 .ctl_name = "E7205" 160 }, 161 }; 162 163 /* FIXME - is this valid for both SECDED and S4ECD4ED? */ 164 static inline int e7xxx_find_channel(u16 syndrome) 165 { 166 debugf3("%s()\n", __func__); 167 168 if ((syndrome & 0xff00) == 0) 169 return 0; 170 171 if ((syndrome & 0x00ff) == 0) 172 return 1; 173 174 if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0) 175 return 0; 176 177 return 1; 178 } 179 180 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci, 181 unsigned long page) 182 { 183 u32 remap; 184 struct e7xxx_pvt *pvt = (struct e7xxx_pvt *) mci->pvt_info; 185 186 debugf3("%s()\n", __func__); 187 188 if ((page < pvt->tolm) || 189 ((page >= 0x100000) && (page < pvt->remapbase))) 190 return page; 191 192 remap = (page - pvt->tolm) + pvt->remapbase; 193 194 if (remap < pvt->remaplimit) 195 return remap; 196 197 e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page); 198 return pvt->tolm - 1; 199 } 200 201 static void process_ce(struct mem_ctl_info *mci, 202 struct e7xxx_error_info *info) 203 { 204 u32 error_1b, page; 205 u16 syndrome; 206 int row; 207 int channel; 208 209 debugf3("%s()\n", __func__); 210 /* read the error address */ 211 error_1b = info->dram_celog_add; 212 /* FIXME - should use PAGE_SHIFT */ 213 page = error_1b >> 6; /* convert the address to 4k page */ 214 /* read the syndrome */ 215 syndrome = info->dram_celog_syndrome; 216 /* FIXME - check for -1 */ 217 row = edac_mc_find_csrow_by_page(mci, page); 218 /* convert syndrome to channel */ 219 channel = e7xxx_find_channel(syndrome); 220 edac_mc_handle_ce(mci, page, 0, syndrome, row, channel, "e7xxx CE"); 221 } 222 223 static void process_ce_no_info(struct mem_ctl_info *mci) 224 { 225 debugf3("%s()\n", __func__); 226 edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow"); 227 } 228 229 static void process_ue(struct mem_ctl_info *mci, 230 struct e7xxx_error_info *info) 231 { 232 u32 error_2b, block_page; 233 int row; 234 235 debugf3("%s()\n", __func__); 236 /* read the error address */ 237 error_2b = info->dram_uelog_add; 238 /* FIXME - should use PAGE_SHIFT */ 239 block_page = error_2b >> 6; /* convert to 4k address */ 240 row = edac_mc_find_csrow_by_page(mci, block_page); 241 edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE"); 242 } 243 244 static void process_ue_no_info(struct mem_ctl_info *mci) 245 { 246 debugf3("%s()\n", __func__); 247 edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow"); 248 } 249 250 static void e7xxx_get_error_info (struct mem_ctl_info *mci, 251 struct e7xxx_error_info *info) 252 { 253 struct e7xxx_pvt *pvt; 254 255 pvt = (struct e7xxx_pvt *) mci->pvt_info; 256 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, 257 &info->dram_ferr); 258 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, 259 &info->dram_nerr); 260 261 if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) { 262 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD, 263 &info->dram_celog_add); 264 pci_read_config_word(pvt->bridge_ck, 265 E7XXX_DRAM_CELOG_SYNDROME, 266 &info->dram_celog_syndrome); 267 } 268 269 if ((info->dram_ferr & 2) || (info->dram_nerr & 2)) 270 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD, 271 &info->dram_uelog_add); 272 273 if (info->dram_ferr & 3) 274 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03); 275 276 if (info->dram_nerr & 3) 277 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03); 278 } 279 280 static int e7xxx_process_error_info (struct mem_ctl_info *mci, 281 struct e7xxx_error_info *info, int handle_errors) 282 { 283 int error_found; 284 285 error_found = 0; 286 287 /* decode and report errors */ 288 if (info->dram_ferr & 1) { /* check first error correctable */ 289 error_found = 1; 290 291 if (handle_errors) 292 process_ce(mci, info); 293 } 294 295 if (info->dram_ferr & 2) { /* check first error uncorrectable */ 296 error_found = 1; 297 298 if (handle_errors) 299 process_ue(mci, info); 300 } 301 302 if (info->dram_nerr & 1) { /* check next error correctable */ 303 error_found = 1; 304 305 if (handle_errors) { 306 if (info->dram_ferr & 1) 307 process_ce_no_info(mci); 308 else 309 process_ce(mci, info); 310 } 311 } 312 313 if (info->dram_nerr & 2) { /* check next error uncorrectable */ 314 error_found = 1; 315 316 if (handle_errors) { 317 if (info->dram_ferr & 2) 318 process_ue_no_info(mci); 319 else 320 process_ue(mci, info); 321 } 322 } 323 324 return error_found; 325 } 326 327 static void e7xxx_check(struct mem_ctl_info *mci) 328 { 329 struct e7xxx_error_info info; 330 331 debugf3("%s()\n", __func__); 332 e7xxx_get_error_info(mci, &info); 333 e7xxx_process_error_info(mci, &info, 1); 334 } 335 336 static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx) 337 { 338 int rc = -ENODEV; 339 int index; 340 u16 pci_data; 341 struct mem_ctl_info *mci = NULL; 342 struct e7xxx_pvt *pvt = NULL; 343 u32 drc; 344 int drc_chan = 1; /* Number of channels 0=1chan,1=2chan */ 345 int drc_drbg = 1; /* DRB granularity 0=32mb,1=64mb */ 346 int drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */ 347 u32 dra; 348 unsigned long last_cumul_size; 349 struct e7xxx_error_info discard; 350 351 debugf0("%s(): mci\n", __func__); 352 353 /* need to find out the number of channels */ 354 pci_read_config_dword(pdev, E7XXX_DRC, &drc); 355 356 /* only e7501 can be single channel */ 357 if (dev_idx == E7501) { 358 drc_chan = ((drc >> 22) & 0x1); 359 drc_drbg = (drc >> 18) & 0x3; 360 } 361 362 drc_ddim = (drc >> 20) & 0x3; 363 mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1); 364 365 if (mci == NULL) { 366 rc = -ENOMEM; 367 goto fail; 368 } 369 370 debugf3("%s(): init mci\n", __func__); 371 mci->mtype_cap = MEM_FLAG_RDDR; 372 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED | 373 EDAC_FLAG_S4ECD4ED; 374 /* FIXME - what if different memory types are in different csrows? */ 375 mci->mod_name = EDAC_MOD_STR; 376 mci->mod_ver = "$Revision: 1.5.2.9 $"; 377 mci->pdev = pdev; 378 379 debugf3("%s(): init pvt\n", __func__); 380 pvt = (struct e7xxx_pvt *) mci->pvt_info; 381 pvt->dev_info = &e7xxx_devs[dev_idx]; 382 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, 383 pvt->dev_info->err_dev, 384 pvt->bridge_ck); 385 386 if (!pvt->bridge_ck) { 387 e7xxx_printk(KERN_ERR, "error reporting device not found:" 388 "vendor %x device 0x%x (broken BIOS?)\n", 389 PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev); 390 goto fail; 391 } 392 393 debugf3("%s(): more mci init\n", __func__); 394 mci->ctl_name = pvt->dev_info->ctl_name; 395 mci->edac_check = e7xxx_check; 396 mci->ctl_page_to_phys = ctl_page_to_phys; 397 398 /* find out the device types */ 399 pci_read_config_dword(pdev, E7XXX_DRA, &dra); 400 401 /* 402 * The dram row boundary (DRB) reg values are boundary address 403 * for each DRAM row with a granularity of 32 or 64MB (single/dual 404 * channel operation). DRB regs are cumulative; therefore DRB7 will 405 * contain the total memory contained in all eight rows. 406 */ 407 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) { 408 u8 value; 409 u32 cumul_size; 410 /* mem_dev 0=x8, 1=x4 */ 411 int mem_dev = (dra >> (index * 4 + 3)) & 0x1; 412 struct csrow_info *csrow = &mci->csrows[index]; 413 414 pci_read_config_byte(mci->pdev, E7XXX_DRB + index, &value); 415 /* convert a 64 or 32 MiB DRB to a page size. */ 416 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); 417 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, 418 cumul_size); 419 420 if (cumul_size == last_cumul_size) 421 continue; /* not populated */ 422 423 csrow->first_page = last_cumul_size; 424 csrow->last_page = cumul_size - 1; 425 csrow->nr_pages = cumul_size - last_cumul_size; 426 last_cumul_size = cumul_size; 427 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ 428 csrow->mtype = MEM_RDDR; /* only one type supported */ 429 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; 430 431 /* 432 * if single channel or x8 devices then SECDED 433 * if dual channel and x4 then S4ECD4ED 434 */ 435 if (drc_ddim) { 436 if (drc_chan && mem_dev) { 437 csrow->edac_mode = EDAC_S4ECD4ED; 438 mci->edac_cap |= EDAC_FLAG_S4ECD4ED; 439 } else { 440 csrow->edac_mode = EDAC_SECDED; 441 mci->edac_cap |= EDAC_FLAG_SECDED; 442 } 443 } else 444 csrow->edac_mode = EDAC_NONE; 445 } 446 447 mci->edac_cap |= EDAC_FLAG_NONE; 448 449 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__); 450 /* load the top of low memory, remap base, and remap limit vars */ 451 pci_read_config_word(mci->pdev, E7XXX_TOLM, &pci_data); 452 pvt->tolm = ((u32) pci_data) << 4; 453 pci_read_config_word(mci->pdev, E7XXX_REMAPBASE, &pci_data); 454 pvt->remapbase = ((u32) pci_data) << 14; 455 pci_read_config_word(mci->pdev, E7XXX_REMAPLIMIT, &pci_data); 456 pvt->remaplimit = ((u32) pci_data) << 14; 457 e7xxx_printk(KERN_INFO, 458 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm, 459 pvt->remapbase, pvt->remaplimit); 460 461 /* clear any pending errors, or initial state bits */ 462 e7xxx_get_error_info(mci, &discard); 463 464 if (edac_mc_add_mc(mci) != 0) { 465 debugf3("%s(): failed edac_mc_add_mc()\n", __func__); 466 goto fail; 467 } 468 469 /* get this far and it's successful */ 470 debugf3("%s(): success\n", __func__); 471 return 0; 472 473 fail: 474 if (mci != NULL) { 475 if(pvt != NULL && pvt->bridge_ck) 476 pci_dev_put(pvt->bridge_ck); 477 edac_mc_free(mci); 478 } 479 480 return rc; 481 } 482 483 /* returns count (>= 0), or negative on error */ 484 static int __devinit e7xxx_init_one(struct pci_dev *pdev, 485 const struct pci_device_id *ent) 486 { 487 debugf0("%s()\n", __func__); 488 489 /* wake up and enable device */ 490 return pci_enable_device(pdev) ? 491 -EIO : e7xxx_probe1(pdev, ent->driver_data); 492 } 493 494 static void __devexit e7xxx_remove_one(struct pci_dev *pdev) 495 { 496 struct mem_ctl_info *mci; 497 struct e7xxx_pvt *pvt; 498 499 debugf0("%s()\n", __func__); 500 501 if ((mci = edac_mc_del_mc(pdev)) == NULL) 502 return; 503 504 pvt = (struct e7xxx_pvt *) mci->pvt_info; 505 pci_dev_put(pvt->bridge_ck); 506 edac_mc_free(mci); 507 } 508 509 static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = { 510 { 511 PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 512 E7205 513 }, 514 { 515 PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 516 E7500 517 }, 518 { 519 PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 520 E7501 521 }, 522 { 523 PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 524 E7505 525 }, 526 { 527 0, 528 } /* 0 terminated list. */ 529 }; 530 531 MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl); 532 533 static struct pci_driver e7xxx_driver = { 534 .name = EDAC_MOD_STR, 535 .probe = e7xxx_init_one, 536 .remove = __devexit_p(e7xxx_remove_one), 537 .id_table = e7xxx_pci_tbl, 538 }; 539 540 static int __init e7xxx_init(void) 541 { 542 return pci_register_driver(&e7xxx_driver); 543 } 544 545 static void __exit e7xxx_exit(void) 546 { 547 pci_unregister_driver(&e7xxx_driver); 548 } 549 550 module_init(e7xxx_init); 551 module_exit(e7xxx_exit); 552 553 MODULE_LICENSE("GPL"); 554 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n" 555 "Based on.work by Dan Hollis et al"); 556 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers"); 557