1 /* 2 * Copyright Altera Corporation (C) 2014-2016. All rights reserved. 3 * Copyright 2011-2012 Calxeda, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 * Adapted from the highbank_mc_edac driver. 18 */ 19 20 #include <asm/cacheflush.h> 21 #include <linux/ctype.h> 22 #include <linux/delay.h> 23 #include <linux/edac.h> 24 #include <linux/genalloc.h> 25 #include <linux/interrupt.h> 26 #include <linux/irqchip/chained_irq.h> 27 #include <linux/kernel.h> 28 #include <linux/mfd/syscon.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/of_platform.h> 32 #include <linux/platform_device.h> 33 #include <linux/regmap.h> 34 #include <linux/types.h> 35 #include <linux/uaccess.h> 36 37 #include "altera_edac.h" 38 #include "edac_core.h" 39 #include "edac_module.h" 40 41 #define EDAC_MOD_STR "altera_edac" 42 #define EDAC_VERSION "1" 43 #define EDAC_DEVICE "Altera" 44 45 static const struct altr_sdram_prv_data c5_data = { 46 .ecc_ctrl_offset = CV_CTLCFG_OFST, 47 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN, 48 .ecc_stat_offset = CV_DRAMSTS_OFST, 49 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR, 50 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR, 51 .ecc_saddr_offset = CV_ERRADDR_OFST, 52 .ecc_daddr_offset = CV_ERRADDR_OFST, 53 .ecc_cecnt_offset = CV_SBECOUNT_OFST, 54 .ecc_uecnt_offset = CV_DBECOUNT_OFST, 55 .ecc_irq_en_offset = CV_DRAMINTR_OFST, 56 .ecc_irq_en_mask = CV_DRAMINTR_INTREN, 57 .ecc_irq_clr_offset = CV_DRAMINTR_OFST, 58 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN), 59 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST, 60 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR, 61 .ce_ue_trgr_offset = CV_CTLCFG_OFST, 62 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR, 63 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR, 64 }; 65 66 static const struct altr_sdram_prv_data a10_data = { 67 .ecc_ctrl_offset = A10_ECCCTRL1_OFST, 68 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, 69 .ecc_stat_offset = A10_INTSTAT_OFST, 70 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, 71 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, 72 .ecc_saddr_offset = A10_SERRADDR_OFST, 73 .ecc_daddr_offset = A10_DERRADDR_OFST, 74 .ecc_irq_en_offset = A10_ERRINTEN_OFST, 75 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, 76 .ecc_irq_clr_offset = A10_INTSTAT_OFST, 77 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), 78 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST, 79 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, 80 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST, 81 .ce_set_mask = A10_DIAGINT_TSERRA_MASK, 82 .ue_set_mask = A10_DIAGINT_TDERRA_MASK, 83 }; 84 85 /*********************** EDAC Memory Controller Functions ****************/ 86 87 /* The SDRAM controller uses the EDAC Memory Controller framework. */ 88 89 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) 90 { 91 struct mem_ctl_info *mci = dev_id; 92 struct altr_sdram_mc_data *drvdata = mci->pvt_info; 93 const struct altr_sdram_prv_data *priv = drvdata->data; 94 u32 status, err_count = 1, err_addr; 95 96 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); 97 98 if (status & priv->ecc_stat_ue_mask) { 99 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset, 100 &err_addr); 101 if (priv->ecc_uecnt_offset) 102 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset, 103 &err_count); 104 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n", 105 err_count, err_addr); 106 } 107 if (status & priv->ecc_stat_ce_mask) { 108 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, 109 &err_addr); 110 if (priv->ecc_uecnt_offset) 111 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset, 112 &err_count); 113 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, 114 err_addr >> PAGE_SHIFT, 115 err_addr & ~PAGE_MASK, 0, 116 0, 0, -1, mci->ctl_name, ""); 117 /* Clear IRQ to resume */ 118 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset, 119 priv->ecc_irq_clr_mask); 120 121 return IRQ_HANDLED; 122 } 123 return IRQ_NONE; 124 } 125 126 static ssize_t altr_sdr_mc_err_inject_write(struct file *file, 127 const char __user *data, 128 size_t count, loff_t *ppos) 129 { 130 struct mem_ctl_info *mci = file->private_data; 131 struct altr_sdram_mc_data *drvdata = mci->pvt_info; 132 const struct altr_sdram_prv_data *priv = drvdata->data; 133 u32 *ptemp; 134 dma_addr_t dma_handle; 135 u32 reg, read_reg; 136 137 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL); 138 if (!ptemp) { 139 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); 140 edac_printk(KERN_ERR, EDAC_MC, 141 "Inject: Buffer Allocation error\n"); 142 return -ENOMEM; 143 } 144 145 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 146 &read_reg); 147 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask); 148 149 /* Error are injected by writing a word while the SBE or DBE 150 * bit in the CTLCFG register is set. Reading the word will 151 * trigger the SBE or DBE error and the corresponding IRQ. 152 */ 153 if (count == 3) { 154 edac_printk(KERN_ALERT, EDAC_MC, 155 "Inject Double bit error\n"); 156 local_irq_disable(); 157 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 158 (read_reg | priv->ue_set_mask)); 159 local_irq_enable(); 160 } else { 161 edac_printk(KERN_ALERT, EDAC_MC, 162 "Inject Single bit error\n"); 163 local_irq_disable(); 164 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 165 (read_reg | priv->ce_set_mask)); 166 local_irq_enable(); 167 } 168 169 ptemp[0] = 0x5A5A5A5A; 170 ptemp[1] = 0xA5A5A5A5; 171 172 /* Clear the error injection bits */ 173 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg); 174 /* Ensure it has been written out */ 175 wmb(); 176 177 /* 178 * To trigger the error, we need to read the data back 179 * (the data was written with errors above). 180 * The ACCESS_ONCE macros and printk are used to prevent the 181 * the compiler optimizing these reads out. 182 */ 183 reg = ACCESS_ONCE(ptemp[0]); 184 read_reg = ACCESS_ONCE(ptemp[1]); 185 /* Force Read */ 186 rmb(); 187 188 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n", 189 reg, read_reg); 190 191 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); 192 193 return count; 194 } 195 196 static const struct file_operations altr_sdr_mc_debug_inject_fops = { 197 .open = simple_open, 198 .write = altr_sdr_mc_err_inject_write, 199 .llseek = generic_file_llseek, 200 }; 201 202 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) 203 { 204 if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) 205 return; 206 207 if (!mci->debugfs) 208 return; 209 210 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci, 211 &altr_sdr_mc_debug_inject_fops); 212 } 213 214 /* Get total memory size from Open Firmware DTB */ 215 static unsigned long get_total_mem(void) 216 { 217 struct device_node *np = NULL; 218 const unsigned int *reg, *reg_end; 219 int len, sw, aw; 220 unsigned long start, size, total_mem = 0; 221 222 for_each_node_by_type(np, "memory") { 223 aw = of_n_addr_cells(np); 224 sw = of_n_size_cells(np); 225 reg = (const unsigned int *)of_get_property(np, "reg", &len); 226 reg_end = reg + (len / sizeof(u32)); 227 228 total_mem = 0; 229 do { 230 start = of_read_number(reg, aw); 231 reg += aw; 232 size = of_read_number(reg, sw); 233 reg += sw; 234 total_mem += size; 235 } while (reg < reg_end); 236 } 237 edac_dbg(0, "total_mem 0x%lx\n", total_mem); 238 return total_mem; 239 } 240 241 static const struct of_device_id altr_sdram_ctrl_of_match[] = { 242 { .compatible = "altr,sdram-edac", .data = &c5_data}, 243 { .compatible = "altr,sdram-edac-a10", .data = &a10_data}, 244 {}, 245 }; 246 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); 247 248 static int a10_init(struct regmap *mc_vbase) 249 { 250 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST, 251 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) { 252 edac_printk(KERN_ERR, EDAC_MC, 253 "Error setting SB IRQ mode\n"); 254 return -ENODEV; 255 } 256 257 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) { 258 edac_printk(KERN_ERR, EDAC_MC, 259 "Error setting trigger count\n"); 260 return -ENODEV; 261 } 262 263 return 0; 264 } 265 266 static int a10_unmask_irq(struct platform_device *pdev, u32 mask) 267 { 268 void __iomem *sm_base; 269 int ret = 0; 270 271 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32), 272 dev_name(&pdev->dev))) { 273 edac_printk(KERN_ERR, EDAC_MC, 274 "Unable to request mem region\n"); 275 return -EBUSY; 276 } 277 278 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32)); 279 if (!sm_base) { 280 edac_printk(KERN_ERR, EDAC_MC, 281 "Unable to ioremap device\n"); 282 283 ret = -ENOMEM; 284 goto release; 285 } 286 287 iowrite32(mask, sm_base); 288 289 iounmap(sm_base); 290 291 release: 292 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32)); 293 294 return ret; 295 } 296 297 static int altr_sdram_probe(struct platform_device *pdev) 298 { 299 const struct of_device_id *id; 300 struct edac_mc_layer layers[2]; 301 struct mem_ctl_info *mci; 302 struct altr_sdram_mc_data *drvdata; 303 const struct altr_sdram_prv_data *priv; 304 struct regmap *mc_vbase; 305 struct dimm_info *dimm; 306 u32 read_reg; 307 int irq, irq2, res = 0; 308 unsigned long mem_size, irqflags = 0; 309 310 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev); 311 if (!id) 312 return -ENODEV; 313 314 /* Grab the register range from the sdr controller in device tree */ 315 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 316 "altr,sdr-syscon"); 317 if (IS_ERR(mc_vbase)) { 318 edac_printk(KERN_ERR, EDAC_MC, 319 "regmap for altr,sdr-syscon lookup failed.\n"); 320 return -ENODEV; 321 } 322 323 /* Check specific dependencies for the module */ 324 priv = of_match_node(altr_sdram_ctrl_of_match, 325 pdev->dev.of_node)->data; 326 327 /* Validate the SDRAM controller has ECC enabled */ 328 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) || 329 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { 330 edac_printk(KERN_ERR, EDAC_MC, 331 "No ECC/ECC disabled [0x%08X]\n", read_reg); 332 return -ENODEV; 333 } 334 335 /* Grab memory size from device tree. */ 336 mem_size = get_total_mem(); 337 if (!mem_size) { 338 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); 339 return -ENODEV; 340 } 341 342 /* Ensure the SDRAM Interrupt is disabled */ 343 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset, 344 priv->ecc_irq_en_mask, 0)) { 345 edac_printk(KERN_ERR, EDAC_MC, 346 "Error disabling SDRAM ECC IRQ\n"); 347 return -ENODEV; 348 } 349 350 /* Toggle to clear the SDRAM Error count */ 351 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, 352 priv->ecc_cnt_rst_mask, 353 priv->ecc_cnt_rst_mask)) { 354 edac_printk(KERN_ERR, EDAC_MC, 355 "Error clearing SDRAM ECC count\n"); 356 return -ENODEV; 357 } 358 359 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, 360 priv->ecc_cnt_rst_mask, 0)) { 361 edac_printk(KERN_ERR, EDAC_MC, 362 "Error clearing SDRAM ECC count\n"); 363 return -ENODEV; 364 } 365 366 irq = platform_get_irq(pdev, 0); 367 if (irq < 0) { 368 edac_printk(KERN_ERR, EDAC_MC, 369 "No irq %d in DT\n", irq); 370 return -ENODEV; 371 } 372 373 /* Arria10 has a 2nd IRQ */ 374 irq2 = platform_get_irq(pdev, 1); 375 376 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 377 layers[0].size = 1; 378 layers[0].is_virt_csrow = true; 379 layers[1].type = EDAC_MC_LAYER_CHANNEL; 380 layers[1].size = 1; 381 layers[1].is_virt_csrow = false; 382 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 383 sizeof(struct altr_sdram_mc_data)); 384 if (!mci) 385 return -ENOMEM; 386 387 mci->pdev = &pdev->dev; 388 drvdata = mci->pvt_info; 389 drvdata->mc_vbase = mc_vbase; 390 drvdata->data = priv; 391 platform_set_drvdata(pdev, mci); 392 393 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { 394 edac_printk(KERN_ERR, EDAC_MC, 395 "Unable to get managed device resource\n"); 396 res = -ENOMEM; 397 goto free; 398 } 399 400 mci->mtype_cap = MEM_FLAG_DDR3; 401 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 402 mci->edac_cap = EDAC_FLAG_SECDED; 403 mci->mod_name = EDAC_MOD_STR; 404 mci->mod_ver = EDAC_VERSION; 405 mci->ctl_name = dev_name(&pdev->dev); 406 mci->scrub_mode = SCRUB_SW_SRC; 407 mci->dev_name = dev_name(&pdev->dev); 408 409 dimm = *mci->dimms; 410 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1; 411 dimm->grain = 8; 412 dimm->dtype = DEV_X8; 413 dimm->mtype = MEM_DDR3; 414 dimm->edac_mode = EDAC_SECDED; 415 416 res = edac_mc_add_mc(mci); 417 if (res < 0) 418 goto err; 419 420 /* Only the Arria10 has separate IRQs */ 421 if (irq2 > 0) { 422 /* Arria10 specific initialization */ 423 res = a10_init(mc_vbase); 424 if (res < 0) 425 goto err2; 426 427 res = devm_request_irq(&pdev->dev, irq2, 428 altr_sdram_mc_err_handler, 429 IRQF_SHARED, dev_name(&pdev->dev), mci); 430 if (res < 0) { 431 edac_mc_printk(mci, KERN_ERR, 432 "Unable to request irq %d\n", irq2); 433 res = -ENODEV; 434 goto err2; 435 } 436 437 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK); 438 if (res < 0) 439 goto err2; 440 441 irqflags = IRQF_SHARED; 442 } 443 444 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, 445 irqflags, dev_name(&pdev->dev), mci); 446 if (res < 0) { 447 edac_mc_printk(mci, KERN_ERR, 448 "Unable to request irq %d\n", irq); 449 res = -ENODEV; 450 goto err2; 451 } 452 453 /* Infrastructure ready - enable the IRQ */ 454 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, 455 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { 456 edac_mc_printk(mci, KERN_ERR, 457 "Error enabling SDRAM ECC IRQ\n"); 458 res = -ENODEV; 459 goto err2; 460 } 461 462 altr_sdr_mc_create_debugfs_nodes(mci); 463 464 devres_close_group(&pdev->dev, NULL); 465 466 return 0; 467 468 err2: 469 edac_mc_del_mc(&pdev->dev); 470 err: 471 devres_release_group(&pdev->dev, NULL); 472 free: 473 edac_mc_free(mci); 474 edac_printk(KERN_ERR, EDAC_MC, 475 "EDAC Probe Failed; Error %d\n", res); 476 477 return res; 478 } 479 480 static int altr_sdram_remove(struct platform_device *pdev) 481 { 482 struct mem_ctl_info *mci = platform_get_drvdata(pdev); 483 484 edac_mc_del_mc(&pdev->dev); 485 edac_mc_free(mci); 486 platform_set_drvdata(pdev, NULL); 487 488 return 0; 489 } 490 491 /* 492 * If you want to suspend, need to disable EDAC by removing it 493 * from the device tree or defconfig. 494 */ 495 #ifdef CONFIG_PM 496 static int altr_sdram_prepare(struct device *dev) 497 { 498 pr_err("Suspend not allowed when EDAC is enabled.\n"); 499 500 return -EPERM; 501 } 502 503 static const struct dev_pm_ops altr_sdram_pm_ops = { 504 .prepare = altr_sdram_prepare, 505 }; 506 #endif 507 508 static struct platform_driver altr_sdram_edac_driver = { 509 .probe = altr_sdram_probe, 510 .remove = altr_sdram_remove, 511 .driver = { 512 .name = "altr_sdram_edac", 513 #ifdef CONFIG_PM 514 .pm = &altr_sdram_pm_ops, 515 #endif 516 .of_match_table = altr_sdram_ctrl_of_match, 517 }, 518 }; 519 520 module_platform_driver(altr_sdram_edac_driver); 521 522 /************************* EDAC Parent Probe *************************/ 523 524 static const struct of_device_id altr_edac_device_of_match[]; 525 526 static const struct of_device_id altr_edac_of_match[] = { 527 { .compatible = "altr,socfpga-ecc-manager" }, 528 {}, 529 }; 530 MODULE_DEVICE_TABLE(of, altr_edac_of_match); 531 532 static int altr_edac_probe(struct platform_device *pdev) 533 { 534 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match, 535 NULL, &pdev->dev); 536 return 0; 537 } 538 539 static struct platform_driver altr_edac_driver = { 540 .probe = altr_edac_probe, 541 .driver = { 542 .name = "socfpga_ecc_manager", 543 .of_match_table = altr_edac_of_match, 544 }, 545 }; 546 module_platform_driver(altr_edac_driver); 547 548 /************************* EDAC Device Functions *************************/ 549 550 /* 551 * EDAC Device Functions (shared between various IPs). 552 * The discrete memories use the EDAC Device framework. The probe 553 * and error handling functions are very similar between memories 554 * so they are shared. The memory allocation and freeing for EDAC 555 * trigger testing are different for each memory. 556 */ 557 558 static const struct edac_device_prv_data ocramecc_data; 559 static const struct edac_device_prv_data l2ecc_data; 560 static const struct edac_device_prv_data a10_ocramecc_data; 561 static const struct edac_device_prv_data a10_l2ecc_data; 562 563 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) 564 { 565 irqreturn_t ret_value = IRQ_NONE; 566 struct edac_device_ctl_info *dci = dev_id; 567 struct altr_edac_device_dev *drvdata = dci->pvt_info; 568 const struct edac_device_prv_data *priv = drvdata->data; 569 570 if (irq == drvdata->sb_irq) { 571 if (priv->ce_clear_mask) 572 writel(priv->ce_clear_mask, drvdata->base); 573 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name); 574 ret_value = IRQ_HANDLED; 575 } else if (irq == drvdata->db_irq) { 576 if (priv->ue_clear_mask) 577 writel(priv->ue_clear_mask, drvdata->base); 578 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name); 579 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 580 ret_value = IRQ_HANDLED; 581 } else { 582 WARN_ON(1); 583 } 584 585 return ret_value; 586 } 587 588 static ssize_t altr_edac_device_trig(struct file *file, 589 const char __user *user_buf, 590 size_t count, loff_t *ppos) 591 592 { 593 u32 *ptemp, i, error_mask; 594 int result = 0; 595 u8 trig_type; 596 unsigned long flags; 597 struct edac_device_ctl_info *edac_dci = file->private_data; 598 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 599 const struct edac_device_prv_data *priv = drvdata->data; 600 void *generic_ptr = edac_dci->dev; 601 602 if (!user_buf || get_user(trig_type, user_buf)) 603 return -EFAULT; 604 605 if (!priv->alloc_mem) 606 return -ENOMEM; 607 608 /* 609 * Note that generic_ptr is initialized to the device * but in 610 * some alloc_functions, this is overridden and returns data. 611 */ 612 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr); 613 if (!ptemp) { 614 edac_printk(KERN_ERR, EDAC_DEVICE, 615 "Inject: Buffer Allocation error\n"); 616 return -ENOMEM; 617 } 618 619 if (trig_type == ALTR_UE_TRIGGER_CHAR) 620 error_mask = priv->ue_set_mask; 621 else 622 error_mask = priv->ce_set_mask; 623 624 edac_printk(KERN_ALERT, EDAC_DEVICE, 625 "Trigger Error Mask (0x%X)\n", error_mask); 626 627 local_irq_save(flags); 628 /* write ECC corrupted data out. */ 629 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) { 630 /* Read data so we're in the correct state */ 631 rmb(); 632 if (ACCESS_ONCE(ptemp[i])) 633 result = -1; 634 /* Toggle Error bit (it is latched), leave ECC enabled */ 635 writel(error_mask, (drvdata->base + priv->set_err_ofst)); 636 writel(priv->ecc_enable_mask, (drvdata->base + 637 priv->set_err_ofst)); 638 ptemp[i] = i; 639 } 640 /* Ensure it has been written out */ 641 wmb(); 642 local_irq_restore(flags); 643 644 if (result) 645 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n"); 646 647 /* Read out written data. ECC error caused here */ 648 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++) 649 if (ACCESS_ONCE(ptemp[i]) != i) 650 edac_printk(KERN_ERR, EDAC_DEVICE, 651 "Read doesn't match written data\n"); 652 653 if (priv->free_mem) 654 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr); 655 656 return count; 657 } 658 659 static const struct file_operations altr_edac_device_inject_fops = { 660 .open = simple_open, 661 .write = altr_edac_device_trig, 662 .llseek = generic_file_llseek, 663 }; 664 665 static ssize_t altr_edac_a10_device_trig(struct file *file, 666 const char __user *user_buf, 667 size_t count, loff_t *ppos); 668 669 static const struct file_operations altr_edac_a10_device_inject_fops = { 670 .open = simple_open, 671 .write = altr_edac_a10_device_trig, 672 .llseek = generic_file_llseek, 673 }; 674 675 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci, 676 const struct edac_device_prv_data *priv) 677 { 678 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 679 680 if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) 681 return; 682 683 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name); 684 if (!drvdata->debugfs_dir) 685 return; 686 687 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR, 688 drvdata->debugfs_dir, edac_dci, 689 priv->inject_fops)) 690 debugfs_remove_recursive(drvdata->debugfs_dir); 691 } 692 693 static const struct of_device_id altr_edac_device_of_match[] = { 694 #ifdef CONFIG_EDAC_ALTERA_L2C 695 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data }, 696 #endif 697 #ifdef CONFIG_EDAC_ALTERA_OCRAM 698 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data }, 699 #endif 700 {}, 701 }; 702 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); 703 704 /* 705 * altr_edac_device_probe() 706 * This is a generic EDAC device driver that will support 707 * various Altera memory devices such as the L2 cache ECC and 708 * OCRAM ECC as well as the memories for other peripherals. 709 * Module specific initialization is done by passing the 710 * function index in the device tree. 711 */ 712 static int altr_edac_device_probe(struct platform_device *pdev) 713 { 714 struct edac_device_ctl_info *dci; 715 struct altr_edac_device_dev *drvdata; 716 struct resource *r; 717 int res = 0; 718 struct device_node *np = pdev->dev.of_node; 719 char *ecc_name = (char *)np->name; 720 static int dev_instance; 721 722 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { 723 edac_printk(KERN_ERR, EDAC_DEVICE, 724 "Unable to open devm\n"); 725 return -ENOMEM; 726 } 727 728 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 729 if (!r) { 730 edac_printk(KERN_ERR, EDAC_DEVICE, 731 "Unable to get mem resource\n"); 732 res = -ENODEV; 733 goto fail; 734 } 735 736 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), 737 dev_name(&pdev->dev))) { 738 edac_printk(KERN_ERR, EDAC_DEVICE, 739 "%s:Error requesting mem region\n", ecc_name); 740 res = -EBUSY; 741 goto fail; 742 } 743 744 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, 745 1, ecc_name, 1, 0, NULL, 0, 746 dev_instance++); 747 748 if (!dci) { 749 edac_printk(KERN_ERR, EDAC_DEVICE, 750 "%s: Unable to allocate EDAC device\n", ecc_name); 751 res = -ENOMEM; 752 goto fail; 753 } 754 755 drvdata = dci->pvt_info; 756 dci->dev = &pdev->dev; 757 platform_set_drvdata(pdev, dci); 758 drvdata->edac_dev_name = ecc_name; 759 760 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); 761 if (!drvdata->base) 762 goto fail1; 763 764 /* Get driver specific data for this EDAC device */ 765 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data; 766 767 /* Check specific dependencies for the module */ 768 if (drvdata->data->setup) { 769 res = drvdata->data->setup(drvdata); 770 if (res) 771 goto fail1; 772 } 773 774 drvdata->sb_irq = platform_get_irq(pdev, 0); 775 res = devm_request_irq(&pdev->dev, drvdata->sb_irq, 776 altr_edac_device_handler, 777 0, dev_name(&pdev->dev), dci); 778 if (res) 779 goto fail1; 780 781 drvdata->db_irq = platform_get_irq(pdev, 1); 782 res = devm_request_irq(&pdev->dev, drvdata->db_irq, 783 altr_edac_device_handler, 784 0, dev_name(&pdev->dev), dci); 785 if (res) 786 goto fail1; 787 788 dci->mod_name = "Altera ECC Manager"; 789 dci->dev_name = drvdata->edac_dev_name; 790 791 res = edac_device_add_device(dci); 792 if (res) 793 goto fail1; 794 795 altr_create_edacdev_dbgfs(dci, drvdata->data); 796 797 devres_close_group(&pdev->dev, NULL); 798 799 return 0; 800 801 fail1: 802 edac_device_free_ctl_info(dci); 803 fail: 804 devres_release_group(&pdev->dev, NULL); 805 edac_printk(KERN_ERR, EDAC_DEVICE, 806 "%s:Error setting up EDAC device: %d\n", ecc_name, res); 807 808 return res; 809 } 810 811 static int altr_edac_device_remove(struct platform_device *pdev) 812 { 813 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); 814 struct altr_edac_device_dev *drvdata = dci->pvt_info; 815 816 debugfs_remove_recursive(drvdata->debugfs_dir); 817 edac_device_del_device(&pdev->dev); 818 edac_device_free_ctl_info(dci); 819 820 return 0; 821 } 822 823 static struct platform_driver altr_edac_device_driver = { 824 .probe = altr_edac_device_probe, 825 .remove = altr_edac_device_remove, 826 .driver = { 827 .name = "altr_edac_device", 828 .of_match_table = altr_edac_device_of_match, 829 }, 830 }; 831 module_platform_driver(altr_edac_device_driver); 832 833 /******************* Arria10 Device ECC Shared Functions *****************/ 834 835 /* 836 * Test for memory's ECC dependencies upon entry because platform specific 837 * startup should have initialized the memory and enabled the ECC. 838 * Can't turn on ECC here because accessing un-initialized memory will 839 * cause CE/UE errors possibly causing an ABORT. 840 */ 841 static int __maybe_unused 842 altr_check_ecc_deps(struct altr_edac_device_dev *device) 843 { 844 void __iomem *base = device->base; 845 const struct edac_device_prv_data *prv = device->data; 846 847 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask) 848 return 0; 849 850 edac_printk(KERN_ERR, EDAC_DEVICE, 851 "%s: No ECC present or ECC disabled.\n", 852 device->edac_dev_name); 853 return -ENODEV; 854 } 855 856 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id) 857 { 858 struct altr_edac_device_dev *dci = dev_id; 859 void __iomem *base = dci->base; 860 861 if (irq == dci->sb_irq) { 862 writel(ALTR_A10_ECC_SERRPENA, 863 base + ALTR_A10_ECC_INTSTAT_OFST); 864 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); 865 866 return IRQ_HANDLED; 867 } else if (irq == dci->db_irq) { 868 writel(ALTR_A10_ECC_DERRPENA, 869 base + ALTR_A10_ECC_INTSTAT_OFST); 870 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); 871 if (dci->data->panic) 872 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 873 874 return IRQ_HANDLED; 875 } 876 877 WARN_ON(1); 878 879 return IRQ_NONE; 880 } 881 882 /******************* Arria10 Memory Buffer Functions *********************/ 883 884 static inline int a10_get_irq_mask(struct device_node *np) 885 { 886 int irq; 887 const u32 *handle = of_get_property(np, "interrupts", NULL); 888 889 if (!handle) 890 return -ENODEV; 891 irq = be32_to_cpup(handle); 892 return irq; 893 } 894 895 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr) 896 { 897 u32 value = readl(ioaddr); 898 899 value |= bit_mask; 900 writel(value, ioaddr); 901 } 902 903 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr) 904 { 905 u32 value = readl(ioaddr); 906 907 value &= ~bit_mask; 908 writel(value, ioaddr); 909 } 910 911 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr) 912 { 913 u32 value = readl(ioaddr); 914 915 return (value & bit_mask) ? 1 : 0; 916 } 917 918 /* 919 * This function uses the memory initialization block in the Arria10 ECC 920 * controller to initialize/clear the entire memory data and ECC data. 921 */ 922 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port) 923 { 924 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US; 925 u32 init_mask, stat_mask, clear_mask; 926 int ret = 0; 927 928 if (port) { 929 init_mask = ALTR_A10_ECC_INITB; 930 stat_mask = ALTR_A10_ECC_INITCOMPLETEB; 931 clear_mask = ALTR_A10_ECC_ERRPENB_MASK; 932 } else { 933 init_mask = ALTR_A10_ECC_INITA; 934 stat_mask = ALTR_A10_ECC_INITCOMPLETEA; 935 clear_mask = ALTR_A10_ECC_ERRPENA_MASK; 936 } 937 938 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST)); 939 while (limit--) { 940 if (ecc_test_bits(stat_mask, 941 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST))) 942 break; 943 udelay(1); 944 } 945 if (limit < 0) 946 ret = -EBUSY; 947 948 /* Clear any pending ECC interrupts */ 949 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST)); 950 951 return ret; 952 } 953 954 static __init int __maybe_unused 955 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask, 956 u32 ecc_ctrl_en_mask, bool dual_port) 957 { 958 int ret = 0; 959 void __iomem *ecc_block_base; 960 struct regmap *ecc_mgr_map; 961 char *ecc_name; 962 struct device_node *np_eccmgr; 963 964 ecc_name = (char *)np->name; 965 966 /* Get the ECC Manager - parent of the device EDACs */ 967 np_eccmgr = of_get_parent(np); 968 ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr, 969 "altr,sysmgr-syscon"); 970 of_node_put(np_eccmgr); 971 if (IS_ERR(ecc_mgr_map)) { 972 edac_printk(KERN_ERR, EDAC_DEVICE, 973 "Unable to get syscon altr,sysmgr-syscon\n"); 974 return -ENODEV; 975 } 976 977 /* Map the ECC Block */ 978 ecc_block_base = of_iomap(np, 0); 979 if (!ecc_block_base) { 980 edac_printk(KERN_ERR, EDAC_DEVICE, 981 "Unable to map %s ECC block\n", ecc_name); 982 return -ENODEV; 983 } 984 985 /* Disable ECC */ 986 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask); 987 writel(ALTR_A10_ECC_SERRINTEN, 988 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST)); 989 ecc_clear_bits(ecc_ctrl_en_mask, 990 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST)); 991 /* Ensure all writes complete */ 992 wmb(); 993 /* Use HW initialization block to initialize memory for ECC */ 994 ret = altr_init_memory_port(ecc_block_base, 0); 995 if (ret) { 996 edac_printk(KERN_ERR, EDAC_DEVICE, 997 "ECC: cannot init %s PORTA memory\n", ecc_name); 998 goto out; 999 } 1000 1001 if (dual_port) { 1002 ret = altr_init_memory_port(ecc_block_base, 1); 1003 if (ret) { 1004 edac_printk(KERN_ERR, EDAC_DEVICE, 1005 "ECC: cannot init %s PORTB memory\n", 1006 ecc_name); 1007 goto out; 1008 } 1009 } 1010 1011 /* Interrupt mode set to every SBERR */ 1012 regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST, 1013 ALTR_A10_ECC_INTMODE); 1014 /* Enable ECC */ 1015 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base + 1016 ALTR_A10_ECC_CTRL_OFST)); 1017 writel(ALTR_A10_ECC_SERRINTEN, 1018 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST)); 1019 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask); 1020 /* Ensure all writes complete */ 1021 wmb(); 1022 out: 1023 iounmap(ecc_block_base); 1024 return ret; 1025 } 1026 1027 static int validate_parent_available(struct device_node *np); 1028 static const struct of_device_id altr_edac_a10_device_of_match[]; 1029 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat) 1030 { 1031 int irq; 1032 struct device_node *child, *np = of_find_compatible_node(NULL, NULL, 1033 "altr,socfpga-a10-ecc-manager"); 1034 if (!np) { 1035 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n"); 1036 return -ENODEV; 1037 } 1038 1039 for_each_child_of_node(np, child) { 1040 const struct of_device_id *pdev_id; 1041 const struct edac_device_prv_data *prv; 1042 1043 if (!of_device_is_available(child)) 1044 continue; 1045 if (!of_device_is_compatible(child, compat)) 1046 continue; 1047 1048 if (validate_parent_available(child)) 1049 continue; 1050 1051 irq = a10_get_irq_mask(child); 1052 if (irq < 0) 1053 continue; 1054 1055 /* Get matching node and check for valid result */ 1056 pdev_id = of_match_node(altr_edac_a10_device_of_match, child); 1057 if (IS_ERR_OR_NULL(pdev_id)) 1058 continue; 1059 1060 /* Validate private data pointer before dereferencing */ 1061 prv = pdev_id->data; 1062 if (!prv) 1063 continue; 1064 1065 altr_init_a10_ecc_block(child, BIT(irq), 1066 prv->ecc_enable_mask, 0); 1067 } 1068 1069 of_node_put(np); 1070 return 0; 1071 } 1072 1073 /*********************** OCRAM EDAC Device Functions *********************/ 1074 1075 #ifdef CONFIG_EDAC_ALTERA_OCRAM 1076 1077 static void *ocram_alloc_mem(size_t size, void **other) 1078 { 1079 struct device_node *np; 1080 struct gen_pool *gp; 1081 void *sram_addr; 1082 1083 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); 1084 if (!np) 1085 return NULL; 1086 1087 gp = of_gen_pool_get(np, "iram", 0); 1088 of_node_put(np); 1089 if (!gp) 1090 return NULL; 1091 1092 sram_addr = (void *)gen_pool_alloc(gp, size); 1093 if (!sram_addr) 1094 return NULL; 1095 1096 memset(sram_addr, 0, size); 1097 /* Ensure data is written out */ 1098 wmb(); 1099 1100 /* Remember this handle for freeing later */ 1101 *other = gp; 1102 1103 return sram_addr; 1104 } 1105 1106 static void ocram_free_mem(void *p, size_t size, void *other) 1107 { 1108 gen_pool_free((struct gen_pool *)other, (u32)p, size); 1109 } 1110 1111 static const struct edac_device_prv_data ocramecc_data = { 1112 .setup = altr_check_ecc_deps, 1113 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR), 1114 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR), 1115 .alloc_mem = ocram_alloc_mem, 1116 .free_mem = ocram_free_mem, 1117 .ecc_enable_mask = ALTR_OCR_ECC_EN, 1118 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET, 1119 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS), 1120 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD), 1121 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET, 1122 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE, 1123 .inject_fops = &altr_edac_device_inject_fops, 1124 }; 1125 1126 static const struct edac_device_prv_data a10_ocramecc_data = { 1127 .setup = altr_check_ecc_deps, 1128 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1129 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1130 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM, 1131 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL, 1132 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1133 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1134 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1135 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1136 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1137 .inject_fops = &altr_edac_a10_device_inject_fops, 1138 /* 1139 * OCRAM panic on uncorrectable error because sleep/resume 1140 * functions and FPGA contents are stored in OCRAM. Prefer 1141 * a kernel panic over executing/loading corrupted data. 1142 */ 1143 .panic = true, 1144 }; 1145 1146 #endif /* CONFIG_EDAC_ALTERA_OCRAM */ 1147 1148 /********************* L2 Cache EDAC Device Functions ********************/ 1149 1150 #ifdef CONFIG_EDAC_ALTERA_L2C 1151 1152 static void *l2_alloc_mem(size_t size, void **other) 1153 { 1154 struct device *dev = *other; 1155 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL); 1156 1157 if (!ptemp) 1158 return NULL; 1159 1160 /* Make sure everything is written out */ 1161 wmb(); 1162 1163 /* 1164 * Clean all cache levels up to LoC (includes L2) 1165 * This ensures the corrupted data is written into 1166 * L2 cache for readback test (which causes ECC error). 1167 */ 1168 flush_cache_all(); 1169 1170 return ptemp; 1171 } 1172 1173 static void l2_free_mem(void *p, size_t size, void *other) 1174 { 1175 struct device *dev = other; 1176 1177 if (dev && p) 1178 devm_kfree(dev, p); 1179 } 1180 1181 /* 1182 * altr_l2_check_deps() 1183 * Test for L2 cache ECC dependencies upon entry because 1184 * platform specific startup should have initialized the L2 1185 * memory and enabled the ECC. 1186 * Bail if ECC is not enabled. 1187 * Note that L2 Cache Enable is forced at build time. 1188 */ 1189 static int altr_l2_check_deps(struct altr_edac_device_dev *device) 1190 { 1191 void __iomem *base = device->base; 1192 const struct edac_device_prv_data *prv = device->data; 1193 1194 if ((readl(base) & prv->ecc_enable_mask) == 1195 prv->ecc_enable_mask) 1196 return 0; 1197 1198 edac_printk(KERN_ERR, EDAC_DEVICE, 1199 "L2: No ECC present, or ECC disabled\n"); 1200 return -ENODEV; 1201 } 1202 1203 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id) 1204 { 1205 struct altr_edac_device_dev *dci = dev_id; 1206 1207 if (irq == dci->sb_irq) { 1208 regmap_write(dci->edac->ecc_mgr_map, 1209 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, 1210 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB); 1211 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); 1212 1213 return IRQ_HANDLED; 1214 } else if (irq == dci->db_irq) { 1215 regmap_write(dci->edac->ecc_mgr_map, 1216 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, 1217 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB); 1218 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); 1219 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 1220 1221 return IRQ_HANDLED; 1222 } 1223 1224 WARN_ON(1); 1225 1226 return IRQ_NONE; 1227 } 1228 1229 static const struct edac_device_prv_data l2ecc_data = { 1230 .setup = altr_l2_check_deps, 1231 .ce_clear_mask = 0, 1232 .ue_clear_mask = 0, 1233 .alloc_mem = l2_alloc_mem, 1234 .free_mem = l2_free_mem, 1235 .ecc_enable_mask = ALTR_L2_ECC_EN, 1236 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS), 1237 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD), 1238 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET, 1239 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, 1240 .inject_fops = &altr_edac_device_inject_fops, 1241 }; 1242 1243 static const struct edac_device_prv_data a10_l2ecc_data = { 1244 .setup = altr_l2_check_deps, 1245 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR, 1246 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR, 1247 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2, 1248 .alloc_mem = l2_alloc_mem, 1249 .free_mem = l2_free_mem, 1250 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL, 1251 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK, 1252 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK, 1253 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST, 1254 .ecc_irq_handler = altr_edac_a10_l2_irq, 1255 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, 1256 .inject_fops = &altr_edac_device_inject_fops, 1257 }; 1258 1259 #endif /* CONFIG_EDAC_ALTERA_L2C */ 1260 1261 /********************* Ethernet Device Functions ********************/ 1262 1263 #ifdef CONFIG_EDAC_ALTERA_ETHERNET 1264 1265 static const struct edac_device_prv_data a10_enetecc_data = { 1266 .setup = altr_check_ecc_deps, 1267 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1268 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1269 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1270 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1271 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1272 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1273 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1274 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1275 .inject_fops = &altr_edac_a10_device_inject_fops, 1276 }; 1277 1278 static int __init socfpga_init_ethernet_ecc(void) 1279 { 1280 return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc"); 1281 } 1282 1283 early_initcall(socfpga_init_ethernet_ecc); 1284 1285 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */ 1286 1287 /********************** NAND Device Functions **********************/ 1288 1289 #ifdef CONFIG_EDAC_ALTERA_NAND 1290 1291 static const struct edac_device_prv_data a10_nandecc_data = { 1292 .setup = altr_check_ecc_deps, 1293 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1294 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1295 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1296 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1297 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1298 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1299 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1300 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1301 .inject_fops = &altr_edac_a10_device_inject_fops, 1302 }; 1303 1304 static int __init socfpga_init_nand_ecc(void) 1305 { 1306 return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc"); 1307 } 1308 1309 early_initcall(socfpga_init_nand_ecc); 1310 1311 #endif /* CONFIG_EDAC_ALTERA_NAND */ 1312 1313 /********************** DMA Device Functions **********************/ 1314 1315 #ifdef CONFIG_EDAC_ALTERA_DMA 1316 1317 static const struct edac_device_prv_data a10_dmaecc_data = { 1318 .setup = altr_check_ecc_deps, 1319 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1320 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1321 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1322 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1323 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1324 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1325 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1326 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1327 .inject_fops = &altr_edac_a10_device_inject_fops, 1328 }; 1329 1330 static int __init socfpga_init_dma_ecc(void) 1331 { 1332 return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc"); 1333 } 1334 1335 early_initcall(socfpga_init_dma_ecc); 1336 1337 #endif /* CONFIG_EDAC_ALTERA_DMA */ 1338 1339 /********************** USB Device Functions **********************/ 1340 1341 #ifdef CONFIG_EDAC_ALTERA_USB 1342 1343 static const struct edac_device_prv_data a10_usbecc_data = { 1344 .setup = altr_check_ecc_deps, 1345 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1346 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1347 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1348 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1349 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1350 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1351 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1352 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1353 .inject_fops = &altr_edac_a10_device_inject_fops, 1354 }; 1355 1356 static int __init socfpga_init_usb_ecc(void) 1357 { 1358 return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc"); 1359 } 1360 1361 early_initcall(socfpga_init_usb_ecc); 1362 1363 #endif /* CONFIG_EDAC_ALTERA_USB */ 1364 1365 /********************** QSPI Device Functions **********************/ 1366 1367 #ifdef CONFIG_EDAC_ALTERA_QSPI 1368 1369 static const struct edac_device_prv_data a10_qspiecc_data = { 1370 .setup = altr_check_ecc_deps, 1371 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1372 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1373 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1374 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1375 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1376 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1377 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1378 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1379 .inject_fops = &altr_edac_a10_device_inject_fops, 1380 }; 1381 1382 static int __init socfpga_init_qspi_ecc(void) 1383 { 1384 return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc"); 1385 } 1386 1387 early_initcall(socfpga_init_qspi_ecc); 1388 1389 #endif /* CONFIG_EDAC_ALTERA_QSPI */ 1390 1391 /********************* SDMMC Device Functions **********************/ 1392 1393 #ifdef CONFIG_EDAC_ALTERA_SDMMC 1394 1395 static const struct edac_device_prv_data a10_sdmmceccb_data; 1396 static int altr_portb_setup(struct altr_edac_device_dev *device) 1397 { 1398 struct edac_device_ctl_info *dci; 1399 struct altr_edac_device_dev *altdev; 1400 char *ecc_name = "sdmmcb-ecc"; 1401 int edac_idx, rc; 1402 struct device_node *np; 1403 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data; 1404 1405 rc = altr_check_ecc_deps(device); 1406 if (rc) 1407 return rc; 1408 1409 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); 1410 if (!np) { 1411 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); 1412 return -ENODEV; 1413 } 1414 1415 /* Create the PortB EDAC device */ 1416 edac_idx = edac_device_alloc_index(); 1417 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1, 1418 ecc_name, 1, 0, NULL, 0, edac_idx); 1419 if (!dci) { 1420 edac_printk(KERN_ERR, EDAC_DEVICE, 1421 "%s: Unable to allocate PortB EDAC device\n", 1422 ecc_name); 1423 return -ENOMEM; 1424 } 1425 1426 /* Initialize the PortB EDAC device structure from PortA structure */ 1427 altdev = dci->pvt_info; 1428 *altdev = *device; 1429 1430 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL)) 1431 return -ENOMEM; 1432 1433 /* Update PortB specific values */ 1434 altdev->edac_dev_name = ecc_name; 1435 altdev->edac_idx = edac_idx; 1436 altdev->edac_dev = dci; 1437 altdev->data = prv; 1438 dci->dev = &altdev->ddev; 1439 dci->ctl_name = "Altera ECC Manager"; 1440 dci->mod_name = ecc_name; 1441 dci->dev_name = ecc_name; 1442 1443 /* Update the IRQs for PortB */ 1444 altdev->sb_irq = irq_of_parse_and_map(np, 2); 1445 if (!altdev->sb_irq) { 1446 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n"); 1447 rc = -ENODEV; 1448 goto err_release_group_1; 1449 } 1450 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq, 1451 prv->ecc_irq_handler, 1452 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1453 ecc_name, altdev); 1454 if (rc) { 1455 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n"); 1456 goto err_release_group_1; 1457 } 1458 1459 altdev->db_irq = irq_of_parse_and_map(np, 3); 1460 if (!altdev->db_irq) { 1461 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n"); 1462 rc = -ENODEV; 1463 goto err_release_group_1; 1464 } 1465 rc = devm_request_irq(&altdev->ddev, altdev->db_irq, 1466 prv->ecc_irq_handler, 1467 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1468 ecc_name, altdev); 1469 if (rc) { 1470 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n"); 1471 goto err_release_group_1; 1472 } 1473 1474 rc = edac_device_add_device(dci); 1475 if (rc) { 1476 edac_printk(KERN_ERR, EDAC_DEVICE, 1477 "edac_device_add_device portB failed\n"); 1478 rc = -ENOMEM; 1479 goto err_release_group_1; 1480 } 1481 altr_create_edacdev_dbgfs(dci, prv); 1482 1483 list_add(&altdev->next, &altdev->edac->a10_ecc_devices); 1484 1485 devres_remove_group(&altdev->ddev, altr_portb_setup); 1486 1487 return 0; 1488 1489 err_release_group_1: 1490 edac_device_free_ctl_info(dci); 1491 devres_release_group(&altdev->ddev, altr_portb_setup); 1492 edac_printk(KERN_ERR, EDAC_DEVICE, 1493 "%s:Error setting up EDAC device: %d\n", ecc_name, rc); 1494 return rc; 1495 } 1496 1497 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id) 1498 { 1499 struct altr_edac_device_dev *ad = dev_id; 1500 void __iomem *base = ad->base; 1501 const struct edac_device_prv_data *priv = ad->data; 1502 1503 if (irq == ad->sb_irq) { 1504 writel(priv->ce_clear_mask, 1505 base + ALTR_A10_ECC_INTSTAT_OFST); 1506 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name); 1507 return IRQ_HANDLED; 1508 } else if (irq == ad->db_irq) { 1509 writel(priv->ue_clear_mask, 1510 base + ALTR_A10_ECC_INTSTAT_OFST); 1511 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name); 1512 return IRQ_HANDLED; 1513 } 1514 1515 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq); 1516 1517 return IRQ_NONE; 1518 } 1519 1520 static const struct edac_device_prv_data a10_sdmmcecca_data = { 1521 .setup = altr_portb_setup, 1522 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1523 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1524 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1525 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1526 .ce_set_mask = ALTR_A10_ECC_SERRPENA, 1527 .ue_set_mask = ALTR_A10_ECC_DERRPENA, 1528 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1529 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1530 .inject_fops = &altr_edac_a10_device_inject_fops, 1531 }; 1532 1533 static const struct edac_device_prv_data a10_sdmmceccb_data = { 1534 .setup = altr_portb_setup, 1535 .ce_clear_mask = ALTR_A10_ECC_SERRPENB, 1536 .ue_clear_mask = ALTR_A10_ECC_DERRPENB, 1537 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1538 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1539 .ce_set_mask = ALTR_A10_ECC_TSERRB, 1540 .ue_set_mask = ALTR_A10_ECC_TDERRB, 1541 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1542 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb, 1543 .inject_fops = &altr_edac_a10_device_inject_fops, 1544 }; 1545 1546 static int __init socfpga_init_sdmmc_ecc(void) 1547 { 1548 int rc = -ENODEV; 1549 struct device_node *child = of_find_compatible_node(NULL, NULL, 1550 "altr,socfpga-sdmmc-ecc"); 1551 if (!child) { 1552 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); 1553 return -ENODEV; 1554 } 1555 1556 if (!of_device_is_available(child)) 1557 goto exit; 1558 1559 if (validate_parent_available(child)) 1560 goto exit; 1561 1562 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK, 1563 a10_sdmmcecca_data.ecc_enable_mask, 1); 1564 exit: 1565 of_node_put(child); 1566 return rc; 1567 } 1568 1569 early_initcall(socfpga_init_sdmmc_ecc); 1570 1571 #endif /* CONFIG_EDAC_ALTERA_SDMMC */ 1572 1573 /********************* Arria10 EDAC Device Functions *************************/ 1574 static const struct of_device_id altr_edac_a10_device_of_match[] = { 1575 #ifdef CONFIG_EDAC_ALTERA_L2C 1576 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data }, 1577 #endif 1578 #ifdef CONFIG_EDAC_ALTERA_OCRAM 1579 { .compatible = "altr,socfpga-a10-ocram-ecc", 1580 .data = &a10_ocramecc_data }, 1581 #endif 1582 #ifdef CONFIG_EDAC_ALTERA_ETHERNET 1583 { .compatible = "altr,socfpga-eth-mac-ecc", 1584 .data = &a10_enetecc_data }, 1585 #endif 1586 #ifdef CONFIG_EDAC_ALTERA_NAND 1587 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data }, 1588 #endif 1589 #ifdef CONFIG_EDAC_ALTERA_DMA 1590 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data }, 1591 #endif 1592 #ifdef CONFIG_EDAC_ALTERA_USB 1593 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data }, 1594 #endif 1595 #ifdef CONFIG_EDAC_ALTERA_QSPI 1596 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data }, 1597 #endif 1598 #ifdef CONFIG_EDAC_ALTERA_SDMMC 1599 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data }, 1600 #endif 1601 {}, 1602 }; 1603 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match); 1604 1605 /* 1606 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5 1607 * because 2 IRQs are shared among the all ECC peripherals. The ECC 1608 * manager manages the IRQs and the children. 1609 * Based on xgene_edac.c peripheral code. 1610 */ 1611 1612 static ssize_t altr_edac_a10_device_trig(struct file *file, 1613 const char __user *user_buf, 1614 size_t count, loff_t *ppos) 1615 { 1616 struct edac_device_ctl_info *edac_dci = file->private_data; 1617 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 1618 const struct edac_device_prv_data *priv = drvdata->data; 1619 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); 1620 unsigned long flags; 1621 u8 trig_type; 1622 1623 if (!user_buf || get_user(trig_type, user_buf)) 1624 return -EFAULT; 1625 1626 local_irq_save(flags); 1627 if (trig_type == ALTR_UE_TRIGGER_CHAR) 1628 writel(priv->ue_set_mask, set_addr); 1629 else 1630 writel(priv->ce_set_mask, set_addr); 1631 /* Ensure the interrupt test bits are set */ 1632 wmb(); 1633 local_irq_restore(flags); 1634 1635 return count; 1636 } 1637 1638 static void altr_edac_a10_irq_handler(struct irq_desc *desc) 1639 { 1640 int dberr, bit, sm_offset, irq_status; 1641 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc); 1642 struct irq_chip *chip = irq_desc_get_chip(desc); 1643 int irq = irq_desc_get_irq(desc); 1644 1645 dberr = (irq == edac->db_irq) ? 1 : 0; 1646 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST : 1647 A10_SYSMGR_ECC_INTSTAT_SERR_OFST; 1648 1649 chained_irq_enter(chip, desc); 1650 1651 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status); 1652 1653 for_each_set_bit(bit, (unsigned long *)&irq_status, 32) { 1654 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit); 1655 if (irq) 1656 generic_handle_irq(irq); 1657 } 1658 1659 chained_irq_exit(chip, desc); 1660 } 1661 1662 static int validate_parent_available(struct device_node *np) 1663 { 1664 struct device_node *parent; 1665 int ret = 0; 1666 1667 /* Ensure parent device is enabled if parent node exists */ 1668 parent = of_parse_phandle(np, "altr,ecc-parent", 0); 1669 if (parent && !of_device_is_available(parent)) 1670 ret = -ENODEV; 1671 1672 of_node_put(parent); 1673 return ret; 1674 } 1675 1676 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac, 1677 struct device_node *np) 1678 { 1679 struct edac_device_ctl_info *dci; 1680 struct altr_edac_device_dev *altdev; 1681 char *ecc_name = (char *)np->name; 1682 struct resource res; 1683 int edac_idx; 1684 int rc = 0; 1685 const struct edac_device_prv_data *prv; 1686 /* Get matching node and check for valid result */ 1687 const struct of_device_id *pdev_id = 1688 of_match_node(altr_edac_a10_device_of_match, np); 1689 if (IS_ERR_OR_NULL(pdev_id)) 1690 return -ENODEV; 1691 1692 /* Get driver specific data for this EDAC device */ 1693 prv = pdev_id->data; 1694 if (IS_ERR_OR_NULL(prv)) 1695 return -ENODEV; 1696 1697 if (validate_parent_available(np)) 1698 return -ENODEV; 1699 1700 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL)) 1701 return -ENOMEM; 1702 1703 rc = of_address_to_resource(np, 0, &res); 1704 if (rc < 0) { 1705 edac_printk(KERN_ERR, EDAC_DEVICE, 1706 "%s: no resource address\n", ecc_name); 1707 goto err_release_group; 1708 } 1709 1710 edac_idx = edac_device_alloc_index(); 1711 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1712 1, ecc_name, 1, 0, NULL, 0, 1713 edac_idx); 1714 1715 if (!dci) { 1716 edac_printk(KERN_ERR, EDAC_DEVICE, 1717 "%s: Unable to allocate EDAC device\n", ecc_name); 1718 rc = -ENOMEM; 1719 goto err_release_group; 1720 } 1721 1722 altdev = dci->pvt_info; 1723 dci->dev = edac->dev; 1724 altdev->edac_dev_name = ecc_name; 1725 altdev->edac_idx = edac_idx; 1726 altdev->edac = edac; 1727 altdev->edac_dev = dci; 1728 altdev->data = prv; 1729 altdev->ddev = *edac->dev; 1730 dci->dev = &altdev->ddev; 1731 dci->ctl_name = "Altera ECC Manager"; 1732 dci->mod_name = ecc_name; 1733 dci->dev_name = ecc_name; 1734 1735 altdev->base = devm_ioremap_resource(edac->dev, &res); 1736 if (IS_ERR(altdev->base)) { 1737 rc = PTR_ERR(altdev->base); 1738 goto err_release_group1; 1739 } 1740 1741 /* Check specific dependencies for the module */ 1742 if (altdev->data->setup) { 1743 rc = altdev->data->setup(altdev); 1744 if (rc) 1745 goto err_release_group1; 1746 } 1747 1748 altdev->sb_irq = irq_of_parse_and_map(np, 0); 1749 if (!altdev->sb_irq) { 1750 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n"); 1751 rc = -ENODEV; 1752 goto err_release_group1; 1753 } 1754 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler, 1755 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1756 ecc_name, altdev); 1757 if (rc) { 1758 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n"); 1759 goto err_release_group1; 1760 } 1761 1762 altdev->db_irq = irq_of_parse_and_map(np, 1); 1763 if (!altdev->db_irq) { 1764 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n"); 1765 rc = -ENODEV; 1766 goto err_release_group1; 1767 } 1768 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler, 1769 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1770 ecc_name, altdev); 1771 if (rc) { 1772 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n"); 1773 goto err_release_group1; 1774 } 1775 1776 rc = edac_device_add_device(dci); 1777 if (rc) { 1778 dev_err(edac->dev, "edac_device_add_device failed\n"); 1779 rc = -ENOMEM; 1780 goto err_release_group1; 1781 } 1782 1783 altr_create_edacdev_dbgfs(dci, prv); 1784 1785 list_add(&altdev->next, &edac->a10_ecc_devices); 1786 1787 devres_remove_group(edac->dev, altr_edac_a10_device_add); 1788 1789 return 0; 1790 1791 err_release_group1: 1792 edac_device_free_ctl_info(dci); 1793 err_release_group: 1794 devres_release_group(edac->dev, NULL); 1795 edac_printk(KERN_ERR, EDAC_DEVICE, 1796 "%s:Error setting up EDAC device: %d\n", ecc_name, rc); 1797 1798 return rc; 1799 } 1800 1801 static void a10_eccmgr_irq_mask(struct irq_data *d) 1802 { 1803 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); 1804 1805 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, 1806 BIT(d->hwirq)); 1807 } 1808 1809 static void a10_eccmgr_irq_unmask(struct irq_data *d) 1810 { 1811 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); 1812 1813 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, 1814 BIT(d->hwirq)); 1815 } 1816 1817 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq, 1818 irq_hw_number_t hwirq) 1819 { 1820 struct altr_arria10_edac *edac = d->host_data; 1821 1822 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq); 1823 irq_set_chip_data(irq, edac); 1824 irq_set_noprobe(irq); 1825 1826 return 0; 1827 } 1828 1829 static struct irq_domain_ops a10_eccmgr_ic_ops = { 1830 .map = a10_eccmgr_irqdomain_map, 1831 .xlate = irq_domain_xlate_twocell, 1832 }; 1833 1834 static int altr_edac_a10_probe(struct platform_device *pdev) 1835 { 1836 struct altr_arria10_edac *edac; 1837 struct device_node *child; 1838 1839 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL); 1840 if (!edac) 1841 return -ENOMEM; 1842 1843 edac->dev = &pdev->dev; 1844 platform_set_drvdata(pdev, edac); 1845 INIT_LIST_HEAD(&edac->a10_ecc_devices); 1846 1847 edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1848 "altr,sysmgr-syscon"); 1849 if (IS_ERR(edac->ecc_mgr_map)) { 1850 edac_printk(KERN_ERR, EDAC_DEVICE, 1851 "Unable to get syscon altr,sysmgr-syscon\n"); 1852 return PTR_ERR(edac->ecc_mgr_map); 1853 } 1854 1855 edac->irq_chip.name = pdev->dev.of_node->name; 1856 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask; 1857 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask; 1858 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64, 1859 &a10_eccmgr_ic_ops, edac); 1860 if (!edac->domain) { 1861 dev_err(&pdev->dev, "Error adding IRQ domain\n"); 1862 return -ENOMEM; 1863 } 1864 1865 edac->sb_irq = platform_get_irq(pdev, 0); 1866 if (edac->sb_irq < 0) { 1867 dev_err(&pdev->dev, "No SBERR IRQ resource\n"); 1868 return edac->sb_irq; 1869 } 1870 1871 irq_set_chained_handler_and_data(edac->sb_irq, 1872 altr_edac_a10_irq_handler, 1873 edac); 1874 1875 edac->db_irq = platform_get_irq(pdev, 1); 1876 if (edac->db_irq < 0) { 1877 dev_err(&pdev->dev, "No DBERR IRQ resource\n"); 1878 return edac->db_irq; 1879 } 1880 irq_set_chained_handler_and_data(edac->db_irq, 1881 altr_edac_a10_irq_handler, 1882 edac); 1883 1884 for_each_child_of_node(pdev->dev.of_node, child) { 1885 if (!of_device_is_available(child)) 1886 continue; 1887 1888 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") || 1889 of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") || 1890 of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") || 1891 of_device_is_compatible(child, "altr,socfpga-nand-ecc") || 1892 of_device_is_compatible(child, "altr,socfpga-dma-ecc") || 1893 of_device_is_compatible(child, "altr,socfpga-usb-ecc") || 1894 of_device_is_compatible(child, "altr,socfpga-qspi-ecc") || 1895 of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc")) 1896 1897 altr_edac_a10_device_add(edac, child); 1898 1899 else if (of_device_is_compatible(child, "altr,sdram-edac-a10")) 1900 of_platform_populate(pdev->dev.of_node, 1901 altr_sdram_ctrl_of_match, 1902 NULL, &pdev->dev); 1903 } 1904 1905 return 0; 1906 } 1907 1908 static const struct of_device_id altr_edac_a10_of_match[] = { 1909 { .compatible = "altr,socfpga-a10-ecc-manager" }, 1910 {}, 1911 }; 1912 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match); 1913 1914 static struct platform_driver altr_edac_a10_driver = { 1915 .probe = altr_edac_a10_probe, 1916 .driver = { 1917 .name = "socfpga_a10_ecc_manager", 1918 .of_match_table = altr_edac_a10_of_match, 1919 }, 1920 }; 1921 module_platform_driver(altr_edac_a10_driver); 1922 1923 MODULE_LICENSE("GPL v2"); 1924 MODULE_AUTHOR("Thor Thayer"); 1925 MODULE_DESCRIPTION("EDAC Driver for Altera Memories"); 1926