1584ec227SDan Williams /* 2584ec227SDan Williams * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3584ec227SDan Williams * 4584ec227SDan Williams * This program is free software; you can redistribute it and/or modify it 5584ec227SDan Williams * under the terms of the GNU General Public License as published by the Free 6584ec227SDan Williams * Software Foundation; either version 2 of the License, or (at your option) 7584ec227SDan Williams * any later version. 8584ec227SDan Williams * 9584ec227SDan Williams * This program is distributed in the hope that it will be useful, but WITHOUT 10584ec227SDan Williams * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11584ec227SDan Williams * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12584ec227SDan Williams * more details. 13584ec227SDan Williams * 14584ec227SDan Williams * You should have received a copy of the GNU General Public License along with 15584ec227SDan Williams * this program; if not, write to the Free Software Foundation, Inc., 59 16584ec227SDan Williams * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17584ec227SDan Williams * 18584ec227SDan Williams * The full GNU General Public License is included in this distribution in the 19584ec227SDan Williams * file called COPYING. 20584ec227SDan Williams */ 21584ec227SDan Williams #ifndef _IOAT_REGISTERS_H_ 22584ec227SDan Williams #define _IOAT_REGISTERS_H_ 23584ec227SDan Williams 24584ec227SDan Williams #define IOAT_PCI_DMACTRL_OFFSET 0x48 25584ec227SDan Williams #define IOAT_PCI_DMACTRL_DMA_EN 0x00000001 26584ec227SDan Williams #define IOAT_PCI_DMACTRL_MSI_EN 0x00000002 27584ec227SDan Williams 28584ec227SDan Williams #define IOAT_PCI_DEVICE_ID_OFFSET 0x02 29584ec227SDan Williams #define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148 30a6d52d70SDan Williams #define IOAT_PCI_CHANERR_INT_OFFSET 0x180 31584ec227SDan Williams #define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184 32584ec227SDan Williams 33584ec227SDan Williams /* MMIO Device Registers */ 34584ec227SDan Williams #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */ 35584ec227SDan Williams 36584ec227SDan Williams #define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */ 37584ec227SDan Williams #define IOAT_XFERCAP_4KB 12 38584ec227SDan Williams #define IOAT_XFERCAP_8KB 13 39584ec227SDan Williams #define IOAT_XFERCAP_16KB 14 40584ec227SDan Williams #define IOAT_XFERCAP_32KB 15 41584ec227SDan Williams #define IOAT_XFERCAP_32GB 0 42584ec227SDan Williams 43584ec227SDan Williams #define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */ 44584ec227SDan Williams #define IOAT_GENCTRL_DEBUG_EN 0x01 45584ec227SDan Williams 46584ec227SDan Williams #define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */ 47584ec227SDan Williams #define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */ 48584ec227SDan Williams #define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */ 49584ec227SDan Williams #define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */ 50584ec227SDan Williams #define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */ 51584ec227SDan Williams 52584ec227SDan Williams #define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */ 53584ec227SDan Williams 54584ec227SDan Williams #define IOAT_VER_OFFSET 0x08 /* 8-bit */ 55584ec227SDan Williams #define IOAT_VER_MAJOR_MASK 0xF0 56584ec227SDan Williams #define IOAT_VER_MINOR_MASK 0x0F 57584ec227SDan Williams #define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4) 58584ec227SDan Williams #define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK) 59584ec227SDan Williams 60584ec227SDan Williams #define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */ 61584ec227SDan Williams 62584ec227SDan Williams #define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */ 63b9cc9869SDan Williams #define IOAT_INTRDELAY_MASK 0x3FFF /* Interrupt Delay Time */ 64584ec227SDan Williams #define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */ 65584ec227SDan Williams 66584ec227SDan Williams #define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */ 67584ec227SDan Williams #define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001 682aec048cSDan Williams #define IOAT_DEVICE_MMIO_RESTRICTED 0x0002 692aec048cSDan Williams #define IOAT_DEVICE_MEMORY_BYPASS 0x0004 702aec048cSDan Williams #define IOAT_DEVICE_ADDRESS_REMAPPING 0x0008 712aec048cSDan Williams 722aec048cSDan Williams #define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */ 732aec048cSDan Williams #define IOAT_CAP_PAGE_BREAK 0x00000001 742aec048cSDan Williams #define IOAT_CAP_CRC 0x00000002 752aec048cSDan Williams #define IOAT_CAP_SKIP_MARKER 0x00000004 762aec048cSDan Williams #define IOAT_CAP_DCA 0x00000010 772aec048cSDan Williams #define IOAT_CAP_CRC_MOVE 0x00000020 782aec048cSDan Williams #define IOAT_CAP_FILL_BLOCK 0x00000040 792aec048cSDan Williams #define IOAT_CAP_APIC 0x00000080 802aec048cSDan Williams #define IOAT_CAP_XOR 0x00000100 812aec048cSDan Williams #define IOAT_CAP_PQ 0x00000200 82584ec227SDan Williams 83584ec227SDan Williams #define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ 84584ec227SDan Williams 85584ec227SDan Williams /* DMA Channel Registers */ 86584ec227SDan Williams #define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */ 87584ec227SDan Williams #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 88e61dacaeSDan Williams #define IOAT3_CHANCTRL_COMPL_DCA_EN 0x0200 89584ec227SDan Williams #define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 90584ec227SDan Williams #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 91584ec227SDan Williams #define IOAT_CHANCTRL_ERR_INT_EN 0x0010 92584ec227SDan Williams #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 93584ec227SDan Williams #define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 94f6ab95b5SDan Williams #define IOAT_CHANCTRL_INT_REARM 0x0001 95f6ab95b5SDan Williams #define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ 96*3f09ede4SDave Jiang IOAT_CHANCTRL_ERR_INT_EN |\ 97*3f09ede4SDave Jiang IOAT_CHANCTRL_ERR_COMPLETION_EN |\ 986f82b83bSDan Williams IOAT_CHANCTRL_ANY_ERR_ABORT_EN) 99584ec227SDan Williams 100584ec227SDan Williams #define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */ 101584ec227SDan Williams #define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ 102584ec227SDan Williams #define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */ 103584ec227SDan Williams 104584ec227SDan Williams 105584ec227SDan Williams #define IOAT1_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */ 106584ec227SDan Williams #define IOAT2_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ 107584ec227SDan Williams #define IOAT_CHANSTS_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 108584ec227SDan Williams ? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET) 109584ec227SDan Williams #define IOAT1_CHANSTS_OFFSET_LOW 0x04 110584ec227SDan Williams #define IOAT2_CHANSTS_OFFSET_LOW 0x08 111584ec227SDan Williams #define IOAT_CHANSTS_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ 112584ec227SDan Williams ? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW) 113584ec227SDan Williams #define IOAT1_CHANSTS_OFFSET_HIGH 0x08 114584ec227SDan Williams #define IOAT2_CHANSTS_OFFSET_HIGH 0x0C 115584ec227SDan Williams #define IOAT_CHANSTS_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ 116584ec227SDan Williams ? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH) 1174fb9b9e8SDan Williams #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL) 1184fb9b9e8SDan Williams #define IOAT_CHANSTS_SOFT_ERR 0x10ULL 1194fb9b9e8SDan Williams #define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL 12009c8a5b8SDan Williams #define IOAT_CHANSTS_STATUS 0x7ULL 12109c8a5b8SDan Williams #define IOAT_CHANSTS_ACTIVE 0x0 12209c8a5b8SDan Williams #define IOAT_CHANSTS_DONE 0x1 12309c8a5b8SDan Williams #define IOAT_CHANSTS_SUSPENDED 0x2 12409c8a5b8SDan Williams #define IOAT_CHANSTS_HALTED 0x3 125584ec227SDan Williams 126584ec227SDan Williams 127584ec227SDan Williams 128584ec227SDan Williams #define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */ 129584ec227SDan Williams 130584ec227SDan Williams #define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */ 131584ec227SDan Williams #define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000 132584ec227SDan Williams #define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */ 133584ec227SDan Williams 134584ec227SDan Williams /* CB DCA Memory Space Registers */ 135584ec227SDan Williams #define IOAT_DCAOFFSET_OFFSET 0x14 136584ec227SDan Williams /* CB_BAR + IOAT_DCAOFFSET value */ 137584ec227SDan Williams #define IOAT_DCA_VER_OFFSET 0x00 138584ec227SDan Williams #define IOAT_DCA_VER_MAJOR_MASK 0xF0 139584ec227SDan Williams #define IOAT_DCA_VER_MINOR_MASK 0x0F 140584ec227SDan Williams 141584ec227SDan Williams #define IOAT_DCA_COMP_OFFSET 0x02 142584ec227SDan Williams #define IOAT_DCA_COMP_V1 0x1 143584ec227SDan Williams 144584ec227SDan Williams #define IOAT_FSB_CAPABILITY_OFFSET 0x04 145584ec227SDan Williams #define IOAT_FSB_CAPABILITY_PREFETCH 0x1 146584ec227SDan Williams 147584ec227SDan Williams #define IOAT_PCI_CAPABILITY_OFFSET 0x06 148584ec227SDan Williams #define IOAT_PCI_CAPABILITY_MEMWR 0x1 149584ec227SDan Williams 150584ec227SDan Williams #define IOAT_FSB_CAP_ENABLE_OFFSET 0x08 151584ec227SDan Williams #define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1 152584ec227SDan Williams 153584ec227SDan Williams #define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A 154584ec227SDan Williams #define IOAT_PCI_CAP_ENABLE_MEMWR 0x1 155584ec227SDan Williams 156584ec227SDan Williams #define IOAT_APICID_TAG_MAP_OFFSET 0x0C 157584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG0 0x0000000F 158584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0 159584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG1 0x000000F0 160584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4 161584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG2 0x00000F00 162584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8 163584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG3 0x0000F000 164584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12 165584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG4 0x000F0000 166584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16 167584ec227SDan Williams #define IOAT_APICID_TAG_CB2_VALID 0x8080808080 168584ec227SDan Williams 169584ec227SDan Williams #define IOAT_DCA_GREQID_OFFSET 0x10 170584ec227SDan Williams #define IOAT_DCA_GREQID_SIZE 0x04 171584ec227SDan Williams #define IOAT_DCA_GREQID_MASK 0xFFFF 172584ec227SDan Williams #define IOAT_DCA_GREQID_IGNOREFUN 0x10000000 173584ec227SDan Williams #define IOAT_DCA_GREQID_VALID 0x20000000 174584ec227SDan Williams #define IOAT_DCA_GREQID_LASTID 0x80000000 175584ec227SDan Williams 176584ec227SDan Williams #define IOAT3_CSI_CAPABILITY_OFFSET 0x08 177584ec227SDan Williams #define IOAT3_CSI_CAPABILITY_PREFETCH 0x1 178584ec227SDan Williams 179584ec227SDan Williams #define IOAT3_PCI_CAPABILITY_OFFSET 0x0A 180584ec227SDan Williams #define IOAT3_PCI_CAPABILITY_MEMWR 0x1 181584ec227SDan Williams 182584ec227SDan Williams #define IOAT3_CSI_CONTROL_OFFSET 0x0C 183584ec227SDan Williams #define IOAT3_CSI_CONTROL_PREFETCH 0x1 184584ec227SDan Williams 185584ec227SDan Williams #define IOAT3_PCI_CONTROL_OFFSET 0x0E 186584ec227SDan Williams #define IOAT3_PCI_CONTROL_MEMWR 0x1 187584ec227SDan Williams 188584ec227SDan Williams #define IOAT3_APICID_TAG_MAP_OFFSET 0x10 189584ec227SDan Williams #define IOAT3_APICID_TAG_MAP_OFFSET_LOW 0x10 190584ec227SDan Williams #define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14 191584ec227SDan Williams 192584ec227SDan Williams #define IOAT3_DCA_GREQID_OFFSET 0x02 193584ec227SDan Williams 194584ec227SDan Williams #define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */ 195584ec227SDan Williams #define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */ 196584ec227SDan Williams #define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 197584ec227SDan Williams ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET) 198584ec227SDan Williams #define IOAT1_CHAINADDR_OFFSET_LOW 0x0C 199584ec227SDan Williams #define IOAT2_CHAINADDR_OFFSET_LOW 0x10 200584ec227SDan Williams #define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ 201584ec227SDan Williams ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW) 202584ec227SDan Williams #define IOAT1_CHAINADDR_OFFSET_HIGH 0x10 203584ec227SDan Williams #define IOAT2_CHAINADDR_OFFSET_HIGH 0x14 204584ec227SDan Williams #define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ 205584ec227SDan Williams ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH) 206584ec227SDan Williams 207584ec227SDan Williams #define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */ 208584ec227SDan Williams #define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */ 209584ec227SDan Williams #define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 210584ec227SDan Williams ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET) 211584ec227SDan Williams #define IOAT_CHANCMD_RESET 0x20 212584ec227SDan Williams #define IOAT_CHANCMD_RESUME 0x10 213584ec227SDan Williams #define IOAT_CHANCMD_ABORT 0x08 214584ec227SDan Williams #define IOAT_CHANCMD_SUSPEND 0x04 215584ec227SDan Williams #define IOAT_CHANCMD_APPEND 0x02 216584ec227SDan Williams #define IOAT_CHANCMD_START 0x01 217584ec227SDan Williams 218584ec227SDan Williams #define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */ 219584ec227SDan Williams #define IOAT_CHANCMP_OFFSET_LOW 0x18 220584ec227SDan Williams #define IOAT_CHANCMP_OFFSET_HIGH 0x1C 221584ec227SDan Williams 222584ec227SDan Williams #define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */ 223584ec227SDan Williams #define IOAT_CDAR_OFFSET_LOW 0x20 224584ec227SDan Williams #define IOAT_CDAR_OFFSET_HIGH 0x24 225584ec227SDan Williams 226584ec227SDan Williams #define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */ 22709c8a5b8SDan Williams #define IOAT_CHANERR_SRC_ADDR_ERR 0x0001 22809c8a5b8SDan Williams #define IOAT_CHANERR_DEST_ADDR_ERR 0x0002 22909c8a5b8SDan Williams #define IOAT_CHANERR_NEXT_ADDR_ERR 0x0004 23009c8a5b8SDan Williams #define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR 0x0008 231584ec227SDan Williams #define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010 232584ec227SDan Williams #define IOAT_CHANERR_CHANCMD_ERR 0x0020 233584ec227SDan Williams #define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040 234584ec227SDan Williams #define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080 235584ec227SDan Williams #define IOAT_CHANERR_READ_DATA_ERR 0x0100 236584ec227SDan Williams #define IOAT_CHANERR_WRITE_DATA_ERR 0x0200 23709c8a5b8SDan Williams #define IOAT_CHANERR_CONTROL_ERR 0x0400 23809c8a5b8SDan Williams #define IOAT_CHANERR_LENGTH_ERR 0x0800 239584ec227SDan Williams #define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000 240584ec227SDan Williams #define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000 241584ec227SDan Williams #define IOAT_CHANERR_SOFT_ERR 0x4000 242584ec227SDan Williams #define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000 2432aec048cSDan Williams #define IOAT_CHANERR_XOR_P_OR_CRC_ERR 0x10000 2442aec048cSDan Williams #define IOAT_CHANERR_XOR_Q_ERR 0x20000 2452aec048cSDan Williams #define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000 246584ec227SDan Williams 247b094ad3bSDan Williams #define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR) 248b094ad3bSDan Williams 249584ec227SDan Williams #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ 250584ec227SDan Williams 251584ec227SDan Williams #endif /* _IOAT_REGISTERS_H_ */ 252