1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * CAAM hardware register-level view 4 * 5 * Copyright 2008-2011 Freescale Semiconductor, Inc. 6 * Copyright 2018 NXP 7 */ 8 9 #ifndef REGS_H 10 #define REGS_H 11 12 #include <linux/types.h> 13 #include <linux/bitops.h> 14 #include <linux/io.h> 15 16 /* 17 * Architecture-specific register access methods 18 * 19 * CAAM's bus-addressable registers are 64 bits internally. 20 * They have been wired to be safely accessible on 32-bit 21 * architectures, however. Registers were organized such 22 * that (a) they can be contained in 32 bits, (b) if not, then they 23 * can be treated as two 32-bit entities, or finally (c) if they 24 * must be treated as a single 64-bit value, then this can safely 25 * be done with two 32-bit cycles. 26 * 27 * For 32-bit operations on 64-bit values, CAAM follows the same 28 * 64-bit register access conventions as it's predecessors, in that 29 * writes are "triggered" by a write to the register at the numerically 30 * higher address, thus, a full 64-bit write cycle requires a write 31 * to the lower address, followed by a write to the higher address, 32 * which will latch/execute the write cycle. 33 * 34 * For example, let's assume a SW reset of CAAM through the master 35 * configuration register. 36 * - SWRST is in bit 31 of MCFG. 37 * - MCFG begins at base+0x0000. 38 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower) 39 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher) 40 * 41 * (and on Power, the convention is 0-31, 32-63, I know...) 42 * 43 * Assuming a 64-bit write to this MCFG to perform a software reset 44 * would then require a write of 0 to base+0x0000, followed by a 45 * write of 0x80000000 to base+0x0004, which would "execute" the 46 * reset. 47 * 48 * Of course, since MCFG 63-32 is all zero, we could cheat and simply 49 * write 0x8000000 to base+0x0004, and the reset would work fine. 50 * However, since CAAM does contain some write-and-read-intended 51 * 64-bit registers, this code defines 64-bit access methods for 52 * the sake of internal consistency and simplicity, and so that a 53 * clean transition to 64-bit is possible when it becomes necessary. 54 * 55 * There are limitations to this that the developer must recognize. 56 * 32-bit architectures cannot enforce an atomic-64 operation, 57 * Therefore: 58 * 59 * - On writes, since the HW is assumed to latch the cycle on the 60 * write of the higher-numeric-address word, then ordered 61 * writes work OK. 62 * 63 * - For reads, where a register contains a relevant value of more 64 * that 32 bits, the hardware employs logic to latch the other 65 * "half" of the data until read, ensuring an accurate value. 66 * This is of particular relevance when dealing with CAAM's 67 * performance counters. 68 * 69 */ 70 71 extern bool caam_little_end; 72 extern bool caam_imx; 73 74 #define caam_to_cpu(len) \ 75 static inline u##len caam##len ## _to_cpu(u##len val) \ 76 { \ 77 if (caam_little_end) \ 78 return le##len ## _to_cpu((__force __le##len)val); \ 79 else \ 80 return be##len ## _to_cpu((__force __be##len)val); \ 81 } 82 83 #define cpu_to_caam(len) \ 84 static inline u##len cpu_to_caam##len(u##len val) \ 85 { \ 86 if (caam_little_end) \ 87 return (__force u##len)cpu_to_le##len(val); \ 88 else \ 89 return (__force u##len)cpu_to_be##len(val); \ 90 } 91 92 caam_to_cpu(16) 93 caam_to_cpu(32) 94 caam_to_cpu(64) 95 cpu_to_caam(16) 96 cpu_to_caam(32) 97 cpu_to_caam(64) 98 99 static inline void wr_reg32_relaxed(void __iomem *reg, u32 data) 100 { 101 if (caam_little_end) 102 writel_relaxed(data, reg); 103 else 104 writel_relaxed(cpu_to_be32(data), reg); 105 } 106 107 static inline void wr_reg32(void __iomem *reg, u32 data) 108 { 109 if (caam_little_end) 110 iowrite32(data, reg); 111 else 112 iowrite32be(data, reg); 113 } 114 115 static inline u32 rd_reg32(void __iomem *reg) 116 { 117 if (caam_little_end) 118 return ioread32(reg); 119 120 return ioread32be(reg); 121 } 122 123 static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set) 124 { 125 if (caam_little_end) 126 iowrite32((ioread32(reg) & ~clear) | set, reg); 127 else 128 iowrite32be((ioread32be(reg) & ~clear) | set, reg); 129 } 130 131 /* 132 * The only users of these wr/rd_reg64 functions is the Job Ring (JR). 133 * The DMA address registers in the JR are handled differently depending on 134 * platform: 135 * 136 * 1. All BE CAAM platforms and i.MX platforms (LE CAAM): 137 * 138 * base + 0x0000 : most-significant 32 bits 139 * base + 0x0004 : least-significant 32 bits 140 * 141 * The 32-bit version of this core therefore has to write to base + 0x0004 142 * to set the 32-bit wide DMA address. 143 * 144 * 2. All other LE CAAM platforms (LS1021A etc.) 145 * base + 0x0000 : least-significant 32 bits 146 * base + 0x0004 : most-significant 32 bits 147 */ 148 #ifdef CONFIG_64BIT 149 static inline void wr_reg64(void __iomem *reg, u64 data) 150 { 151 if (caam_little_end) 152 iowrite64(data, reg); 153 else 154 iowrite64be(data, reg); 155 } 156 157 static inline u64 rd_reg64(void __iomem *reg) 158 { 159 if (caam_little_end) 160 return ioread64(reg); 161 else 162 return ioread64be(reg); 163 } 164 165 #else /* CONFIG_64BIT */ 166 static inline void wr_reg64(void __iomem *reg, u64 data) 167 { 168 if (!caam_imx && caam_little_end) { 169 wr_reg32((u32 __iomem *)(reg) + 1, data >> 32); 170 wr_reg32((u32 __iomem *)(reg), data); 171 } else { 172 wr_reg32((u32 __iomem *)(reg), data >> 32); 173 wr_reg32((u32 __iomem *)(reg) + 1, data); 174 } 175 } 176 177 static inline u64 rd_reg64(void __iomem *reg) 178 { 179 if (!caam_imx && caam_little_end) 180 return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 | 181 (u64)rd_reg32((u32 __iomem *)(reg))); 182 183 return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 | 184 (u64)rd_reg32((u32 __iomem *)(reg) + 1)); 185 } 186 #endif /* CONFIG_64BIT */ 187 188 static inline u64 cpu_to_caam_dma64(dma_addr_t value) 189 { 190 if (caam_imx) 191 return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | 192 (u64)cpu_to_caam32(upper_32_bits(value))); 193 194 return cpu_to_caam64(value); 195 } 196 197 static inline u64 caam_dma64_to_cpu(u64 value) 198 { 199 if (caam_imx) 200 return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) | 201 (u64)caam32_to_cpu(upper_32_bits(value))); 202 203 return caam64_to_cpu(value); 204 } 205 206 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 207 #define cpu_to_caam_dma(value) cpu_to_caam_dma64(value) 208 #define caam_dma_to_cpu(value) caam_dma64_to_cpu(value) 209 #else 210 #define cpu_to_caam_dma(value) cpu_to_caam32(value) 211 #define caam_dma_to_cpu(value) caam32_to_cpu(value) 212 #endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */ 213 214 /* 215 * jr_outentry 216 * Represents each entry in a JobR output ring 217 */ 218 struct jr_outentry { 219 dma_addr_t desc;/* Pointer to completed descriptor */ 220 u32 jrstatus; /* Status for completed descriptor */ 221 } __packed; 222 223 /* Version registers (Era 10+) e80-eff */ 224 struct version_regs { 225 u32 crca; /* CRCA_VERSION */ 226 u32 afha; /* AFHA_VERSION */ 227 u32 kfha; /* KFHA_VERSION */ 228 u32 pkha; /* PKHA_VERSION */ 229 u32 aesa; /* AESA_VERSION */ 230 u32 mdha; /* MDHA_VERSION */ 231 u32 desa; /* DESA_VERSION */ 232 u32 snw8a; /* SNW8A_VERSION */ 233 u32 snw9a; /* SNW9A_VERSION */ 234 u32 zuce; /* ZUCE_VERSION */ 235 u32 zuca; /* ZUCA_VERSION */ 236 u32 ccha; /* CCHA_VERSION */ 237 u32 ptha; /* PTHA_VERSION */ 238 u32 rng; /* RNG_VERSION */ 239 u32 trng; /* TRNG_VERSION */ 240 u32 aaha; /* AAHA_VERSION */ 241 u32 rsvd[10]; 242 u32 sr; /* SR_VERSION */ 243 u32 dma; /* DMA_VERSION */ 244 u32 ai; /* AI_VERSION */ 245 u32 qi; /* QI_VERSION */ 246 u32 jr; /* JR_VERSION */ 247 u32 deco; /* DECO_VERSION */ 248 }; 249 250 /* Version registers bitfields */ 251 252 /* Number of CHAs instantiated */ 253 #define CHA_VER_NUM_MASK 0xffull 254 /* CHA Miscellaneous Information */ 255 #define CHA_VER_MISC_SHIFT 8 256 #define CHA_VER_MISC_MASK (0xffull << CHA_VER_MISC_SHIFT) 257 /* CHA Revision Number */ 258 #define CHA_VER_REV_SHIFT 16 259 #define CHA_VER_REV_MASK (0xffull << CHA_VER_REV_SHIFT) 260 /* CHA Version ID */ 261 #define CHA_VER_VID_SHIFT 24 262 #define CHA_VER_VID_MASK (0xffull << CHA_VER_VID_SHIFT) 263 264 /* CHA Miscellaneous Information - AESA_MISC specific */ 265 #define CHA_VER_MISC_AES_GCM BIT(1 + CHA_VER_MISC_SHIFT) 266 267 /* 268 * caam_perfmon - Performance Monitor/Secure Memory Status/ 269 * CAAM Global Status/Component Version IDs 270 * 271 * Spans f00-fff wherever instantiated 272 */ 273 274 /* Number of DECOs */ 275 #define CHA_NUM_MS_DECONUM_SHIFT 24 276 #define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT) 277 278 /* 279 * CHA version IDs / instantiation bitfields (< Era 10) 280 * Defined for use with the cha_id fields in perfmon, but the same shift/mask 281 * selectors can be used to pull out the number of instantiated blocks within 282 * cha_num fields in perfmon because the locations are the same. 283 */ 284 #define CHA_ID_LS_AES_SHIFT 0 285 #define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT) 286 287 #define CHA_ID_LS_DES_SHIFT 4 288 #define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT) 289 290 #define CHA_ID_LS_ARC4_SHIFT 8 291 #define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT) 292 293 #define CHA_ID_LS_MD_SHIFT 12 294 #define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT) 295 296 #define CHA_ID_LS_RNG_SHIFT 16 297 #define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT) 298 299 #define CHA_ID_LS_SNW8_SHIFT 20 300 #define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT) 301 302 #define CHA_ID_LS_KAS_SHIFT 24 303 #define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT) 304 305 #define CHA_ID_LS_PK_SHIFT 28 306 #define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT) 307 308 #define CHA_ID_MS_CRC_SHIFT 0 309 #define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT) 310 311 #define CHA_ID_MS_SNW9_SHIFT 4 312 #define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT) 313 314 #define CHA_ID_MS_DECO_SHIFT 24 315 #define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT) 316 317 #define CHA_ID_MS_JR_SHIFT 28 318 #define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT) 319 320 /* Specific CHA version IDs */ 321 #define CHA_VER_VID_AES_LP 0x3ull 322 #define CHA_VER_VID_AES_HP 0x4ull 323 #define CHA_VER_VID_MD_LP256 0x0ull 324 #define CHA_VER_VID_MD_LP512 0x1ull 325 #define CHA_VER_VID_MD_HP 0x2ull 326 327 struct sec_vid { 328 u16 ip_id; 329 u8 maj_rev; 330 u8 min_rev; 331 }; 332 333 struct caam_perfmon { 334 /* Performance Monitor Registers f00-f9f */ 335 u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */ 336 u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */ 337 u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */ 338 u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */ 339 u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */ 340 u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */ 341 u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */ 342 u64 rsvd[13]; 343 344 /* CAAM Hardware Instantiation Parameters fa0-fbf */ 345 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/ 346 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/ 347 #define CTPR_MS_QI_SHIFT 25 348 #define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT) 349 #define CTPR_MS_DPAA2 BIT(13) 350 #define CTPR_MS_VIRT_EN_INCL 0x00000001 351 #define CTPR_MS_VIRT_EN_POR 0x00000002 352 #define CTPR_MS_PG_SZ_MASK 0x10 353 #define CTPR_MS_PG_SZ_SHIFT 4 354 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ 355 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ 356 u64 rsvd1[2]; 357 358 /* CAAM Global Status fc0-fdf */ 359 u64 faultaddr; /* FAR - Fault Address */ 360 u32 faultliodn; /* FALR - Fault Address LIODN */ 361 u32 faultdetail; /* FADR - Fault Addr Detail */ 362 u32 rsvd2; 363 #define CSTA_PLEND BIT(10) 364 #define CSTA_ALT_PLEND BIT(18) 365 u32 status; /* CSTA - CAAM Status */ 366 u64 rsvd3; 367 368 /* Component Instantiation Parameters fe0-fff */ 369 u32 rtic_id; /* RVID - RTIC Version ID */ 370 #define CCBVID_ERA_MASK 0xff000000 371 #define CCBVID_ERA_SHIFT 24 372 u32 ccb_id; /* CCBVID - CCB Version ID */ 373 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/ 374 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/ 375 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */ 376 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/ 377 #define SECVID_MS_IPID_MASK 0xffff0000 378 #define SECVID_MS_IPID_SHIFT 16 379 #define SECVID_MS_MAJ_REV_MASK 0x0000ff00 380 #define SECVID_MS_MAJ_REV_SHIFT 8 381 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */ 382 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ 383 }; 384 385 /* LIODN programming for DMA configuration */ 386 #define MSTRID_LOCK_LIODN 0x80000000 387 #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ 388 389 #define MSTRID_LIODN_MASK 0x0fff 390 struct masterid { 391 u32 liodn_ms; /* lock and make-trusted control bits */ 392 u32 liodn_ls; /* LIODN for non-sequence and seq access */ 393 }; 394 395 /* Partition ID for DMA configuration */ 396 struct partid { 397 u32 rsvd1; 398 u32 pidr; /* partition ID, DECO */ 399 }; 400 401 /* RNGB test mode (replicated twice in some configurations) */ 402 /* Padded out to 0x100 */ 403 struct rngtst { 404 u32 mode; /* RTSTMODEx - Test mode */ 405 u32 rsvd1[3]; 406 u32 reset; /* RTSTRESETx - Test reset control */ 407 u32 rsvd2[3]; 408 u32 status; /* RTSTSSTATUSx - Test status */ 409 u32 rsvd3; 410 u32 errstat; /* RTSTERRSTATx - Test error status */ 411 u32 rsvd4; 412 u32 errctl; /* RTSTERRCTLx - Test error control */ 413 u32 rsvd5; 414 u32 entropy; /* RTSTENTROPYx - Test entropy */ 415 u32 rsvd6[15]; 416 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */ 417 u32 rsvd7; 418 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */ 419 u32 rsvd8; 420 u32 verifdata; /* RTSTVERIFDx - Test verification data */ 421 u32 rsvd9; 422 u32 xkey; /* RTSTXKEYx - Test XKEY */ 423 u32 rsvd10; 424 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */ 425 u32 rsvd11; 426 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */ 427 u32 rsvd12; 428 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */ 429 u32 rsvd13[2]; 430 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */ 431 u32 rsvd14[15]; 432 }; 433 434 /* RNG4 TRNG test registers */ 435 struct rng4tst { 436 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ 437 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in 438 both entropy shifter and 439 statistical checker */ 440 #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both 441 entropy shifter and 442 statistical checker */ 443 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in 444 entropy shifter, raw data 445 in statistical checker */ 446 #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ 447 u32 rtmctl; /* misc. control register */ 448 u32 rtscmisc; /* statistical check misc. register */ 449 u32 rtpkrrng; /* poker range register */ 450 union { 451 u32 rtpkrmax; /* PRGM=1: poker max. limit register */ 452 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ 453 }; 454 #define RTSDCTL_ENT_DLY_SHIFT 16 455 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) 456 #define RTSDCTL_ENT_DLY_MIN 3200 457 #define RTSDCTL_ENT_DLY_MAX 12800 458 u32 rtsdctl; /* seed control register */ 459 union { 460 u32 rtsblim; /* PRGM=1: sparse bit limit register */ 461 u32 rttotsam; /* PRGM=0: total samples register */ 462 }; 463 u32 rtfrqmin; /* frequency count min. limit register */ 464 #define RTFRQMAX_DISABLE (1 << 20) 465 union { 466 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ 467 u32 rtfrqcnt; /* PRGM=0: freq. count register */ 468 }; 469 u32 rsvd1[40]; 470 #define RDSTA_SKVT 0x80000000 471 #define RDSTA_SKVN 0x40000000 472 #define RDSTA_IF0 0x00000001 473 #define RDSTA_IF1 0x00000002 474 #define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0) 475 u32 rdsta; 476 u32 rsvd2[15]; 477 }; 478 479 /* 480 * caam_ctrl - basic core configuration 481 * starts base + 0x0000 padded out to 0x1000 482 */ 483 484 #define KEK_KEY_SIZE 8 485 #define TKEK_KEY_SIZE 8 486 #define TDSK_KEY_SIZE 8 487 488 #define DECO_RESET 1 /* Use with DECO reset/availability regs */ 489 #define DECO_RESET_0 (DECO_RESET << 0) 490 #define DECO_RESET_1 (DECO_RESET << 1) 491 #define DECO_RESET_2 (DECO_RESET << 2) 492 #define DECO_RESET_3 (DECO_RESET << 3) 493 #define DECO_RESET_4 (DECO_RESET << 4) 494 495 struct caam_ctrl { 496 /* Basic Configuration Section 000-01f */ 497 /* Read/Writable */ 498 u32 rsvd1; 499 u32 mcr; /* MCFG Master Config Register */ 500 u32 rsvd2; 501 u32 scfgr; /* SCFGR, Security Config Register */ 502 503 /* Bus Access Configuration Section 010-11f */ 504 /* Read/Writable */ 505 struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */ 506 u32 rsvd3[11]; 507 u32 jrstart; /* JRSTART - Job Ring Start Register */ 508 struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */ 509 u32 rsvd4[5]; 510 u32 deco_rsr; /* DECORSR - Deco Request Source */ 511 u32 rsvd11; 512 u32 deco_rq; /* DECORR - DECO Request */ 513 struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ 514 u32 rsvd5[22]; 515 516 /* DECO Availability/Reset Section 120-3ff */ 517 u32 deco_avail; /* DAR - DECO availability */ 518 u32 deco_reset; /* DRR - DECO reset */ 519 u32 rsvd6[182]; 520 521 /* Key Encryption/Decryption Configuration 400-5ff */ 522 /* Read/Writable only while in Non-secure mode */ 523 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */ 524 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */ 525 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */ 526 u32 rsvd7[32]; 527 u64 sknonce; /* SKNR - Secure Key Nonce */ 528 u32 rsvd8[70]; 529 530 /* RNG Test/Verification/Debug Access 600-7ff */ 531 /* (Useful in Test/Debug modes only...) */ 532 union { 533 struct rngtst rtst[2]; 534 struct rng4tst r4tst[2]; 535 }; 536 537 u32 rsvd9[416]; 538 539 /* Version registers - introduced with era 10 e80-eff */ 540 struct version_regs vreg; 541 /* Performance Monitor f00-fff */ 542 struct caam_perfmon perfmon; 543 }; 544 545 /* 546 * Controller master config register defs 547 */ 548 #define MCFGR_SWRESET 0x80000000 /* software reset */ 549 #define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */ 550 #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */ 551 #define MCFGR_DMA_RESET 0x10000000 552 #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ 553 #define SCFGR_RDBENABLE 0x00000400 554 #define SCFGR_VIRT_EN 0x00008000 555 #define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */ 556 #define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */ 557 #define DECORSR_VALID 0x80000000 558 #define DECORR_DEN0 0x00010000 /* DECO0 available for access*/ 559 560 /* AXI read cache control */ 561 #define MCFGR_ARCACHE_SHIFT 12 562 #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) 563 #define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT) 564 #define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT) 565 #define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT) 566 567 /* AXI write cache control */ 568 #define MCFGR_AWCACHE_SHIFT 8 569 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) 570 #define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT) 571 #define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT) 572 #define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT) 573 574 /* AXI pipeline depth */ 575 #define MCFGR_AXIPIPE_SHIFT 4 576 #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT) 577 578 #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */ 579 #define MCFGR_LARGE_BURST 0x00000004 /* 128/256-byte burst size */ 580 #define MCFGR_BURST_64 0x00000001 /* 64-byte burst size */ 581 582 /* JRSTART register offsets */ 583 #define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */ 584 #define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */ 585 #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ 586 #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ 587 588 /* 589 * caam_job_ring - direct job ring setup 590 * 1-4 possible per instantiation, base + 1000/2000/3000/4000 591 * Padded out to 0x1000 592 */ 593 struct caam_job_ring { 594 /* Input ring */ 595 u64 inpring_base; /* IRBAx - Input desc ring baseaddr */ 596 u32 rsvd1; 597 u32 inpring_size; /* IRSx - Input ring size */ 598 u32 rsvd2; 599 u32 inpring_avail; /* IRSAx - Input ring room remaining */ 600 u32 rsvd3; 601 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */ 602 603 /* Output Ring */ 604 u64 outring_base; /* ORBAx - Output status ring base addr */ 605 u32 rsvd4; 606 u32 outring_size; /* ORSx - Output ring size */ 607 u32 rsvd5; 608 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */ 609 u32 rsvd6; 610 u32 outring_used; /* ORSFx - Output ring slots full */ 611 612 /* Status/Configuration */ 613 u32 rsvd7; 614 u32 jroutstatus; /* JRSTAx - JobR output status */ 615 u32 rsvd8; 616 u32 jrintstatus; /* JRINTx - JobR interrupt status */ 617 u32 rconfig_hi; /* JRxCFG - Ring configuration */ 618 u32 rconfig_lo; 619 620 /* Indices. CAAM maintains as "heads" of each queue */ 621 u32 rsvd9; 622 u32 inp_rdidx; /* IRRIx - Input ring read index */ 623 u32 rsvd10; 624 u32 out_wtidx; /* ORWIx - Output ring write index */ 625 626 /* Command/control */ 627 u32 rsvd11; 628 u32 jrcommand; /* JRCRx - JobR command */ 629 630 u32 rsvd12[900]; 631 632 /* Version registers - introduced with era 10 e80-eff */ 633 struct version_regs vreg; 634 /* Performance Monitor f00-fff */ 635 struct caam_perfmon perfmon; 636 }; 637 638 #define JR_RINGSIZE_MASK 0x03ff 639 /* 640 * jrstatus - Job Ring Output Status 641 * All values in lo word 642 * Also note, same values written out as status through QI 643 * in the command/status field of a frame descriptor 644 */ 645 #define JRSTA_SSRC_SHIFT 28 646 #define JRSTA_SSRC_MASK 0xf0000000 647 648 #define JRSTA_SSRC_NONE 0x00000000 649 #define JRSTA_SSRC_CCB_ERROR 0x20000000 650 #define JRSTA_SSRC_JUMP_HALT_USER 0x30000000 651 #define JRSTA_SSRC_DECO 0x40000000 652 #define JRSTA_SSRC_JRERROR 0x60000000 653 #define JRSTA_SSRC_JUMP_HALT_CC 0x70000000 654 655 #define JRSTA_DECOERR_JUMP 0x08000000 656 #define JRSTA_DECOERR_INDEX_SHIFT 8 657 #define JRSTA_DECOERR_INDEX_MASK 0xff00 658 #define JRSTA_DECOERR_ERROR_MASK 0x00ff 659 660 #define JRSTA_DECOERR_NONE 0x00 661 #define JRSTA_DECOERR_LINKLEN 0x01 662 #define JRSTA_DECOERR_LINKPTR 0x02 663 #define JRSTA_DECOERR_JRCTRL 0x03 664 #define JRSTA_DECOERR_DESCCMD 0x04 665 #define JRSTA_DECOERR_ORDER 0x05 666 #define JRSTA_DECOERR_KEYCMD 0x06 667 #define JRSTA_DECOERR_LOADCMD 0x07 668 #define JRSTA_DECOERR_STORECMD 0x08 669 #define JRSTA_DECOERR_OPCMD 0x09 670 #define JRSTA_DECOERR_FIFOLDCMD 0x0a 671 #define JRSTA_DECOERR_FIFOSTCMD 0x0b 672 #define JRSTA_DECOERR_MOVECMD 0x0c 673 #define JRSTA_DECOERR_JUMPCMD 0x0d 674 #define JRSTA_DECOERR_MATHCMD 0x0e 675 #define JRSTA_DECOERR_SHASHCMD 0x0f 676 #define JRSTA_DECOERR_SEQCMD 0x10 677 #define JRSTA_DECOERR_DECOINTERNAL 0x11 678 #define JRSTA_DECOERR_SHDESCHDR 0x12 679 #define JRSTA_DECOERR_HDRLEN 0x13 680 #define JRSTA_DECOERR_BURSTER 0x14 681 #define JRSTA_DECOERR_DESCSIGNATURE 0x15 682 #define JRSTA_DECOERR_DMA 0x16 683 #define JRSTA_DECOERR_BURSTFIFO 0x17 684 #define JRSTA_DECOERR_JRRESET 0x1a 685 #define JRSTA_DECOERR_JOBFAIL 0x1b 686 #define JRSTA_DECOERR_DNRERR 0x80 687 #define JRSTA_DECOERR_UNDEFPCL 0x81 688 #define JRSTA_DECOERR_PDBERR 0x82 689 #define JRSTA_DECOERR_ANRPLY_LATE 0x83 690 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84 691 #define JRSTA_DECOERR_SEQOVF 0x85 692 #define JRSTA_DECOERR_INVSIGN 0x86 693 #define JRSTA_DECOERR_DSASIGN 0x87 694 695 #define JRSTA_QIERR_ERROR_MASK 0x00ff 696 697 #define JRSTA_CCBERR_JUMP 0x08000000 698 #define JRSTA_CCBERR_INDEX_MASK 0xff00 699 #define JRSTA_CCBERR_INDEX_SHIFT 8 700 #define JRSTA_CCBERR_CHAID_MASK 0x00f0 701 #define JRSTA_CCBERR_CHAID_SHIFT 4 702 #define JRSTA_CCBERR_ERRID_MASK 0x000f 703 704 #define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT) 705 #define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT) 706 #define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT) 707 #define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT) 708 #define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT) 709 #define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT) 710 #define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT) 711 #define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT) 712 #define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT) 713 714 #define JRSTA_CCBERR_ERRID_NONE 0x00 715 #define JRSTA_CCBERR_ERRID_MODE 0x01 716 #define JRSTA_CCBERR_ERRID_DATASIZ 0x02 717 #define JRSTA_CCBERR_ERRID_KEYSIZ 0x03 718 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04 719 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05 720 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06 721 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07 722 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08 723 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09 724 #define JRSTA_CCBERR_ERRID_ICVCHK 0x0a 725 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b 726 #define JRSTA_CCBERR_ERRID_CCMAAD 0x0c 727 #define JRSTA_CCBERR_ERRID_INVCHA 0x0f 728 729 #define JRINT_ERR_INDEX_MASK 0x3fff0000 730 #define JRINT_ERR_INDEX_SHIFT 16 731 #define JRINT_ERR_TYPE_MASK 0xf00 732 #define JRINT_ERR_TYPE_SHIFT 8 733 #define JRINT_ERR_HALT_MASK 0xc 734 #define JRINT_ERR_HALT_SHIFT 2 735 #define JRINT_ERR_HALT_INPROGRESS 0x4 736 #define JRINT_ERR_HALT_COMPLETE 0x8 737 #define JRINT_JR_ERROR 0x02 738 #define JRINT_JR_INT 0x01 739 740 #define JRINT_ERR_TYPE_WRITE 1 741 #define JRINT_ERR_TYPE_BAD_INPADDR 3 742 #define JRINT_ERR_TYPE_BAD_OUTADDR 4 743 #define JRINT_ERR_TYPE_INV_INPWRT 5 744 #define JRINT_ERR_TYPE_INV_OUTWRT 6 745 #define JRINT_ERR_TYPE_RESET 7 746 #define JRINT_ERR_TYPE_REMOVE_OFL 8 747 #define JRINT_ERR_TYPE_ADD_OFL 9 748 749 #define JRCFG_SOE 0x04 750 #define JRCFG_ICEN 0x02 751 #define JRCFG_IMSK 0x01 752 #define JRCFG_ICDCT_SHIFT 8 753 #define JRCFG_ICTT_SHIFT 16 754 755 #define JRCR_RESET 0x01 756 757 /* 758 * caam_assurance - Assurance Controller View 759 * base + 0x6000 padded out to 0x1000 760 */ 761 762 struct rtic_element { 763 u64 address; 764 u32 rsvd; 765 u32 length; 766 }; 767 768 struct rtic_block { 769 struct rtic_element element[2]; 770 }; 771 772 struct rtic_memhash { 773 u32 memhash_be[32]; 774 u32 memhash_le[32]; 775 }; 776 777 struct caam_assurance { 778 /* Status/Command/Watchdog */ 779 u32 rsvd1; 780 u32 status; /* RSTA - Status */ 781 u32 rsvd2; 782 u32 cmd; /* RCMD - Command */ 783 u32 rsvd3; 784 u32 ctrl; /* RCTL - Control */ 785 u32 rsvd4; 786 u32 throttle; /* RTHR - Throttle */ 787 u32 rsvd5[2]; 788 u64 watchdog; /* RWDOG - Watchdog Timer */ 789 u32 rsvd6; 790 u32 rend; /* REND - Endian corrections */ 791 u32 rsvd7[50]; 792 793 /* Block access/configuration @ 100/110/120/130 */ 794 struct rtic_block memblk[4]; /* Memory Blocks A-D */ 795 u32 rsvd8[32]; 796 797 /* Block hashes @ 200/300/400/500 */ 798 struct rtic_memhash hash[4]; /* Block hash values A-D */ 799 u32 rsvd_3[640]; 800 }; 801 802 /* 803 * caam_queue_if - QI configuration and control 804 * starts base + 0x7000, padded out to 0x1000 long 805 */ 806 807 struct caam_queue_if { 808 u32 qi_control_hi; /* QICTL - QI Control */ 809 u32 qi_control_lo; 810 u32 rsvd1; 811 u32 qi_status; /* QISTA - QI Status */ 812 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */ 813 u32 qi_deq_cfg_lo; 814 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */ 815 u32 qi_enq_cfg_lo; 816 u32 rsvd2[1016]; 817 }; 818 819 /* QI control bits - low word */ 820 #define QICTL_DQEN 0x01 /* Enable frame pop */ 821 #define QICTL_STOP 0x02 /* Stop dequeue/enqueue */ 822 #define QICTL_SOE 0x04 /* Stop on error */ 823 824 /* QI control bits - high word */ 825 #define QICTL_MBSI 0x01 826 #define QICTL_MHWSI 0x02 827 #define QICTL_MWSI 0x04 828 #define QICTL_MDWSI 0x08 829 #define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */ 830 #define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */ 831 #define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */ 832 #define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */ 833 #define QICTL_MBSO 0x0100 834 #define QICTL_MHWSO 0x0200 835 #define QICTL_MWSO 0x0400 836 #define QICTL_MDWSO 0x0800 837 #define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */ 838 #define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */ 839 #define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */ 840 #define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */ 841 #define QICTL_DMBS 0x010000 842 #define QICTL_EPO 0x020000 843 844 /* QI status bits */ 845 #define QISTA_PHRDERR 0x01 /* PreHeader Read Error */ 846 #define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */ 847 #define QISTA_OFWRERR 0x04 /* Output Frame Read Error */ 848 #define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */ 849 #define QISTA_BTSERR 0x10 /* Buffer Undersize */ 850 #define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */ 851 #define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */ 852 853 /* deco_sg_table - DECO view of scatter/gather table */ 854 struct deco_sg_table { 855 u64 addr; /* Segment Address */ 856 u32 elen; /* E, F bits + 30-bit length */ 857 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */ 858 }; 859 860 /* 861 * caam_deco - descriptor controller - CHA cluster block 862 * 863 * Only accessible when direct DECO access is turned on 864 * (done in DECORR, via MID programmed in DECOxMID 865 * 866 * 5 typical, base + 0x8000/9000/a000/b000 867 * Padded out to 0x1000 long 868 */ 869 struct caam_deco { 870 u32 rsvd1; 871 u32 cls1_mode; /* CxC1MR - Class 1 Mode */ 872 u32 rsvd2; 873 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */ 874 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */ 875 u32 cls1_datasize_lo; 876 u32 rsvd3; 877 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */ 878 u32 rsvd4[5]; 879 u32 cha_ctrl; /* CCTLR - CHA control */ 880 u32 rsvd5; 881 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */ 882 u32 rsvd6; 883 u32 clr_written; /* CxCWR - Clear-Written */ 884 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */ 885 u32 ccb_status_lo; 886 u32 rsvd7[3]; 887 u32 aad_size; /* CxAADSZR - Current AAD Size */ 888 u32 rsvd8; 889 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */ 890 u32 rsvd9[7]; 891 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */ 892 u32 rsvd10; 893 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */ 894 u32 rsvd11; 895 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */ 896 u32 rsvd12; 897 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */ 898 u32 rsvd13[24]; 899 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */ 900 u32 rsvd14[48]; 901 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */ 902 u32 rsvd15[121]; 903 u32 cls2_mode; /* CxC2MR - Class 2 Mode */ 904 u32 rsvd16; 905 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */ 906 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */ 907 u32 cls2_datasize_lo; 908 u32 rsvd17; 909 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */ 910 u32 rsvd18[56]; 911 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */ 912 u32 rsvd19[46]; 913 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */ 914 u32 rsvd20[84]; 915 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */ 916 u32 inp_infofifo_lo; 917 u32 rsvd21[2]; 918 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */ 919 u32 rsvd22[2]; 920 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */ 921 u32 rsvd23[2]; 922 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */ 923 u32 jr_ctl_lo; 924 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */ 925 #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF 926 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */ 927 u32 op_status_lo; 928 u32 rsvd24[2]; 929 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */ 930 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */ 931 u32 rsvd26[6]; 932 u64 math[4]; /* DxMTH - Math register */ 933 u32 rsvd27[8]; 934 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */ 935 u32 rsvd28[16]; 936 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */ 937 u32 rsvd29[48]; 938 u32 descbuf[64]; /* DxDESB - Descriptor buffer */ 939 u32 rscvd30[193]; 940 #define DESC_DBG_DECO_STAT_VALID 0x80000000 941 #define DESC_DBG_DECO_STAT_MASK 0x00F00000 942 #define DESC_DBG_DECO_STAT_SHIFT 20 943 u32 desc_dbg; /* DxDDR - DECO Debug Register */ 944 u32 rsvd31[13]; 945 #define DESC_DER_DECO_STAT_MASK 0x000F0000 946 #define DESC_DER_DECO_STAT_SHIFT 16 947 u32 dbg_exec; /* DxDER - DECO Debug Exec Register */ 948 u32 rsvd32[112]; 949 }; 950 951 #define DECO_STAT_HOST_ERR 0xD 952 953 #define DECO_JQCR_WHL 0x20000000 954 #define DECO_JQCR_FOUR 0x10000000 955 956 #define JR_BLOCK_NUMBER 1 957 #define ASSURE_BLOCK_NUMBER 6 958 #define QI_BLOCK_NUMBER 7 959 #define DECO_BLOCK_NUMBER 8 960 #define PG_SIZE_4K 0x1000 961 #define PG_SIZE_64K 0x10000 962 #endif /* REGS_H */ 963