1*d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2e6b7f580SIvan Khoronzhuk /*
3e6b7f580SIvan Khoronzhuk * Keystone broadcast clock-event
4e6b7f580SIvan Khoronzhuk *
5e6b7f580SIvan Khoronzhuk * Copyright 2013 Texas Instruments, Inc.
6e6b7f580SIvan Khoronzhuk *
7e6b7f580SIvan Khoronzhuk * Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
8e6b7f580SIvan Khoronzhuk */
9e6b7f580SIvan Khoronzhuk
10e6b7f580SIvan Khoronzhuk #include <linux/clk.h>
11e6b7f580SIvan Khoronzhuk #include <linux/clockchips.h>
12e6b7f580SIvan Khoronzhuk #include <linux/clocksource.h>
13e6b7f580SIvan Khoronzhuk #include <linux/interrupt.h>
14e6b7f580SIvan Khoronzhuk #include <linux/of_address.h>
15e6b7f580SIvan Khoronzhuk #include <linux/of_irq.h>
16e6b7f580SIvan Khoronzhuk
17e6b7f580SIvan Khoronzhuk #define TIMER_NAME "timer-keystone"
18e6b7f580SIvan Khoronzhuk
19e6b7f580SIvan Khoronzhuk /* Timer register offsets */
20e6b7f580SIvan Khoronzhuk #define TIM12 0x10
21e6b7f580SIvan Khoronzhuk #define TIM34 0x14
22e6b7f580SIvan Khoronzhuk #define PRD12 0x18
23e6b7f580SIvan Khoronzhuk #define PRD34 0x1c
24e6b7f580SIvan Khoronzhuk #define TCR 0x20
25e6b7f580SIvan Khoronzhuk #define TGCR 0x24
26e6b7f580SIvan Khoronzhuk #define INTCTLSTAT 0x44
27e6b7f580SIvan Khoronzhuk
28e6b7f580SIvan Khoronzhuk /* Timer register bitfields */
29e6b7f580SIvan Khoronzhuk #define TCR_ENAMODE_MASK 0xC0
30e6b7f580SIvan Khoronzhuk #define TCR_ENAMODE_ONESHOT_MASK 0x40
31e6b7f580SIvan Khoronzhuk #define TCR_ENAMODE_PERIODIC_MASK 0x80
32e6b7f580SIvan Khoronzhuk
33e6b7f580SIvan Khoronzhuk #define TGCR_TIM_UNRESET_MASK 0x03
34e6b7f580SIvan Khoronzhuk #define INTCTLSTAT_ENINT_MASK 0x01
35e6b7f580SIvan Khoronzhuk
36e6b7f580SIvan Khoronzhuk /**
37e6b7f580SIvan Khoronzhuk * struct keystone_timer: holds timer's data
38e6b7f580SIvan Khoronzhuk * @base: timer memory base address
39e6b7f580SIvan Khoronzhuk * @hz_period: cycles per HZ period
40e6b7f580SIvan Khoronzhuk * @event_dev: event device based on timer
41e6b7f580SIvan Khoronzhuk */
42e6b7f580SIvan Khoronzhuk static struct keystone_timer {
43e6b7f580SIvan Khoronzhuk void __iomem *base;
44e6b7f580SIvan Khoronzhuk unsigned long hz_period;
45e6b7f580SIvan Khoronzhuk struct clock_event_device event_dev;
46e6b7f580SIvan Khoronzhuk } timer;
47e6b7f580SIvan Khoronzhuk
keystone_timer_readl(unsigned long rg)48e6b7f580SIvan Khoronzhuk static inline u32 keystone_timer_readl(unsigned long rg)
49e6b7f580SIvan Khoronzhuk {
50e6b7f580SIvan Khoronzhuk return readl_relaxed(timer.base + rg);
51e6b7f580SIvan Khoronzhuk }
52e6b7f580SIvan Khoronzhuk
keystone_timer_writel(u32 val,unsigned long rg)53e6b7f580SIvan Khoronzhuk static inline void keystone_timer_writel(u32 val, unsigned long rg)
54e6b7f580SIvan Khoronzhuk {
55e6b7f580SIvan Khoronzhuk writel_relaxed(val, timer.base + rg);
56e6b7f580SIvan Khoronzhuk }
57e6b7f580SIvan Khoronzhuk
58e6b7f580SIvan Khoronzhuk /**
59e6b7f580SIvan Khoronzhuk * keystone_timer_barrier: write memory barrier
60e6b7f580SIvan Khoronzhuk * use explicit barrier to avoid using readl/writel non relaxed function
61e6b7f580SIvan Khoronzhuk * variants, because in our case non relaxed variants hide the true places
62e6b7f580SIvan Khoronzhuk * where barrier is needed.
63e6b7f580SIvan Khoronzhuk */
keystone_timer_barrier(void)64e6b7f580SIvan Khoronzhuk static inline void keystone_timer_barrier(void)
65e6b7f580SIvan Khoronzhuk {
66e6b7f580SIvan Khoronzhuk __iowmb();
67e6b7f580SIvan Khoronzhuk }
68e6b7f580SIvan Khoronzhuk
69e6b7f580SIvan Khoronzhuk /**
70e6b7f580SIvan Khoronzhuk * keystone_timer_config: configures timer to work in oneshot/periodic modes.
71634eb0ecSViresh Kumar * @ mask: mask of the mode to configure
72e6b7f580SIvan Khoronzhuk * @ period: cycles number to configure for
73e6b7f580SIvan Khoronzhuk */
keystone_timer_config(u64 period,int mask)74634eb0ecSViresh Kumar static int keystone_timer_config(u64 period, int mask)
75e6b7f580SIvan Khoronzhuk {
76e6b7f580SIvan Khoronzhuk u32 tcr;
77e6b7f580SIvan Khoronzhuk u32 off;
78e6b7f580SIvan Khoronzhuk
79e6b7f580SIvan Khoronzhuk tcr = keystone_timer_readl(TCR);
80e6b7f580SIvan Khoronzhuk off = tcr & ~(TCR_ENAMODE_MASK);
81e6b7f580SIvan Khoronzhuk
82e6b7f580SIvan Khoronzhuk /* set enable mode */
83634eb0ecSViresh Kumar tcr |= mask;
84e6b7f580SIvan Khoronzhuk
85e6b7f580SIvan Khoronzhuk /* disable timer */
86e6b7f580SIvan Khoronzhuk keystone_timer_writel(off, TCR);
87e6b7f580SIvan Khoronzhuk /* here we have to be sure the timer has been disabled */
88e6b7f580SIvan Khoronzhuk keystone_timer_barrier();
89e6b7f580SIvan Khoronzhuk
90e6b7f580SIvan Khoronzhuk /* reset counter to zero, set new period */
91e6b7f580SIvan Khoronzhuk keystone_timer_writel(0, TIM12);
92e6b7f580SIvan Khoronzhuk keystone_timer_writel(0, TIM34);
93e6b7f580SIvan Khoronzhuk keystone_timer_writel(period & 0xffffffff, PRD12);
94e6b7f580SIvan Khoronzhuk keystone_timer_writel(period >> 32, PRD34);
95e6b7f580SIvan Khoronzhuk
96e6b7f580SIvan Khoronzhuk /*
97e6b7f580SIvan Khoronzhuk * enable timer
98e6b7f580SIvan Khoronzhuk * here we have to be sure that CNTLO, CNTHI, PRDLO, PRDHI registers
99e6b7f580SIvan Khoronzhuk * have been written.
100e6b7f580SIvan Khoronzhuk */
101e6b7f580SIvan Khoronzhuk keystone_timer_barrier();
102e6b7f580SIvan Khoronzhuk keystone_timer_writel(tcr, TCR);
103e6b7f580SIvan Khoronzhuk return 0;
104e6b7f580SIvan Khoronzhuk }
105e6b7f580SIvan Khoronzhuk
keystone_timer_disable(void)106e6b7f580SIvan Khoronzhuk static void keystone_timer_disable(void)
107e6b7f580SIvan Khoronzhuk {
108e6b7f580SIvan Khoronzhuk u32 tcr;
109e6b7f580SIvan Khoronzhuk
110e6b7f580SIvan Khoronzhuk tcr = keystone_timer_readl(TCR);
111e6b7f580SIvan Khoronzhuk
112e6b7f580SIvan Khoronzhuk /* disable timer */
113e6b7f580SIvan Khoronzhuk tcr &= ~(TCR_ENAMODE_MASK);
114e6b7f580SIvan Khoronzhuk keystone_timer_writel(tcr, TCR);
115e6b7f580SIvan Khoronzhuk }
116e6b7f580SIvan Khoronzhuk
keystone_timer_interrupt(int irq,void * dev_id)117e6b7f580SIvan Khoronzhuk static irqreturn_t keystone_timer_interrupt(int irq, void *dev_id)
118e6b7f580SIvan Khoronzhuk {
119e6b7f580SIvan Khoronzhuk struct clock_event_device *evt = dev_id;
120e6b7f580SIvan Khoronzhuk
121e6b7f580SIvan Khoronzhuk evt->event_handler(evt);
122e6b7f580SIvan Khoronzhuk return IRQ_HANDLED;
123e6b7f580SIvan Khoronzhuk }
124e6b7f580SIvan Khoronzhuk
keystone_set_next_event(unsigned long cycles,struct clock_event_device * evt)125e6b7f580SIvan Khoronzhuk static int keystone_set_next_event(unsigned long cycles,
126e6b7f580SIvan Khoronzhuk struct clock_event_device *evt)
127e6b7f580SIvan Khoronzhuk {
128634eb0ecSViresh Kumar return keystone_timer_config(cycles, TCR_ENAMODE_ONESHOT_MASK);
129e6b7f580SIvan Khoronzhuk }
130e6b7f580SIvan Khoronzhuk
keystone_shutdown(struct clock_event_device * evt)131634eb0ecSViresh Kumar static int keystone_shutdown(struct clock_event_device *evt)
132e6b7f580SIvan Khoronzhuk {
133e6b7f580SIvan Khoronzhuk keystone_timer_disable();
134634eb0ecSViresh Kumar return 0;
135e6b7f580SIvan Khoronzhuk }
136634eb0ecSViresh Kumar
keystone_set_periodic(struct clock_event_device * evt)137634eb0ecSViresh Kumar static int keystone_set_periodic(struct clock_event_device *evt)
138634eb0ecSViresh Kumar {
139634eb0ecSViresh Kumar keystone_timer_config(timer.hz_period, TCR_ENAMODE_PERIODIC_MASK);
140634eb0ecSViresh Kumar return 0;
141e6b7f580SIvan Khoronzhuk }
142e6b7f580SIvan Khoronzhuk
keystone_timer_init(struct device_node * np)14353186505SDaniel Lezcano static int __init keystone_timer_init(struct device_node *np)
144e6b7f580SIvan Khoronzhuk {
145e6b7f580SIvan Khoronzhuk struct clock_event_device *event_dev = &timer.event_dev;
146e6b7f580SIvan Khoronzhuk unsigned long rate;
147e6b7f580SIvan Khoronzhuk struct clk *clk;
148e6b7f580SIvan Khoronzhuk int irq, error;
149e6b7f580SIvan Khoronzhuk
150e6b7f580SIvan Khoronzhuk irq = irq_of_parse_and_map(np, 0);
151bdf7344eSDaniel Lezcano if (!irq) {
152e6b7f580SIvan Khoronzhuk pr_err("%s: failed to map interrupts\n", __func__);
15353186505SDaniel Lezcano return -EINVAL;
154e6b7f580SIvan Khoronzhuk }
155e6b7f580SIvan Khoronzhuk
156e6b7f580SIvan Khoronzhuk timer.base = of_iomap(np, 0);
157e6b7f580SIvan Khoronzhuk if (!timer.base) {
158e6b7f580SIvan Khoronzhuk pr_err("%s: failed to map registers\n", __func__);
15953186505SDaniel Lezcano return -ENXIO;
160e6b7f580SIvan Khoronzhuk }
161e6b7f580SIvan Khoronzhuk
162e6b7f580SIvan Khoronzhuk clk = of_clk_get(np, 0);
163e6b7f580SIvan Khoronzhuk if (IS_ERR(clk)) {
164e6b7f580SIvan Khoronzhuk pr_err("%s: failed to get clock\n", __func__);
165e6b7f580SIvan Khoronzhuk iounmap(timer.base);
16653186505SDaniel Lezcano return PTR_ERR(clk);
167e6b7f580SIvan Khoronzhuk }
168e6b7f580SIvan Khoronzhuk
169e6b7f580SIvan Khoronzhuk error = clk_prepare_enable(clk);
170e6b7f580SIvan Khoronzhuk if (error) {
171e6b7f580SIvan Khoronzhuk pr_err("%s: failed to enable clock\n", __func__);
172e6b7f580SIvan Khoronzhuk goto err;
173e6b7f580SIvan Khoronzhuk }
174e6b7f580SIvan Khoronzhuk
175e6b7f580SIvan Khoronzhuk rate = clk_get_rate(clk);
176e6b7f580SIvan Khoronzhuk
177e6b7f580SIvan Khoronzhuk /* disable, use internal clock source */
178e6b7f580SIvan Khoronzhuk keystone_timer_writel(0, TCR);
179e6b7f580SIvan Khoronzhuk /* here we have to be sure the timer has been disabled */
180e6b7f580SIvan Khoronzhuk keystone_timer_barrier();
181e6b7f580SIvan Khoronzhuk
182e6b7f580SIvan Khoronzhuk /* reset timer as 64-bit, no pre-scaler, plus features are disabled */
183e6b7f580SIvan Khoronzhuk keystone_timer_writel(0, TGCR);
184e6b7f580SIvan Khoronzhuk
185e6b7f580SIvan Khoronzhuk /* unreset timer */
186e099d01eSMatthias Brugger keystone_timer_writel(TGCR_TIM_UNRESET_MASK, TGCR);
187e6b7f580SIvan Khoronzhuk
188e6b7f580SIvan Khoronzhuk /* init counter to zero */
189e6b7f580SIvan Khoronzhuk keystone_timer_writel(0, TIM12);
190e6b7f580SIvan Khoronzhuk keystone_timer_writel(0, TIM34);
191e6b7f580SIvan Khoronzhuk
192e6b7f580SIvan Khoronzhuk timer.hz_period = DIV_ROUND_UP(rate, HZ);
193e6b7f580SIvan Khoronzhuk
194e6b7f580SIvan Khoronzhuk /* enable timer interrupts */
195e6b7f580SIvan Khoronzhuk keystone_timer_writel(INTCTLSTAT_ENINT_MASK, INTCTLSTAT);
196e6b7f580SIvan Khoronzhuk
197e6b7f580SIvan Khoronzhuk error = request_irq(irq, keystone_timer_interrupt, IRQF_TIMER,
198e6b7f580SIvan Khoronzhuk TIMER_NAME, event_dev);
199e6b7f580SIvan Khoronzhuk if (error) {
200e6b7f580SIvan Khoronzhuk pr_err("%s: failed to setup irq\n", __func__);
201e6b7f580SIvan Khoronzhuk goto err;
202e6b7f580SIvan Khoronzhuk }
203e6b7f580SIvan Khoronzhuk
204e6b7f580SIvan Khoronzhuk /* setup clockevent */
205e6b7f580SIvan Khoronzhuk event_dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
206e6b7f580SIvan Khoronzhuk event_dev->set_next_event = keystone_set_next_event;
207634eb0ecSViresh Kumar event_dev->set_state_shutdown = keystone_shutdown;
208634eb0ecSViresh Kumar event_dev->set_state_periodic = keystone_set_periodic;
209634eb0ecSViresh Kumar event_dev->set_state_oneshot = keystone_shutdown;
210f8f5fe86SSudeep Holla event_dev->cpumask = cpu_possible_mask;
211e6b7f580SIvan Khoronzhuk event_dev->owner = THIS_MODULE;
212e6b7f580SIvan Khoronzhuk event_dev->name = TIMER_NAME;
213e6b7f580SIvan Khoronzhuk event_dev->irq = irq;
214e6b7f580SIvan Khoronzhuk
215e6b7f580SIvan Khoronzhuk clockevents_config_and_register(event_dev, rate, 1, ULONG_MAX);
216e6b7f580SIvan Khoronzhuk
217e6b7f580SIvan Khoronzhuk pr_info("keystone timer clock @%lu Hz\n", rate);
21853186505SDaniel Lezcano return 0;
219e6b7f580SIvan Khoronzhuk err:
220e6b7f580SIvan Khoronzhuk clk_put(clk);
221e6b7f580SIvan Khoronzhuk iounmap(timer.base);
22253186505SDaniel Lezcano return error;
223e6b7f580SIvan Khoronzhuk }
224e6b7f580SIvan Khoronzhuk
22517273395SDaniel Lezcano TIMER_OF_DECLARE(keystone_timer, "ti,keystone-timer",
226e6b7f580SIvan Khoronzhuk keystone_timer_init);
227