1c53bb605SFabio Estevam // SPDX-License-Identifier: GPL-2.0+ 2c53bb605SFabio Estevam // 3c53bb605SFabio Estevam // Copyright (C) 2000-2001 Deep Blue Solutions 4c53bb605SFabio Estevam // Copyright (C) 2002 Shane Nay (shane@minirl.com) 5c53bb605SFabio Estevam // Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) 6c53bb605SFabio Estevam // Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 7bea5af41SShawn Guo 8bea5af41SShawn Guo #include <linux/interrupt.h> 9bea5af41SShawn Guo #include <linux/irq.h> 10bea5af41SShawn Guo #include <linux/clockchips.h> 11bea5af41SShawn Guo #include <linux/clk.h> 12bea5af41SShawn Guo #include <linux/delay.h> 13bea5af41SShawn Guo #include <linux/err.h> 14bea5af41SShawn Guo #include <linux/sched_clock.h> 15bea5af41SShawn Guo #include <linux/slab.h> 16bea5af41SShawn Guo #include <linux/of.h> 17bea5af41SShawn Guo #include <linux/of_address.h> 18bea5af41SShawn Guo #include <linux/of_irq.h> 19bea5af41SShawn Guo #include <soc/imx/timer.h> 20bea5af41SShawn Guo 21bea5af41SShawn Guo /* 22bea5af41SShawn Guo * There are 4 versions of the timer hardware on Freescale MXC hardware. 23bea5af41SShawn Guo * - MX1/MXL 24bea5af41SShawn Guo * - MX21, MX27. 25bea5af41SShawn Guo * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0) 26bea5af41SShawn Guo * - MX6DL, MX6SX, MX6Q(rev1.1+) 27bea5af41SShawn Guo */ 28bea5af41SShawn Guo 29bea5af41SShawn Guo /* defines common for all i.MX */ 30bea5af41SShawn Guo #define MXC_TCTL 0x00 31bea5af41SShawn Guo #define MXC_TCTL_TEN (1 << 0) /* Enable module */ 32bea5af41SShawn Guo #define MXC_TPRER 0x04 33bea5af41SShawn Guo 34bea5af41SShawn Guo /* MX1, MX21, MX27 */ 35bea5af41SShawn Guo #define MX1_2_TCTL_CLK_PCLK1 (1 << 1) 36bea5af41SShawn Guo #define MX1_2_TCTL_IRQEN (1 << 4) 37bea5af41SShawn Guo #define MX1_2_TCTL_FRR (1 << 8) 38bea5af41SShawn Guo #define MX1_2_TCMP 0x08 39bea5af41SShawn Guo #define MX1_2_TCN 0x10 40bea5af41SShawn Guo #define MX1_2_TSTAT 0x14 41bea5af41SShawn Guo 42bea5af41SShawn Guo /* MX21, MX27 */ 43bea5af41SShawn Guo #define MX2_TSTAT_CAPT (1 << 1) 44bea5af41SShawn Guo #define MX2_TSTAT_COMP (1 << 0) 45bea5af41SShawn Guo 46bea5af41SShawn Guo /* MX31, MX35, MX25, MX5, MX6 */ 47bea5af41SShawn Guo #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ 48bea5af41SShawn Guo #define V2_TCTL_CLK_IPG (1 << 6) 49bea5af41SShawn Guo #define V2_TCTL_CLK_PER (2 << 6) 50bea5af41SShawn Guo #define V2_TCTL_CLK_OSC_DIV8 (5 << 6) 51bea5af41SShawn Guo #define V2_TCTL_FRR (1 << 9) 52bea5af41SShawn Guo #define V2_TCTL_24MEN (1 << 10) 53bea5af41SShawn Guo #define V2_TPRER_PRE24M 12 54bea5af41SShawn Guo #define V2_IR 0x0c 55bea5af41SShawn Guo #define V2_TSTAT 0x08 56bea5af41SShawn Guo #define V2_TSTAT_OF1 (1 << 0) 57bea5af41SShawn Guo #define V2_TCN 0x24 58bea5af41SShawn Guo #define V2_TCMP 0x10 59bea5af41SShawn Guo 60bea5af41SShawn Guo #define V2_TIMER_RATE_OSC_DIV8 3000000 61bea5af41SShawn Guo 62bea5af41SShawn Guo struct imx_timer { 63bea5af41SShawn Guo enum imx_gpt_type type; 64bea5af41SShawn Guo void __iomem *base; 65bea5af41SShawn Guo int irq; 66bea5af41SShawn Guo struct clk *clk_per; 67bea5af41SShawn Guo struct clk *clk_ipg; 68bea5af41SShawn Guo const struct imx_gpt_data *gpt; 69bea5af41SShawn Guo struct clock_event_device ced; 70bea5af41SShawn Guo struct irqaction act; 71bea5af41SShawn Guo }; 72bea5af41SShawn Guo 73bea5af41SShawn Guo struct imx_gpt_data { 74bea5af41SShawn Guo int reg_tstat; 75bea5af41SShawn Guo int reg_tcn; 76bea5af41SShawn Guo int reg_tcmp; 77bea5af41SShawn Guo void (*gpt_setup_tctl)(struct imx_timer *imxtm); 78bea5af41SShawn Guo void (*gpt_irq_enable)(struct imx_timer *imxtm); 79bea5af41SShawn Guo void (*gpt_irq_disable)(struct imx_timer *imxtm); 80bea5af41SShawn Guo void (*gpt_irq_acknowledge)(struct imx_timer *imxtm); 81bea5af41SShawn Guo int (*set_next_event)(unsigned long evt, 82bea5af41SShawn Guo struct clock_event_device *ced); 83bea5af41SShawn Guo }; 84bea5af41SShawn Guo 85bea5af41SShawn Guo static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced) 86bea5af41SShawn Guo { 87bea5af41SShawn Guo return container_of(ced, struct imx_timer, ced); 88bea5af41SShawn Guo } 89bea5af41SShawn Guo 90bea5af41SShawn Guo static void imx1_gpt_irq_disable(struct imx_timer *imxtm) 91bea5af41SShawn Guo { 92bea5af41SShawn Guo unsigned int tmp; 93bea5af41SShawn Guo 94bea5af41SShawn Guo tmp = readl_relaxed(imxtm->base + MXC_TCTL); 95bea5af41SShawn Guo writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); 96bea5af41SShawn Guo } 97bea5af41SShawn Guo #define imx21_gpt_irq_disable imx1_gpt_irq_disable 98bea5af41SShawn Guo 99bea5af41SShawn Guo static void imx31_gpt_irq_disable(struct imx_timer *imxtm) 100bea5af41SShawn Guo { 101bea5af41SShawn Guo writel_relaxed(0, imxtm->base + V2_IR); 102bea5af41SShawn Guo } 103bea5af41SShawn Guo #define imx6dl_gpt_irq_disable imx31_gpt_irq_disable 104bea5af41SShawn Guo 105bea5af41SShawn Guo static void imx1_gpt_irq_enable(struct imx_timer *imxtm) 106bea5af41SShawn Guo { 107bea5af41SShawn Guo unsigned int tmp; 108bea5af41SShawn Guo 109bea5af41SShawn Guo tmp = readl_relaxed(imxtm->base + MXC_TCTL); 110bea5af41SShawn Guo writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); 111bea5af41SShawn Guo } 112bea5af41SShawn Guo #define imx21_gpt_irq_enable imx1_gpt_irq_enable 113bea5af41SShawn Guo 114bea5af41SShawn Guo static void imx31_gpt_irq_enable(struct imx_timer *imxtm) 115bea5af41SShawn Guo { 116bea5af41SShawn Guo writel_relaxed(1<<0, imxtm->base + V2_IR); 117bea5af41SShawn Guo } 118bea5af41SShawn Guo #define imx6dl_gpt_irq_enable imx31_gpt_irq_enable 119bea5af41SShawn Guo 120bea5af41SShawn Guo static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm) 121bea5af41SShawn Guo { 122bea5af41SShawn Guo writel_relaxed(0, imxtm->base + MX1_2_TSTAT); 123bea5af41SShawn Guo } 124bea5af41SShawn Guo 125bea5af41SShawn Guo static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm) 126bea5af41SShawn Guo { 127bea5af41SShawn Guo writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, 128bea5af41SShawn Guo imxtm->base + MX1_2_TSTAT); 129bea5af41SShawn Guo } 130bea5af41SShawn Guo 131bea5af41SShawn Guo static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm) 132bea5af41SShawn Guo { 133bea5af41SShawn Guo writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT); 134bea5af41SShawn Guo } 135bea5af41SShawn Guo #define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge 136bea5af41SShawn Guo 137bea5af41SShawn Guo static void __iomem *sched_clock_reg; 138bea5af41SShawn Guo 139bea5af41SShawn Guo static u64 notrace mxc_read_sched_clock(void) 140bea5af41SShawn Guo { 141bea5af41SShawn Guo return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0; 142bea5af41SShawn Guo } 143bea5af41SShawn Guo 144*df181e38SAnson Huang #if defined(CONFIG_ARM) 145bea5af41SShawn Guo static struct delay_timer imx_delay_timer; 146bea5af41SShawn Guo 147bea5af41SShawn Guo static unsigned long imx_read_current_timer(void) 148bea5af41SShawn Guo { 149bea5af41SShawn Guo return readl_relaxed(sched_clock_reg); 150bea5af41SShawn Guo } 151*df181e38SAnson Huang #endif 152bea5af41SShawn Guo 153bea5af41SShawn Guo static int __init mxc_clocksource_init(struct imx_timer *imxtm) 154bea5af41SShawn Guo { 155bea5af41SShawn Guo unsigned int c = clk_get_rate(imxtm->clk_per); 156bea5af41SShawn Guo void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn; 157bea5af41SShawn Guo 158*df181e38SAnson Huang #if defined(CONFIG_ARM) 159bea5af41SShawn Guo imx_delay_timer.read_current_timer = &imx_read_current_timer; 160bea5af41SShawn Guo imx_delay_timer.freq = c; 161bea5af41SShawn Guo register_current_timer_delay(&imx_delay_timer); 162*df181e38SAnson Huang #endif 163bea5af41SShawn Guo 164bea5af41SShawn Guo sched_clock_reg = reg; 165bea5af41SShawn Guo 166bea5af41SShawn Guo sched_clock_register(mxc_read_sched_clock, 32, c); 167bea5af41SShawn Guo return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, 168bea5af41SShawn Guo clocksource_mmio_readl_up); 169bea5af41SShawn Guo } 170bea5af41SShawn Guo 171bea5af41SShawn Guo /* clock event */ 172bea5af41SShawn Guo 173bea5af41SShawn Guo static int mx1_2_set_next_event(unsigned long evt, 174bea5af41SShawn Guo struct clock_event_device *ced) 175bea5af41SShawn Guo { 176bea5af41SShawn Guo struct imx_timer *imxtm = to_imx_timer(ced); 177bea5af41SShawn Guo unsigned long tcmp; 178bea5af41SShawn Guo 179bea5af41SShawn Guo tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt; 180bea5af41SShawn Guo 181bea5af41SShawn Guo writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP); 182bea5af41SShawn Guo 183bea5af41SShawn Guo return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ? 184bea5af41SShawn Guo -ETIME : 0; 185bea5af41SShawn Guo } 186bea5af41SShawn Guo 187bea5af41SShawn Guo static int v2_set_next_event(unsigned long evt, 188bea5af41SShawn Guo struct clock_event_device *ced) 189bea5af41SShawn Guo { 190bea5af41SShawn Guo struct imx_timer *imxtm = to_imx_timer(ced); 191bea5af41SShawn Guo unsigned long tcmp; 192bea5af41SShawn Guo 193bea5af41SShawn Guo tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt; 194bea5af41SShawn Guo 195bea5af41SShawn Guo writel_relaxed(tcmp, imxtm->base + V2_TCMP); 196bea5af41SShawn Guo 197bea5af41SShawn Guo return evt < 0x7fffffff && 198bea5af41SShawn Guo (int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ? 199bea5af41SShawn Guo -ETIME : 0; 200bea5af41SShawn Guo } 201bea5af41SShawn Guo 20226b91f04SViresh Kumar static int mxc_shutdown(struct clock_event_device *ced) 20326b91f04SViresh Kumar { 20426b91f04SViresh Kumar struct imx_timer *imxtm = to_imx_timer(ced); 20526b91f04SViresh Kumar unsigned long flags; 20626b91f04SViresh Kumar u32 tcn; 20726b91f04SViresh Kumar 20826b91f04SViresh Kumar /* 20926b91f04SViresh Kumar * The timer interrupt generation is disabled at least 21026b91f04SViresh Kumar * for enough time to call mxc_set_next_event() 21126b91f04SViresh Kumar */ 21226b91f04SViresh Kumar local_irq_save(flags); 21326b91f04SViresh Kumar 21426b91f04SViresh Kumar /* Disable interrupt in GPT module */ 21526b91f04SViresh Kumar imxtm->gpt->gpt_irq_disable(imxtm); 21626b91f04SViresh Kumar 21726b91f04SViresh Kumar tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); 21826b91f04SViresh Kumar /* Set event time into far-far future */ 21926b91f04SViresh Kumar writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); 22026b91f04SViresh Kumar 22126b91f04SViresh Kumar /* Clear pending interrupt */ 22226b91f04SViresh Kumar imxtm->gpt->gpt_irq_acknowledge(imxtm); 22326b91f04SViresh Kumar 224bea5af41SShawn Guo #ifdef DEBUG 22526b91f04SViresh Kumar printk(KERN_INFO "%s: changing mode\n", __func__); 226bea5af41SShawn Guo #endif /* DEBUG */ 227bea5af41SShawn Guo 22826b91f04SViresh Kumar local_irq_restore(flags); 22926b91f04SViresh Kumar 23026b91f04SViresh Kumar return 0; 23126b91f04SViresh Kumar } 23226b91f04SViresh Kumar 23326b91f04SViresh Kumar static int mxc_set_oneshot(struct clock_event_device *ced) 234bea5af41SShawn Guo { 235bea5af41SShawn Guo struct imx_timer *imxtm = to_imx_timer(ced); 236bea5af41SShawn Guo unsigned long flags; 237bea5af41SShawn Guo 238bea5af41SShawn Guo /* 239bea5af41SShawn Guo * The timer interrupt generation is disabled at least 240bea5af41SShawn Guo * for enough time to call mxc_set_next_event() 241bea5af41SShawn Guo */ 242bea5af41SShawn Guo local_irq_save(flags); 243bea5af41SShawn Guo 244bea5af41SShawn Guo /* Disable interrupt in GPT module */ 245bea5af41SShawn Guo imxtm->gpt->gpt_irq_disable(imxtm); 246bea5af41SShawn Guo 24726b91f04SViresh Kumar if (!clockevent_state_oneshot(ced)) { 248bea5af41SShawn Guo u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); 249bea5af41SShawn Guo /* Set event time into far-far future */ 250bea5af41SShawn Guo writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); 251bea5af41SShawn Guo 252bea5af41SShawn Guo /* Clear pending interrupt */ 253bea5af41SShawn Guo imxtm->gpt->gpt_irq_acknowledge(imxtm); 254bea5af41SShawn Guo } 255bea5af41SShawn Guo 256bea5af41SShawn Guo #ifdef DEBUG 25726b91f04SViresh Kumar printk(KERN_INFO "%s: changing mode\n", __func__); 258bea5af41SShawn Guo #endif /* DEBUG */ 259bea5af41SShawn Guo 260bea5af41SShawn Guo /* 261bea5af41SShawn Guo * Do not put overhead of interrupt enable/disable into 262bea5af41SShawn Guo * mxc_set_next_event(), the core has about 4 minutes 263bea5af41SShawn Guo * to call mxc_set_next_event() or shutdown clock after 264bea5af41SShawn Guo * mode switching 265bea5af41SShawn Guo */ 266bea5af41SShawn Guo imxtm->gpt->gpt_irq_enable(imxtm); 267bea5af41SShawn Guo local_irq_restore(flags); 26826b91f04SViresh Kumar 26926b91f04SViresh Kumar return 0; 270bea5af41SShawn Guo } 271bea5af41SShawn Guo 272bea5af41SShawn Guo /* 273bea5af41SShawn Guo * IRQ handler for the timer 274bea5af41SShawn Guo */ 275bea5af41SShawn Guo static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) 276bea5af41SShawn Guo { 277bea5af41SShawn Guo struct clock_event_device *ced = dev_id; 278bea5af41SShawn Guo struct imx_timer *imxtm = to_imx_timer(ced); 279bea5af41SShawn Guo uint32_t tstat; 280bea5af41SShawn Guo 281bea5af41SShawn Guo tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat); 282bea5af41SShawn Guo 283bea5af41SShawn Guo imxtm->gpt->gpt_irq_acknowledge(imxtm); 284bea5af41SShawn Guo 285bea5af41SShawn Guo ced->event_handler(ced); 286bea5af41SShawn Guo 287bea5af41SShawn Guo return IRQ_HANDLED; 288bea5af41SShawn Guo } 289bea5af41SShawn Guo 290bea5af41SShawn Guo static int __init mxc_clockevent_init(struct imx_timer *imxtm) 291bea5af41SShawn Guo { 292bea5af41SShawn Guo struct clock_event_device *ced = &imxtm->ced; 293bea5af41SShawn Guo struct irqaction *act = &imxtm->act; 294bea5af41SShawn Guo 295bea5af41SShawn Guo ced->name = "mxc_timer1"; 296f1c08c9bSLucas Stach ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ; 29726b91f04SViresh Kumar ced->set_state_shutdown = mxc_shutdown; 29826b91f04SViresh Kumar ced->set_state_oneshot = mxc_set_oneshot; 29926b91f04SViresh Kumar ced->tick_resume = mxc_shutdown; 300bea5af41SShawn Guo ced->set_next_event = imxtm->gpt->set_next_event; 301bea5af41SShawn Guo ced->rating = 200; 302bea5af41SShawn Guo ced->cpumask = cpumask_of(0); 303f1c08c9bSLucas Stach ced->irq = imxtm->irq; 304bea5af41SShawn Guo clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per), 305bea5af41SShawn Guo 0xff, 0xfffffffe); 306bea5af41SShawn Guo 307bea5af41SShawn Guo act->name = "i.MX Timer Tick"; 308bea5af41SShawn Guo act->flags = IRQF_TIMER | IRQF_IRQPOLL; 309bea5af41SShawn Guo act->handler = mxc_timer_interrupt; 310bea5af41SShawn Guo act->dev_id = ced; 311bea5af41SShawn Guo 312bea5af41SShawn Guo return setup_irq(imxtm->irq, act); 313bea5af41SShawn Guo } 314bea5af41SShawn Guo 315bea5af41SShawn Guo static void imx1_gpt_setup_tctl(struct imx_timer *imxtm) 316bea5af41SShawn Guo { 317bea5af41SShawn Guo u32 tctl_val; 318bea5af41SShawn Guo 319bea5af41SShawn Guo tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; 320bea5af41SShawn Guo writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); 321bea5af41SShawn Guo } 322bea5af41SShawn Guo #define imx21_gpt_setup_tctl imx1_gpt_setup_tctl 323bea5af41SShawn Guo 324bea5af41SShawn Guo static void imx31_gpt_setup_tctl(struct imx_timer *imxtm) 325bea5af41SShawn Guo { 326bea5af41SShawn Guo u32 tctl_val; 327bea5af41SShawn Guo 328bea5af41SShawn Guo tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; 329bea5af41SShawn Guo if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) 330bea5af41SShawn Guo tctl_val |= V2_TCTL_CLK_OSC_DIV8; 331bea5af41SShawn Guo else 332bea5af41SShawn Guo tctl_val |= V2_TCTL_CLK_PER; 333bea5af41SShawn Guo 334bea5af41SShawn Guo writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); 335bea5af41SShawn Guo } 336bea5af41SShawn Guo 337bea5af41SShawn Guo static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm) 338bea5af41SShawn Guo { 339bea5af41SShawn Guo u32 tctl_val; 340bea5af41SShawn Guo 341bea5af41SShawn Guo tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; 342bea5af41SShawn Guo if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) { 343bea5af41SShawn Guo tctl_val |= V2_TCTL_CLK_OSC_DIV8; 344bea5af41SShawn Guo /* 24 / 8 = 3 MHz */ 345bea5af41SShawn Guo writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER); 346bea5af41SShawn Guo tctl_val |= V2_TCTL_24MEN; 347bea5af41SShawn Guo } else { 348bea5af41SShawn Guo tctl_val |= V2_TCTL_CLK_PER; 349bea5af41SShawn Guo } 350bea5af41SShawn Guo 351bea5af41SShawn Guo writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); 352bea5af41SShawn Guo } 353bea5af41SShawn Guo 354bea5af41SShawn Guo static const struct imx_gpt_data imx1_gpt_data = { 355bea5af41SShawn Guo .reg_tstat = MX1_2_TSTAT, 356bea5af41SShawn Guo .reg_tcn = MX1_2_TCN, 357bea5af41SShawn Guo .reg_tcmp = MX1_2_TCMP, 358bea5af41SShawn Guo .gpt_irq_enable = imx1_gpt_irq_enable, 359bea5af41SShawn Guo .gpt_irq_disable = imx1_gpt_irq_disable, 360bea5af41SShawn Guo .gpt_irq_acknowledge = imx1_gpt_irq_acknowledge, 361bea5af41SShawn Guo .gpt_setup_tctl = imx1_gpt_setup_tctl, 362bea5af41SShawn Guo .set_next_event = mx1_2_set_next_event, 363bea5af41SShawn Guo }; 364bea5af41SShawn Guo 365bea5af41SShawn Guo static const struct imx_gpt_data imx21_gpt_data = { 366bea5af41SShawn Guo .reg_tstat = MX1_2_TSTAT, 367bea5af41SShawn Guo .reg_tcn = MX1_2_TCN, 368bea5af41SShawn Guo .reg_tcmp = MX1_2_TCMP, 369bea5af41SShawn Guo .gpt_irq_enable = imx21_gpt_irq_enable, 370bea5af41SShawn Guo .gpt_irq_disable = imx21_gpt_irq_disable, 371bea5af41SShawn Guo .gpt_irq_acknowledge = imx21_gpt_irq_acknowledge, 372bea5af41SShawn Guo .gpt_setup_tctl = imx21_gpt_setup_tctl, 373bea5af41SShawn Guo .set_next_event = mx1_2_set_next_event, 374bea5af41SShawn Guo }; 375bea5af41SShawn Guo 376bea5af41SShawn Guo static const struct imx_gpt_data imx31_gpt_data = { 377bea5af41SShawn Guo .reg_tstat = V2_TSTAT, 378bea5af41SShawn Guo .reg_tcn = V2_TCN, 379bea5af41SShawn Guo .reg_tcmp = V2_TCMP, 380bea5af41SShawn Guo .gpt_irq_enable = imx31_gpt_irq_enable, 381bea5af41SShawn Guo .gpt_irq_disable = imx31_gpt_irq_disable, 382bea5af41SShawn Guo .gpt_irq_acknowledge = imx31_gpt_irq_acknowledge, 383bea5af41SShawn Guo .gpt_setup_tctl = imx31_gpt_setup_tctl, 384bea5af41SShawn Guo .set_next_event = v2_set_next_event, 385bea5af41SShawn Guo }; 386bea5af41SShawn Guo 387bea5af41SShawn Guo static const struct imx_gpt_data imx6dl_gpt_data = { 388bea5af41SShawn Guo .reg_tstat = V2_TSTAT, 389bea5af41SShawn Guo .reg_tcn = V2_TCN, 390bea5af41SShawn Guo .reg_tcmp = V2_TCMP, 391bea5af41SShawn Guo .gpt_irq_enable = imx6dl_gpt_irq_enable, 392bea5af41SShawn Guo .gpt_irq_disable = imx6dl_gpt_irq_disable, 393bea5af41SShawn Guo .gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge, 394bea5af41SShawn Guo .gpt_setup_tctl = imx6dl_gpt_setup_tctl, 395bea5af41SShawn Guo .set_next_event = v2_set_next_event, 396bea5af41SShawn Guo }; 397bea5af41SShawn Guo 398c11cd416SDaniel Lezcano static int __init _mxc_timer_init(struct imx_timer *imxtm) 399bea5af41SShawn Guo { 400c11cd416SDaniel Lezcano int ret; 401c11cd416SDaniel Lezcano 402bea5af41SShawn Guo switch (imxtm->type) { 403bea5af41SShawn Guo case GPT_TYPE_IMX1: 404bea5af41SShawn Guo imxtm->gpt = &imx1_gpt_data; 405bea5af41SShawn Guo break; 406bea5af41SShawn Guo case GPT_TYPE_IMX21: 407bea5af41SShawn Guo imxtm->gpt = &imx21_gpt_data; 408bea5af41SShawn Guo break; 409bea5af41SShawn Guo case GPT_TYPE_IMX31: 410bea5af41SShawn Guo imxtm->gpt = &imx31_gpt_data; 411bea5af41SShawn Guo break; 412bea5af41SShawn Guo case GPT_TYPE_IMX6DL: 413bea5af41SShawn Guo imxtm->gpt = &imx6dl_gpt_data; 414bea5af41SShawn Guo break; 415bea5af41SShawn Guo default: 416c11cd416SDaniel Lezcano return -EINVAL; 417bea5af41SShawn Guo } 418bea5af41SShawn Guo 419bea5af41SShawn Guo if (IS_ERR(imxtm->clk_per)) { 420bea5af41SShawn Guo pr_err("i.MX timer: unable to get clk\n"); 421c11cd416SDaniel Lezcano return PTR_ERR(imxtm->clk_per); 422bea5af41SShawn Guo } 423bea5af41SShawn Guo 424bea5af41SShawn Guo if (!IS_ERR(imxtm->clk_ipg)) 425bea5af41SShawn Guo clk_prepare_enable(imxtm->clk_ipg); 426bea5af41SShawn Guo 427bea5af41SShawn Guo clk_prepare_enable(imxtm->clk_per); 428bea5af41SShawn Guo 429bea5af41SShawn Guo /* 430bea5af41SShawn Guo * Initialise to a known state (all timers off, and timing reset) 431bea5af41SShawn Guo */ 432bea5af41SShawn Guo 433bea5af41SShawn Guo writel_relaxed(0, imxtm->base + MXC_TCTL); 434bea5af41SShawn Guo writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */ 435bea5af41SShawn Guo 436bea5af41SShawn Guo imxtm->gpt->gpt_setup_tctl(imxtm); 437bea5af41SShawn Guo 438bea5af41SShawn Guo /* init and register the timer to the framework */ 439c11cd416SDaniel Lezcano ret = mxc_clocksource_init(imxtm); 440c11cd416SDaniel Lezcano if (ret) 441c11cd416SDaniel Lezcano return ret; 442c11cd416SDaniel Lezcano 443c11cd416SDaniel Lezcano return mxc_clockevent_init(imxtm); 444bea5af41SShawn Guo } 445bea5af41SShawn Guo 446bea5af41SShawn Guo void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type) 447bea5af41SShawn Guo { 448bea5af41SShawn Guo struct imx_timer *imxtm; 449bea5af41SShawn Guo 450bea5af41SShawn Guo imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); 451bea5af41SShawn Guo BUG_ON(!imxtm); 452bea5af41SShawn Guo 453bea5af41SShawn Guo imxtm->clk_per = clk_get_sys("imx-gpt.0", "per"); 454bea5af41SShawn Guo imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); 455bea5af41SShawn Guo 456bea5af41SShawn Guo imxtm->base = ioremap(pbase, SZ_4K); 457bea5af41SShawn Guo BUG_ON(!imxtm->base); 458bea5af41SShawn Guo 459bea5af41SShawn Guo imxtm->type = type; 460be3b0f9bSGuenter Roeck imxtm->irq = irq; 461bea5af41SShawn Guo 462bea5af41SShawn Guo _mxc_timer_init(imxtm); 463bea5af41SShawn Guo } 464bea5af41SShawn Guo 465c11cd416SDaniel Lezcano static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type) 466bea5af41SShawn Guo { 467bea5af41SShawn Guo struct imx_timer *imxtm; 468bea5af41SShawn Guo static int initialized; 469c11cd416SDaniel Lezcano int ret; 470bea5af41SShawn Guo 471bea5af41SShawn Guo /* Support one instance only */ 472bea5af41SShawn Guo if (initialized) 473c11cd416SDaniel Lezcano return 0; 474bea5af41SShawn Guo 475bea5af41SShawn Guo imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); 476c11cd416SDaniel Lezcano if (!imxtm) 477c11cd416SDaniel Lezcano return -ENOMEM; 478bea5af41SShawn Guo 479bea5af41SShawn Guo imxtm->base = of_iomap(np, 0); 480c11cd416SDaniel Lezcano if (!imxtm->base) 481c11cd416SDaniel Lezcano return -ENXIO; 482c11cd416SDaniel Lezcano 483bea5af41SShawn Guo imxtm->irq = irq_of_parse_and_map(np, 0); 484c11cd416SDaniel Lezcano if (imxtm->irq <= 0) 485c11cd416SDaniel Lezcano return -EINVAL; 486bea5af41SShawn Guo 487bea5af41SShawn Guo imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); 488bea5af41SShawn Guo 489bea5af41SShawn Guo /* Try osc_per first, and fall back to per otherwise */ 490bea5af41SShawn Guo imxtm->clk_per = of_clk_get_by_name(np, "osc_per"); 491bea5af41SShawn Guo if (IS_ERR(imxtm->clk_per)) 492bea5af41SShawn Guo imxtm->clk_per = of_clk_get_by_name(np, "per"); 493bea5af41SShawn Guo 494bea5af41SShawn Guo imxtm->type = type; 495bea5af41SShawn Guo 496c11cd416SDaniel Lezcano ret = _mxc_timer_init(imxtm); 497c11cd416SDaniel Lezcano if (ret) 498c11cd416SDaniel Lezcano return ret; 499bea5af41SShawn Guo 500bea5af41SShawn Guo initialized = 1; 501c11cd416SDaniel Lezcano 502c11cd416SDaniel Lezcano return 0; 503bea5af41SShawn Guo } 504bea5af41SShawn Guo 505c11cd416SDaniel Lezcano static int __init imx1_timer_init_dt(struct device_node *np) 506bea5af41SShawn Guo { 507c11cd416SDaniel Lezcano return mxc_timer_init_dt(np, GPT_TYPE_IMX1); 508bea5af41SShawn Guo } 509bea5af41SShawn Guo 510c11cd416SDaniel Lezcano static int __init imx21_timer_init_dt(struct device_node *np) 511bea5af41SShawn Guo { 512c11cd416SDaniel Lezcano return mxc_timer_init_dt(np, GPT_TYPE_IMX21); 513bea5af41SShawn Guo } 514bea5af41SShawn Guo 515c11cd416SDaniel Lezcano static int __init imx31_timer_init_dt(struct device_node *np) 516bea5af41SShawn Guo { 517bea5af41SShawn Guo enum imx_gpt_type type = GPT_TYPE_IMX31; 518bea5af41SShawn Guo 519bea5af41SShawn Guo /* 520bea5af41SShawn Guo * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S 521bea5af41SShawn Guo * GPT device, while they actually have different programming model. 522bea5af41SShawn Guo * This is a workaround to keep the existing i.MX6DL/S DTBs continue 523bea5af41SShawn Guo * working with the new kernel. 524bea5af41SShawn Guo */ 525bea5af41SShawn Guo if (of_machine_is_compatible("fsl,imx6dl")) 526bea5af41SShawn Guo type = GPT_TYPE_IMX6DL; 527bea5af41SShawn Guo 528c11cd416SDaniel Lezcano return mxc_timer_init_dt(np, type); 529bea5af41SShawn Guo } 530bea5af41SShawn Guo 531c11cd416SDaniel Lezcano static int __init imx6dl_timer_init_dt(struct device_node *np) 532bea5af41SShawn Guo { 533c11cd416SDaniel Lezcano return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL); 534bea5af41SShawn Guo } 535bea5af41SShawn Guo 53617273395SDaniel Lezcano TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt); 53717273395SDaniel Lezcano TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt); 53817273395SDaniel Lezcano TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt); 53917273395SDaniel Lezcano TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt); 54017273395SDaniel Lezcano TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt); 54117273395SDaniel Lezcano TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt); 54217273395SDaniel Lezcano TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt); 54317273395SDaniel Lezcano TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt); 54417273395SDaniel Lezcano TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt); 54517273395SDaniel Lezcano TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt); 54617273395SDaniel Lezcano TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt); 54717273395SDaniel Lezcano TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt); 548