106c3df49SJamie Iles /* 206c3df49SJamie Iles * (C) Copyright 2009 Intel Corporation 306c3df49SJamie Iles * Author: Jacob Pan (jacob.jun.pan@intel.com) 406c3df49SJamie Iles * 506c3df49SJamie Iles * Shared with ARM platforms, Jamie Iles, Picochip 2011 606c3df49SJamie Iles * 706c3df49SJamie Iles * This program is free software; you can redistribute it and/or modify 806c3df49SJamie Iles * it under the terms of the GNU General Public License version 2 as 906c3df49SJamie Iles * published by the Free Software Foundation. 1006c3df49SJamie Iles * 1106c3df49SJamie Iles * Support for the Synopsys DesignWare APB Timers. 1206c3df49SJamie Iles */ 1306c3df49SJamie Iles #include <linux/dw_apb_timer.h> 1406c3df49SJamie Iles #include <linux/delay.h> 1506c3df49SJamie Iles #include <linux/kernel.h> 1606c3df49SJamie Iles #include <linux/interrupt.h> 1706c3df49SJamie Iles #include <linux/irq.h> 1806c3df49SJamie Iles #include <linux/io.h> 1906c3df49SJamie Iles #include <linux/slab.h> 2006c3df49SJamie Iles 2106c3df49SJamie Iles #define APBT_MIN_PERIOD 4 2206c3df49SJamie Iles #define APBT_MIN_DELTA_USEC 200 2306c3df49SJamie Iles 2406c3df49SJamie Iles #define APBTMR_N_LOAD_COUNT 0x00 2506c3df49SJamie Iles #define APBTMR_N_CURRENT_VALUE 0x04 2606c3df49SJamie Iles #define APBTMR_N_CONTROL 0x08 2706c3df49SJamie Iles #define APBTMR_N_EOI 0x0c 2806c3df49SJamie Iles #define APBTMR_N_INT_STATUS 0x10 2906c3df49SJamie Iles 3006c3df49SJamie Iles #define APBTMRS_INT_STATUS 0xa0 3106c3df49SJamie Iles #define APBTMRS_EOI 0xa4 3206c3df49SJamie Iles #define APBTMRS_RAW_INT_STATUS 0xa8 3306c3df49SJamie Iles #define APBTMRS_COMP_VERSION 0xac 3406c3df49SJamie Iles 3506c3df49SJamie Iles #define APBTMR_CONTROL_ENABLE (1 << 0) 3606c3df49SJamie Iles /* 1: periodic, 0:free running. */ 3706c3df49SJamie Iles #define APBTMR_CONTROL_MODE_PERIODIC (1 << 1) 3806c3df49SJamie Iles #define APBTMR_CONTROL_INT (1 << 2) 3906c3df49SJamie Iles 4006c3df49SJamie Iles static inline struct dw_apb_clock_event_device * 4106c3df49SJamie Iles ced_to_dw_apb_ced(struct clock_event_device *evt) 4206c3df49SJamie Iles { 4306c3df49SJamie Iles return container_of(evt, struct dw_apb_clock_event_device, ced); 4406c3df49SJamie Iles } 4506c3df49SJamie Iles 4606c3df49SJamie Iles static inline struct dw_apb_clocksource * 4706c3df49SJamie Iles clocksource_to_dw_apb_clocksource(struct clocksource *cs) 4806c3df49SJamie Iles { 4906c3df49SJamie Iles return container_of(cs, struct dw_apb_clocksource, cs); 5006c3df49SJamie Iles } 5106c3df49SJamie Iles 5206c3df49SJamie Iles static unsigned long apbt_readl(struct dw_apb_timer *timer, unsigned long offs) 5306c3df49SJamie Iles { 5406c3df49SJamie Iles return readl(timer->base + offs); 5506c3df49SJamie Iles } 5606c3df49SJamie Iles 5706c3df49SJamie Iles static void apbt_writel(struct dw_apb_timer *timer, unsigned long val, 5806c3df49SJamie Iles unsigned long offs) 5906c3df49SJamie Iles { 6006c3df49SJamie Iles writel(val, timer->base + offs); 6106c3df49SJamie Iles } 6206c3df49SJamie Iles 6306c3df49SJamie Iles static void apbt_disable_int(struct dw_apb_timer *timer) 6406c3df49SJamie Iles { 6506c3df49SJamie Iles unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL); 6606c3df49SJamie Iles 6706c3df49SJamie Iles ctrl |= APBTMR_CONTROL_INT; 6806c3df49SJamie Iles apbt_writel(timer, ctrl, APBTMR_N_CONTROL); 6906c3df49SJamie Iles } 7006c3df49SJamie Iles 7106c3df49SJamie Iles /** 7206c3df49SJamie Iles * dw_apb_clockevent_pause() - stop the clock_event_device from running 7306c3df49SJamie Iles * 7406c3df49SJamie Iles * @dw_ced: The APB clock to stop generating events. 7506c3df49SJamie Iles */ 7606c3df49SJamie Iles void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced) 7706c3df49SJamie Iles { 7806c3df49SJamie Iles disable_irq(dw_ced->timer.irq); 7906c3df49SJamie Iles apbt_disable_int(&dw_ced->timer); 8006c3df49SJamie Iles } 8106c3df49SJamie Iles 8206c3df49SJamie Iles static void apbt_eoi(struct dw_apb_timer *timer) 8306c3df49SJamie Iles { 8406c3df49SJamie Iles apbt_readl(timer, APBTMR_N_EOI); 8506c3df49SJamie Iles } 8606c3df49SJamie Iles 8706c3df49SJamie Iles static irqreturn_t dw_apb_clockevent_irq(int irq, void *data) 8806c3df49SJamie Iles { 8906c3df49SJamie Iles struct clock_event_device *evt = data; 9006c3df49SJamie Iles struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); 9106c3df49SJamie Iles 9206c3df49SJamie Iles if (!evt->event_handler) { 9306c3df49SJamie Iles pr_info("Spurious APBT timer interrupt %d", irq); 9406c3df49SJamie Iles return IRQ_NONE; 9506c3df49SJamie Iles } 9606c3df49SJamie Iles 9706c3df49SJamie Iles if (dw_ced->eoi) 9806c3df49SJamie Iles dw_ced->eoi(&dw_ced->timer); 9906c3df49SJamie Iles 10006c3df49SJamie Iles evt->event_handler(evt); 10106c3df49SJamie Iles return IRQ_HANDLED; 10206c3df49SJamie Iles } 10306c3df49SJamie Iles 10406c3df49SJamie Iles static void apbt_enable_int(struct dw_apb_timer *timer) 10506c3df49SJamie Iles { 10606c3df49SJamie Iles unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL); 10706c3df49SJamie Iles /* clear pending intr */ 10806c3df49SJamie Iles apbt_readl(timer, APBTMR_N_EOI); 10906c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_INT; 11006c3df49SJamie Iles apbt_writel(timer, ctrl, APBTMR_N_CONTROL); 11106c3df49SJamie Iles } 11206c3df49SJamie Iles 11306c3df49SJamie Iles static void apbt_set_mode(enum clock_event_mode mode, 11406c3df49SJamie Iles struct clock_event_device *evt) 11506c3df49SJamie Iles { 11606c3df49SJamie Iles unsigned long ctrl; 11706c3df49SJamie Iles unsigned long period; 11806c3df49SJamie Iles struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); 11906c3df49SJamie Iles 12006c3df49SJamie Iles pr_debug("%s CPU %d mode=%d\n", __func__, first_cpu(*evt->cpumask), 12106c3df49SJamie Iles mode); 12206c3df49SJamie Iles 12306c3df49SJamie Iles switch (mode) { 12406c3df49SJamie Iles case CLOCK_EVT_MODE_PERIODIC: 12506c3df49SJamie Iles period = DIV_ROUND_UP(dw_ced->timer.freq, HZ); 12606c3df49SJamie Iles ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); 12706c3df49SJamie Iles ctrl |= APBTMR_CONTROL_MODE_PERIODIC; 12806c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 12906c3df49SJamie Iles /* 13006c3df49SJamie Iles * DW APB p. 46, have to disable timer before load counter, 13106c3df49SJamie Iles * may cause sync problem. 13206c3df49SJamie Iles */ 13306c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE; 13406c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 13506c3df49SJamie Iles udelay(1); 13606c3df49SJamie Iles pr_debug("Setting clock period %lu for HZ %d\n", period, HZ); 13706c3df49SJamie Iles apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT); 13806c3df49SJamie Iles ctrl |= APBTMR_CONTROL_ENABLE; 13906c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 14006c3df49SJamie Iles break; 14106c3df49SJamie Iles 14206c3df49SJamie Iles case CLOCK_EVT_MODE_ONESHOT: 14306c3df49SJamie Iles ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); 14406c3df49SJamie Iles /* 14506c3df49SJamie Iles * set free running mode, this mode will let timer reload max 14606c3df49SJamie Iles * timeout which will give time (3min on 25MHz clock) to rearm 14706c3df49SJamie Iles * the next event, therefore emulate the one-shot mode. 14806c3df49SJamie Iles */ 14906c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE; 15006c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; 15106c3df49SJamie Iles 15206c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 15306c3df49SJamie Iles /* write again to set free running mode */ 15406c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 15506c3df49SJamie Iles 15606c3df49SJamie Iles /* 15706c3df49SJamie Iles * DW APB p. 46, load counter with all 1s before starting free 15806c3df49SJamie Iles * running mode. 15906c3df49SJamie Iles */ 16006c3df49SJamie Iles apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT); 16106c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_INT; 16206c3df49SJamie Iles ctrl |= APBTMR_CONTROL_ENABLE; 16306c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 16406c3df49SJamie Iles break; 16506c3df49SJamie Iles 16606c3df49SJamie Iles case CLOCK_EVT_MODE_UNUSED: 16706c3df49SJamie Iles case CLOCK_EVT_MODE_SHUTDOWN: 16806c3df49SJamie Iles ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); 16906c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE; 17006c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 17106c3df49SJamie Iles break; 17206c3df49SJamie Iles 17306c3df49SJamie Iles case CLOCK_EVT_MODE_RESUME: 17406c3df49SJamie Iles apbt_enable_int(&dw_ced->timer); 17506c3df49SJamie Iles break; 17606c3df49SJamie Iles } 17706c3df49SJamie Iles } 17806c3df49SJamie Iles 17906c3df49SJamie Iles static int apbt_next_event(unsigned long delta, 18006c3df49SJamie Iles struct clock_event_device *evt) 18106c3df49SJamie Iles { 18206c3df49SJamie Iles unsigned long ctrl; 18306c3df49SJamie Iles struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt); 18406c3df49SJamie Iles 18506c3df49SJamie Iles /* Disable timer */ 18606c3df49SJamie Iles ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); 18706c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE; 18806c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 18906c3df49SJamie Iles /* write new count */ 19006c3df49SJamie Iles apbt_writel(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT); 19106c3df49SJamie Iles ctrl |= APBTMR_CONTROL_ENABLE; 19206c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); 19306c3df49SJamie Iles 19406c3df49SJamie Iles return 0; 19506c3df49SJamie Iles } 19606c3df49SJamie Iles 19706c3df49SJamie Iles /** 19806c3df49SJamie Iles * dw_apb_clockevent_init() - use an APB timer as a clock_event_device 19906c3df49SJamie Iles * 20006c3df49SJamie Iles * @cpu: The CPU the events will be targeted at. 20106c3df49SJamie Iles * @name: The name used for the timer and the IRQ for it. 20206c3df49SJamie Iles * @rating: The rating to give the timer. 20306c3df49SJamie Iles * @base: I/O base for the timer registers. 20406c3df49SJamie Iles * @irq: The interrupt number to use for the timer. 20506c3df49SJamie Iles * @freq: The frequency that the timer counts at. 20606c3df49SJamie Iles * 20706c3df49SJamie Iles * This creates a clock_event_device for using with the generic clock layer 20806c3df49SJamie Iles * but does not start and register it. This should be done with 20906c3df49SJamie Iles * dw_apb_clockevent_register() as the next step. If this is the first time 21006c3df49SJamie Iles * it has been called for a timer then the IRQ will be requested, if not it 21106c3df49SJamie Iles * just be enabled to allow CPU hotplug to avoid repeatedly requesting and 21206c3df49SJamie Iles * releasing the IRQ. 21306c3df49SJamie Iles */ 21406c3df49SJamie Iles struct dw_apb_clock_event_device * 21506c3df49SJamie Iles dw_apb_clockevent_init(int cpu, const char *name, unsigned rating, 21606c3df49SJamie Iles void __iomem *base, int irq, unsigned long freq) 21706c3df49SJamie Iles { 21806c3df49SJamie Iles struct dw_apb_clock_event_device *dw_ced = 21906c3df49SJamie Iles kzalloc(sizeof(*dw_ced), GFP_KERNEL); 22006c3df49SJamie Iles int err; 22106c3df49SJamie Iles 22206c3df49SJamie Iles if (!dw_ced) 22306c3df49SJamie Iles return NULL; 22406c3df49SJamie Iles 22506c3df49SJamie Iles dw_ced->timer.base = base; 22606c3df49SJamie Iles dw_ced->timer.irq = irq; 22706c3df49SJamie Iles dw_ced->timer.freq = freq; 22806c3df49SJamie Iles 22906c3df49SJamie Iles clockevents_calc_mult_shift(&dw_ced->ced, freq, APBT_MIN_PERIOD); 23006c3df49SJamie Iles dw_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff, 23106c3df49SJamie Iles &dw_ced->ced); 23206c3df49SJamie Iles dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced); 23306c3df49SJamie Iles dw_ced->ced.cpumask = cpumask_of(cpu); 23406c3df49SJamie Iles dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 23506c3df49SJamie Iles dw_ced->ced.set_mode = apbt_set_mode; 23606c3df49SJamie Iles dw_ced->ced.set_next_event = apbt_next_event; 23706c3df49SJamie Iles dw_ced->ced.irq = dw_ced->timer.irq; 23806c3df49SJamie Iles dw_ced->ced.rating = rating; 23906c3df49SJamie Iles dw_ced->ced.name = name; 24006c3df49SJamie Iles 24106c3df49SJamie Iles dw_ced->irqaction.name = dw_ced->ced.name; 24206c3df49SJamie Iles dw_ced->irqaction.handler = dw_apb_clockevent_irq; 24306c3df49SJamie Iles dw_ced->irqaction.dev_id = &dw_ced->ced; 24406c3df49SJamie Iles dw_ced->irqaction.irq = irq; 24506c3df49SJamie Iles dw_ced->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | 24606c3df49SJamie Iles IRQF_NOBALANCING | 24706c3df49SJamie Iles IRQF_DISABLED; 24806c3df49SJamie Iles 24906c3df49SJamie Iles dw_ced->eoi = apbt_eoi; 25006c3df49SJamie Iles err = setup_irq(irq, &dw_ced->irqaction); 25106c3df49SJamie Iles if (err) { 25206c3df49SJamie Iles pr_err("failed to request timer irq\n"); 25306c3df49SJamie Iles kfree(dw_ced); 25406c3df49SJamie Iles dw_ced = NULL; 25506c3df49SJamie Iles } 25606c3df49SJamie Iles 25706c3df49SJamie Iles return dw_ced; 25806c3df49SJamie Iles } 25906c3df49SJamie Iles 26006c3df49SJamie Iles /** 26106c3df49SJamie Iles * dw_apb_clockevent_resume() - resume a clock that has been paused. 26206c3df49SJamie Iles * 26306c3df49SJamie Iles * @dw_ced: The APB clock to resume. 26406c3df49SJamie Iles */ 26506c3df49SJamie Iles void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced) 26606c3df49SJamie Iles { 26706c3df49SJamie Iles enable_irq(dw_ced->timer.irq); 26806c3df49SJamie Iles } 26906c3df49SJamie Iles 27006c3df49SJamie Iles /** 27106c3df49SJamie Iles * dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ. 27206c3df49SJamie Iles * 27306c3df49SJamie Iles * @dw_ced: The APB clock to stop generating the events. 27406c3df49SJamie Iles */ 27506c3df49SJamie Iles void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced) 27606c3df49SJamie Iles { 27706c3df49SJamie Iles free_irq(dw_ced->timer.irq, &dw_ced->ced); 27806c3df49SJamie Iles } 27906c3df49SJamie Iles 28006c3df49SJamie Iles /** 28106c3df49SJamie Iles * dw_apb_clockevent_register() - register the clock with the generic layer 28206c3df49SJamie Iles * 28306c3df49SJamie Iles * @dw_ced: The APB clock to register as a clock_event_device. 28406c3df49SJamie Iles */ 28506c3df49SJamie Iles void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced) 28606c3df49SJamie Iles { 28706c3df49SJamie Iles apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL); 28806c3df49SJamie Iles clockevents_register_device(&dw_ced->ced); 28906c3df49SJamie Iles apbt_enable_int(&dw_ced->timer); 29006c3df49SJamie Iles } 29106c3df49SJamie Iles 29206c3df49SJamie Iles /** 29306c3df49SJamie Iles * dw_apb_clocksource_start() - start the clocksource counting. 29406c3df49SJamie Iles * 29506c3df49SJamie Iles * @dw_cs: The clocksource to start. 29606c3df49SJamie Iles * 29706c3df49SJamie Iles * This is used to start the clocksource before registration and can be used 29806c3df49SJamie Iles * to enable calibration of timers. 29906c3df49SJamie Iles */ 30006c3df49SJamie Iles void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs) 30106c3df49SJamie Iles { 30206c3df49SJamie Iles /* 30306c3df49SJamie Iles * start count down from 0xffff_ffff. this is done by toggling the 30406c3df49SJamie Iles * enable bit then load initial load count to ~0. 30506c3df49SJamie Iles */ 30606c3df49SJamie Iles unsigned long ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL); 30706c3df49SJamie Iles 30806c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE; 30906c3df49SJamie Iles apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL); 31006c3df49SJamie Iles apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT); 31106c3df49SJamie Iles /* enable, mask interrupt */ 31206c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; 31306c3df49SJamie Iles ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT); 31406c3df49SJamie Iles apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL); 31506c3df49SJamie Iles /* read it once to get cached counter value initialized */ 31606c3df49SJamie Iles dw_apb_clocksource_read(dw_cs); 31706c3df49SJamie Iles } 31806c3df49SJamie Iles 31906c3df49SJamie Iles static cycle_t __apbt_read_clocksource(struct clocksource *cs) 32006c3df49SJamie Iles { 32106c3df49SJamie Iles unsigned long current_count; 32206c3df49SJamie Iles struct dw_apb_clocksource *dw_cs = 32306c3df49SJamie Iles clocksource_to_dw_apb_clocksource(cs); 32406c3df49SJamie Iles 32506c3df49SJamie Iles current_count = apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE); 32606c3df49SJamie Iles 32706c3df49SJamie Iles return (cycle_t)~current_count; 32806c3df49SJamie Iles } 32906c3df49SJamie Iles 33006c3df49SJamie Iles static void apbt_restart_clocksource(struct clocksource *cs) 33106c3df49SJamie Iles { 33206c3df49SJamie Iles struct dw_apb_clocksource *dw_cs = 33306c3df49SJamie Iles clocksource_to_dw_apb_clocksource(cs); 33406c3df49SJamie Iles 33506c3df49SJamie Iles dw_apb_clocksource_start(dw_cs); 33606c3df49SJamie Iles } 33706c3df49SJamie Iles 33806c3df49SJamie Iles /** 33906c3df49SJamie Iles * dw_apb_clocksource_init() - use an APB timer as a clocksource. 34006c3df49SJamie Iles * 34106c3df49SJamie Iles * @rating: The rating to give the clocksource. 34206c3df49SJamie Iles * @name: The name for the clocksource. 34306c3df49SJamie Iles * @base: The I/O base for the timer registers. 34406c3df49SJamie Iles * @freq: The frequency that the timer counts at. 34506c3df49SJamie Iles * 34606c3df49SJamie Iles * This creates a clocksource using an APB timer but does not yet register it 34706c3df49SJamie Iles * with the clocksource system. This should be done with 34806c3df49SJamie Iles * dw_apb_clocksource_register() as the next step. 34906c3df49SJamie Iles */ 35006c3df49SJamie Iles struct dw_apb_clocksource * 351*a1330228SJamie Iles dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base, 35206c3df49SJamie Iles unsigned long freq) 35306c3df49SJamie Iles { 35406c3df49SJamie Iles struct dw_apb_clocksource *dw_cs = kzalloc(sizeof(*dw_cs), GFP_KERNEL); 35506c3df49SJamie Iles 35606c3df49SJamie Iles if (!dw_cs) 35706c3df49SJamie Iles return NULL; 35806c3df49SJamie Iles 35906c3df49SJamie Iles dw_cs->timer.base = base; 36006c3df49SJamie Iles dw_cs->timer.freq = freq; 36106c3df49SJamie Iles dw_cs->cs.name = name; 36206c3df49SJamie Iles dw_cs->cs.rating = rating; 36306c3df49SJamie Iles dw_cs->cs.read = __apbt_read_clocksource; 36406c3df49SJamie Iles dw_cs->cs.mask = CLOCKSOURCE_MASK(32); 36506c3df49SJamie Iles dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; 36606c3df49SJamie Iles dw_cs->cs.resume = apbt_restart_clocksource; 36706c3df49SJamie Iles 36806c3df49SJamie Iles return dw_cs; 36906c3df49SJamie Iles } 37006c3df49SJamie Iles 37106c3df49SJamie Iles /** 37206c3df49SJamie Iles * dw_apb_clocksource_register() - register the APB clocksource. 37306c3df49SJamie Iles * 37406c3df49SJamie Iles * @dw_cs: The clocksource to register. 37506c3df49SJamie Iles */ 37606c3df49SJamie Iles void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs) 37706c3df49SJamie Iles { 37806c3df49SJamie Iles clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq); 37906c3df49SJamie Iles } 38006c3df49SJamie Iles 38106c3df49SJamie Iles /** 38206c3df49SJamie Iles * dw_apb_clocksource_read() - read the current value of a clocksource. 38306c3df49SJamie Iles * 38406c3df49SJamie Iles * @dw_cs: The clocksource to read. 38506c3df49SJamie Iles */ 38606c3df49SJamie Iles cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs) 38706c3df49SJamie Iles { 38806c3df49SJamie Iles return (cycle_t)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE); 38906c3df49SJamie Iles } 39006c3df49SJamie Iles 39106c3df49SJamie Iles /** 39206c3df49SJamie Iles * dw_apb_clocksource_unregister() - unregister and free a clocksource. 39306c3df49SJamie Iles * 39406c3df49SJamie Iles * @dw_cs: The clocksource to unregister/free. 39506c3df49SJamie Iles */ 39606c3df49SJamie Iles void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs) 39706c3df49SJamie Iles { 39806c3df49SJamie Iles clocksource_unregister(&dw_cs->cs); 39906c3df49SJamie Iles 40006c3df49SJamie Iles kfree(dw_cs); 40106c3df49SJamie Iles } 402