1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
206c3df49SJamie Iles /*
306c3df49SJamie Iles * (C) Copyright 2009 Intel Corporation
406c3df49SJamie Iles * Author: Jacob Pan (jacob.jun.pan@intel.com)
506c3df49SJamie Iles *
606c3df49SJamie Iles * Shared with ARM platforms, Jamie Iles, Picochip 2011
706c3df49SJamie Iles *
806c3df49SJamie Iles * Support for the Synopsys DesignWare APB Timers.
906c3df49SJamie Iles */
1006c3df49SJamie Iles #include <linux/dw_apb_timer.h>
1106c3df49SJamie Iles #include <linux/delay.h>
1206c3df49SJamie Iles #include <linux/kernel.h>
1306c3df49SJamie Iles #include <linux/interrupt.h>
1406c3df49SJamie Iles #include <linux/irq.h>
1506c3df49SJamie Iles #include <linux/io.h>
1606c3df49SJamie Iles #include <linux/slab.h>
1706c3df49SJamie Iles
1806c3df49SJamie Iles #define APBT_MIN_PERIOD 4
1906c3df49SJamie Iles #define APBT_MIN_DELTA_USEC 200
2006c3df49SJamie Iles
21d3d8fee4SJohn Stultz #define APBTMR_N_LOAD_COUNT 0x00
22d3d8fee4SJohn Stultz #define APBTMR_N_CURRENT_VALUE 0x04
23d3d8fee4SJohn Stultz #define APBTMR_N_CONTROL 0x08
24d3d8fee4SJohn Stultz #define APBTMR_N_EOI 0x0c
25d3d8fee4SJohn Stultz #define APBTMR_N_INT_STATUS 0x10
26d3d8fee4SJohn Stultz
2706c3df49SJamie Iles #define APBTMRS_INT_STATUS 0xa0
2806c3df49SJamie Iles #define APBTMRS_EOI 0xa4
2906c3df49SJamie Iles #define APBTMRS_RAW_INT_STATUS 0xa8
3006c3df49SJamie Iles #define APBTMRS_COMP_VERSION 0xac
3106c3df49SJamie Iles
3206c3df49SJamie Iles #define APBTMR_CONTROL_ENABLE (1 << 0)
3306c3df49SJamie Iles /* 1: periodic, 0:free running. */
3406c3df49SJamie Iles #define APBTMR_CONTROL_MODE_PERIODIC (1 << 1)
3506c3df49SJamie Iles #define APBTMR_CONTROL_INT (1 << 2)
3606c3df49SJamie Iles
3706c3df49SJamie Iles static inline struct dw_apb_clock_event_device *
ced_to_dw_apb_ced(struct clock_event_device * evt)3806c3df49SJamie Iles ced_to_dw_apb_ced(struct clock_event_device *evt)
3906c3df49SJamie Iles {
4006c3df49SJamie Iles return container_of(evt, struct dw_apb_clock_event_device, ced);
4106c3df49SJamie Iles }
4206c3df49SJamie Iles
4306c3df49SJamie Iles static inline struct dw_apb_clocksource *
clocksource_to_dw_apb_clocksource(struct clocksource * cs)4406c3df49SJamie Iles clocksource_to_dw_apb_clocksource(struct clocksource *cs)
4506c3df49SJamie Iles {
4606c3df49SJamie Iles return container_of(cs, struct dw_apb_clocksource, cs);
4706c3df49SJamie Iles }
4806c3df49SJamie Iles
apbt_readl(struct dw_apb_timer * timer,unsigned long offs)49520ddad4SJisheng Zhang static inline u32 apbt_readl(struct dw_apb_timer *timer, unsigned long offs)
5006c3df49SJamie Iles {
5106c3df49SJamie Iles return readl(timer->base + offs);
5206c3df49SJamie Iles }
5306c3df49SJamie Iles
apbt_writel(struct dw_apb_timer * timer,u32 val,unsigned long offs)54520ddad4SJisheng Zhang static inline void apbt_writel(struct dw_apb_timer *timer, u32 val,
5506c3df49SJamie Iles unsigned long offs)
5606c3df49SJamie Iles {
5706c3df49SJamie Iles writel(val, timer->base + offs);
5806c3df49SJamie Iles }
5906c3df49SJamie Iles
apbt_readl_relaxed(struct dw_apb_timer * timer,unsigned long offs)6039d3611fSJisheng Zhang static inline u32 apbt_readl_relaxed(struct dw_apb_timer *timer, unsigned long offs)
6139d3611fSJisheng Zhang {
6239d3611fSJisheng Zhang return readl_relaxed(timer->base + offs);
6339d3611fSJisheng Zhang }
6439d3611fSJisheng Zhang
apbt_writel_relaxed(struct dw_apb_timer * timer,u32 val,unsigned long offs)6539d3611fSJisheng Zhang static inline void apbt_writel_relaxed(struct dw_apb_timer *timer, u32 val,
6639d3611fSJisheng Zhang unsigned long offs)
6739d3611fSJisheng Zhang {
6839d3611fSJisheng Zhang writel_relaxed(val, timer->base + offs);
6939d3611fSJisheng Zhang }
7039d3611fSJisheng Zhang
apbt_disable_int(struct dw_apb_timer * timer)7106c3df49SJamie Iles static void apbt_disable_int(struct dw_apb_timer *timer)
7206c3df49SJamie Iles {
739f4165dcSJisheng Zhang u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
7406c3df49SJamie Iles
7506c3df49SJamie Iles ctrl |= APBTMR_CONTROL_INT;
7606c3df49SJamie Iles apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
7706c3df49SJamie Iles }
7806c3df49SJamie Iles
7906c3df49SJamie Iles /**
8006c3df49SJamie Iles * dw_apb_clockevent_pause() - stop the clock_event_device from running
8106c3df49SJamie Iles *
8206c3df49SJamie Iles * @dw_ced: The APB clock to stop generating events.
8306c3df49SJamie Iles */
dw_apb_clockevent_pause(struct dw_apb_clock_event_device * dw_ced)8406c3df49SJamie Iles void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced)
8506c3df49SJamie Iles {
8606c3df49SJamie Iles disable_irq(dw_ced->timer.irq);
8706c3df49SJamie Iles apbt_disable_int(&dw_ced->timer);
8806c3df49SJamie Iles }
8906c3df49SJamie Iles
apbt_eoi(struct dw_apb_timer * timer)9006c3df49SJamie Iles static void apbt_eoi(struct dw_apb_timer *timer)
9106c3df49SJamie Iles {
9239d3611fSJisheng Zhang apbt_readl_relaxed(timer, APBTMR_N_EOI);
9306c3df49SJamie Iles }
9406c3df49SJamie Iles
dw_apb_clockevent_irq(int irq,void * data)9506c3df49SJamie Iles static irqreturn_t dw_apb_clockevent_irq(int irq, void *data)
9606c3df49SJamie Iles {
9706c3df49SJamie Iles struct clock_event_device *evt = data;
9806c3df49SJamie Iles struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
9906c3df49SJamie Iles
10006c3df49SJamie Iles if (!evt->event_handler) {
101ac9ce6d1SRafał Miłecki pr_info("Spurious APBT timer interrupt %d\n", irq);
10206c3df49SJamie Iles return IRQ_NONE;
10306c3df49SJamie Iles }
10406c3df49SJamie Iles
10506c3df49SJamie Iles if (dw_ced->eoi)
10606c3df49SJamie Iles dw_ced->eoi(&dw_ced->timer);
10706c3df49SJamie Iles
10806c3df49SJamie Iles evt->event_handler(evt);
10906c3df49SJamie Iles return IRQ_HANDLED;
11006c3df49SJamie Iles }
11106c3df49SJamie Iles
apbt_enable_int(struct dw_apb_timer * timer)11206c3df49SJamie Iles static void apbt_enable_int(struct dw_apb_timer *timer)
11306c3df49SJamie Iles {
1149f4165dcSJisheng Zhang u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
11506c3df49SJamie Iles /* clear pending intr */
11606c3df49SJamie Iles apbt_readl(timer, APBTMR_N_EOI);
11706c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_INT;
11806c3df49SJamie Iles apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
11906c3df49SJamie Iles }
12006c3df49SJamie Iles
apbt_shutdown(struct clock_event_device * evt)121226be92bSViresh Kumar static int apbt_shutdown(struct clock_event_device *evt)
12206c3df49SJamie Iles {
12306c3df49SJamie Iles struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
1249f4165dcSJisheng Zhang u32 ctrl;
12506c3df49SJamie Iles
126226be92bSViresh Kumar pr_debug("%s CPU %d state=shutdown\n", __func__,
127226be92bSViresh Kumar cpumask_first(evt->cpumask));
12806c3df49SJamie Iles
12906c3df49SJamie Iles ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
13006c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE;
13106c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
132226be92bSViresh Kumar return 0;
133226be92bSViresh Kumar }
13406c3df49SJamie Iles
apbt_set_oneshot(struct clock_event_device * evt)135226be92bSViresh Kumar static int apbt_set_oneshot(struct clock_event_device *evt)
136226be92bSViresh Kumar {
137226be92bSViresh Kumar struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
1389f4165dcSJisheng Zhang u32 ctrl;
139226be92bSViresh Kumar
140226be92bSViresh Kumar pr_debug("%s CPU %d state=oneshot\n", __func__,
141226be92bSViresh Kumar cpumask_first(evt->cpumask));
142226be92bSViresh Kumar
14306c3df49SJamie Iles ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
14406c3df49SJamie Iles /*
14506c3df49SJamie Iles * set free running mode, this mode will let timer reload max
14606c3df49SJamie Iles * timeout which will give time (3min on 25MHz clock) to rearm
14706c3df49SJamie Iles * the next event, therefore emulate the one-shot mode.
14806c3df49SJamie Iles */
14906c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE;
15006c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
15106c3df49SJamie Iles
15206c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
15306c3df49SJamie Iles /* write again to set free running mode */
15406c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
15506c3df49SJamie Iles
15606c3df49SJamie Iles /*
15706c3df49SJamie Iles * DW APB p. 46, load counter with all 1s before starting free
15806c3df49SJamie Iles * running mode.
15906c3df49SJamie Iles */
16006c3df49SJamie Iles apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
16106c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_INT;
16206c3df49SJamie Iles ctrl |= APBTMR_CONTROL_ENABLE;
16306c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
164226be92bSViresh Kumar return 0;
165226be92bSViresh Kumar }
16606c3df49SJamie Iles
apbt_set_periodic(struct clock_event_device * evt)167226be92bSViresh Kumar static int apbt_set_periodic(struct clock_event_device *evt)
168226be92bSViresh Kumar {
169226be92bSViresh Kumar struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
170226be92bSViresh Kumar unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
1719f4165dcSJisheng Zhang u32 ctrl;
172226be92bSViresh Kumar
173226be92bSViresh Kumar pr_debug("%s CPU %d state=periodic\n", __func__,
174226be92bSViresh Kumar cpumask_first(evt->cpumask));
175226be92bSViresh Kumar
17606c3df49SJamie Iles ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
177226be92bSViresh Kumar ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
178226be92bSViresh Kumar apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
179226be92bSViresh Kumar /*
180226be92bSViresh Kumar * DW APB p. 46, have to disable timer before load counter,
181226be92bSViresh Kumar * may cause sync problem.
182226be92bSViresh Kumar */
18306c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE;
18406c3df49SJamie Iles apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
185226be92bSViresh Kumar udelay(1);
186226be92bSViresh Kumar pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
187226be92bSViresh Kumar apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
188226be92bSViresh Kumar ctrl |= APBTMR_CONTROL_ENABLE;
189226be92bSViresh Kumar apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
190226be92bSViresh Kumar return 0;
19106c3df49SJamie Iles }
192226be92bSViresh Kumar
apbt_resume(struct clock_event_device * evt)193226be92bSViresh Kumar static int apbt_resume(struct clock_event_device *evt)
194226be92bSViresh Kumar {
195226be92bSViresh Kumar struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
196226be92bSViresh Kumar
197226be92bSViresh Kumar pr_debug("%s CPU %d state=resume\n", __func__,
198226be92bSViresh Kumar cpumask_first(evt->cpumask));
199226be92bSViresh Kumar
200226be92bSViresh Kumar apbt_enable_int(&dw_ced->timer);
201226be92bSViresh Kumar return 0;
20206c3df49SJamie Iles }
20306c3df49SJamie Iles
apbt_next_event(unsigned long delta,struct clock_event_device * evt)20406c3df49SJamie Iles static int apbt_next_event(unsigned long delta,
20506c3df49SJamie Iles struct clock_event_device *evt)
20606c3df49SJamie Iles {
2079f4165dcSJisheng Zhang u32 ctrl;
20806c3df49SJamie Iles struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
20906c3df49SJamie Iles
21006c3df49SJamie Iles /* Disable timer */
21139d3611fSJisheng Zhang ctrl = apbt_readl_relaxed(&dw_ced->timer, APBTMR_N_CONTROL);
21206c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE;
21339d3611fSJisheng Zhang apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
21406c3df49SJamie Iles /* write new count */
21539d3611fSJisheng Zhang apbt_writel_relaxed(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT);
21606c3df49SJamie Iles ctrl |= APBTMR_CONTROL_ENABLE;
21739d3611fSJisheng Zhang apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
21806c3df49SJamie Iles
21906c3df49SJamie Iles return 0;
22006c3df49SJamie Iles }
22106c3df49SJamie Iles
22206c3df49SJamie Iles /**
22306c3df49SJamie Iles * dw_apb_clockevent_init() - use an APB timer as a clock_event_device
22406c3df49SJamie Iles *
225*cee43dbfSSerge Semin * @cpu: The CPU the events will be targeted at or -1 if CPU affiliation
226*cee43dbfSSerge Semin * isn't required.
22706c3df49SJamie Iles * @name: The name used for the timer and the IRQ for it.
22806c3df49SJamie Iles * @rating: The rating to give the timer.
22906c3df49SJamie Iles * @base: I/O base for the timer registers.
23006c3df49SJamie Iles * @irq: The interrupt number to use for the timer.
23106c3df49SJamie Iles * @freq: The frequency that the timer counts at.
23206c3df49SJamie Iles *
23306c3df49SJamie Iles * This creates a clock_event_device for using with the generic clock layer
23406c3df49SJamie Iles * but does not start and register it. This should be done with
23506c3df49SJamie Iles * dw_apb_clockevent_register() as the next step. If this is the first time
23606c3df49SJamie Iles * it has been called for a timer then the IRQ will be requested, if not it
23706c3df49SJamie Iles * just be enabled to allow CPU hotplug to avoid repeatedly requesting and
23806c3df49SJamie Iles * releasing the IRQ.
23906c3df49SJamie Iles */
24006c3df49SJamie Iles struct dw_apb_clock_event_device *
dw_apb_clockevent_init(int cpu,const char * name,unsigned rating,void __iomem * base,int irq,unsigned long freq)24106c3df49SJamie Iles dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
24206c3df49SJamie Iles void __iomem *base, int irq, unsigned long freq)
24306c3df49SJamie Iles {
24406c3df49SJamie Iles struct dw_apb_clock_event_device *dw_ced =
24506c3df49SJamie Iles kzalloc(sizeof(*dw_ced), GFP_KERNEL);
24606c3df49SJamie Iles int err;
24706c3df49SJamie Iles
24806c3df49SJamie Iles if (!dw_ced)
24906c3df49SJamie Iles return NULL;
25006c3df49SJamie Iles
25106c3df49SJamie Iles dw_ced->timer.base = base;
25206c3df49SJamie Iles dw_ced->timer.irq = irq;
25306c3df49SJamie Iles dw_ced->timer.freq = freq;
25406c3df49SJamie Iles
25506c3df49SJamie Iles clockevents_calc_mult_shift(&dw_ced->ced, freq, APBT_MIN_PERIOD);
25606c3df49SJamie Iles dw_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff,
25706c3df49SJamie Iles &dw_ced->ced);
2588317b53fSNicolai Stange dw_ced->ced.max_delta_ticks = 0x7fffffff;
25906c3df49SJamie Iles dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
2608317b53fSNicolai Stange dw_ced->ced.min_delta_ticks = 5000;
261*cee43dbfSSerge Semin dw_ced->ced.cpumask = cpu < 0 ? cpu_possible_mask : cpumask_of(cpu);
2628b5f0010SJisheng Zhang dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC |
2638b5f0010SJisheng Zhang CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
264226be92bSViresh Kumar dw_ced->ced.set_state_shutdown = apbt_shutdown;
265226be92bSViresh Kumar dw_ced->ced.set_state_periodic = apbt_set_periodic;
266226be92bSViresh Kumar dw_ced->ced.set_state_oneshot = apbt_set_oneshot;
26745735326SJisheng Zhang dw_ced->ced.set_state_oneshot_stopped = apbt_shutdown;
268226be92bSViresh Kumar dw_ced->ced.tick_resume = apbt_resume;
26906c3df49SJamie Iles dw_ced->ced.set_next_event = apbt_next_event;
27006c3df49SJamie Iles dw_ced->ced.irq = dw_ced->timer.irq;
27106c3df49SJamie Iles dw_ced->ced.rating = rating;
27206c3df49SJamie Iles dw_ced->ced.name = name;
27306c3df49SJamie Iles
27406c3df49SJamie Iles dw_ced->eoi = apbt_eoi;
275cc2550b4Safzal mohammed err = request_irq(irq, dw_apb_clockevent_irq,
276cc2550b4Safzal mohammed IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
277cc2550b4Safzal mohammed dw_ced->ced.name, &dw_ced->ced);
27806c3df49SJamie Iles if (err) {
27906c3df49SJamie Iles pr_err("failed to request timer irq\n");
28006c3df49SJamie Iles kfree(dw_ced);
28106c3df49SJamie Iles dw_ced = NULL;
28206c3df49SJamie Iles }
28306c3df49SJamie Iles
28406c3df49SJamie Iles return dw_ced;
28506c3df49SJamie Iles }
28606c3df49SJamie Iles
28706c3df49SJamie Iles /**
28806c3df49SJamie Iles * dw_apb_clockevent_resume() - resume a clock that has been paused.
28906c3df49SJamie Iles *
29006c3df49SJamie Iles * @dw_ced: The APB clock to resume.
29106c3df49SJamie Iles */
dw_apb_clockevent_resume(struct dw_apb_clock_event_device * dw_ced)29206c3df49SJamie Iles void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced)
29306c3df49SJamie Iles {
29406c3df49SJamie Iles enable_irq(dw_ced->timer.irq);
29506c3df49SJamie Iles }
29606c3df49SJamie Iles
29706c3df49SJamie Iles /**
29806c3df49SJamie Iles * dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ.
29906c3df49SJamie Iles *
30006c3df49SJamie Iles * @dw_ced: The APB clock to stop generating the events.
30106c3df49SJamie Iles */
dw_apb_clockevent_stop(struct dw_apb_clock_event_device * dw_ced)30206c3df49SJamie Iles void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced)
30306c3df49SJamie Iles {
30406c3df49SJamie Iles free_irq(dw_ced->timer.irq, &dw_ced->ced);
30506c3df49SJamie Iles }
30606c3df49SJamie Iles
30706c3df49SJamie Iles /**
30806c3df49SJamie Iles * dw_apb_clockevent_register() - register the clock with the generic layer
30906c3df49SJamie Iles *
31006c3df49SJamie Iles * @dw_ced: The APB clock to register as a clock_event_device.
31106c3df49SJamie Iles */
dw_apb_clockevent_register(struct dw_apb_clock_event_device * dw_ced)31206c3df49SJamie Iles void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced)
31306c3df49SJamie Iles {
31406c3df49SJamie Iles apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL);
31506c3df49SJamie Iles clockevents_register_device(&dw_ced->ced);
31606c3df49SJamie Iles apbt_enable_int(&dw_ced->timer);
31706c3df49SJamie Iles }
31806c3df49SJamie Iles
31906c3df49SJamie Iles /**
32006c3df49SJamie Iles * dw_apb_clocksource_start() - start the clocksource counting.
32106c3df49SJamie Iles *
32206c3df49SJamie Iles * @dw_cs: The clocksource to start.
32306c3df49SJamie Iles *
32406c3df49SJamie Iles * This is used to start the clocksource before registration and can be used
32506c3df49SJamie Iles * to enable calibration of timers.
32606c3df49SJamie Iles */
dw_apb_clocksource_start(struct dw_apb_clocksource * dw_cs)32706c3df49SJamie Iles void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs)
32806c3df49SJamie Iles {
32906c3df49SJamie Iles /*
33006c3df49SJamie Iles * start count down from 0xffff_ffff. this is done by toggling the
33106c3df49SJamie Iles * enable bit then load initial load count to ~0.
33206c3df49SJamie Iles */
3339f4165dcSJisheng Zhang u32 ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL);
33406c3df49SJamie Iles
33506c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_ENABLE;
33606c3df49SJamie Iles apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
33706c3df49SJamie Iles apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT);
33806c3df49SJamie Iles /* enable, mask interrupt */
33906c3df49SJamie Iles ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
34006c3df49SJamie Iles ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
34106c3df49SJamie Iles apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
34206c3df49SJamie Iles /* read it once to get cached counter value initialized */
34306c3df49SJamie Iles dw_apb_clocksource_read(dw_cs);
34406c3df49SJamie Iles }
34506c3df49SJamie Iles
__apbt_read_clocksource(struct clocksource * cs)346a5a1d1c2SThomas Gleixner static u64 __apbt_read_clocksource(struct clocksource *cs)
34706c3df49SJamie Iles {
3489f4165dcSJisheng Zhang u32 current_count;
34906c3df49SJamie Iles struct dw_apb_clocksource *dw_cs =
35006c3df49SJamie Iles clocksource_to_dw_apb_clocksource(cs);
35106c3df49SJamie Iles
35239d3611fSJisheng Zhang current_count = apbt_readl_relaxed(&dw_cs->timer,
35339d3611fSJisheng Zhang APBTMR_N_CURRENT_VALUE);
35406c3df49SJamie Iles
355a5a1d1c2SThomas Gleixner return (u64)~current_count;
35606c3df49SJamie Iles }
35706c3df49SJamie Iles
apbt_restart_clocksource(struct clocksource * cs)35806c3df49SJamie Iles static void apbt_restart_clocksource(struct clocksource *cs)
35906c3df49SJamie Iles {
36006c3df49SJamie Iles struct dw_apb_clocksource *dw_cs =
36106c3df49SJamie Iles clocksource_to_dw_apb_clocksource(cs);
36206c3df49SJamie Iles
36306c3df49SJamie Iles dw_apb_clocksource_start(dw_cs);
36406c3df49SJamie Iles }
36506c3df49SJamie Iles
36606c3df49SJamie Iles /**
36706c3df49SJamie Iles * dw_apb_clocksource_init() - use an APB timer as a clocksource.
36806c3df49SJamie Iles *
36906c3df49SJamie Iles * @rating: The rating to give the clocksource.
37006c3df49SJamie Iles * @name: The name for the clocksource.
37106c3df49SJamie Iles * @base: The I/O base for the timer registers.
37206c3df49SJamie Iles * @freq: The frequency that the timer counts at.
37306c3df49SJamie Iles *
37406c3df49SJamie Iles * This creates a clocksource using an APB timer but does not yet register it
37506c3df49SJamie Iles * with the clocksource system. This should be done with
37606c3df49SJamie Iles * dw_apb_clocksource_register() as the next step.
37706c3df49SJamie Iles */
37806c3df49SJamie Iles struct dw_apb_clocksource *
dw_apb_clocksource_init(unsigned rating,const char * name,void __iomem * base,unsigned long freq)379a1330228SJamie Iles dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base,
38006c3df49SJamie Iles unsigned long freq)
38106c3df49SJamie Iles {
38206c3df49SJamie Iles struct dw_apb_clocksource *dw_cs = kzalloc(sizeof(*dw_cs), GFP_KERNEL);
38306c3df49SJamie Iles
38406c3df49SJamie Iles if (!dw_cs)
38506c3df49SJamie Iles return NULL;
38606c3df49SJamie Iles
38706c3df49SJamie Iles dw_cs->timer.base = base;
38806c3df49SJamie Iles dw_cs->timer.freq = freq;
38906c3df49SJamie Iles dw_cs->cs.name = name;
39006c3df49SJamie Iles dw_cs->cs.rating = rating;
39106c3df49SJamie Iles dw_cs->cs.read = __apbt_read_clocksource;
39206c3df49SJamie Iles dw_cs->cs.mask = CLOCKSOURCE_MASK(32);
39306c3df49SJamie Iles dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
39406c3df49SJamie Iles dw_cs->cs.resume = apbt_restart_clocksource;
39506c3df49SJamie Iles
39606c3df49SJamie Iles return dw_cs;
39706c3df49SJamie Iles }
39806c3df49SJamie Iles
39906c3df49SJamie Iles /**
40006c3df49SJamie Iles * dw_apb_clocksource_register() - register the APB clocksource.
40106c3df49SJamie Iles *
40206c3df49SJamie Iles * @dw_cs: The clocksource to register.
40306c3df49SJamie Iles */
dw_apb_clocksource_register(struct dw_apb_clocksource * dw_cs)40406c3df49SJamie Iles void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs)
40506c3df49SJamie Iles {
40606c3df49SJamie Iles clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);
40706c3df49SJamie Iles }
40806c3df49SJamie Iles
40906c3df49SJamie Iles /**
41006c3df49SJamie Iles * dw_apb_clocksource_read() - read the current value of a clocksource.
41106c3df49SJamie Iles *
41206c3df49SJamie Iles * @dw_cs: The clocksource to read.
41306c3df49SJamie Iles */
dw_apb_clocksource_read(struct dw_apb_clocksource * dw_cs)414a5a1d1c2SThomas Gleixner u64 dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs)
41506c3df49SJamie Iles {
416a5a1d1c2SThomas Gleixner return (u64)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
41706c3df49SJamie Iles }
418