1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2251a449dSTero Kristo /* 3251a449dSTero Kristo * DRA7 Clock init 4251a449dSTero Kristo * 5251a449dSTero Kristo * Copyright (C) 2013 Texas Instruments, Inc. 6251a449dSTero Kristo * 7251a449dSTero Kristo * Tero Kristo (t-kristo@ti.com) 8251a449dSTero Kristo */ 9251a449dSTero Kristo 10251a449dSTero Kristo #include <linux/kernel.h> 11251a449dSTero Kristo #include <linux/list.h> 12e387088aSStephen Boyd #include <linux/clk.h> 13251a449dSTero Kristo #include <linux/clkdev.h> 14251a449dSTero Kristo #include <linux/clk/ti.h> 1524d504a3STero Kristo #include <dt-bindings/clock/dra7.h> 16251a449dSTero Kristo 17a3314e9cSTero Kristo #include "clock.h" 18a3314e9cSTero Kristo 19251a449dSTero Kristo #define DRA7_DPLL_GMAC_DEFFREQ 1000000000 2094e72ae5SRoger Quadros #define DRA7_DPLL_USB_DEFFREQ 960000000 21251a449dSTero Kristo 22dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = { 23dffa9051STero Kristo { DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, 24dffa9051STero Kristo { 0 }, 25dffa9051STero Kristo }; 26dffa9051STero Kristo 27dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = { 28*9063ea46STero Kristo { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" }, 29dffa9051STero Kristo { 0 }, 30dffa9051STero Kristo }; 31dffa9051STero Kristo 32dffa9051STero Kristo static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = { 33dffa9051STero Kristo "dpll_abe_m2x2_ck", 34dffa9051STero Kristo "dpll_core_h22x2_ck", 35dffa9051STero Kristo NULL, 36dffa9051STero Kristo }; 37dffa9051STero Kristo 38dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = { 39dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL }, 40dffa9051STero Kristo { 0 }, 41dffa9051STero Kristo }; 42dffa9051STero Kristo 43dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = { 44*9063ea46STero Kristo { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:0000:24" }, 45dffa9051STero Kristo { 0 }, 46dffa9051STero Kristo }; 47dffa9051STero Kristo 48dffa9051STero Kristo static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = { 49dffa9051STero Kristo "per_abe_x1_gfclk2_div", 50dffa9051STero Kristo "video1_clk2_div", 51dffa9051STero Kristo "video2_clk2_div", 52dffa9051STero Kristo "hdmi_clk2_div", 53dffa9051STero Kristo NULL, 54dffa9051STero Kristo }; 55dffa9051STero Kristo 56dffa9051STero Kristo static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = { 57dffa9051STero Kristo "abe_24m_fclk", 58dffa9051STero Kristo "abe_sys_clk_div", 59dffa9051STero Kristo "func_24m_clk", 60dffa9051STero Kristo "atl_clkin3_ck", 61dffa9051STero Kristo "atl_clkin2_ck", 62dffa9051STero Kristo "atl_clkin1_ck", 63dffa9051STero Kristo "atl_clkin0_ck", 64dffa9051STero Kristo "sys_clkin2", 65dffa9051STero Kristo "ref_clkin0_ck", 66dffa9051STero Kristo "ref_clkin1_ck", 67dffa9051STero Kristo "ref_clkin2_ck", 68dffa9051STero Kristo "ref_clkin3_ck", 69dffa9051STero Kristo "mlb_clk", 70dffa9051STero Kristo "mlbp_clk", 71dffa9051STero Kristo NULL, 72dffa9051STero Kristo }; 73dffa9051STero Kristo 74dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = { 75dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 76dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 77dffa9051STero Kristo { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 78dffa9051STero Kristo { 0 }, 79dffa9051STero Kristo }; 80dffa9051STero Kristo 81dffa9051STero Kristo static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = { 82dffa9051STero Kristo "timer_sys_clk_div", 83dffa9051STero Kristo "sys_32k_ck", 84dffa9051STero Kristo "sys_clkin2", 85dffa9051STero Kristo "ref_clkin0_ck", 86dffa9051STero Kristo "ref_clkin1_ck", 87dffa9051STero Kristo "ref_clkin2_ck", 88dffa9051STero Kristo "ref_clkin3_ck", 89dffa9051STero Kristo "abe_giclk_div", 90dffa9051STero Kristo "video1_div_clk", 91dffa9051STero Kristo "video2_div_clk", 92dffa9051STero Kristo "hdmi_div_clk", 93dffa9051STero Kristo "clkoutmux0_clk_mux", 94dffa9051STero Kristo NULL, 95dffa9051STero Kristo }; 96dffa9051STero Kristo 97dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = { 98dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 99dffa9051STero Kristo { 0 }, 100dffa9051STero Kristo }; 101dffa9051STero Kristo 102dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = { 103dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 104dffa9051STero Kristo { 0 }, 105dffa9051STero Kristo }; 106dffa9051STero Kristo 107dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = { 108dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 109dffa9051STero Kristo { 0 }, 110dffa9051STero Kristo }; 111dffa9051STero Kristo 112dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = { 113dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 114dffa9051STero Kristo { 0 }, 115dffa9051STero Kristo }; 116dffa9051STero Kristo 117dffa9051STero Kristo static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = { 118dffa9051STero Kristo "func_48m_fclk", 119dffa9051STero Kristo "dpll_per_m2x2_ck", 120dffa9051STero Kristo NULL, 121dffa9051STero Kristo }; 122dffa9051STero Kristo 123dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = { 124dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 125dffa9051STero Kristo { 0 }, 126dffa9051STero Kristo }; 127dffa9051STero Kristo 128dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = { 129dffa9051STero Kristo { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" }, 130dffa9051STero Kristo { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" }, 131dffa9051STero Kristo { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" }, 132dffa9051STero Kristo { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" }, 133dffa9051STero Kristo { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" }, 134dffa9051STero Kristo { DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 135dffa9051STero Kristo { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" }, 136dffa9051STero Kristo { 0 }, 137dffa9051STero Kristo }; 138dffa9051STero Kristo 139dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = { 140*9063ea46STero Kristo { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" }, 141dffa9051STero Kristo { 0 }, 142dffa9051STero Kristo }; 143dffa9051STero Kristo 144dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = { 145dffa9051STero Kristo { DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 146dffa9051STero Kristo { 0 }, 147dffa9051STero Kristo }; 148dffa9051STero Kristo 149dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = { 150dffa9051STero Kristo { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, 151dffa9051STero Kristo { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, 152dffa9051STero Kristo { 0 }, 153dffa9051STero Kristo }; 154dffa9051STero Kristo 155dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = { 156dffa9051STero Kristo { DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 157dffa9051STero Kristo { DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 158dffa9051STero Kristo { DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" }, 159dffa9051STero Kristo { DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 160dffa9051STero Kristo { DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 161dffa9051STero Kristo { DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 162dffa9051STero Kristo { DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 163dffa9051STero Kristo { 0 }, 164dffa9051STero Kristo }; 165dffa9051STero Kristo 166dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = { 167*9063ea46STero Kristo { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" }, 168dffa9051STero Kristo { 0 }, 169dffa9051STero Kristo }; 170dffa9051STero Kristo 171dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = { 172dffa9051STero Kristo { DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 173dffa9051STero Kristo { 0 }, 174dffa9051STero Kristo }; 175dffa9051STero Kristo 176dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = { 177dffa9051STero Kristo { DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 178dffa9051STero Kristo { 0 }, 179dffa9051STero Kristo }; 180dffa9051STero Kristo 181dffa9051STero Kristo static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = { 182dffa9051STero Kristo "sys_32k_ck", 183dffa9051STero Kristo "video1_clkin_ck", 184dffa9051STero Kristo "video2_clkin_ck", 185dffa9051STero Kristo "hdmi_clkin_ck", 186dffa9051STero Kristo NULL, 187dffa9051STero Kristo }; 188dffa9051STero Kristo 189dffa9051STero Kristo static const char * const dra7_atl_gfclk_mux_parents[] __initconst = { 190dffa9051STero Kristo "l3_iclk_div", 191dffa9051STero Kristo "dpll_abe_m2_ck", 192dffa9051STero Kristo "atl-clkctrl:0000:24", 193dffa9051STero Kristo NULL, 194dffa9051STero Kristo }; 195dffa9051STero Kristo 196dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = { 197dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL }, 198dffa9051STero Kristo { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL }, 199dffa9051STero Kristo { 0 }, 200dffa9051STero Kristo }; 201dffa9051STero Kristo 202dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = { 203dffa9051STero Kristo { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" }, 204dffa9051STero Kristo { 0 }, 205dffa9051STero Kristo }; 206dffa9051STero Kristo 207dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = { 208dffa9051STero Kristo { DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" }, 209dffa9051STero Kristo { DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" }, 210dffa9051STero Kristo { DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 211dffa9051STero Kristo { DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 212dffa9051STero Kristo { DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" }, 213dffa9051STero Kristo { DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" }, 214dffa9051STero Kristo { DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" }, 215dffa9051STero Kristo { DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" }, 216dffa9051STero Kristo { DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" }, 217dffa9051STero Kristo { DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" }, 218dffa9051STero Kristo { DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" }, 219dffa9051STero Kristo { DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" }, 220dffa9051STero Kristo { DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" }, 221dffa9051STero Kristo { DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" }, 222dffa9051STero Kristo { DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" }, 223dffa9051STero Kristo { 0 }, 224dffa9051STero Kristo }; 225dffa9051STero Kristo 226dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = { 227dffa9051STero Kristo { DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 228dffa9051STero Kristo { DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 229dffa9051STero Kristo { 0 }, 230dffa9051STero Kristo }; 231dffa9051STero Kristo 232dffa9051STero Kristo static const char * const dra7_dss_dss_clk_parents[] __initconst = { 233dffa9051STero Kristo "dpll_per_h12x2_ck", 234dffa9051STero Kristo NULL, 235dffa9051STero Kristo }; 236dffa9051STero Kristo 237dffa9051STero Kristo static const char * const dra7_dss_48mhz_clk_parents[] __initconst = { 238dffa9051STero Kristo "func_48m_fclk", 239dffa9051STero Kristo NULL, 240dffa9051STero Kristo }; 241dffa9051STero Kristo 242dffa9051STero Kristo static const char * const dra7_dss_hdmi_clk_parents[] __initconst = { 243dffa9051STero Kristo "hdmi_dpll_clk_mux", 244dffa9051STero Kristo NULL, 245dffa9051STero Kristo }; 246dffa9051STero Kristo 247dffa9051STero Kristo static const char * const dra7_dss_32khz_clk_parents[] __initconst = { 248dffa9051STero Kristo "sys_32k_ck", 249dffa9051STero Kristo NULL, 250dffa9051STero Kristo }; 251dffa9051STero Kristo 252dffa9051STero Kristo static const char * const dra7_dss_video1_clk_parents[] __initconst = { 253dffa9051STero Kristo "video1_dpll_clk_mux", 254dffa9051STero Kristo NULL, 255dffa9051STero Kristo }; 256dffa9051STero Kristo 257dffa9051STero Kristo static const char * const dra7_dss_video2_clk_parents[] __initconst = { 258dffa9051STero Kristo "video2_dpll_clk_mux", 259dffa9051STero Kristo NULL, 260dffa9051STero Kristo }; 261dffa9051STero Kristo 262dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = { 263dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL }, 264dffa9051STero Kristo { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL }, 265dffa9051STero Kristo { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL }, 266dffa9051STero Kristo { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 267dffa9051STero Kristo { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL }, 268dffa9051STero Kristo { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL }, 269dffa9051STero Kristo { 0 }, 270dffa9051STero Kristo }; 271dffa9051STero Kristo 272dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = { 273dffa9051STero Kristo { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" }, 274dffa9051STero Kristo { DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" }, 275dffa9051STero Kristo { 0 }, 276dffa9051STero Kristo }; 277dffa9051STero Kristo 278dffa9051STero Kristo static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = { 279dffa9051STero Kristo "func_128m_clk", 280dffa9051STero Kristo "dpll_per_m2x2_ck", 281dffa9051STero Kristo NULL, 282dffa9051STero Kristo }; 283dffa9051STero Kristo 284dffa9051STero Kristo static const char * const dra7_mmc1_fclk_div_parents[] __initconst = { 285dffa9051STero Kristo "l3init-clkctrl:0008:24", 286dffa9051STero Kristo NULL, 287dffa9051STero Kristo }; 288dffa9051STero Kristo 289dffa9051STero Kristo static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = { 290dffa9051STero Kristo .max_div = 4, 291dffa9051STero Kristo .flags = CLK_DIVIDER_POWER_OF_TWO, 292dffa9051STero Kristo }; 293dffa9051STero Kristo 294dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = { 295dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 296dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL }, 297dffa9051STero Kristo { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data }, 298dffa9051STero Kristo { 0 }, 299dffa9051STero Kristo }; 300dffa9051STero Kristo 301dffa9051STero Kristo static const char * const dra7_mmc2_fclk_div_parents[] __initconst = { 302dffa9051STero Kristo "l3init-clkctrl:0010:24", 303dffa9051STero Kristo NULL, 304dffa9051STero Kristo }; 305dffa9051STero Kristo 306dffa9051STero Kristo static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = { 307dffa9051STero Kristo .max_div = 4, 308dffa9051STero Kristo .flags = CLK_DIVIDER_POWER_OF_TWO, 309dffa9051STero Kristo }; 310dffa9051STero Kristo 311dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = { 312dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 313dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL }, 314dffa9051STero Kristo { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data }, 315dffa9051STero Kristo { 0 }, 316dffa9051STero Kristo }; 317dffa9051STero Kristo 318dffa9051STero Kristo static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = { 319dffa9051STero Kristo "l3init_960m_gfclk", 320dffa9051STero Kristo NULL, 321dffa9051STero Kristo }; 322dffa9051STero Kristo 323dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = { 324dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, 325dffa9051STero Kristo { 0 }, 326dffa9051STero Kristo }; 327dffa9051STero Kristo 328dffa9051STero Kristo static const char * const dra7_sata_ref_clk_parents[] __initconst = { 329dffa9051STero Kristo "sys_clkin1", 330dffa9051STero Kristo NULL, 331dffa9051STero Kristo }; 332dffa9051STero Kristo 333dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = { 334dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL }, 335dffa9051STero Kristo { 0 }, 336dffa9051STero Kristo }; 337dffa9051STero Kristo 338dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = { 339dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, 340dffa9051STero Kristo { 0 }, 341dffa9051STero Kristo }; 342dffa9051STero Kristo 343dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = { 344dffa9051STero Kristo { DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" }, 345dffa9051STero Kristo { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" }, 346dffa9051STero Kristo { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 347dffa9051STero Kristo { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 3482b1202d7STero Kristo { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" }, 349dffa9051STero Kristo { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, 350dffa9051STero Kristo { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 351dffa9051STero Kristo { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 352dffa9051STero Kristo { DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 353dffa9051STero Kristo { 0 }, 354dffa9051STero Kristo }; 355dffa9051STero Kristo 356dffa9051STero Kristo static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = { 357dffa9051STero Kristo "apll_pcie_ck", 358dffa9051STero Kristo NULL, 359dffa9051STero Kristo }; 360dffa9051STero Kristo 361dffa9051STero Kristo static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = { 362dffa9051STero Kristo "optfclk_pciephy_div", 363dffa9051STero Kristo NULL, 364dffa9051STero Kristo }; 365dffa9051STero Kristo 366dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = { 367dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 368dffa9051STero Kristo { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL }, 369dffa9051STero Kristo { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL }, 370dffa9051STero Kristo { 0 }, 371dffa9051STero Kristo }; 372dffa9051STero Kristo 373dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = { 374dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 375dffa9051STero Kristo { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL }, 376dffa9051STero Kristo { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL }, 377dffa9051STero Kristo { 0 }, 378dffa9051STero Kristo }; 379dffa9051STero Kristo 380dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = { 381dffa9051STero Kristo { DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" }, 382dffa9051STero Kristo { DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" }, 383dffa9051STero Kristo { 0 }, 384dffa9051STero Kristo }; 385dffa9051STero Kristo 386dffa9051STero Kristo static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = { 387dffa9051STero Kristo "dpll_gmac_h11x2_ck", 388dffa9051STero Kristo "rmii_clk_ck", 389dffa9051STero Kristo NULL, 390dffa9051STero Kristo }; 391dffa9051STero Kristo 392dffa9051STero Kristo static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = { 393dffa9051STero Kristo "video1_clkin_ck", 394dffa9051STero Kristo "video2_clkin_ck", 395dffa9051STero Kristo "dpll_abe_m2_ck", 396dffa9051STero Kristo "hdmi_clkin_ck", 397dffa9051STero Kristo "l3_iclk_div", 398dffa9051STero Kristo NULL, 399dffa9051STero Kristo }; 400dffa9051STero Kristo 401dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = { 402dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL }, 403dffa9051STero Kristo { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL }, 404dffa9051STero Kristo { 0 }, 405dffa9051STero Kristo }; 406dffa9051STero Kristo 407dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = { 408dffa9051STero Kristo { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck" }, 409dffa9051STero Kristo { 0 }, 410dffa9051STero Kristo }; 411dffa9051STero Kristo 412dffa9051STero Kristo static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = { 413dffa9051STero Kristo "timer_sys_clk_div", 414dffa9051STero Kristo "sys_32k_ck", 415dffa9051STero Kristo "sys_clkin2", 416dffa9051STero Kristo "ref_clkin0_ck", 417dffa9051STero Kristo "ref_clkin1_ck", 418dffa9051STero Kristo "ref_clkin2_ck", 419dffa9051STero Kristo "ref_clkin3_ck", 420dffa9051STero Kristo "abe_giclk_div", 421dffa9051STero Kristo "video1_div_clk", 422dffa9051STero Kristo "video2_div_clk", 423dffa9051STero Kristo "hdmi_div_clk", 424dffa9051STero Kristo NULL, 425dffa9051STero Kristo }; 426dffa9051STero Kristo 427dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = { 428dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 429dffa9051STero Kristo { 0 }, 430dffa9051STero Kristo }; 431dffa9051STero Kristo 432dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = { 433dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 434dffa9051STero Kristo { 0 }, 435dffa9051STero Kristo }; 436dffa9051STero Kristo 437dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = { 438dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 439dffa9051STero Kristo { 0 }, 440dffa9051STero Kristo }; 441dffa9051STero Kristo 442dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = { 443dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 444dffa9051STero Kristo { 0 }, 445dffa9051STero Kristo }; 446dffa9051STero Kristo 447dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = { 448dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 449dffa9051STero Kristo { 0 }, 450dffa9051STero Kristo }; 451dffa9051STero Kristo 452dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = { 453dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 454dffa9051STero Kristo { 0 }, 455dffa9051STero Kristo }; 456dffa9051STero Kristo 457dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = { 458dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 459dffa9051STero Kristo { 0 }, 460dffa9051STero Kristo }; 461dffa9051STero Kristo 462dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = { 463dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 464dffa9051STero Kristo { 0 }, 465dffa9051STero Kristo }; 466dffa9051STero Kristo 467dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = { 468dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 469dffa9051STero Kristo { 0 }, 470dffa9051STero Kristo }; 471dffa9051STero Kristo 472dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = { 473dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 474dffa9051STero Kristo { 0 }, 475dffa9051STero Kristo }; 476dffa9051STero Kristo 477dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = { 478dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 479dffa9051STero Kristo { 0 }, 480dffa9051STero Kristo }; 481dffa9051STero Kristo 482dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = { 483dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 484dffa9051STero Kristo { 0 }, 485dffa9051STero Kristo }; 486dffa9051STero Kristo 487dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = { 488dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 489dffa9051STero Kristo { 0 }, 490dffa9051STero Kristo }; 491dffa9051STero Kristo 492dffa9051STero Kristo static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = { 493dffa9051STero Kristo "l4per-clkctrl:00f8:24", 494dffa9051STero Kristo NULL, 495dffa9051STero Kristo }; 496dffa9051STero Kristo 497dffa9051STero Kristo static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = { 498dffa9051STero Kristo .max_div = 4, 499dffa9051STero Kristo .flags = CLK_DIVIDER_POWER_OF_TWO, 500dffa9051STero Kristo }; 501dffa9051STero Kristo 502dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = { 503dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 504dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 505dffa9051STero Kristo { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data }, 506dffa9051STero Kristo { 0 }, 507dffa9051STero Kristo }; 508dffa9051STero Kristo 509dffa9051STero Kristo static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = { 510dffa9051STero Kristo "l4per-clkctrl:0100:24", 511dffa9051STero Kristo NULL, 512dffa9051STero Kristo }; 513dffa9051STero Kristo 514dffa9051STero Kristo static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = { 515dffa9051STero Kristo .max_div = 4, 516dffa9051STero Kristo .flags = CLK_DIVIDER_POWER_OF_TWO, 517dffa9051STero Kristo }; 518dffa9051STero Kristo 519dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = { 520dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 521dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 522dffa9051STero Kristo { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data }, 523dffa9051STero Kristo { 0 }, 524dffa9051STero Kristo }; 525dffa9051STero Kristo 526dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = { 527dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 528dffa9051STero Kristo { 0 }, 529dffa9051STero Kristo }; 530dffa9051STero Kristo 531dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = { 532dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 533dffa9051STero Kristo { 0 }, 534dffa9051STero Kristo }; 535dffa9051STero Kristo 536dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = { 537dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 538dffa9051STero Kristo { 0 }, 539dffa9051STero Kristo }; 540dffa9051STero Kristo 541dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = { 542dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 543dffa9051STero Kristo { 0 }, 544dffa9051STero Kristo }; 545dffa9051STero Kristo 546dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = { 547dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 548dffa9051STero Kristo { 0 }, 549dffa9051STero Kristo }; 550dffa9051STero Kristo 551dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = { 552dffa9051STero Kristo { DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" }, 553dffa9051STero Kristo { DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" }, 554dffa9051STero Kristo { DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" }, 555dffa9051STero Kristo { DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" }, 556dffa9051STero Kristo { DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" }, 557dffa9051STero Kristo { DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" }, 558dffa9051STero Kristo { DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 559dffa9051STero Kristo { DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 560dffa9051STero Kristo { DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 561dffa9051STero Kristo { DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 562dffa9051STero Kristo { DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 563dffa9051STero Kristo { DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 564dffa9051STero Kristo { DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" }, 565dffa9051STero Kristo { DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 566dffa9051STero Kristo { DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 567dffa9051STero Kristo { DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 568dffa9051STero Kristo { DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 569dffa9051STero Kristo { DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 570dffa9051STero Kristo { DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 571dffa9051STero Kristo { DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 572dffa9051STero Kristo { DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 573dffa9051STero Kristo { DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 574dffa9051STero Kristo { DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 575dffa9051STero Kristo { DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 576dffa9051STero Kristo { DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" }, 577dffa9051STero Kristo { DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" }, 578dffa9051STero Kristo { DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" }, 579dffa9051STero Kristo { DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" }, 580dffa9051STero Kristo { DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" }, 581dffa9051STero Kristo { DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" }, 582dffa9051STero Kristo { DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" }, 583dffa9051STero Kristo { 0 }, 584dffa9051STero Kristo }; 585dffa9051STero Kristo 586dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = { 587dffa9051STero Kristo { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 588dffa9051STero Kristo { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 589dffa9051STero Kristo { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 590869decd1STero Kristo { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, 591dffa9051STero Kristo { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 592dffa9051STero Kristo { 0 }, 593dffa9051STero Kristo }; 594dffa9051STero Kristo 595dffa9051STero Kristo static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = { 596dffa9051STero Kristo "func_128m_clk", 597dffa9051STero Kristo "dpll_per_h13x2_ck", 598dffa9051STero Kristo NULL, 599dffa9051STero Kristo }; 600dffa9051STero Kristo 601dffa9051STero Kristo static const char * const dra7_qspi_gfclk_div_parents[] __initconst = { 602dffa9051STero Kristo "l4per2-clkctrl:012c:24", 603dffa9051STero Kristo NULL, 604dffa9051STero Kristo }; 605dffa9051STero Kristo 606dffa9051STero Kristo static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = { 607dffa9051STero Kristo .max_div = 4, 608dffa9051STero Kristo .flags = CLK_DIVIDER_POWER_OF_TWO, 609dffa9051STero Kristo }; 610dffa9051STero Kristo 611dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = { 612dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL }, 613dffa9051STero Kristo { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data }, 614dffa9051STero Kristo { 0 }, 615dffa9051STero Kristo }; 616dffa9051STero Kristo 617dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = { 618dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 619dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 620dffa9051STero Kristo { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 621dffa9051STero Kristo { 0 }, 622dffa9051STero Kristo }; 623dffa9051STero Kristo 624dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = { 625dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 626dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 627dffa9051STero Kristo { 0 }, 628dffa9051STero Kristo }; 629dffa9051STero Kristo 630dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = { 631dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 632dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 633dffa9051STero Kristo { 0 }, 634dffa9051STero Kristo }; 635dffa9051STero Kristo 636dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = { 637dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 638dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 639dffa9051STero Kristo { 0 }, 640dffa9051STero Kristo }; 641dffa9051STero Kristo 642dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = { 643dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 644dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 645dffa9051STero Kristo { 0 }, 646dffa9051STero Kristo }; 647dffa9051STero Kristo 648dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = { 649dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 650dffa9051STero Kristo { 0 }, 651dffa9051STero Kristo }; 652dffa9051STero Kristo 653dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = { 654dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 655dffa9051STero Kristo { 0 }, 656dffa9051STero Kristo }; 657dffa9051STero Kristo 658dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = { 659dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 660dffa9051STero Kristo { 0 }, 661dffa9051STero Kristo }; 662dffa9051STero Kristo 663dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = { 664dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 665dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 666dffa9051STero Kristo { 0 }, 667dffa9051STero Kristo }; 668dffa9051STero Kristo 669dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = { 670dffa9051STero Kristo { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 671dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 672dffa9051STero Kristo { 0 }, 673dffa9051STero Kristo }; 674dffa9051STero Kristo 675dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = { 676dffa9051STero Kristo { DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 677dffa9051STero Kristo { DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" }, 678dffa9051STero Kristo { DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" }, 679dffa9051STero Kristo { DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" }, 680dffa9051STero Kristo { DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" }, 681dffa9051STero Kristo { DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" }, 682dffa9051STero Kristo { DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" }, 683dffa9051STero Kristo { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" }, 684dffa9051STero Kristo { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" }, 685dffa9051STero Kristo { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" }, 686dffa9051STero Kristo { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" }, 687dffa9051STero Kristo { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" }, 688dffa9051STero Kristo { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" }, 689dffa9051STero Kristo { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" }, 690dffa9051STero Kristo { DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" }, 691dffa9051STero Kristo { DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" }, 692dffa9051STero Kristo { DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" }, 693dffa9051STero Kristo { DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" }, 694dffa9051STero Kristo { 0 }, 695dffa9051STero Kristo }; 696dffa9051STero Kristo 697dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = { 698dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 699dffa9051STero Kristo { 0 }, 700dffa9051STero Kristo }; 701dffa9051STero Kristo 702dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = { 703dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 704dffa9051STero Kristo { 0 }, 705dffa9051STero Kristo }; 706dffa9051STero Kristo 707dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = { 708dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 709dffa9051STero Kristo { 0 }, 710dffa9051STero Kristo }; 711dffa9051STero Kristo 712dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = { 713dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 714dffa9051STero Kristo { 0 }, 715dffa9051STero Kristo }; 716dffa9051STero Kristo 717dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = { 718dffa9051STero Kristo { DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" }, 719dffa9051STero Kristo { DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" }, 720dffa9051STero Kristo { DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" }, 721dffa9051STero Kristo { DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" }, 722dffa9051STero Kristo { DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" }, 723dffa9051STero Kristo { 0 }, 724dffa9051STero Kristo }; 725dffa9051STero Kristo 726dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = { 727dffa9051STero Kristo { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 728dffa9051STero Kristo { 0 }, 729dffa9051STero Kristo }; 730dffa9051STero Kristo 731dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = { 732dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 733dffa9051STero Kristo { 0 }, 734dffa9051STero Kristo }; 735dffa9051STero Kristo 736dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = { 737dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 738dffa9051STero Kristo { 0 }, 739dffa9051STero Kristo }; 740dffa9051STero Kristo 741dffa9051STero Kristo static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = { 742dffa9051STero Kristo "sys_clkin1", 743dffa9051STero Kristo "sys_clkin2", 744dffa9051STero Kristo NULL, 745dffa9051STero Kristo }; 746dffa9051STero Kristo 747dffa9051STero Kristo static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = { 748dffa9051STero Kristo { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL }, 749dffa9051STero Kristo { 0 }, 750dffa9051STero Kristo }; 751dffa9051STero Kristo 752dffa9051STero Kristo static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = { 753dffa9051STero Kristo { DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 754dffa9051STero Kristo { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 755dffa9051STero Kristo { DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, 756dffa9051STero Kristo { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" }, 757869decd1STero Kristo { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" }, 758dffa9051STero Kristo { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 759dffa9051STero Kristo { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" }, 760dffa9051STero Kristo { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" }, 761dffa9051STero Kristo { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk" }, 762dffa9051STero Kristo { 0 }, 763dffa9051STero Kristo }; 764dffa9051STero Kristo 765dffa9051STero Kristo const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = { 766dffa9051STero Kristo { 0x4a005320, dra7_mpu_clkctrl_regs }, 767dffa9051STero Kristo { 0x4a005420, dra7_dsp1_clkctrl_regs }, 768dffa9051STero Kristo { 0x4a005520, dra7_ipu1_clkctrl_regs }, 769dffa9051STero Kristo { 0x4a005550, dra7_ipu_clkctrl_regs }, 770dffa9051STero Kristo { 0x4a005620, dra7_dsp2_clkctrl_regs }, 771dffa9051STero Kristo { 0x4a005720, dra7_rtc_clkctrl_regs }, 772dffa9051STero Kristo { 0x4a008620, dra7_coreaon_clkctrl_regs }, 773dffa9051STero Kristo { 0x4a008720, dra7_l3main1_clkctrl_regs }, 774dffa9051STero Kristo { 0x4a008920, dra7_ipu2_clkctrl_regs }, 775dffa9051STero Kristo { 0x4a008a20, dra7_dma_clkctrl_regs }, 776dffa9051STero Kristo { 0x4a008b20, dra7_emif_clkctrl_regs }, 777dffa9051STero Kristo { 0x4a008c00, dra7_atl_clkctrl_regs }, 778dffa9051STero Kristo { 0x4a008d20, dra7_l4cfg_clkctrl_regs }, 779dffa9051STero Kristo { 0x4a008e20, dra7_l3instr_clkctrl_regs }, 780dffa9051STero Kristo { 0x4a009120, dra7_dss_clkctrl_regs }, 781dffa9051STero Kristo { 0x4a009320, dra7_l3init_clkctrl_regs }, 782dffa9051STero Kristo { 0x4a0093b0, dra7_pcie_clkctrl_regs }, 783dffa9051STero Kristo { 0x4a0093d0, dra7_gmac_clkctrl_regs }, 784dffa9051STero Kristo { 0x4a009728, dra7_l4per_clkctrl_regs }, 785dffa9051STero Kristo { 0x4a0098a0, dra7_l4sec_clkctrl_regs }, 786dffa9051STero Kristo { 0x4a00970c, dra7_l4per2_clkctrl_regs }, 787dffa9051STero Kristo { 0x4a009714, dra7_l4per3_clkctrl_regs }, 788dffa9051STero Kristo { 0x4ae07820, dra7_wkupaon_clkctrl_regs }, 789dffa9051STero Kristo { 0 }, 790dffa9051STero Kristo }; 791dffa9051STero Kristo 792dffa9051STero Kristo static struct ti_dt_clk dra7xx_clks[] = { 793dffa9051STero Kristo DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 794dffa9051STero Kristo DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"), 795dffa9051STero Kristo DT_CLK(NULL, "sys_clkin", "sys_clkin1"), 796dffa9051STero Kristo DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"), 797dffa9051STero Kristo DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"), 798dffa9051STero Kristo DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"), 799dffa9051STero Kristo DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"), 800dffa9051STero Kristo DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"), 801dffa9051STero Kristo DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"), 802dffa9051STero Kristo DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"), 803dffa9051STero Kristo DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"), 804dffa9051STero Kristo DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"), 805dffa9051STero Kristo DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"), 806dffa9051STero Kristo DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"), 807dffa9051STero Kristo DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"), 808dffa9051STero Kristo DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"), 809dffa9051STero Kristo DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"), 810dffa9051STero Kristo DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"), 811dffa9051STero Kristo DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"), 812dffa9051STero Kristo DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"), 813dffa9051STero Kristo DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"), 814dffa9051STero Kristo DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"), 815dffa9051STero Kristo DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"), 816dffa9051STero Kristo DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"), 817dffa9051STero Kristo DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"), 818dffa9051STero Kristo DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"), 819dffa9051STero Kristo DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"), 820dffa9051STero Kristo DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"), 821dffa9051STero Kristo DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"), 822dffa9051STero Kristo DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"), 823dffa9051STero Kristo DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"), 824dffa9051STero Kristo DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"), 825dffa9051STero Kristo DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"), 826dffa9051STero Kristo DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"), 827dffa9051STero Kristo DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"), 828dffa9051STero Kristo DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"), 829dffa9051STero Kristo DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"), 830dffa9051STero Kristo DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"), 831dffa9051STero Kristo DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:22"), 832dffa9051STero Kristo DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:24"), 833dffa9051STero Kristo DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"), 834dffa9051STero Kristo DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"), 835dffa9051STero Kristo DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"), 836dffa9051STero Kristo DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"), 837dffa9051STero Kristo DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"), 838dffa9051STero Kristo DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"), 839dffa9051STero Kristo DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"), 840dffa9051STero Kristo DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"), 841dffa9051STero Kristo DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"), 842dffa9051STero Kristo DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"), 843dffa9051STero Kristo DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"), 844dffa9051STero Kristo DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"), 845dffa9051STero Kristo DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"), 846dffa9051STero Kristo DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"), 847dffa9051STero Kristo DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"), 848dffa9051STero Kristo DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"), 849dffa9051STero Kristo DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"), 850dffa9051STero Kristo DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"), 851dffa9051STero Kristo DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"), 852dffa9051STero Kristo DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"), 853dffa9051STero Kristo DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"), 854dffa9051STero Kristo DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"), 855dffa9051STero Kristo DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"), 856dffa9051STero Kristo DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"), 857dffa9051STero Kristo DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"), 858dffa9051STero Kristo DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"), 859dffa9051STero Kristo DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"), 860dffa9051STero Kristo DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"), 861dffa9051STero Kristo DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"), 862dffa9051STero Kristo DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"), 863dffa9051STero Kristo DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"), 864dffa9051STero Kristo DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"), 865dffa9051STero Kristo DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"), 866dffa9051STero Kristo DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"), 867dffa9051STero Kristo DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"), 868dffa9051STero Kristo DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"), 869dffa9051STero Kristo DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"), 870dffa9051STero Kristo DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"), 871dffa9051STero Kristo DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"), 872dffa9051STero Kristo DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"), 873dffa9051STero Kristo DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"), 874dffa9051STero Kristo DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"), 875dffa9051STero Kristo DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"), 876dffa9051STero Kristo DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"), 877dffa9051STero Kristo DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"), 878dffa9051STero Kristo DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"), 879dffa9051STero Kristo DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"), 880dffa9051STero Kristo DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"), 881dffa9051STero Kristo DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"), 882dffa9051STero Kristo { .node_name = NULL }, 883dffa9051STero Kristo }; 884dffa9051STero Kristo 885251a449dSTero Kristo int __init dra7xx_dt_clk_init(void) 886251a449dSTero Kristo { 887251a449dSTero Kristo int rc; 8884b3061b3SPeter Ujfalusi struct clk *dpll_ck, *hdcp_ck; 889251a449dSTero Kristo 890dffa9051STero Kristo if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) 89143c56e04STero Kristo ti_dt_clocks_register(dra7xx_compat_clks); 892dffa9051STero Kristo else 893dffa9051STero Kristo ti_dt_clocks_register(dra7xx_clks); 894251a449dSTero Kristo 895251a449dSTero Kristo omap2_clk_disable_autoidle_all(); 896251a449dSTero Kristo 897a8202cd5STero Kristo ti_clk_add_aliases(); 898a8202cd5STero Kristo 899251a449dSTero Kristo dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); 900251a449dSTero Kristo rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); 901251a449dSTero Kristo if (rc) 902251a449dSTero Kristo pr_err("%s: failed to configure GMAC DPLL!\n", __func__); 903251a449dSTero Kristo 90494e72ae5SRoger Quadros dpll_ck = clk_get_sys(NULL, "dpll_usb_ck"); 90594e72ae5SRoger Quadros rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ); 90694e72ae5SRoger Quadros if (rc) 90794e72ae5SRoger Quadros pr_err("%s: failed to configure USB DPLL!\n", __func__); 90894e72ae5SRoger Quadros 90994e72ae5SRoger Quadros dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck"); 91094e72ae5SRoger Quadros rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2); 91194e72ae5SRoger Quadros if (rc) 91294e72ae5SRoger Quadros pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); 91394e72ae5SRoger Quadros 914f892b203STomi Valkeinen hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk"); 915f892b203STomi Valkeinen rc = clk_prepare_enable(hdcp_ck); 916f892b203STomi Valkeinen if (rc) 917f892b203STomi Valkeinen pr_err("%s: failed to set dss_deshdcp_clk\n", __func__); 918f892b203STomi Valkeinen 919251a449dSTero Kristo return rc; 920251a449dSTero Kristo } 921