1*c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 20577e485SMaxime Ripard /* 30577e485SMaxime Ripard * Copyright 2016 Maxime Ripard 40577e485SMaxime Ripard * 50577e485SMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com> 60577e485SMaxime Ripard */ 70577e485SMaxime Ripard 80577e485SMaxime Ripard #ifndef _CCU_SUN8I_H3_H_ 90577e485SMaxime Ripard #define _CCU_SUN8I_H3_H_ 100577e485SMaxime Ripard 110577e485SMaxime Ripard #include <dt-bindings/clock/sun8i-h3-ccu.h> 120577e485SMaxime Ripard #include <dt-bindings/reset/sun8i-h3-ccu.h> 130577e485SMaxime Ripard 140577e485SMaxime Ripard #define CLK_PLL_CPUX 0 150577e485SMaxime Ripard #define CLK_PLL_AUDIO_BASE 1 160577e485SMaxime Ripard #define CLK_PLL_AUDIO 2 170577e485SMaxime Ripard #define CLK_PLL_AUDIO_2X 3 180577e485SMaxime Ripard #define CLK_PLL_AUDIO_4X 4 190577e485SMaxime Ripard #define CLK_PLL_AUDIO_8X 5 2055de0f31SJernej Skrabec 2155de0f31SJernej Skrabec /* PLL_VIDEO is exported */ 2255de0f31SJernej Skrabec 230577e485SMaxime Ripard #define CLK_PLL_VE 7 240577e485SMaxime Ripard #define CLK_PLL_DDR 8 25c4be8c68SChen-Yu Tsai 26c4be8c68SChen-Yu Tsai /* PLL_PERIPH0 exported for PRCM */ 27c4be8c68SChen-Yu Tsai 280577e485SMaxime Ripard #define CLK_PLL_PERIPH0_2X 10 290577e485SMaxime Ripard #define CLK_PLL_GPU 11 300577e485SMaxime Ripard #define CLK_PLL_PERIPH1 12 310577e485SMaxime Ripard #define CLK_PLL_DE 13 320577e485SMaxime Ripard 330577e485SMaxime Ripard /* The CPUX clock is exported */ 340577e485SMaxime Ripard 350577e485SMaxime Ripard #define CLK_AXI 15 360577e485SMaxime Ripard #define CLK_AHB1 16 370577e485SMaxime Ripard #define CLK_APB1 17 380577e485SMaxime Ripard #define CLK_APB2 18 390577e485SMaxime Ripard #define CLK_AHB2 19 400577e485SMaxime Ripard 410577e485SMaxime Ripard /* All the bus gates are exported */ 420577e485SMaxime Ripard 430577e485SMaxime Ripard /* The first bunch of module clocks are exported */ 440577e485SMaxime Ripard 450577e485SMaxime Ripard /* All the DRAM gates are exported */ 460577e485SMaxime Ripard 470577e485SMaxime Ripard /* Some more module clocks are exported */ 480577e485SMaxime Ripard 499be1c8afSIcenowy Zheng #define CLK_NUMBER_H3 (CLK_GPU + 1) 509be1c8afSIcenowy Zheng #define CLK_NUMBER_H5 (CLK_BUS_SCR1 + 1) 510577e485SMaxime Ripard 520577e485SMaxime Ripard #endif /* _CCU_SUN8I_H3_H_ */ 53