1dae5448aSXingyu Wu // SPDX-License-Identifier: GPL-2.0 2dae5448aSXingyu Wu /* 3dae5448aSXingyu Wu * StarFive JH7110 Video-Output Clock Driver 4dae5448aSXingyu Wu * 5dae5448aSXingyu Wu * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. 6dae5448aSXingyu Wu */ 7dae5448aSXingyu Wu 8dae5448aSXingyu Wu #include <linux/clk.h> 9dae5448aSXingyu Wu #include <linux/clk-provider.h> 10dae5448aSXingyu Wu #include <linux/io.h> 11dae5448aSXingyu Wu #include <linux/platform_device.h> 12dae5448aSXingyu Wu #include <linux/pm_runtime.h> 13dae5448aSXingyu Wu #include <linux/reset.h> 14dae5448aSXingyu Wu 15dae5448aSXingyu Wu #include <dt-bindings/clock/starfive,jh7110-crg.h> 16dae5448aSXingyu Wu 17dae5448aSXingyu Wu #include "clk-starfive-jh7110.h" 18dae5448aSXingyu Wu 19dae5448aSXingyu Wu /* external clocks */ 20dae5448aSXingyu Wu #define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0) 21dae5448aSXingyu Wu #define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1) 22dae5448aSXingyu Wu #define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2) 23dae5448aSXingyu Wu #define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3) 24dae5448aSXingyu Wu #define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4) 25dae5448aSXingyu Wu #define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5) 26dae5448aSXingyu Wu #define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6) 27dae5448aSXingyu Wu 28dae5448aSXingyu Wu static struct clk_bulk_data jh7110_vout_top_clks[] = { 29dae5448aSXingyu Wu { .id = "vout_src" }, 30dae5448aSXingyu Wu { .id = "vout_top_ahb" } 31dae5448aSXingyu Wu }; 32dae5448aSXingyu Wu 33dae5448aSXingyu Wu static const struct jh71x0_clk_data jh7110_voutclk_data[] = { 34dae5448aSXingyu Wu /* divider */ 35dae5448aSXingyu Wu JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB), 36dae5448aSXingyu Wu JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC), 37dae5448aSXingyu Wu JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC), 38dae5448aSXingyu Wu JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB), 39dae5448aSXingyu Wu /* dc8200 */ 40dae5448aSXingyu Wu JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), 41dae5448aSXingyu Wu JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), 42dae5448aSXingyu Wu JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB), 43dae5448aSXingyu Wu JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2, 44dae5448aSXingyu Wu JH7110_VOUTCLK_DC8200_PIX, 45dae5448aSXingyu Wu JH7110_VOUTCLK_HDMITX0_PIXELCLK), 46dae5448aSXingyu Wu JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2, 47dae5448aSXingyu Wu JH7110_VOUTCLK_DC8200_PIX, 48dae5448aSXingyu Wu JH7110_VOUTCLK_HDMITX0_PIXELCLK), 49dae5448aSXingyu Wu /* LCD */ 50dae5448aSXingyu Wu JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2, 51dae5448aSXingyu Wu JH7110_VOUTCLK_DC8200_PIX0, 52dae5448aSXingyu Wu JH7110_VOUTCLK_DC8200_PIX1), 53dae5448aSXingyu Wu /* dsiTx */ 54dae5448aSXingyu Wu JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS), 55dae5448aSXingyu Wu JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS), 56dae5448aSXingyu Wu JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2, 57dae5448aSXingyu Wu JH7110_VOUTCLK_DC8200_PIX, 58dae5448aSXingyu Wu JH7110_VOUTCLK_HDMITX0_PIXELCLK), 59dae5448aSXingyu Wu JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC), 60dae5448aSXingyu Wu /* mipitx DPHY */ 61dae5448aSXingyu Wu JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0, 62dae5448aSXingyu Wu JH7110_VOUTCLK_TX_ESC), 63dae5448aSXingyu Wu /* hdmi */ 64dae5448aSXingyu Wu JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0, 65dae5448aSXingyu Wu JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK), 66dae5448aSXingyu Wu JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0, 67dae5448aSXingyu Wu JH7110_VOUTCLK_I2STX0_BCLK), 68dae5448aSXingyu Wu JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB), 69dae5448aSXingyu Wu }; 70dae5448aSXingyu Wu 71dae5448aSXingyu Wu static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv) 72dae5448aSXingyu Wu { 73dae5448aSXingyu Wu struct reset_control *top_rst; 74dae5448aSXingyu Wu 75dae5448aSXingyu Wu /* The reset should be shared and other Vout modules will use its. */ 76dae5448aSXingyu Wu top_rst = devm_reset_control_get_shared(priv->dev, NULL); 77dae5448aSXingyu Wu if (IS_ERR(top_rst)) 78dae5448aSXingyu Wu return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n"); 79dae5448aSXingyu Wu 80dae5448aSXingyu Wu return reset_control_deassert(top_rst); 81dae5448aSXingyu Wu } 82dae5448aSXingyu Wu 83dae5448aSXingyu Wu static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data) 84dae5448aSXingyu Wu { 85dae5448aSXingyu Wu struct jh71x0_clk_priv *priv = data; 86dae5448aSXingyu Wu unsigned int idx = clkspec->args[0]; 87dae5448aSXingyu Wu 88dae5448aSXingyu Wu if (idx < JH7110_VOUTCLK_END) 89dae5448aSXingyu Wu return &priv->reg[idx].hw; 90dae5448aSXingyu Wu 91dae5448aSXingyu Wu return ERR_PTR(-EINVAL); 92dae5448aSXingyu Wu } 93dae5448aSXingyu Wu 94dae5448aSXingyu Wu #ifdef CONFIG_PM 95dae5448aSXingyu Wu static int jh7110_voutcrg_suspend(struct device *dev) 96dae5448aSXingyu Wu { 97dae5448aSXingyu Wu struct jh7110_top_sysclk *top = dev_get_drvdata(dev); 98dae5448aSXingyu Wu 99dae5448aSXingyu Wu clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks); 100dae5448aSXingyu Wu 101dae5448aSXingyu Wu return 0; 102dae5448aSXingyu Wu } 103dae5448aSXingyu Wu 104dae5448aSXingyu Wu static int jh7110_voutcrg_resume(struct device *dev) 105dae5448aSXingyu Wu { 106dae5448aSXingyu Wu struct jh7110_top_sysclk *top = dev_get_drvdata(dev); 107dae5448aSXingyu Wu 108dae5448aSXingyu Wu return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks); 109dae5448aSXingyu Wu } 110dae5448aSXingyu Wu 111dae5448aSXingyu Wu static const struct dev_pm_ops jh7110_voutcrg_pm_ops = { 112dae5448aSXingyu Wu RUNTIME_PM_OPS(jh7110_voutcrg_suspend, jh7110_voutcrg_resume, NULL) 113dae5448aSXingyu Wu }; 114dae5448aSXingyu Wu #endif 115dae5448aSXingyu Wu 116dae5448aSXingyu Wu static int jh7110_voutcrg_probe(struct platform_device *pdev) 117dae5448aSXingyu Wu { 118dae5448aSXingyu Wu struct jh71x0_clk_priv *priv; 119dae5448aSXingyu Wu struct jh7110_top_sysclk *top; 120dae5448aSXingyu Wu unsigned int idx; 121dae5448aSXingyu Wu int ret; 122dae5448aSXingyu Wu 123dae5448aSXingyu Wu priv = devm_kzalloc(&pdev->dev, 124dae5448aSXingyu Wu struct_size(priv, reg, JH7110_VOUTCLK_END), 125dae5448aSXingyu Wu GFP_KERNEL); 126dae5448aSXingyu Wu if (!priv) 127dae5448aSXingyu Wu return -ENOMEM; 128dae5448aSXingyu Wu 129dae5448aSXingyu Wu top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL); 130dae5448aSXingyu Wu if (!top) 131dae5448aSXingyu Wu return -ENOMEM; 132dae5448aSXingyu Wu 133dae5448aSXingyu Wu spin_lock_init(&priv->rmw_lock); 134dae5448aSXingyu Wu priv->dev = &pdev->dev; 135dae5448aSXingyu Wu priv->base = devm_platform_ioremap_resource(pdev, 0); 136dae5448aSXingyu Wu if (IS_ERR(priv->base)) 137dae5448aSXingyu Wu return PTR_ERR(priv->base); 138dae5448aSXingyu Wu 139dae5448aSXingyu Wu top->top_clks = jh7110_vout_top_clks; 140dae5448aSXingyu Wu top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks); 141dae5448aSXingyu Wu ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks); 142dae5448aSXingyu Wu if (ret) 143dae5448aSXingyu Wu return dev_err_probe(priv->dev, ret, "failed to get top clocks\n"); 144dae5448aSXingyu Wu dev_set_drvdata(priv->dev, top); 145dae5448aSXingyu Wu 146dae5448aSXingyu Wu /* enable power domain and clocks */ 147dae5448aSXingyu Wu pm_runtime_enable(priv->dev); 14855c312c1SYuntao Liu ret = pm_runtime_resume_and_get(priv->dev); 149dae5448aSXingyu Wu if (ret < 0) 150dae5448aSXingyu Wu return dev_err_probe(priv->dev, ret, "failed to turn on power\n"); 151dae5448aSXingyu Wu 152dae5448aSXingyu Wu ret = jh7110_vout_top_rst_init(priv); 153dae5448aSXingyu Wu if (ret) 154dae5448aSXingyu Wu goto err_exit; 155dae5448aSXingyu Wu 156dae5448aSXingyu Wu for (idx = 0; idx < JH7110_VOUTCLK_END; idx++) { 157dae5448aSXingyu Wu u32 max = jh7110_voutclk_data[idx].max; 158dae5448aSXingyu Wu struct clk_parent_data parents[4] = {}; 159dae5448aSXingyu Wu struct clk_init_data init = { 160dae5448aSXingyu Wu .name = jh7110_voutclk_data[idx].name, 161dae5448aSXingyu Wu .ops = starfive_jh71x0_clk_ops(max), 162dae5448aSXingyu Wu .parent_data = parents, 163dae5448aSXingyu Wu .num_parents = 164dae5448aSXingyu Wu ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, 165dae5448aSXingyu Wu .flags = jh7110_voutclk_data[idx].flags, 166dae5448aSXingyu Wu }; 167dae5448aSXingyu Wu struct jh71x0_clk *clk = &priv->reg[idx]; 168dae5448aSXingyu Wu unsigned int i; 169dae5448aSXingyu Wu const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = { 170dae5448aSXingyu Wu "vout_src", 171dae5448aSXingyu Wu "vout_top_ahb", 172dae5448aSXingyu Wu "vout_top_axi", 173dae5448aSXingyu Wu "vout_top_hdmitx0_mclk", 174dae5448aSXingyu Wu "i2stx0_bclk", 175dae5448aSXingyu Wu "hdmitx0_pixelclk" 176dae5448aSXingyu Wu }; 177dae5448aSXingyu Wu 178dae5448aSXingyu Wu for (i = 0; i < init.num_parents; i++) { 179dae5448aSXingyu Wu unsigned int pidx = jh7110_voutclk_data[idx].parents[i]; 180dae5448aSXingyu Wu 181dae5448aSXingyu Wu if (pidx < JH7110_VOUTCLK_END) 182dae5448aSXingyu Wu parents[i].hw = &priv->reg[pidx].hw; 183dae5448aSXingyu Wu else if (pidx < JH7110_VOUTCLK_EXT_END) 184dae5448aSXingyu Wu parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END]; 185dae5448aSXingyu Wu } 186dae5448aSXingyu Wu 187dae5448aSXingyu Wu clk->hw.init = &init; 188dae5448aSXingyu Wu clk->idx = idx; 189dae5448aSXingyu Wu clk->max_div = max & JH71X0_CLK_DIV_MASK; 190dae5448aSXingyu Wu 191dae5448aSXingyu Wu ret = devm_clk_hw_register(&pdev->dev, &clk->hw); 192dae5448aSXingyu Wu if (ret) 193dae5448aSXingyu Wu goto err_exit; 194dae5448aSXingyu Wu } 195dae5448aSXingyu Wu 196dae5448aSXingyu Wu ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_voutclk_get, priv); 197dae5448aSXingyu Wu if (ret) 198dae5448aSXingyu Wu goto err_exit; 199dae5448aSXingyu Wu 200dae5448aSXingyu Wu ret = jh7110_reset_controller_register(priv, "rst-vo", 4); 201dae5448aSXingyu Wu if (ret) 202dae5448aSXingyu Wu goto err_exit; 203dae5448aSXingyu Wu 204dae5448aSXingyu Wu return 0; 205dae5448aSXingyu Wu 206dae5448aSXingyu Wu err_exit: 207dae5448aSXingyu Wu pm_runtime_put_sync(priv->dev); 208dae5448aSXingyu Wu pm_runtime_disable(priv->dev); 209dae5448aSXingyu Wu return ret; 210dae5448aSXingyu Wu } 211dae5448aSXingyu Wu 212d963f257SUwe Kleine-König static void jh7110_voutcrg_remove(struct platform_device *pdev) 213dae5448aSXingyu Wu { 214dae5448aSXingyu Wu pm_runtime_put_sync(&pdev->dev); 215dae5448aSXingyu Wu pm_runtime_disable(&pdev->dev); 216dae5448aSXingyu Wu } 217dae5448aSXingyu Wu 218dae5448aSXingyu Wu static const struct of_device_id jh7110_voutcrg_match[] = { 219dae5448aSXingyu Wu { .compatible = "starfive,jh7110-voutcrg" }, 220dae5448aSXingyu Wu { /* sentinel */ } 221dae5448aSXingyu Wu }; 222dae5448aSXingyu Wu MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match); 223dae5448aSXingyu Wu 224dae5448aSXingyu Wu static struct platform_driver jh7110_voutcrg_driver = { 225dae5448aSXingyu Wu .probe = jh7110_voutcrg_probe, 226*f00b45dbSUwe Kleine-König .remove = jh7110_voutcrg_remove, 227dae5448aSXingyu Wu .driver = { 228dae5448aSXingyu Wu .name = "clk-starfive-jh7110-vout", 229dae5448aSXingyu Wu .of_match_table = jh7110_voutcrg_match, 230dae5448aSXingyu Wu .pm = pm_ptr(&jh7110_voutcrg_pm_ops), 231dae5448aSXingyu Wu }, 232dae5448aSXingyu Wu }; 233dae5448aSXingyu Wu module_platform_driver(jh7110_voutcrg_driver); 234dae5448aSXingyu Wu 235dae5448aSXingyu Wu MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>"); 236dae5448aSXingyu Wu MODULE_DESCRIPTION("StarFive JH7110 Video-Output clock driver"); 237dae5448aSXingyu Wu MODULE_LICENSE("GPL"); 238