1 /* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 6 * Author: Xing Zheng <zhengxing@rock-chips.com> 7 * 8 * based on 9 * 10 * samsung/clk.h 11 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 12 * Copyright (c) 2013 Linaro Ltd. 13 * Author: Thomas Abraham <thomas.ab@samsung.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 */ 25 26 #ifndef CLK_ROCKCHIP_CLK_H 27 #define CLK_ROCKCHIP_CLK_H 28 29 #include <linux/io.h> 30 #include <linux/clk-provider.h> 31 32 struct clk; 33 34 #define HIWORD_UPDATE(val, mask, shift) \ 35 ((val) << (shift) | (mask) << ((shift) + 16)) 36 37 /* register positions shared by RK1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */ 38 #define RK1108_PLL_CON(x) ((x) * 0x4) 39 #define RK1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 40 #define RK1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120) 41 #define RK1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180) 42 #define RK1108_GLB_SRST_FST 0x1c0 43 #define RK1108_GLB_SRST_SND 0x1c4 44 #define RK1108_MISC_CON 0x1cc 45 #define RK1108_SDMMC_CON0 0x1d8 46 #define RK1108_SDMMC_CON1 0x1dc 47 #define RK1108_SDIO_CON0 0x1e0 48 #define RK1108_SDIO_CON1 0x1e4 49 #define RK1108_EMMC_CON0 0x1e8 50 #define RK1108_EMMC_CON1 0x1ec 51 52 #define RK2928_PLL_CON(x) ((x) * 0x4) 53 #define RK2928_MODE_CON 0x40 54 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) 55 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0) 56 #define RK2928_GLB_SRST_FST 0x100 57 #define RK2928_GLB_SRST_SND 0x104 58 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110) 59 #define RK2928_MISC_CON 0x134 60 61 #define RK3036_SDMMC_CON0 0x144 62 #define RK3036_SDMMC_CON1 0x148 63 #define RK3036_SDIO_CON0 0x14c 64 #define RK3036_SDIO_CON1 0x150 65 #define RK3036_EMMC_CON0 0x154 66 #define RK3036_EMMC_CON1 0x158 67 68 #define RK3228_GLB_SRST_FST 0x1f0 69 #define RK3228_GLB_SRST_SND 0x1f4 70 #define RK3228_SDMMC_CON0 0x1c0 71 #define RK3228_SDMMC_CON1 0x1c4 72 #define RK3228_SDIO_CON0 0x1c8 73 #define RK3228_SDIO_CON1 0x1cc 74 #define RK3228_EMMC_CON0 0x1d8 75 #define RK3228_EMMC_CON1 0x1dc 76 77 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x) 78 #define RK3288_MODE_CON 0x50 79 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 80 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160) 81 #define RK3288_GLB_SRST_FST 0x1b0 82 #define RK3288_GLB_SRST_SND 0x1b4 83 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8) 84 #define RK3288_MISC_CON 0x1e8 85 #define RK3288_SDMMC_CON0 0x200 86 #define RK3288_SDMMC_CON1 0x204 87 #define RK3288_SDIO0_CON0 0x208 88 #define RK3288_SDIO0_CON1 0x20c 89 #define RK3288_SDIO1_CON0 0x210 90 #define RK3288_SDIO1_CON1 0x214 91 #define RK3288_EMMC_CON0 0x218 92 #define RK3288_EMMC_CON1 0x21c 93 94 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x) 95 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 96 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 97 #define RK3368_GLB_SRST_FST 0x280 98 #define RK3368_GLB_SRST_SND 0x284 99 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300) 100 #define RK3368_MISC_CON 0x380 101 #define RK3368_SDMMC_CON0 0x400 102 #define RK3368_SDMMC_CON1 0x404 103 #define RK3368_SDIO0_CON0 0x408 104 #define RK3368_SDIO0_CON1 0x40c 105 #define RK3368_SDIO1_CON0 0x410 106 #define RK3368_SDIO1_CON1 0x414 107 #define RK3368_EMMC_CON0 0x418 108 #define RK3368_EMMC_CON1 0x41c 109 110 #define RK3399_PLL_CON(x) RK2928_PLL_CON(x) 111 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 112 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300) 113 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400) 114 #define RK3399_GLB_SRST_FST 0x500 115 #define RK3399_GLB_SRST_SND 0x504 116 #define RK3399_GLB_CNT_TH 0x508 117 #define RK3399_MISC_CON 0x50c 118 #define RK3399_RST_CON 0x510 119 #define RK3399_RST_ST 0x514 120 #define RK3399_SDMMC_CON0 0x580 121 #define RK3399_SDMMC_CON1 0x584 122 #define RK3399_SDIO_CON0 0x588 123 #define RK3399_SDIO_CON1 0x58c 124 125 #define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x) 126 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80) 127 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) 128 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) 129 130 enum rockchip_pll_type { 131 pll_rk3036, 132 pll_rk3066, 133 pll_rk3399, 134 }; 135 136 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 137 _postdiv2, _dsmpd, _frac) \ 138 { \ 139 .rate = _rate##U, \ 140 .fbdiv = _fbdiv, \ 141 .postdiv1 = _postdiv1, \ 142 .refdiv = _refdiv, \ 143 .postdiv2 = _postdiv2, \ 144 .dsmpd = _dsmpd, \ 145 .frac = _frac, \ 146 } 147 148 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \ 149 { \ 150 .rate = _rate##U, \ 151 .nr = _nr, \ 152 .nf = _nf, \ 153 .no = _no, \ 154 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \ 155 } 156 157 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \ 158 { \ 159 .rate = _rate##U, \ 160 .nr = _nr, \ 161 .nf = _nf, \ 162 .no = _no, \ 163 .nb = _nb, \ 164 } 165 166 /** 167 * struct rockchip_clk_provider - information about clock provider 168 * @reg_base: virtual address for the register base. 169 * @clk_data: holds clock related data like clk* and number of clocks. 170 * @cru_node: device-node of the clock-provider 171 * @grf: regmap of the general-register-files syscon 172 * @lock: maintains exclusion between callbacks for a given clock-provider. 173 */ 174 struct rockchip_clk_provider { 175 void __iomem *reg_base; 176 struct clk_onecell_data clk_data; 177 struct device_node *cru_node; 178 struct regmap *grf; 179 spinlock_t lock; 180 }; 181 182 struct rockchip_pll_rate_table { 183 unsigned long rate; 184 unsigned int nr; 185 unsigned int nf; 186 unsigned int no; 187 unsigned int nb; 188 /* for RK3036/RK3399 */ 189 unsigned int fbdiv; 190 unsigned int postdiv1; 191 unsigned int refdiv; 192 unsigned int postdiv2; 193 unsigned int dsmpd; 194 unsigned int frac; 195 }; 196 197 /** 198 * struct rockchip_pll_clock - information about pll clock 199 * @id: platform specific id of the clock. 200 * @name: name of this pll clock. 201 * @parent_names: name of the parent clock. 202 * @num_parents: number of parents 203 * @flags: optional flags for basic clock. 204 * @con_offset: offset of the register for configuring the PLL. 205 * @mode_offset: offset of the register for configuring the PLL-mode. 206 * @mode_shift: offset inside the mode-register for the mode of this pll. 207 * @lock_shift: offset inside the lock register for the lock status. 208 * @type: Type of PLL to be registered. 209 * @pll_flags: hardware-specific flags 210 * @rate_table: Table of usable pll rates 211 * 212 * Flags: 213 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the 214 * rate_table parameters and ajust them if necessary. 215 */ 216 struct rockchip_pll_clock { 217 unsigned int id; 218 const char *name; 219 const char *const *parent_names; 220 u8 num_parents; 221 unsigned long flags; 222 int con_offset; 223 int mode_offset; 224 int mode_shift; 225 int lock_shift; 226 enum rockchip_pll_type type; 227 u8 pll_flags; 228 struct rockchip_pll_rate_table *rate_table; 229 }; 230 231 #define ROCKCHIP_PLL_SYNC_RATE BIT(0) 232 233 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ 234 _lshift, _pflags, _rtable) \ 235 { \ 236 .id = _id, \ 237 .type = _type, \ 238 .name = _name, \ 239 .parent_names = _pnames, \ 240 .num_parents = ARRAY_SIZE(_pnames), \ 241 .flags = CLK_GET_RATE_NOCACHE | _flags, \ 242 .con_offset = _con, \ 243 .mode_offset = _mode, \ 244 .mode_shift = _mshift, \ 245 .lock_shift = _lshift, \ 246 .pll_flags = _pflags, \ 247 .rate_table = _rtable, \ 248 } 249 250 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, 251 enum rockchip_pll_type pll_type, 252 const char *name, const char *const *parent_names, 253 u8 num_parents, int con_offset, int grf_lock_offset, 254 int lock_shift, int mode_offset, int mode_shift, 255 struct rockchip_pll_rate_table *rate_table, 256 unsigned long flags, u8 clk_pll_flags); 257 258 struct rockchip_cpuclk_clksel { 259 int reg; 260 u32 val; 261 }; 262 263 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2 264 struct rockchip_cpuclk_rate_table { 265 unsigned long prate; 266 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; 267 }; 268 269 /** 270 * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock 271 * @core_reg: register offset of the core settings register 272 * @div_core_shift: core divider offset used to divide the pll value 273 * @div_core_mask: core divider mask 274 * @mux_core_alt: mux value to select alternate parent 275 * @mux_core_main: mux value to select main parent of core 276 * @mux_core_shift: offset of the core multiplexer 277 * @mux_core_mask: core multiplexer mask 278 */ 279 struct rockchip_cpuclk_reg_data { 280 int core_reg; 281 u8 div_core_shift; 282 u32 div_core_mask; 283 u8 mux_core_alt; 284 u8 mux_core_main; 285 u8 mux_core_shift; 286 u32 mux_core_mask; 287 }; 288 289 struct clk *rockchip_clk_register_cpuclk(const char *name, 290 const char *const *parent_names, u8 num_parents, 291 const struct rockchip_cpuclk_reg_data *reg_data, 292 const struct rockchip_cpuclk_rate_table *rates, 293 int nrates, void __iomem *reg_base, spinlock_t *lock); 294 295 struct clk *rockchip_clk_register_mmc(const char *name, 296 const char *const *parent_names, u8 num_parents, 297 void __iomem *reg, int shift); 298 299 /* 300 * DDRCLK flags, including method of setting the rate 301 * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate. 302 */ 303 #define ROCKCHIP_DDRCLK_SIP BIT(0) 304 305 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, 306 const char *const *parent_names, 307 u8 num_parents, int mux_offset, 308 int mux_shift, int mux_width, 309 int div_shift, int div_width, 310 int ddr_flags, void __iomem *reg_base, 311 spinlock_t *lock); 312 313 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0) 314 315 struct clk *rockchip_clk_register_inverter(const char *name, 316 const char *const *parent_names, u8 num_parents, 317 void __iomem *reg, int shift, int flags, 318 spinlock_t *lock); 319 320 #define PNAME(x) static const char *const x[] __initconst 321 322 enum rockchip_clk_branch_type { 323 branch_composite, 324 branch_mux, 325 branch_divider, 326 branch_fraction_divider, 327 branch_gate, 328 branch_mmc, 329 branch_inverter, 330 branch_factor, 331 branch_ddrclk, 332 }; 333 334 struct rockchip_clk_branch { 335 unsigned int id; 336 enum rockchip_clk_branch_type branch_type; 337 const char *name; 338 const char *const *parent_names; 339 u8 num_parents; 340 unsigned long flags; 341 int muxdiv_offset; 342 u8 mux_shift; 343 u8 mux_width; 344 u8 mux_flags; 345 u8 div_shift; 346 u8 div_width; 347 u8 div_flags; 348 struct clk_div_table *div_table; 349 int gate_offset; 350 u8 gate_shift; 351 u8 gate_flags; 352 struct rockchip_clk_branch *child; 353 }; 354 355 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ 356 df, go, gs, gf) \ 357 { \ 358 .id = _id, \ 359 .branch_type = branch_composite, \ 360 .name = cname, \ 361 .parent_names = pnames, \ 362 .num_parents = ARRAY_SIZE(pnames), \ 363 .flags = f, \ 364 .muxdiv_offset = mo, \ 365 .mux_shift = ms, \ 366 .mux_width = mw, \ 367 .mux_flags = mf, \ 368 .div_shift = ds, \ 369 .div_width = dw, \ 370 .div_flags = df, \ 371 .gate_offset = go, \ 372 .gate_shift = gs, \ 373 .gate_flags = gf, \ 374 } 375 376 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \ 377 go, gs, gf) \ 378 { \ 379 .id = _id, \ 380 .branch_type = branch_composite, \ 381 .name = cname, \ 382 .parent_names = (const char *[]){ pname }, \ 383 .num_parents = 1, \ 384 .flags = f, \ 385 .muxdiv_offset = mo, \ 386 .div_shift = ds, \ 387 .div_width = dw, \ 388 .div_flags = df, \ 389 .gate_offset = go, \ 390 .gate_shift = gs, \ 391 .gate_flags = gf, \ 392 } 393 394 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\ 395 df, dt, go, gs, gf) \ 396 { \ 397 .id = _id, \ 398 .branch_type = branch_composite, \ 399 .name = cname, \ 400 .parent_names = (const char *[]){ pname }, \ 401 .num_parents = 1, \ 402 .flags = f, \ 403 .muxdiv_offset = mo, \ 404 .div_shift = ds, \ 405 .div_width = dw, \ 406 .div_flags = df, \ 407 .div_table = dt, \ 408 .gate_offset = go, \ 409 .gate_shift = gs, \ 410 .gate_flags = gf, \ 411 } 412 413 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \ 414 go, gs, gf) \ 415 { \ 416 .id = _id, \ 417 .branch_type = branch_composite, \ 418 .name = cname, \ 419 .parent_names = pnames, \ 420 .num_parents = ARRAY_SIZE(pnames), \ 421 .flags = f, \ 422 .muxdiv_offset = mo, \ 423 .mux_shift = ms, \ 424 .mux_width = mw, \ 425 .mux_flags = mf, \ 426 .gate_offset = go, \ 427 .gate_shift = gs, \ 428 .gate_flags = gf, \ 429 } 430 431 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \ 432 ds, dw, df) \ 433 { \ 434 .id = _id, \ 435 .branch_type = branch_composite, \ 436 .name = cname, \ 437 .parent_names = pnames, \ 438 .num_parents = ARRAY_SIZE(pnames), \ 439 .flags = f, \ 440 .muxdiv_offset = mo, \ 441 .mux_shift = ms, \ 442 .mux_width = mw, \ 443 .mux_flags = mf, \ 444 .div_shift = ds, \ 445 .div_width = dw, \ 446 .div_flags = df, \ 447 .gate_offset = -1, \ 448 } 449 450 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \ 451 mw, mf, ds, dw, df, dt) \ 452 { \ 453 .id = _id, \ 454 .branch_type = branch_composite, \ 455 .name = cname, \ 456 .parent_names = pnames, \ 457 .num_parents = ARRAY_SIZE(pnames), \ 458 .flags = f, \ 459 .muxdiv_offset = mo, \ 460 .mux_shift = ms, \ 461 .mux_width = mw, \ 462 .mux_flags = mf, \ 463 .div_shift = ds, \ 464 .div_width = dw, \ 465 .div_flags = df, \ 466 .div_table = dt, \ 467 .gate_offset = -1, \ 468 } 469 470 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\ 471 { \ 472 .id = _id, \ 473 .branch_type = branch_fraction_divider, \ 474 .name = cname, \ 475 .parent_names = (const char *[]){ pname }, \ 476 .num_parents = 1, \ 477 .flags = f, \ 478 .muxdiv_offset = mo, \ 479 .div_shift = 16, \ 480 .div_width = 16, \ 481 .div_flags = df, \ 482 .gate_offset = go, \ 483 .gate_shift = gs, \ 484 .gate_flags = gf, \ 485 } 486 487 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \ 488 { \ 489 .id = _id, \ 490 .branch_type = branch_fraction_divider, \ 491 .name = cname, \ 492 .parent_names = (const char *[]){ pname }, \ 493 .num_parents = 1, \ 494 .flags = f, \ 495 .muxdiv_offset = mo, \ 496 .div_shift = 16, \ 497 .div_width = 16, \ 498 .div_flags = df, \ 499 .gate_offset = go, \ 500 .gate_shift = gs, \ 501 .gate_flags = gf, \ 502 .child = ch, \ 503 } 504 505 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \ 506 { \ 507 .id = _id, \ 508 .branch_type = branch_fraction_divider, \ 509 .name = cname, \ 510 .parent_names = (const char *[]){ pname }, \ 511 .num_parents = 1, \ 512 .flags = f, \ 513 .muxdiv_offset = mo, \ 514 .div_shift = 16, \ 515 .div_width = 16, \ 516 .div_flags = df, \ 517 .gate_offset = -1, \ 518 .child = ch, \ 519 } 520 521 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \ 522 ds, dw, df) \ 523 { \ 524 .id = _id, \ 525 .branch_type = branch_ddrclk, \ 526 .name = cname, \ 527 .parent_names = pnames, \ 528 .num_parents = ARRAY_SIZE(pnames), \ 529 .flags = f, \ 530 .muxdiv_offset = mo, \ 531 .mux_shift = ms, \ 532 .mux_width = mw, \ 533 .div_shift = ds, \ 534 .div_width = dw, \ 535 .div_flags = df, \ 536 .gate_offset = -1, \ 537 } 538 539 #define MUX(_id, cname, pnames, f, o, s, w, mf) \ 540 { \ 541 .id = _id, \ 542 .branch_type = branch_mux, \ 543 .name = cname, \ 544 .parent_names = pnames, \ 545 .num_parents = ARRAY_SIZE(pnames), \ 546 .flags = f, \ 547 .muxdiv_offset = o, \ 548 .mux_shift = s, \ 549 .mux_width = w, \ 550 .mux_flags = mf, \ 551 .gate_offset = -1, \ 552 } 553 554 #define DIV(_id, cname, pname, f, o, s, w, df) \ 555 { \ 556 .id = _id, \ 557 .branch_type = branch_divider, \ 558 .name = cname, \ 559 .parent_names = (const char *[]){ pname }, \ 560 .num_parents = 1, \ 561 .flags = f, \ 562 .muxdiv_offset = o, \ 563 .div_shift = s, \ 564 .div_width = w, \ 565 .div_flags = df, \ 566 .gate_offset = -1, \ 567 } 568 569 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \ 570 { \ 571 .id = _id, \ 572 .branch_type = branch_divider, \ 573 .name = cname, \ 574 .parent_names = (const char *[]){ pname }, \ 575 .num_parents = 1, \ 576 .flags = f, \ 577 .muxdiv_offset = o, \ 578 .div_shift = s, \ 579 .div_width = w, \ 580 .div_flags = df, \ 581 .div_table = dt, \ 582 } 583 584 #define GATE(_id, cname, pname, f, o, b, gf) \ 585 { \ 586 .id = _id, \ 587 .branch_type = branch_gate, \ 588 .name = cname, \ 589 .parent_names = (const char *[]){ pname }, \ 590 .num_parents = 1, \ 591 .flags = f, \ 592 .gate_offset = o, \ 593 .gate_shift = b, \ 594 .gate_flags = gf, \ 595 } 596 597 #define MMC(_id, cname, pname, offset, shift) \ 598 { \ 599 .id = _id, \ 600 .branch_type = branch_mmc, \ 601 .name = cname, \ 602 .parent_names = (const char *[]){ pname }, \ 603 .num_parents = 1, \ 604 .muxdiv_offset = offset, \ 605 .div_shift = shift, \ 606 } 607 608 #define INVERTER(_id, cname, pname, io, is, if) \ 609 { \ 610 .id = _id, \ 611 .branch_type = branch_inverter, \ 612 .name = cname, \ 613 .parent_names = (const char *[]){ pname }, \ 614 .num_parents = 1, \ 615 .muxdiv_offset = io, \ 616 .div_shift = is, \ 617 .div_flags = if, \ 618 } 619 620 #define FACTOR(_id, cname, pname, f, fm, fd) \ 621 { \ 622 .id = _id, \ 623 .branch_type = branch_factor, \ 624 .name = cname, \ 625 .parent_names = (const char *[]){ pname }, \ 626 .num_parents = 1, \ 627 .flags = f, \ 628 .div_shift = fm, \ 629 .div_width = fd, \ 630 } 631 632 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \ 633 { \ 634 .id = _id, \ 635 .branch_type = branch_factor, \ 636 .name = cname, \ 637 .parent_names = (const char *[]){ pname }, \ 638 .num_parents = 1, \ 639 .flags = f, \ 640 .div_shift = fm, \ 641 .div_width = fd, \ 642 .gate_offset = go, \ 643 .gate_shift = gb, \ 644 .gate_flags = gf, \ 645 } 646 647 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, 648 void __iomem *base, unsigned long nr_clks); 649 void rockchip_clk_of_add_provider(struct device_node *np, 650 struct rockchip_clk_provider *ctx); 651 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, 652 struct clk *clk, unsigned int id); 653 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, 654 struct rockchip_clk_branch *list, 655 unsigned int nr_clk); 656 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, 657 struct rockchip_pll_clock *pll_list, 658 unsigned int nr_pll, int grf_lock_offset); 659 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, 660 unsigned int lookup_id, const char *name, 661 const char *const *parent_names, u8 num_parents, 662 const struct rockchip_cpuclk_reg_data *reg_data, 663 const struct rockchip_cpuclk_rate_table *rates, 664 int nrates); 665 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks); 666 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, 667 unsigned int reg, void (*cb)(void)); 668 669 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0) 670 671 #ifdef CONFIG_RESET_CONTROLLER 672 void rockchip_register_softrst(struct device_node *np, 673 unsigned int num_regs, 674 void __iomem *base, u8 flags); 675 #else 676 static inline void rockchip_register_softrst(struct device_node *np, 677 unsigned int num_regs, 678 void __iomem *base, u8 flags) 679 { 680 } 681 #endif 682 683 #endif 684