1635e5e73SDaire McNamara // SPDX-License-Identifier: GPL-2.0-only 2635e5e73SDaire McNamara /* 3635e5e73SDaire McNamara * Daire McNamara,<daire.mcnamara@microchip.com> 4635e5e73SDaire McNamara * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. 5635e5e73SDaire McNamara */ 6b56bae2dSConor Dooley #include <linux/auxiliary_bus.h> 7635e5e73SDaire McNamara #include <linux/clk-provider.h> 8635e5e73SDaire McNamara #include <linux/io.h> 9635e5e73SDaire McNamara #include <linux/module.h> 10635e5e73SDaire McNamara #include <linux/platform_device.h> 11635e5e73SDaire McNamara #include <linux/slab.h> 12635e5e73SDaire McNamara #include <dt-bindings/clock/microchip,mpfs-clock.h> 13b56bae2dSConor Dooley #include <soc/microchip/mpfs.h> 14635e5e73SDaire McNamara 15635e5e73SDaire McNamara /* address offset of control registers */ 16445c2da8SConor Dooley #define REG_MSSPLL_REF_CR 0x08u 17445c2da8SConor Dooley #define REG_MSSPLL_POSTDIV_CR 0x10u 18445c2da8SConor Dooley #define REG_MSSPLL_SSCG_2_CR 0x2Cu 19635e5e73SDaire McNamara #define REG_CLOCK_CONFIG_CR 0x08u 201c6a7ea3SConor Dooley #define REG_RTC_CLOCK_CR 0x0Cu 21635e5e73SDaire McNamara #define REG_SUBBLK_CLOCK_CR 0x84u 22635e5e73SDaire McNamara #define REG_SUBBLK_RESET_CR 0x88u 23635e5e73SDaire McNamara 24445c2da8SConor Dooley #define MSSPLL_FBDIV_SHIFT 0x00u 25445c2da8SConor Dooley #define MSSPLL_FBDIV_WIDTH 0x0Cu 26445c2da8SConor Dooley #define MSSPLL_REFDIV_SHIFT 0x08u 27445c2da8SConor Dooley #define MSSPLL_REFDIV_WIDTH 0x06u 28445c2da8SConor Dooley #define MSSPLL_POSTDIV_SHIFT 0x08u 29445c2da8SConor Dooley #define MSSPLL_POSTDIV_WIDTH 0x07u 30445c2da8SConor Dooley #define MSSPLL_FIXED_DIV 4u 31445c2da8SConor Dooley 32635e5e73SDaire McNamara struct mpfs_clock_data { 33b56bae2dSConor Dooley struct device *dev; 34635e5e73SDaire McNamara void __iomem *base; 35445c2da8SConor Dooley void __iomem *msspll_base; 36635e5e73SDaire McNamara struct clk_hw_onecell_data hw_data; 37635e5e73SDaire McNamara }; 38635e5e73SDaire McNamara 39445c2da8SConor Dooley struct mpfs_msspll_hw_clock { 40445c2da8SConor Dooley void __iomem *base; 41445c2da8SConor Dooley unsigned int id; 42445c2da8SConor Dooley u32 reg_offset; 43445c2da8SConor Dooley u32 shift; 44445c2da8SConor Dooley u32 width; 45445c2da8SConor Dooley u32 flags; 46445c2da8SConor Dooley struct clk_hw hw; 47445c2da8SConor Dooley struct clk_init_data init; 48445c2da8SConor Dooley }; 49445c2da8SConor Dooley 50445c2da8SConor Dooley #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) 51445c2da8SConor Dooley 52635e5e73SDaire McNamara struct mpfs_cfg_clock { 53635e5e73SDaire McNamara const struct clk_div_table *table; 54635e5e73SDaire McNamara unsigned int id; 55445c2da8SConor Dooley u32 reg_offset; 56635e5e73SDaire McNamara u8 shift; 57635e5e73SDaire McNamara u8 width; 58445c2da8SConor Dooley u8 flags; 59635e5e73SDaire McNamara }; 60635e5e73SDaire McNamara 61635e5e73SDaire McNamara struct mpfs_cfg_hw_clock { 62635e5e73SDaire McNamara struct mpfs_cfg_clock cfg; 63635e5e73SDaire McNamara void __iomem *sys_base; 64635e5e73SDaire McNamara struct clk_hw hw; 65635e5e73SDaire McNamara struct clk_init_data init; 66635e5e73SDaire McNamara }; 67635e5e73SDaire McNamara 68635e5e73SDaire McNamara #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) 69635e5e73SDaire McNamara 70635e5e73SDaire McNamara struct mpfs_periph_clock { 71635e5e73SDaire McNamara unsigned int id; 72635e5e73SDaire McNamara u8 shift; 73635e5e73SDaire McNamara }; 74635e5e73SDaire McNamara 75635e5e73SDaire McNamara struct mpfs_periph_hw_clock { 76635e5e73SDaire McNamara struct mpfs_periph_clock periph; 77635e5e73SDaire McNamara void __iomem *sys_base; 78635e5e73SDaire McNamara struct clk_hw hw; 79635e5e73SDaire McNamara }; 80635e5e73SDaire McNamara 81635e5e73SDaire McNamara #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) 82635e5e73SDaire McNamara 83635e5e73SDaire McNamara /* 84635e5e73SDaire McNamara * mpfs_clk_lock prevents anything else from writing to the 85635e5e73SDaire McNamara * mpfs clk block while a software locked register is being written. 86635e5e73SDaire McNamara */ 87635e5e73SDaire McNamara static DEFINE_SPINLOCK(mpfs_clk_lock); 88635e5e73SDaire McNamara 89445c2da8SConor Dooley static const struct clk_parent_data mpfs_ext_ref[] = { 90635e5e73SDaire McNamara { .index = 0 }, 91635e5e73SDaire McNamara }; 92635e5e73SDaire McNamara 93635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_cpu_axi_table[] = { 94635e5e73SDaire McNamara { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 95635e5e73SDaire McNamara { 0, 0 } 96635e5e73SDaire McNamara }; 97635e5e73SDaire McNamara 98635e5e73SDaire McNamara static const struct clk_div_table mpfs_div_ahb_table[] = { 99635e5e73SDaire McNamara { 1, 2 }, { 2, 4}, { 3, 8 }, 100635e5e73SDaire McNamara { 0, 0 } 101635e5e73SDaire McNamara }; 102635e5e73SDaire McNamara 1031c6a7ea3SConor Dooley /* 1041c6a7ea3SConor Dooley * The only two supported reference clock frequencies for the PolarFire SoC are 1051c6a7ea3SConor Dooley * 100 and 125 MHz, as the rtc reference is required to be 1 MHz. 1061c6a7ea3SConor Dooley * It therefore only needs to have divider table entries corresponding to 1071c6a7ea3SConor Dooley * divide by 100 and 125. 1081c6a7ea3SConor Dooley */ 1091c6a7ea3SConor Dooley static const struct clk_div_table mpfs_div_rtcref_table[] = { 1101c6a7ea3SConor Dooley { 100, 100 }, { 125, 125 }, 1111c6a7ea3SConor Dooley { 0, 0 } 1121c6a7ea3SConor Dooley }; 1131c6a7ea3SConor Dooley 114445c2da8SConor Dooley static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) 115445c2da8SConor Dooley { 116445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 117445c2da8SConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 118445c2da8SConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 119445c2da8SConor Dooley void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 120445c2da8SConor Dooley u32 mult, ref_div, postdiv; 121445c2da8SConor Dooley 122445c2da8SConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 123445c2da8SConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 124445c2da8SConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 125445c2da8SConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 126445c2da8SConor Dooley postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; 127445c2da8SConor Dooley postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); 128445c2da8SConor Dooley 129445c2da8SConor Dooley return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); 130445c2da8SConor Dooley } 131445c2da8SConor Dooley 132*14016e4aSConor Dooley static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 133*14016e4aSConor Dooley { 134*14016e4aSConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 135*14016e4aSConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 136*14016e4aSConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 137*14016e4aSConor Dooley u32 mult, ref_div; 138*14016e4aSConor Dooley unsigned long rate_before_ctrl; 139*14016e4aSConor Dooley 140*14016e4aSConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 141*14016e4aSConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 142*14016e4aSConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 143*14016e4aSConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 144*14016e4aSConor Dooley 145*14016e4aSConor Dooley rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 146*14016e4aSConor Dooley 147*14016e4aSConor Dooley return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 148*14016e4aSConor Dooley msspll_hw->flags); 149*14016e4aSConor Dooley } 150*14016e4aSConor Dooley 151*14016e4aSConor Dooley static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 152*14016e4aSConor Dooley { 153*14016e4aSConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 154*14016e4aSConor Dooley void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 155*14016e4aSConor Dooley void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 156*14016e4aSConor Dooley void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 157*14016e4aSConor Dooley u32 mult, ref_div, postdiv; 158*14016e4aSConor Dooley int divider_setting; 159*14016e4aSConor Dooley unsigned long rate_before_ctrl, flags; 160*14016e4aSConor Dooley 161*14016e4aSConor Dooley mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 162*14016e4aSConor Dooley mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 163*14016e4aSConor Dooley ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 164*14016e4aSConor Dooley ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 165*14016e4aSConor Dooley 166*14016e4aSConor Dooley rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 167*14016e4aSConor Dooley divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 168*14016e4aSConor Dooley msspll_hw->flags); 169*14016e4aSConor Dooley 170*14016e4aSConor Dooley if (divider_setting < 0) 171*14016e4aSConor Dooley return divider_setting; 172*14016e4aSConor Dooley 173*14016e4aSConor Dooley spin_lock_irqsave(&mpfs_clk_lock, flags); 174*14016e4aSConor Dooley 175*14016e4aSConor Dooley postdiv = readl_relaxed(postdiv_addr); 176*14016e4aSConor Dooley postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); 177*14016e4aSConor Dooley writel_relaxed(postdiv, postdiv_addr); 178*14016e4aSConor Dooley 179*14016e4aSConor Dooley spin_unlock_irqrestore(&mpfs_clk_lock, flags); 180*14016e4aSConor Dooley 181*14016e4aSConor Dooley return 0; 182*14016e4aSConor Dooley } 183*14016e4aSConor Dooley 184445c2da8SConor Dooley static const struct clk_ops mpfs_clk_msspll_ops = { 185445c2da8SConor Dooley .recalc_rate = mpfs_clk_msspll_recalc_rate, 186*14016e4aSConor Dooley .round_rate = mpfs_clk_msspll_round_rate, 187*14016e4aSConor Dooley .set_rate = mpfs_clk_msspll_set_rate, 188445c2da8SConor Dooley }; 189445c2da8SConor Dooley 190445c2da8SConor Dooley #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ 191445c2da8SConor Dooley .id = _id, \ 192445c2da8SConor Dooley .shift = _shift, \ 193445c2da8SConor Dooley .width = _width, \ 194445c2da8SConor Dooley .reg_offset = _offset, \ 195445c2da8SConor Dooley .flags = _flags, \ 196445c2da8SConor Dooley .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ 197445c2da8SConor Dooley } 198445c2da8SConor Dooley 199445c2da8SConor Dooley static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { 200445c2da8SConor Dooley CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, 201445c2da8SConor Dooley MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), 202445c2da8SConor Dooley }; 203445c2da8SConor Dooley 204445c2da8SConor Dooley static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hw, 205445c2da8SConor Dooley void __iomem *base) 206445c2da8SConor Dooley { 207445c2da8SConor Dooley msspll_hw->base = base; 208445c2da8SConor Dooley 209445c2da8SConor Dooley return devm_clk_hw_register(dev, &msspll_hw->hw); 210445c2da8SConor Dooley } 211445c2da8SConor Dooley 212445c2da8SConor Dooley static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, 213445c2da8SConor Dooley unsigned int num_clks, struct mpfs_clock_data *data) 214445c2da8SConor Dooley { 215445c2da8SConor Dooley void __iomem *base = data->msspll_base; 216445c2da8SConor Dooley unsigned int i; 217445c2da8SConor Dooley int ret; 218445c2da8SConor Dooley 219445c2da8SConor Dooley for (i = 0; i < num_clks; i++) { 220445c2da8SConor Dooley struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; 221445c2da8SConor Dooley 222445c2da8SConor Dooley ret = mpfs_clk_register_msspll(dev, msspll_hw, base); 223445c2da8SConor Dooley if (ret) 224445c2da8SConor Dooley return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", 225445c2da8SConor Dooley CLK_MSSPLL); 226445c2da8SConor Dooley 227445c2da8SConor Dooley data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; 228445c2da8SConor Dooley } 229445c2da8SConor Dooley 230445c2da8SConor Dooley return 0; 231445c2da8SConor Dooley } 232445c2da8SConor Dooley 233445c2da8SConor Dooley /* 234445c2da8SConor Dooley * "CFG" clocks 235445c2da8SConor Dooley */ 236445c2da8SConor Dooley 237635e5e73SDaire McNamara static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) 238635e5e73SDaire McNamara { 239635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 240635e5e73SDaire McNamara struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 241635e5e73SDaire McNamara void __iomem *base_addr = cfg_hw->sys_base; 242635e5e73SDaire McNamara u32 val; 243635e5e73SDaire McNamara 244445c2da8SConor Dooley val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; 245635e5e73SDaire McNamara val &= clk_div_mask(cfg->width); 246635e5e73SDaire McNamara 247445c2da8SConor Dooley return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); 248635e5e73SDaire McNamara } 249635e5e73SDaire McNamara 250635e5e73SDaire McNamara static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 251635e5e73SDaire McNamara { 252635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 253635e5e73SDaire McNamara struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 254635e5e73SDaire McNamara 255635e5e73SDaire McNamara return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); 256635e5e73SDaire McNamara } 257635e5e73SDaire McNamara 258635e5e73SDaire McNamara static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 259635e5e73SDaire McNamara { 260635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); 261635e5e73SDaire McNamara struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; 262635e5e73SDaire McNamara void __iomem *base_addr = cfg_hw->sys_base; 263635e5e73SDaire McNamara unsigned long flags; 264635e5e73SDaire McNamara u32 val; 265635e5e73SDaire McNamara int divider_setting; 266635e5e73SDaire McNamara 267635e5e73SDaire McNamara divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); 268635e5e73SDaire McNamara 269635e5e73SDaire McNamara if (divider_setting < 0) 270635e5e73SDaire McNamara return divider_setting; 271635e5e73SDaire McNamara 272635e5e73SDaire McNamara spin_lock_irqsave(&mpfs_clk_lock, flags); 273445c2da8SConor Dooley val = readl_relaxed(base_addr + cfg->reg_offset); 274635e5e73SDaire McNamara val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); 275635e5e73SDaire McNamara val |= divider_setting << cfg->shift; 276445c2da8SConor Dooley writel_relaxed(val, base_addr + cfg->reg_offset); 277635e5e73SDaire McNamara 278635e5e73SDaire McNamara spin_unlock_irqrestore(&mpfs_clk_lock, flags); 279635e5e73SDaire McNamara 280635e5e73SDaire McNamara return 0; 281635e5e73SDaire McNamara } 282635e5e73SDaire McNamara 283635e5e73SDaire McNamara static const struct clk_ops mpfs_clk_cfg_ops = { 284635e5e73SDaire McNamara .recalc_rate = mpfs_cfg_clk_recalc_rate, 285635e5e73SDaire McNamara .round_rate = mpfs_cfg_clk_round_rate, 286635e5e73SDaire McNamara .set_rate = mpfs_cfg_clk_set_rate, 287635e5e73SDaire McNamara }; 288635e5e73SDaire McNamara 289445c2da8SConor Dooley #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ 290635e5e73SDaire McNamara .cfg.id = _id, \ 291635e5e73SDaire McNamara .cfg.shift = _shift, \ 292635e5e73SDaire McNamara .cfg.width = _width, \ 293635e5e73SDaire McNamara .cfg.table = _table, \ 294445c2da8SConor Dooley .cfg.reg_offset = _offset, \ 295445c2da8SConor Dooley .cfg.flags = _flags, \ 296445c2da8SConor Dooley .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ 297635e5e73SDaire McNamara } 298635e5e73SDaire McNamara 2995da39ac5SConor Dooley #define CLK_CPU_OFFSET 0u 3005da39ac5SConor Dooley #define CLK_AXI_OFFSET 1u 3015da39ac5SConor Dooley #define CLK_AHB_OFFSET 2u 3025da39ac5SConor Dooley #define CLK_RTCREF_OFFSET 3u 3035da39ac5SConor Dooley 304635e5e73SDaire McNamara static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { 305445c2da8SConor Dooley CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0, 306445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 307445c2da8SConor Dooley CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0, 308445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 309445c2da8SConor Dooley CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, 310445c2da8SConor Dooley REG_CLOCK_CONFIG_CR), 3111c6a7ea3SConor Dooley { 3121c6a7ea3SConor Dooley .cfg.id = CLK_RTCREF, 3131c6a7ea3SConor Dooley .cfg.shift = 0, 3141c6a7ea3SConor Dooley .cfg.width = 12, 3151c6a7ea3SConor Dooley .cfg.table = mpfs_div_rtcref_table, 3161c6a7ea3SConor Dooley .cfg.reg_offset = REG_RTC_CLOCK_CR, 3171c6a7ea3SConor Dooley .cfg.flags = CLK_DIVIDER_ONE_BASED, 3181c6a7ea3SConor Dooley .hw.init = 3191c6a7ea3SConor Dooley CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), 3201c6a7ea3SConor Dooley } 321635e5e73SDaire McNamara }; 322635e5e73SDaire McNamara 323635e5e73SDaire McNamara static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, 324635e5e73SDaire McNamara void __iomem *sys_base) 325635e5e73SDaire McNamara { 326635e5e73SDaire McNamara cfg_hw->sys_base = sys_base; 327635e5e73SDaire McNamara 328635e5e73SDaire McNamara return devm_clk_hw_register(dev, &cfg_hw->hw); 329635e5e73SDaire McNamara } 330635e5e73SDaire McNamara 331635e5e73SDaire McNamara static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, 332635e5e73SDaire McNamara unsigned int num_clks, struct mpfs_clock_data *data) 333635e5e73SDaire McNamara { 334635e5e73SDaire McNamara void __iomem *sys_base = data->base; 335635e5e73SDaire McNamara unsigned int i, id; 336635e5e73SDaire McNamara int ret; 337635e5e73SDaire McNamara 338635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) { 339635e5e73SDaire McNamara struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; 340635e5e73SDaire McNamara 341635e5e73SDaire McNamara ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); 342635e5e73SDaire McNamara if (ret) 343635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 344635e5e73SDaire McNamara cfg_hw->cfg.id); 345635e5e73SDaire McNamara 346445c2da8SConor Dooley id = cfg_hw->cfg.id; 347635e5e73SDaire McNamara data->hw_data.hws[id] = &cfg_hw->hw; 348635e5e73SDaire McNamara } 349635e5e73SDaire McNamara 350635e5e73SDaire McNamara return 0; 351635e5e73SDaire McNamara } 352635e5e73SDaire McNamara 353445c2da8SConor Dooley /* 354445c2da8SConor Dooley * peripheral clocks - devices connected to axi or ahb buses. 355445c2da8SConor Dooley */ 356445c2da8SConor Dooley 357635e5e73SDaire McNamara static int mpfs_periph_clk_enable(struct clk_hw *hw) 358635e5e73SDaire McNamara { 359635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 360635e5e73SDaire McNamara struct mpfs_periph_clock *periph = &periph_hw->periph; 361635e5e73SDaire McNamara void __iomem *base_addr = periph_hw->sys_base; 362635e5e73SDaire McNamara u32 reg, val; 363635e5e73SDaire McNamara unsigned long flags; 364635e5e73SDaire McNamara 365635e5e73SDaire McNamara spin_lock_irqsave(&mpfs_clk_lock, flags); 366635e5e73SDaire McNamara 367635e5e73SDaire McNamara reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 368635e5e73SDaire McNamara val = reg | (1u << periph->shift); 369635e5e73SDaire McNamara writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 370635e5e73SDaire McNamara 371635e5e73SDaire McNamara spin_unlock_irqrestore(&mpfs_clk_lock, flags); 372635e5e73SDaire McNamara 373635e5e73SDaire McNamara return 0; 374635e5e73SDaire McNamara } 375635e5e73SDaire McNamara 376635e5e73SDaire McNamara static void mpfs_periph_clk_disable(struct clk_hw *hw) 377635e5e73SDaire McNamara { 378635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 379635e5e73SDaire McNamara struct mpfs_periph_clock *periph = &periph_hw->periph; 380635e5e73SDaire McNamara void __iomem *base_addr = periph_hw->sys_base; 381635e5e73SDaire McNamara u32 reg, val; 382635e5e73SDaire McNamara unsigned long flags; 383635e5e73SDaire McNamara 384635e5e73SDaire McNamara spin_lock_irqsave(&mpfs_clk_lock, flags); 385635e5e73SDaire McNamara 386635e5e73SDaire McNamara reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 387635e5e73SDaire McNamara val = reg & ~(1u << periph->shift); 388635e5e73SDaire McNamara writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); 389635e5e73SDaire McNamara 390635e5e73SDaire McNamara spin_unlock_irqrestore(&mpfs_clk_lock, flags); 391635e5e73SDaire McNamara } 392635e5e73SDaire McNamara 393635e5e73SDaire McNamara static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) 394635e5e73SDaire McNamara { 395635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); 396635e5e73SDaire McNamara struct mpfs_periph_clock *periph = &periph_hw->periph; 397635e5e73SDaire McNamara void __iomem *base_addr = periph_hw->sys_base; 398635e5e73SDaire McNamara u32 reg; 399635e5e73SDaire McNamara 400635e5e73SDaire McNamara reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); 401635e5e73SDaire McNamara if (reg & (1u << periph->shift)) 402635e5e73SDaire McNamara return 1; 403635e5e73SDaire McNamara 404635e5e73SDaire McNamara return 0; 405635e5e73SDaire McNamara } 406635e5e73SDaire McNamara 407635e5e73SDaire McNamara static const struct clk_ops mpfs_periph_clk_ops = { 408635e5e73SDaire McNamara .enable = mpfs_periph_clk_enable, 409635e5e73SDaire McNamara .disable = mpfs_periph_clk_disable, 410635e5e73SDaire McNamara .is_enabled = mpfs_periph_clk_is_enabled, 411635e5e73SDaire McNamara }; 412635e5e73SDaire McNamara 413635e5e73SDaire McNamara #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ 414635e5e73SDaire McNamara .periph.id = _id, \ 415635e5e73SDaire McNamara .periph.shift = _shift, \ 416635e5e73SDaire McNamara .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ 417635e5e73SDaire McNamara _flags), \ 418635e5e73SDaire McNamara } 419635e5e73SDaire McNamara 4205da39ac5SConor Dooley #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw) 421635e5e73SDaire McNamara 422635e5e73SDaire McNamara /* 423635e5e73SDaire McNamara * Critical clocks: 424635e5e73SDaire McNamara * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt 425635e5e73SDaire McNamara * trap handler 426635e5e73SDaire McNamara * - CLK_MMUART0: reserved by the hss 427635e5e73SDaire McNamara * - CLK_DDRC: provides clock to the ddr subsystem 42805d27090SConor Dooley * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop 42905d27090SConor Dooley * if the AHB interface clock is disabled 430a2438f82SConor Dooley * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect) 431a2438f82SConor Dooley * clock domain crossers which provide the interface to the FPGA fabric. Disabling them 432a2438f82SConor Dooley * causes the FPGA fabric to go into reset. 433a2438f82SConor Dooley * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire. 434635e5e73SDaire McNamara */ 435635e5e73SDaire McNamara 436635e5e73SDaire McNamara static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { 437635e5e73SDaire McNamara CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL), 438635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), 439635e5e73SDaire McNamara CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), 440635e5e73SDaire McNamara CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), 4411c6a7ea3SConor Dooley CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0), 442635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), 443635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), 444635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), 445635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0), 446635e5e73SDaire McNamara CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0), 447635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0), 448635e5e73SDaire McNamara CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0), 449635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0), 450635e5e73SDaire McNamara CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0), 451635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), 452635e5e73SDaire McNamara CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), 453635e5e73SDaire McNamara CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), 45405d27090SConor Dooley CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL), 455635e5e73SDaire McNamara CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), 456635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), 457635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0), 458635e5e73SDaire McNamara CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0), 459635e5e73SDaire McNamara CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL), 4608f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL), 4618f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL), 4628f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL), 4638f9fb2abSConor Dooley CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL), 464a2438f82SConor Dooley CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL), 465635e5e73SDaire McNamara CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), 466635e5e73SDaire McNamara }; 467635e5e73SDaire McNamara 468635e5e73SDaire McNamara static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, 469635e5e73SDaire McNamara void __iomem *sys_base) 470635e5e73SDaire McNamara { 471635e5e73SDaire McNamara periph_hw->sys_base = sys_base; 472635e5e73SDaire McNamara 473635e5e73SDaire McNamara return devm_clk_hw_register(dev, &periph_hw->hw); 474635e5e73SDaire McNamara } 475635e5e73SDaire McNamara 476635e5e73SDaire McNamara static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, 477635e5e73SDaire McNamara int num_clks, struct mpfs_clock_data *data) 478635e5e73SDaire McNamara { 479635e5e73SDaire McNamara void __iomem *sys_base = data->base; 480635e5e73SDaire McNamara unsigned int i, id; 481635e5e73SDaire McNamara int ret; 482635e5e73SDaire McNamara 483635e5e73SDaire McNamara for (i = 0; i < num_clks; i++) { 484635e5e73SDaire McNamara struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; 485635e5e73SDaire McNamara 486635e5e73SDaire McNamara ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); 487635e5e73SDaire McNamara if (ret) 488635e5e73SDaire McNamara return dev_err_probe(dev, ret, "failed to register clock id: %d\n", 489635e5e73SDaire McNamara periph_hw->periph.id); 490635e5e73SDaire McNamara 491635e5e73SDaire McNamara id = periph_hws[i].periph.id; 492635e5e73SDaire McNamara data->hw_data.hws[id] = &periph_hw->hw; 493635e5e73SDaire McNamara } 494635e5e73SDaire McNamara 495635e5e73SDaire McNamara return 0; 496635e5e73SDaire McNamara } 497635e5e73SDaire McNamara 498b56bae2dSConor Dooley /* 499b56bae2dSConor Dooley * Peripheral clock resets 500b56bae2dSConor Dooley */ 501b56bae2dSConor Dooley 502b56bae2dSConor Dooley #if IS_ENABLED(CONFIG_RESET_CONTROLLER) 503b56bae2dSConor Dooley 504b56bae2dSConor Dooley u32 mpfs_reset_read(struct device *dev) 505b56bae2dSConor Dooley { 506b56bae2dSConor Dooley struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 507b56bae2dSConor Dooley 508b56bae2dSConor Dooley return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); 509b56bae2dSConor Dooley } 510b56bae2dSConor Dooley EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); 511b56bae2dSConor Dooley 512b56bae2dSConor Dooley void mpfs_reset_write(struct device *dev, u32 val) 513b56bae2dSConor Dooley { 514b56bae2dSConor Dooley struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); 515b56bae2dSConor Dooley 516b56bae2dSConor Dooley writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); 517b56bae2dSConor Dooley } 518b56bae2dSConor Dooley EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); 519b56bae2dSConor Dooley 520b56bae2dSConor Dooley static void mpfs_reset_unregister_adev(void *_adev) 521b56bae2dSConor Dooley { 522b56bae2dSConor Dooley struct auxiliary_device *adev = _adev; 523b56bae2dSConor Dooley 524b56bae2dSConor Dooley auxiliary_device_delete(adev); 525b56bae2dSConor Dooley } 526b56bae2dSConor Dooley 527b56bae2dSConor Dooley static void mpfs_reset_adev_release(struct device *dev) 528b56bae2dSConor Dooley { 529b56bae2dSConor Dooley struct auxiliary_device *adev = to_auxiliary_dev(dev); 530b56bae2dSConor Dooley 531b56bae2dSConor Dooley auxiliary_device_uninit(adev); 532b56bae2dSConor Dooley 533b56bae2dSConor Dooley kfree(adev); 534b56bae2dSConor Dooley } 535b56bae2dSConor Dooley 536b56bae2dSConor Dooley static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data) 537b56bae2dSConor Dooley { 538b56bae2dSConor Dooley struct auxiliary_device *adev; 539b56bae2dSConor Dooley int ret; 540b56bae2dSConor Dooley 541b56bae2dSConor Dooley adev = kzalloc(sizeof(*adev), GFP_KERNEL); 542b56bae2dSConor Dooley if (!adev) 543b56bae2dSConor Dooley return ERR_PTR(-ENOMEM); 544b56bae2dSConor Dooley 545b56bae2dSConor Dooley adev->name = "reset-mpfs"; 546b56bae2dSConor Dooley adev->dev.parent = clk_data->dev; 547b56bae2dSConor Dooley adev->dev.release = mpfs_reset_adev_release; 548b56bae2dSConor Dooley adev->id = 666u; 549b56bae2dSConor Dooley 550b56bae2dSConor Dooley ret = auxiliary_device_init(adev); 551b56bae2dSConor Dooley if (ret) { 552b56bae2dSConor Dooley kfree(adev); 553b56bae2dSConor Dooley return ERR_PTR(ret); 554b56bae2dSConor Dooley } 555b56bae2dSConor Dooley 556b56bae2dSConor Dooley return adev; 557b56bae2dSConor Dooley } 558b56bae2dSConor Dooley 559b56bae2dSConor Dooley static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 560b56bae2dSConor Dooley { 561b56bae2dSConor Dooley struct auxiliary_device *adev; 562b56bae2dSConor Dooley int ret; 563b56bae2dSConor Dooley 564b56bae2dSConor Dooley adev = mpfs_reset_adev_alloc(clk_data); 565b56bae2dSConor Dooley if (IS_ERR(adev)) 566b56bae2dSConor Dooley return PTR_ERR(adev); 567b56bae2dSConor Dooley 568b56bae2dSConor Dooley ret = auxiliary_device_add(adev); 569b56bae2dSConor Dooley if (ret) { 570b56bae2dSConor Dooley auxiliary_device_uninit(adev); 571b56bae2dSConor Dooley return ret; 572b56bae2dSConor Dooley } 573b56bae2dSConor Dooley 574b56bae2dSConor Dooley return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev); 575b56bae2dSConor Dooley } 576b56bae2dSConor Dooley 577b56bae2dSConor Dooley #else /* !CONFIG_RESET_CONTROLLER */ 578b56bae2dSConor Dooley 579b56bae2dSConor Dooley static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) 580b56bae2dSConor Dooley { 581b56bae2dSConor Dooley return 0; 582b56bae2dSConor Dooley } 583b56bae2dSConor Dooley 584b56bae2dSConor Dooley #endif /* !CONFIG_RESET_CONTROLLER */ 585b56bae2dSConor Dooley 586635e5e73SDaire McNamara static int mpfs_clk_probe(struct platform_device *pdev) 587635e5e73SDaire McNamara { 588635e5e73SDaire McNamara struct device *dev = &pdev->dev; 589635e5e73SDaire McNamara struct mpfs_clock_data *clk_data; 590635e5e73SDaire McNamara unsigned int num_clks; 591635e5e73SDaire McNamara int ret; 592635e5e73SDaire McNamara 593445c2da8SConor Dooley /* CLK_RESERVED is not part of clock arrays, so add 1 */ 594445c2da8SConor Dooley num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) 595445c2da8SConor Dooley + ARRAY_SIZE(mpfs_periph_clks) + 1; 596635e5e73SDaire McNamara 597635e5e73SDaire McNamara clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); 598635e5e73SDaire McNamara if (!clk_data) 599635e5e73SDaire McNamara return -ENOMEM; 600635e5e73SDaire McNamara 601635e5e73SDaire McNamara clk_data->base = devm_platform_ioremap_resource(pdev, 0); 602635e5e73SDaire McNamara if (IS_ERR(clk_data->base)) 603635e5e73SDaire McNamara return PTR_ERR(clk_data->base); 604635e5e73SDaire McNamara 605445c2da8SConor Dooley clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1); 606445c2da8SConor Dooley if (IS_ERR(clk_data->msspll_base)) 607445c2da8SConor Dooley return PTR_ERR(clk_data->msspll_base); 608445c2da8SConor Dooley 609635e5e73SDaire McNamara clk_data->hw_data.num = num_clks; 610b56bae2dSConor Dooley clk_data->dev = dev; 611b56bae2dSConor Dooley dev_set_drvdata(dev, clk_data); 612635e5e73SDaire McNamara 613445c2da8SConor Dooley ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), 614445c2da8SConor Dooley clk_data); 615445c2da8SConor Dooley if (ret) 616445c2da8SConor Dooley return ret; 617445c2da8SConor Dooley 618635e5e73SDaire McNamara ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); 619635e5e73SDaire McNamara if (ret) 620635e5e73SDaire McNamara return ret; 621635e5e73SDaire McNamara 622635e5e73SDaire McNamara ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks), 623635e5e73SDaire McNamara clk_data); 624635e5e73SDaire McNamara if (ret) 625635e5e73SDaire McNamara return ret; 626635e5e73SDaire McNamara 627635e5e73SDaire McNamara ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); 628635e5e73SDaire McNamara if (ret) 629635e5e73SDaire McNamara return ret; 630635e5e73SDaire McNamara 631b56bae2dSConor Dooley return mpfs_reset_controller_register(clk_data); 632635e5e73SDaire McNamara } 633635e5e73SDaire McNamara 634635e5e73SDaire McNamara static const struct of_device_id mpfs_clk_of_match_table[] = { 635635e5e73SDaire McNamara { .compatible = "microchip,mpfs-clkcfg", }, 636635e5e73SDaire McNamara {} 637635e5e73SDaire McNamara }; 638b56bae2dSConor Dooley MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table); 639635e5e73SDaire McNamara 640635e5e73SDaire McNamara static struct platform_driver mpfs_clk_driver = { 641635e5e73SDaire McNamara .probe = mpfs_clk_probe, 642635e5e73SDaire McNamara .driver = { 643635e5e73SDaire McNamara .name = "microchip-mpfs-clkcfg", 644635e5e73SDaire McNamara .of_match_table = mpfs_clk_of_match_table, 645635e5e73SDaire McNamara }, 646635e5e73SDaire McNamara }; 647635e5e73SDaire McNamara 648635e5e73SDaire McNamara static int __init clk_mpfs_init(void) 649635e5e73SDaire McNamara { 650635e5e73SDaire McNamara return platform_driver_register(&mpfs_clk_driver); 651635e5e73SDaire McNamara } 652635e5e73SDaire McNamara core_initcall(clk_mpfs_init); 653635e5e73SDaire McNamara 654635e5e73SDaire McNamara static void __exit clk_mpfs_exit(void) 655635e5e73SDaire McNamara { 656635e5e73SDaire McNamara platform_driver_unregister(&mpfs_clk_driver); 657635e5e73SDaire McNamara } 658635e5e73SDaire McNamara module_exit(clk_mpfs_exit); 659635e5e73SDaire McNamara 660635e5e73SDaire McNamara MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); 661635e5e73SDaire McNamara MODULE_LICENSE("GPL v2"); 662