1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 211f68120SShawn Guo #include <linux/kernel.h> 311f68120SShawn Guo #include <linux/clk.h> 411f68120SShawn Guo #include <linux/io.h> 511f68120SShawn Guo #include <linux/errno.h> 611f68120SShawn Guo #include <linux/delay.h> 711f68120SShawn Guo #include <linux/slab.h> 811f68120SShawn Guo #include <linux/err.h> 911f68120SShawn Guo 1011f68120SShawn Guo #include <asm/div64.h> 1111f68120SShawn Guo 1211f68120SShawn Guo #include "clk.h" 1311f68120SShawn Guo 1411f68120SShawn Guo #define to_clk_pllv2(clk) (container_of(clk, struct clk_pllv2, clk)) 1511f68120SShawn Guo 1611f68120SShawn Guo /* PLL Register Offsets */ 1711f68120SShawn Guo #define MXC_PLL_DP_CTL 0x00 1811f68120SShawn Guo #define MXC_PLL_DP_CONFIG 0x04 1911f68120SShawn Guo #define MXC_PLL_DP_OP 0x08 2011f68120SShawn Guo #define MXC_PLL_DP_MFD 0x0C 2111f68120SShawn Guo #define MXC_PLL_DP_MFN 0x10 2211f68120SShawn Guo #define MXC_PLL_DP_MFNMINUS 0x14 2311f68120SShawn Guo #define MXC_PLL_DP_MFNPLUS 0x18 2411f68120SShawn Guo #define MXC_PLL_DP_HFS_OP 0x1C 2511f68120SShawn Guo #define MXC_PLL_DP_HFS_MFD 0x20 2611f68120SShawn Guo #define MXC_PLL_DP_HFS_MFN 0x24 2711f68120SShawn Guo #define MXC_PLL_DP_MFN_TOGC 0x28 2811f68120SShawn Guo #define MXC_PLL_DP_DESTAT 0x2c 2911f68120SShawn Guo 3011f68120SShawn Guo /* PLL Register Bit definitions */ 3111f68120SShawn Guo #define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 3211f68120SShawn Guo #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 3311f68120SShawn Guo #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 3411f68120SShawn Guo #define MXC_PLL_DP_CTL_ADE 0x800 3511f68120SShawn Guo #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 3611f68120SShawn Guo #define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) 3711f68120SShawn Guo #define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 3811f68120SShawn Guo #define MXC_PLL_DP_CTL_HFSM 0x80 3911f68120SShawn Guo #define MXC_PLL_DP_CTL_PRE 0x40 4011f68120SShawn Guo #define MXC_PLL_DP_CTL_UPEN 0x20 4111f68120SShawn Guo #define MXC_PLL_DP_CTL_RST 0x10 4211f68120SShawn Guo #define MXC_PLL_DP_CTL_RCP 0x8 4311f68120SShawn Guo #define MXC_PLL_DP_CTL_PLM 0x4 4411f68120SShawn Guo #define MXC_PLL_DP_CTL_BRM0 0x2 4511f68120SShawn Guo #define MXC_PLL_DP_CTL_LRF 0x1 4611f68120SShawn Guo 4711f68120SShawn Guo #define MXC_PLL_DP_CONFIG_BIST 0x8 4811f68120SShawn Guo #define MXC_PLL_DP_CONFIG_SJC_CE 0x4 4911f68120SShawn Guo #define MXC_PLL_DP_CONFIG_AREN 0x2 5011f68120SShawn Guo #define MXC_PLL_DP_CONFIG_LDREQ 0x1 5111f68120SShawn Guo 5211f68120SShawn Guo #define MXC_PLL_DP_OP_MFI_OFFSET 4 5311f68120SShawn Guo #define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) 5411f68120SShawn Guo #define MXC_PLL_DP_OP_PDF_OFFSET 0 5511f68120SShawn Guo #define MXC_PLL_DP_OP_PDF_MASK 0xF 5611f68120SShawn Guo 5711f68120SShawn Guo #define MXC_PLL_DP_MFD_OFFSET 0 5811f68120SShawn Guo #define MXC_PLL_DP_MFD_MASK 0x07FFFFFF 5911f68120SShawn Guo 6011f68120SShawn Guo #define MXC_PLL_DP_MFN_OFFSET 0x0 6111f68120SShawn Guo #define MXC_PLL_DP_MFN_MASK 0x07FFFFFF 6211f68120SShawn Guo 6311f68120SShawn Guo #define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) 6411f68120SShawn Guo #define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) 6511f68120SShawn Guo #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 6611f68120SShawn Guo #define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF 6711f68120SShawn Guo 6811f68120SShawn Guo #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) 6911f68120SShawn Guo #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF 7011f68120SShawn Guo 7111f68120SShawn Guo #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ 7211f68120SShawn Guo 7311f68120SShawn Guo struct clk_pllv2 { 7411f68120SShawn Guo struct clk_hw hw; 7511f68120SShawn Guo void __iomem *base; 7611f68120SShawn Guo }; 7711f68120SShawn Guo 7811f68120SShawn Guo static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate, 7911f68120SShawn Guo u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn) 8011f68120SShawn Guo { 8153fdc8fdSMartin Kepplinger long mfi, mfn, mfd, pdf, ref_clk; 8211f68120SShawn Guo unsigned long dbl; 830d2681e1SNicolas Pitre u64 temp; 8411f68120SShawn Guo 8511f68120SShawn Guo dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; 8611f68120SShawn Guo 8711f68120SShawn Guo pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; 8811f68120SShawn Guo mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; 8911f68120SShawn Guo mfi = (mfi <= 5) ? 5 : mfi; 9011f68120SShawn Guo mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; 9153fdc8fdSMartin Kepplinger mfn = dp_mfn & MXC_PLL_DP_MFN_MASK; 9253fdc8fdSMartin Kepplinger mfn = sign_extend32(mfn, 26); 9311f68120SShawn Guo 9411f68120SShawn Guo ref_clk = 2 * parent_rate; 9511f68120SShawn Guo if (dbl != 0) 9611f68120SShawn Guo ref_clk *= 2; 9711f68120SShawn Guo 9811f68120SShawn Guo ref_clk /= (pdf + 1); 9953fdc8fdSMartin Kepplinger temp = (u64) ref_clk * abs(mfn); 10011f68120SShawn Guo do_div(temp, mfd + 1); 10111f68120SShawn Guo if (mfn < 0) 1020d2681e1SNicolas Pitre temp = (ref_clk * mfi) - temp; 1030d2681e1SNicolas Pitre else 10411f68120SShawn Guo temp = (ref_clk * mfi) + temp; 10511f68120SShawn Guo 10611f68120SShawn Guo return temp; 10711f68120SShawn Guo } 10811f68120SShawn Guo 10911f68120SShawn Guo static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw, 11011f68120SShawn Guo unsigned long parent_rate) 11111f68120SShawn Guo { 11211f68120SShawn Guo u32 dp_op, dp_mfd, dp_mfn, dp_ctl; 11311f68120SShawn Guo void __iomem *pllbase; 11411f68120SShawn Guo struct clk_pllv2 *pll = to_clk_pllv2(hw); 11511f68120SShawn Guo 11611f68120SShawn Guo pllbase = pll->base; 11711f68120SShawn Guo 11811f68120SShawn Guo dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); 11911f68120SShawn Guo dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); 12011f68120SShawn Guo dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); 12111f68120SShawn Guo dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); 12211f68120SShawn Guo 12311f68120SShawn Guo return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn); 12411f68120SShawn Guo } 12511f68120SShawn Guo 12611f68120SShawn Guo static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate, 12711f68120SShawn Guo u32 *dp_op, u32 *dp_mfd, u32 *dp_mfn) 12811f68120SShawn Guo { 12911f68120SShawn Guo u32 reg; 13011f68120SShawn Guo long mfi, pdf, mfn, mfd = 999999; 1310d2681e1SNicolas Pitre u64 temp64; 13211f68120SShawn Guo unsigned long quad_parent_rate; 13311f68120SShawn Guo 13411f68120SShawn Guo quad_parent_rate = 4 * parent_rate; 13511f68120SShawn Guo pdf = mfi = -1; 13611f68120SShawn Guo while (++pdf < 16 && mfi < 5) 13711f68120SShawn Guo mfi = rate * (pdf+1) / quad_parent_rate; 13811f68120SShawn Guo if (mfi > 15) 13911f68120SShawn Guo return -EINVAL; 14011f68120SShawn Guo pdf--; 14111f68120SShawn Guo 14211f68120SShawn Guo temp64 = rate * (pdf + 1) - quad_parent_rate * mfi; 14311f68120SShawn Guo do_div(temp64, quad_parent_rate / 1000000); 14411f68120SShawn Guo mfn = (long)temp64; 14511f68120SShawn Guo 14611f68120SShawn Guo reg = mfi << 4 | pdf; 14711f68120SShawn Guo 14811f68120SShawn Guo *dp_op = reg; 14911f68120SShawn Guo *dp_mfd = mfd; 15011f68120SShawn Guo *dp_mfn = mfn; 15111f68120SShawn Guo 15211f68120SShawn Guo return 0; 15311f68120SShawn Guo } 15411f68120SShawn Guo 15511f68120SShawn Guo static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate, 15611f68120SShawn Guo unsigned long parent_rate) 15711f68120SShawn Guo { 15811f68120SShawn Guo struct clk_pllv2 *pll = to_clk_pllv2(hw); 15911f68120SShawn Guo void __iomem *pllbase; 16011f68120SShawn Guo u32 dp_ctl, dp_op, dp_mfd, dp_mfn; 16111f68120SShawn Guo int ret; 16211f68120SShawn Guo 16311f68120SShawn Guo pllbase = pll->base; 16411f68120SShawn Guo 16511f68120SShawn Guo 16611f68120SShawn Guo ret = __clk_pllv2_set_rate(rate, parent_rate, &dp_op, &dp_mfd, &dp_mfn); 16711f68120SShawn Guo if (ret) 16811f68120SShawn Guo return ret; 16911f68120SShawn Guo 17011f68120SShawn Guo dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); 17111f68120SShawn Guo /* use dpdck0_2 */ 17211f68120SShawn Guo __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); 17311f68120SShawn Guo 17411f68120SShawn Guo __raw_writel(dp_op, pllbase + MXC_PLL_DP_OP); 17511f68120SShawn Guo __raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD); 17611f68120SShawn Guo __raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN); 17711f68120SShawn Guo 17811f68120SShawn Guo return 0; 17911f68120SShawn Guo } 18011f68120SShawn Guo 18111f68120SShawn Guo static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate, 18211f68120SShawn Guo unsigned long *prate) 18311f68120SShawn Guo { 18411f68120SShawn Guo u32 dp_op, dp_mfd, dp_mfn; 18593abad36SLucas Stach int ret; 18611f68120SShawn Guo 18793abad36SLucas Stach ret = __clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn); 18893abad36SLucas Stach if (ret) 18993abad36SLucas Stach return ret; 19093abad36SLucas Stach 19111f68120SShawn Guo return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN, 19211f68120SShawn Guo dp_op, dp_mfd, dp_mfn); 19311f68120SShawn Guo } 19411f68120SShawn Guo 19511f68120SShawn Guo static int clk_pllv2_prepare(struct clk_hw *hw) 19611f68120SShawn Guo { 19711f68120SShawn Guo struct clk_pllv2 *pll = to_clk_pllv2(hw); 19811f68120SShawn Guo u32 reg; 19911f68120SShawn Guo void __iomem *pllbase; 20011f68120SShawn Guo int i = 0; 20111f68120SShawn Guo 20211f68120SShawn Guo pllbase = pll->base; 20311f68120SShawn Guo reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; 20411f68120SShawn Guo __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); 20511f68120SShawn Guo 20611f68120SShawn Guo /* Wait for lock */ 20711f68120SShawn Guo do { 20811f68120SShawn Guo reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); 20911f68120SShawn Guo if (reg & MXC_PLL_DP_CTL_LRF) 21011f68120SShawn Guo break; 21111f68120SShawn Guo 21211f68120SShawn Guo udelay(1); 21311f68120SShawn Guo } while (++i < MAX_DPLL_WAIT_TRIES); 21411f68120SShawn Guo 21511f68120SShawn Guo if (i == MAX_DPLL_WAIT_TRIES) { 21611f68120SShawn Guo pr_err("MX5: pll locking failed\n"); 21711f68120SShawn Guo return -EINVAL; 21811f68120SShawn Guo } 21911f68120SShawn Guo 22011f68120SShawn Guo return 0; 22111f68120SShawn Guo } 22211f68120SShawn Guo 22311f68120SShawn Guo static void clk_pllv2_unprepare(struct clk_hw *hw) 22411f68120SShawn Guo { 22511f68120SShawn Guo struct clk_pllv2 *pll = to_clk_pllv2(hw); 22611f68120SShawn Guo u32 reg; 22711f68120SShawn Guo void __iomem *pllbase; 22811f68120SShawn Guo 22911f68120SShawn Guo pllbase = pll->base; 23011f68120SShawn Guo reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; 23111f68120SShawn Guo __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); 23211f68120SShawn Guo } 23311f68120SShawn Guo 234fa1da981SBhumika Goyal static const struct clk_ops clk_pllv2_ops = { 23511f68120SShawn Guo .prepare = clk_pllv2_prepare, 23611f68120SShawn Guo .unprepare = clk_pllv2_unprepare, 23711f68120SShawn Guo .recalc_rate = clk_pllv2_recalc_rate, 23811f68120SShawn Guo .round_rate = clk_pllv2_round_rate, 23911f68120SShawn Guo .set_rate = clk_pllv2_set_rate, 24011f68120SShawn Guo }; 24111f68120SShawn Guo 242*87052383SAbel Vesa struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent, 24311f68120SShawn Guo void __iomem *base) 24411f68120SShawn Guo { 24511f68120SShawn Guo struct clk_pllv2 *pll; 246*87052383SAbel Vesa struct clk_hw *hw; 24711f68120SShawn Guo struct clk_init_data init; 248*87052383SAbel Vesa int ret; 24911f68120SShawn Guo 25011f68120SShawn Guo pll = kzalloc(sizeof(*pll), GFP_KERNEL); 25111f68120SShawn Guo if (!pll) 25211f68120SShawn Guo return ERR_PTR(-ENOMEM); 25311f68120SShawn Guo 25411f68120SShawn Guo pll->base = base; 25511f68120SShawn Guo 25611f68120SShawn Guo init.name = name; 25711f68120SShawn Guo init.ops = &clk_pllv2_ops; 25811f68120SShawn Guo init.flags = 0; 25911f68120SShawn Guo init.parent_names = &parent; 26011f68120SShawn Guo init.num_parents = 1; 26111f68120SShawn Guo 26211f68120SShawn Guo pll->hw.init = &init; 263*87052383SAbel Vesa hw = &pll->hw; 26411f68120SShawn Guo 265*87052383SAbel Vesa ret = clk_hw_register(NULL, hw); 266*87052383SAbel Vesa if (ret) { 26711f68120SShawn Guo kfree(pll); 268*87052383SAbel Vesa return ERR_PTR(ret); 269*87052383SAbel Vesa } 27011f68120SShawn Guo 271*87052383SAbel Vesa return hw; 27211f68120SShawn Guo } 273