1f51b7662SDaniel Vetter /* 2f51b7662SDaniel Vetter * Intel GTT (Graphics Translation Table) routines 3f51b7662SDaniel Vetter * 4f51b7662SDaniel Vetter * Caveat: This driver implements the linux agp interface, but this is far from 5f51b7662SDaniel Vetter * a agp driver! GTT support ended up here for purely historical reasons: The 6f51b7662SDaniel Vetter * old userspace intel graphics drivers needed an interface to map memory into 7f51b7662SDaniel Vetter * the GTT. And the drm provides a default interface for graphic devices sitting 8f51b7662SDaniel Vetter * on an agp port. So it made sense to fake the GTT support as an agp port to 9f51b7662SDaniel Vetter * avoid having to create a new api. 10f51b7662SDaniel Vetter * 11f51b7662SDaniel Vetter * With gem this does not make much sense anymore, just needlessly complicates 12f51b7662SDaniel Vetter * the code. But as long as the old graphics stack is still support, it's stuck 13f51b7662SDaniel Vetter * here. 14f51b7662SDaniel Vetter * 15f51b7662SDaniel Vetter * /fairy-tale-mode off 16f51b7662SDaniel Vetter */ 17f51b7662SDaniel Vetter 18e2404e7cSDaniel Vetter #include <linux/module.h> 19e2404e7cSDaniel Vetter #include <linux/pci.h> 20e2404e7cSDaniel Vetter #include <linux/init.h> 21e2404e7cSDaniel Vetter #include <linux/kernel.h> 22e2404e7cSDaniel Vetter #include <linux/pagemap.h> 23e2404e7cSDaniel Vetter #include <linux/agp_backend.h> 24bdb8b975SChris Wilson #include <linux/delay.h> 25e2404e7cSDaniel Vetter #include <asm/smp.h> 26e2404e7cSDaniel Vetter #include "agp.h" 27e2404e7cSDaniel Vetter #include "intel-agp.h" 280ade6386SDaniel Vetter #include <drm/intel-gtt.h> 29e2404e7cSDaniel Vetter 30f51b7662SDaniel Vetter /* 31f51b7662SDaniel Vetter * If we have Intel graphics, we're not going to have anything other than 32f51b7662SDaniel Vetter * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 33d3f13810SSuresh Siddha * on the Intel IOMMU support (CONFIG_INTEL_IOMMU). 34f51b7662SDaniel Vetter * Only newer chipsets need to bother with this, of course. 35f51b7662SDaniel Vetter */ 36d3f13810SSuresh Siddha #ifdef CONFIG_INTEL_IOMMU 37f51b7662SDaniel Vetter #define USE_PCI_DMA_API 1 380e87d2b0SDaniel Vetter #else 390e87d2b0SDaniel Vetter #define USE_PCI_DMA_API 0 40f51b7662SDaniel Vetter #endif 41f51b7662SDaniel Vetter 421a997ff2SDaniel Vetter struct intel_gtt_driver { 431a997ff2SDaniel Vetter unsigned int gen : 8; 441a997ff2SDaniel Vetter unsigned int is_g33 : 1; 451a997ff2SDaniel Vetter unsigned int is_pineview : 1; 461a997ff2SDaniel Vetter unsigned int is_ironlake : 1; 47100519e2SChris Wilson unsigned int has_pgtbl_enable : 1; 4822533b49SDaniel Vetter unsigned int dma_mask_size : 8; 4973800422SDaniel Vetter /* Chipset specific GTT setup */ 5073800422SDaniel Vetter int (*setup)(void); 51ae83dd5cSDaniel Vetter /* This should undo anything done in ->setup() save the unmapping 52ae83dd5cSDaniel Vetter * of the mmio register file, that's done in the generic code. */ 53ae83dd5cSDaniel Vetter void (*cleanup)(void); 54351bb278SDaniel Vetter void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); 55351bb278SDaniel Vetter /* Flags is a more or less chipset specific opaque value. 56351bb278SDaniel Vetter * For chipsets that need to support old ums (non-gem) code, this 57351bb278SDaniel Vetter * needs to be identical to the various supported agp memory types! */ 585cbecafcSDaniel Vetter bool (*check_flags)(unsigned int flags); 591b263f24SDaniel Vetter void (*chipset_flush)(void); 601a997ff2SDaniel Vetter }; 611a997ff2SDaniel Vetter 62f51b7662SDaniel Vetter static struct _intel_private { 631a997ff2SDaniel Vetter const struct intel_gtt_driver *driver; 64f51b7662SDaniel Vetter struct pci_dev *pcidev; /* device one */ 65d7cca2f7SDaniel Vetter struct pci_dev *bridge_dev; 66f51b7662SDaniel Vetter u8 __iomem *registers; 675acc4ce4SBjorn Helgaas phys_addr_t gtt_phys_addr; 68b3eafc5aSDaniel Vetter u32 PGETBL_save; 69f51b7662SDaniel Vetter u32 __iomem *gtt; /* I915G */ 70bee4a186SChris Wilson bool clear_fake_agp; /* on first access via agp, fill with scratch */ 71f51b7662SDaniel Vetter int num_dcache_entries; 72f51b7662SDaniel Vetter void __iomem *i9xx_flush_page; 73820647b9SDaniel Vetter char *i81x_gtt_table; 74f51b7662SDaniel Vetter struct resource ifp_resource; 75f51b7662SDaniel Vetter int resource_valid; 760e87d2b0SDaniel Vetter struct page *scratch_page; 779c61a32dSBen Widawsky phys_addr_t scratch_page_dma; 7814be93ddSDaniel Vetter int refcount; 798d2e6308SBen Widawsky /* Whether i915 needs to use the dmar apis or not. */ 808d2e6308SBen Widawsky unsigned int needs_dmar : 1; 81e5c65377SBen Widawsky phys_addr_t gma_bus_addr; 82a54c0c27SBen Widawsky /* Size of memory reserved for graphics by the BIOS */ 83a54c0c27SBen Widawsky unsigned int stolen_size; 84a54c0c27SBen Widawsky /* Total number of gtt entries. */ 85a54c0c27SBen Widawsky unsigned int gtt_total_entries; 86a54c0c27SBen Widawsky /* Part of the gtt that is mappable by the cpu, for those chips where 87a54c0c27SBen Widawsky * this is not the full gtt. */ 88a54c0c27SBen Widawsky unsigned int gtt_mappable_entries; 89f51b7662SDaniel Vetter } intel_private; 90f51b7662SDaniel Vetter 911a997ff2SDaniel Vetter #define INTEL_GTT_GEN intel_private.driver->gen 921a997ff2SDaniel Vetter #define IS_G33 intel_private.driver->is_g33 931a997ff2SDaniel Vetter #define IS_PINEVIEW intel_private.driver->is_pineview 941a997ff2SDaniel Vetter #define IS_IRONLAKE intel_private.driver->is_ironlake 95100519e2SChris Wilson #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable 961a997ff2SDaniel Vetter 979da3da66SChris Wilson static int intel_gtt_map_memory(struct page **pages, 989da3da66SChris Wilson unsigned int num_entries, 999da3da66SChris Wilson struct sg_table *st) 100f51b7662SDaniel Vetter { 101f51b7662SDaniel Vetter struct scatterlist *sg; 102f51b7662SDaniel Vetter int i; 103f51b7662SDaniel Vetter 1044080775bSDaniel Vetter DBG("try mapping %lu pages\n", (unsigned long)num_entries); 105f51b7662SDaniel Vetter 1069da3da66SChris Wilson if (sg_alloc_table(st, num_entries, GFP_KERNEL)) 107831cd445SChris Wilson goto err; 108f51b7662SDaniel Vetter 1099da3da66SChris Wilson for_each_sg(st->sgl, sg, num_entries, i) 1104080775bSDaniel Vetter sg_set_page(sg, pages[i], PAGE_SIZE, 0); 111f51b7662SDaniel Vetter 1129da3da66SChris Wilson if (!pci_map_sg(intel_private.pcidev, 1139da3da66SChris Wilson st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL)) 114831cd445SChris Wilson goto err; 115831cd445SChris Wilson 116f51b7662SDaniel Vetter return 0; 117831cd445SChris Wilson 118831cd445SChris Wilson err: 1199da3da66SChris Wilson sg_free_table(st); 120831cd445SChris Wilson return -ENOMEM; 121f51b7662SDaniel Vetter } 122f51b7662SDaniel Vetter 1239da3da66SChris Wilson static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) 124f51b7662SDaniel Vetter { 1254080775bSDaniel Vetter struct sg_table st; 126f51b7662SDaniel Vetter DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 127f51b7662SDaniel Vetter 1284080775bSDaniel Vetter pci_unmap_sg(intel_private.pcidev, sg_list, 1294080775bSDaniel Vetter num_sg, PCI_DMA_BIDIRECTIONAL); 1304080775bSDaniel Vetter 1314080775bSDaniel Vetter st.sgl = sg_list; 1324080775bSDaniel Vetter st.orig_nents = st.nents = num_sg; 1334080775bSDaniel Vetter 1344080775bSDaniel Vetter sg_free_table(&st); 135f51b7662SDaniel Vetter } 136f51b7662SDaniel Vetter 137ffdd7510SDaniel Vetter static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) 138f51b7662SDaniel Vetter { 139f51b7662SDaniel Vetter return; 140f51b7662SDaniel Vetter } 141f51b7662SDaniel Vetter 142f51b7662SDaniel Vetter /* Exists to support ARGB cursors */ 143f51b7662SDaniel Vetter static struct page *i8xx_alloc_pages(void) 144f51b7662SDaniel Vetter { 145f51b7662SDaniel Vetter struct page *page; 146f51b7662SDaniel Vetter 147f51b7662SDaniel Vetter page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 148f51b7662SDaniel Vetter if (page == NULL) 149f51b7662SDaniel Vetter return NULL; 150f51b7662SDaniel Vetter 151f51b7662SDaniel Vetter if (set_pages_uc(page, 4) < 0) { 152f51b7662SDaniel Vetter set_pages_wb(page, 4); 153f51b7662SDaniel Vetter __free_pages(page, 2); 154f51b7662SDaniel Vetter return NULL; 155f51b7662SDaniel Vetter } 156f51b7662SDaniel Vetter get_page(page); 157f51b7662SDaniel Vetter atomic_inc(&agp_bridge->current_memory_agp); 158f51b7662SDaniel Vetter return page; 159f51b7662SDaniel Vetter } 160f51b7662SDaniel Vetter 161f51b7662SDaniel Vetter static void i8xx_destroy_pages(struct page *page) 162f51b7662SDaniel Vetter { 163f51b7662SDaniel Vetter if (page == NULL) 164f51b7662SDaniel Vetter return; 165f51b7662SDaniel Vetter 166f51b7662SDaniel Vetter set_pages_wb(page, 4); 167f51b7662SDaniel Vetter put_page(page); 168f51b7662SDaniel Vetter __free_pages(page, 2); 169f51b7662SDaniel Vetter atomic_dec(&agp_bridge->current_memory_agp); 170f51b7662SDaniel Vetter } 171f51b7662SDaniel Vetter 172820647b9SDaniel Vetter #define I810_GTT_ORDER 4 173820647b9SDaniel Vetter static int i810_setup(void) 174820647b9SDaniel Vetter { 175*d3572532SBjorn Helgaas phys_addr_t reg_addr; 176820647b9SDaniel Vetter char *gtt_table; 177820647b9SDaniel Vetter 178820647b9SDaniel Vetter /* i81x does not preallocate the gtt. It's always 64kb in size. */ 179820647b9SDaniel Vetter gtt_table = alloc_gatt_pages(I810_GTT_ORDER); 180820647b9SDaniel Vetter if (gtt_table == NULL) 181820647b9SDaniel Vetter return -ENOMEM; 182820647b9SDaniel Vetter intel_private.i81x_gtt_table = gtt_table; 183820647b9SDaniel Vetter 184*d3572532SBjorn Helgaas reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); 185820647b9SDaniel Vetter 186820647b9SDaniel Vetter intel_private.registers = ioremap(reg_addr, KB(64)); 187820647b9SDaniel Vetter if (!intel_private.registers) 188820647b9SDaniel Vetter return -ENOMEM; 189820647b9SDaniel Vetter 190820647b9SDaniel Vetter writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, 191820647b9SDaniel Vetter intel_private.registers+I810_PGETBL_CTL); 192820647b9SDaniel Vetter 1935acc4ce4SBjorn Helgaas intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; 194820647b9SDaniel Vetter 195820647b9SDaniel Vetter if ((readl(intel_private.registers+I810_DRAM_CTL) 196820647b9SDaniel Vetter & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 197820647b9SDaniel Vetter dev_info(&intel_private.pcidev->dev, 198820647b9SDaniel Vetter "detected 4MB dedicated video ram\n"); 199820647b9SDaniel Vetter intel_private.num_dcache_entries = 1024; 200820647b9SDaniel Vetter } 201820647b9SDaniel Vetter 202820647b9SDaniel Vetter return 0; 203820647b9SDaniel Vetter } 204820647b9SDaniel Vetter 205820647b9SDaniel Vetter static void i810_cleanup(void) 206820647b9SDaniel Vetter { 207820647b9SDaniel Vetter writel(0, intel_private.registers+I810_PGETBL_CTL); 208820647b9SDaniel Vetter free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); 209820647b9SDaniel Vetter } 210820647b9SDaniel Vetter 211ff26860fSDaniel Vetter static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, 212f51b7662SDaniel Vetter int type) 213f51b7662SDaniel Vetter { 214f51b7662SDaniel Vetter int i; 215f51b7662SDaniel Vetter 216625dd9d3SDaniel Vetter if ((pg_start + mem->page_count) 217625dd9d3SDaniel Vetter > intel_private.num_dcache_entries) 218625dd9d3SDaniel Vetter return -EINVAL; 219f51b7662SDaniel Vetter 220625dd9d3SDaniel Vetter if (!mem->is_flushed) 221625dd9d3SDaniel Vetter global_cache_flush(); 222625dd9d3SDaniel Vetter 223625dd9d3SDaniel Vetter for (i = pg_start; i < (pg_start + mem->page_count); i++) { 224625dd9d3SDaniel Vetter dma_addr_t addr = i << PAGE_SHIFT; 225625dd9d3SDaniel Vetter intel_private.driver->write_entry(addr, 226625dd9d3SDaniel Vetter i, type); 227f51b7662SDaniel Vetter } 228625dd9d3SDaniel Vetter readl(intel_private.gtt+i-1); 229f51b7662SDaniel Vetter 230f51b7662SDaniel Vetter return 0; 231f51b7662SDaniel Vetter } 232f51b7662SDaniel Vetter 233f51b7662SDaniel Vetter /* 234f51b7662SDaniel Vetter * The i810/i830 requires a physical address to program its mouse 235f51b7662SDaniel Vetter * pointer into hardware. 236f51b7662SDaniel Vetter * However the Xserver still writes to it through the agp aperture. 237f51b7662SDaniel Vetter */ 238f51b7662SDaniel Vetter static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 239f51b7662SDaniel Vetter { 240f51b7662SDaniel Vetter struct agp_memory *new; 241f51b7662SDaniel Vetter struct page *page; 242f51b7662SDaniel Vetter 243f51b7662SDaniel Vetter switch (pg_count) { 244f51b7662SDaniel Vetter case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 245f51b7662SDaniel Vetter break; 246f51b7662SDaniel Vetter case 4: 247f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 248f51b7662SDaniel Vetter page = i8xx_alloc_pages(); 249f51b7662SDaniel Vetter break; 250f51b7662SDaniel Vetter default: 251f51b7662SDaniel Vetter return NULL; 252f51b7662SDaniel Vetter } 253f51b7662SDaniel Vetter 254f51b7662SDaniel Vetter if (page == NULL) 255f51b7662SDaniel Vetter return NULL; 256f51b7662SDaniel Vetter 257f51b7662SDaniel Vetter new = agp_create_memory(pg_count); 258f51b7662SDaniel Vetter if (new == NULL) 259f51b7662SDaniel Vetter return NULL; 260f51b7662SDaniel Vetter 261f51b7662SDaniel Vetter new->pages[0] = page; 262f51b7662SDaniel Vetter if (pg_count == 4) { 263f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 264f51b7662SDaniel Vetter new->pages[1] = new->pages[0] + 1; 265f51b7662SDaniel Vetter new->pages[2] = new->pages[1] + 1; 266f51b7662SDaniel Vetter new->pages[3] = new->pages[2] + 1; 267f51b7662SDaniel Vetter } 268f51b7662SDaniel Vetter new->page_count = pg_count; 269f51b7662SDaniel Vetter new->num_scratch_pages = pg_count; 270f51b7662SDaniel Vetter new->type = AGP_PHYS_MEMORY; 271f51b7662SDaniel Vetter new->physical = page_to_phys(new->pages[0]); 272f51b7662SDaniel Vetter return new; 273f51b7662SDaniel Vetter } 274f51b7662SDaniel Vetter 275f51b7662SDaniel Vetter static void intel_i810_free_by_type(struct agp_memory *curr) 276f51b7662SDaniel Vetter { 277f51b7662SDaniel Vetter agp_free_key(curr->key); 278f51b7662SDaniel Vetter if (curr->type == AGP_PHYS_MEMORY) { 279f51b7662SDaniel Vetter if (curr->page_count == 4) 280f51b7662SDaniel Vetter i8xx_destroy_pages(curr->pages[0]); 281f51b7662SDaniel Vetter else { 282f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 283f51b7662SDaniel Vetter AGP_PAGE_DESTROY_UNMAP); 284f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 285f51b7662SDaniel Vetter AGP_PAGE_DESTROY_FREE); 286f51b7662SDaniel Vetter } 287f51b7662SDaniel Vetter agp_free_page_array(curr); 288f51b7662SDaniel Vetter } 289f51b7662SDaniel Vetter kfree(curr); 290f51b7662SDaniel Vetter } 291f51b7662SDaniel Vetter 2920e87d2b0SDaniel Vetter static int intel_gtt_setup_scratch_page(void) 2930e87d2b0SDaniel Vetter { 2940e87d2b0SDaniel Vetter struct page *page; 2950e87d2b0SDaniel Vetter dma_addr_t dma_addr; 2960e87d2b0SDaniel Vetter 2970e87d2b0SDaniel Vetter page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); 2980e87d2b0SDaniel Vetter if (page == NULL) 2990e87d2b0SDaniel Vetter return -ENOMEM; 3000e87d2b0SDaniel Vetter get_page(page); 3010e87d2b0SDaniel Vetter set_pages_uc(page, 1); 3020e87d2b0SDaniel Vetter 3038d2e6308SBen Widawsky if (intel_private.needs_dmar) { 3040e87d2b0SDaniel Vetter dma_addr = pci_map_page(intel_private.pcidev, page, 0, 3050e87d2b0SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 3060e87d2b0SDaniel Vetter if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) 3070e87d2b0SDaniel Vetter return -EINVAL; 3080e87d2b0SDaniel Vetter 3099c61a32dSBen Widawsky intel_private.scratch_page_dma = dma_addr; 3100e87d2b0SDaniel Vetter } else 3119c61a32dSBen Widawsky intel_private.scratch_page_dma = page_to_phys(page); 3120e87d2b0SDaniel Vetter 3130e87d2b0SDaniel Vetter intel_private.scratch_page = page; 3140e87d2b0SDaniel Vetter 3150e87d2b0SDaniel Vetter return 0; 3160e87d2b0SDaniel Vetter } 3170e87d2b0SDaniel Vetter 318625dd9d3SDaniel Vetter static void i810_write_entry(dma_addr_t addr, unsigned int entry, 319625dd9d3SDaniel Vetter unsigned int flags) 320625dd9d3SDaniel Vetter { 321625dd9d3SDaniel Vetter u32 pte_flags = I810_PTE_VALID; 322625dd9d3SDaniel Vetter 323625dd9d3SDaniel Vetter switch (flags) { 324625dd9d3SDaniel Vetter case AGP_DCACHE_MEMORY: 325625dd9d3SDaniel Vetter pte_flags |= I810_PTE_LOCAL; 326625dd9d3SDaniel Vetter break; 327625dd9d3SDaniel Vetter case AGP_USER_CACHED_MEMORY: 328625dd9d3SDaniel Vetter pte_flags |= I830_PTE_SYSTEM_CACHED; 329625dd9d3SDaniel Vetter break; 330625dd9d3SDaniel Vetter } 331625dd9d3SDaniel Vetter 332625dd9d3SDaniel Vetter writel(addr | pte_flags, intel_private.gtt + entry); 333625dd9d3SDaniel Vetter } 334625dd9d3SDaniel Vetter 3357bdc9ab0SChris Wilson static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { 336820647b9SDaniel Vetter {32, 8192, 3}, 337820647b9SDaniel Vetter {64, 16384, 4}, 338f51b7662SDaniel Vetter {128, 32768, 5}, 339f51b7662SDaniel Vetter {256, 65536, 6}, 340f51b7662SDaniel Vetter {512, 131072, 7}, 341f51b7662SDaniel Vetter }; 342f51b7662SDaniel Vetter 343c64f7ba5SChris Wilson static unsigned int intel_gtt_stolen_size(void) 344f51b7662SDaniel Vetter { 345f51b7662SDaniel Vetter u16 gmch_ctrl; 346f51b7662SDaniel Vetter u8 rdct; 347f51b7662SDaniel Vetter int local = 0; 348f51b7662SDaniel Vetter static const int ddt[4] = { 0, 16, 32, 64 }; 349d8d9abcdSDaniel Vetter unsigned int stolen_size = 0; 350f51b7662SDaniel Vetter 351820647b9SDaniel Vetter if (INTEL_GTT_GEN == 1) 352820647b9SDaniel Vetter return 0; /* no stolen mem on i81x */ 353820647b9SDaniel Vetter 354d7cca2f7SDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 355d7cca2f7SDaniel Vetter I830_GMCH_CTRL, &gmch_ctrl); 356f51b7662SDaniel Vetter 357d7cca2f7SDaniel Vetter if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 358d7cca2f7SDaniel Vetter intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 359f51b7662SDaniel Vetter switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 360f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_512: 361d8d9abcdSDaniel Vetter stolen_size = KB(512); 362f51b7662SDaniel Vetter break; 363f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_1024: 364d8d9abcdSDaniel Vetter stolen_size = MB(1); 365f51b7662SDaniel Vetter break; 366f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_8192: 367d8d9abcdSDaniel Vetter stolen_size = MB(8); 368f51b7662SDaniel Vetter break; 369f51b7662SDaniel Vetter case I830_GMCH_GMS_LOCAL: 370f51b7662SDaniel Vetter rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 371d8d9abcdSDaniel Vetter stolen_size = (I830_RDRAM_ND(rdct) + 1) * 372f51b7662SDaniel Vetter MB(ddt[I830_RDRAM_DDT(rdct)]); 373f51b7662SDaniel Vetter local = 1; 374f51b7662SDaniel Vetter break; 375f51b7662SDaniel Vetter default: 376d8d9abcdSDaniel Vetter stolen_size = 0; 377f51b7662SDaniel Vetter break; 378f51b7662SDaniel Vetter } 379f51b7662SDaniel Vetter } else { 380f51b7662SDaniel Vetter switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 381f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_1M: 382d8d9abcdSDaniel Vetter stolen_size = MB(1); 383f51b7662SDaniel Vetter break; 384f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_4M: 385d8d9abcdSDaniel Vetter stolen_size = MB(4); 386f51b7662SDaniel Vetter break; 387f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_8M: 388d8d9abcdSDaniel Vetter stolen_size = MB(8); 389f51b7662SDaniel Vetter break; 390f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_16M: 391d8d9abcdSDaniel Vetter stolen_size = MB(16); 392f51b7662SDaniel Vetter break; 393f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_32M: 394d8d9abcdSDaniel Vetter stolen_size = MB(32); 395f51b7662SDaniel Vetter break; 396f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_48M: 397d8d9abcdSDaniel Vetter stolen_size = MB(48); 398f51b7662SDaniel Vetter break; 399f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_64M: 400d8d9abcdSDaniel Vetter stolen_size = MB(64); 401f51b7662SDaniel Vetter break; 402f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_128M: 403d8d9abcdSDaniel Vetter stolen_size = MB(128); 404f51b7662SDaniel Vetter break; 405f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_256M: 406d8d9abcdSDaniel Vetter stolen_size = MB(256); 407f51b7662SDaniel Vetter break; 408f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_96M: 409d8d9abcdSDaniel Vetter stolen_size = MB(96); 410f51b7662SDaniel Vetter break; 411f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_160M: 412d8d9abcdSDaniel Vetter stolen_size = MB(160); 413f51b7662SDaniel Vetter break; 414f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_224M: 415d8d9abcdSDaniel Vetter stolen_size = MB(224); 416f51b7662SDaniel Vetter break; 417f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_352M: 418d8d9abcdSDaniel Vetter stolen_size = MB(352); 419f51b7662SDaniel Vetter break; 420f51b7662SDaniel Vetter default: 421d8d9abcdSDaniel Vetter stolen_size = 0; 422f51b7662SDaniel Vetter break; 423f51b7662SDaniel Vetter } 424f51b7662SDaniel Vetter } 4251784a5fbSDaniel Vetter 4261b6064d7SChris Wilson if (stolen_size > 0) { 427d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", 428d8d9abcdSDaniel Vetter stolen_size / KB(1), local ? "local" : "stolen"); 429f51b7662SDaniel Vetter } else { 430d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, 431f51b7662SDaniel Vetter "no pre-allocated video memory detected\n"); 432d8d9abcdSDaniel Vetter stolen_size = 0; 433f51b7662SDaniel Vetter } 434f51b7662SDaniel Vetter 435c64f7ba5SChris Wilson return stolen_size; 436f51b7662SDaniel Vetter } 437f51b7662SDaniel Vetter 43820172842SDaniel Vetter static void i965_adjust_pgetbl_size(unsigned int size_flag) 43920172842SDaniel Vetter { 44020172842SDaniel Vetter u32 pgetbl_ctl, pgetbl_ctl2; 44120172842SDaniel Vetter 44220172842SDaniel Vetter /* ensure that ppgtt is disabled */ 44320172842SDaniel Vetter pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); 44420172842SDaniel Vetter pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; 44520172842SDaniel Vetter writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); 44620172842SDaniel Vetter 44720172842SDaniel Vetter /* write the new ggtt size */ 44820172842SDaniel Vetter pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 44920172842SDaniel Vetter pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; 45020172842SDaniel Vetter pgetbl_ctl |= size_flag; 45120172842SDaniel Vetter writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); 45220172842SDaniel Vetter } 45320172842SDaniel Vetter 45420172842SDaniel Vetter static unsigned int i965_gtt_total_entries(void) 455fbe40783SDaniel Vetter { 456fbe40783SDaniel Vetter int size; 457fbe40783SDaniel Vetter u32 pgetbl_ctl; 45820172842SDaniel Vetter u16 gmch_ctl; 45920172842SDaniel Vetter 46020172842SDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 46120172842SDaniel Vetter I830_GMCH_CTRL, &gmch_ctl); 46220172842SDaniel Vetter 46320172842SDaniel Vetter if (INTEL_GTT_GEN == 5) { 46420172842SDaniel Vetter switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { 46520172842SDaniel Vetter case G4x_GMCH_SIZE_1M: 46620172842SDaniel Vetter case G4x_GMCH_SIZE_VT_1M: 46720172842SDaniel Vetter i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); 46820172842SDaniel Vetter break; 46920172842SDaniel Vetter case G4x_GMCH_SIZE_VT_1_5M: 47020172842SDaniel Vetter i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); 47120172842SDaniel Vetter break; 47220172842SDaniel Vetter case G4x_GMCH_SIZE_2M: 47320172842SDaniel Vetter case G4x_GMCH_SIZE_VT_2M: 47420172842SDaniel Vetter i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); 47520172842SDaniel Vetter break; 47620172842SDaniel Vetter } 47720172842SDaniel Vetter } 47820172842SDaniel Vetter 479fbe40783SDaniel Vetter pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 480fbe40783SDaniel Vetter 481fbe40783SDaniel Vetter switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 482fbe40783SDaniel Vetter case I965_PGETBL_SIZE_128KB: 483e5e408fcSDaniel Vetter size = KB(128); 484fbe40783SDaniel Vetter break; 485fbe40783SDaniel Vetter case I965_PGETBL_SIZE_256KB: 486e5e408fcSDaniel Vetter size = KB(256); 487fbe40783SDaniel Vetter break; 488fbe40783SDaniel Vetter case I965_PGETBL_SIZE_512KB: 489e5e408fcSDaniel Vetter size = KB(512); 490fbe40783SDaniel Vetter break; 49120172842SDaniel Vetter /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ 492fbe40783SDaniel Vetter case I965_PGETBL_SIZE_1MB: 493e5e408fcSDaniel Vetter size = KB(1024); 494fbe40783SDaniel Vetter break; 495fbe40783SDaniel Vetter case I965_PGETBL_SIZE_2MB: 496e5e408fcSDaniel Vetter size = KB(2048); 497fbe40783SDaniel Vetter break; 498fbe40783SDaniel Vetter case I965_PGETBL_SIZE_1_5MB: 499e5e408fcSDaniel Vetter size = KB(1024 + 512); 500fbe40783SDaniel Vetter break; 501fbe40783SDaniel Vetter default: 502fbe40783SDaniel Vetter dev_info(&intel_private.pcidev->dev, 503fbe40783SDaniel Vetter "unknown page table size, assuming 512KB\n"); 504e5e408fcSDaniel Vetter size = KB(512); 505fbe40783SDaniel Vetter } 506e5e408fcSDaniel Vetter 507e5e408fcSDaniel Vetter return size/4; 50820172842SDaniel Vetter } 50920172842SDaniel Vetter 51020172842SDaniel Vetter static unsigned int intel_gtt_total_entries(void) 51120172842SDaniel Vetter { 51220172842SDaniel Vetter if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) 51320172842SDaniel Vetter return i965_gtt_total_entries(); 514009946f8SBen Widawsky else { 515fbe40783SDaniel Vetter /* On previous hardware, the GTT size was just what was 516fbe40783SDaniel Vetter * required to map the aperture. 517fbe40783SDaniel Vetter */ 518a54c0c27SBen Widawsky return intel_private.gtt_mappable_entries; 519fbe40783SDaniel Vetter } 520fbe40783SDaniel Vetter } 521fbe40783SDaniel Vetter 5221784a5fbSDaniel Vetter static unsigned int intel_gtt_mappable_entries(void) 5231784a5fbSDaniel Vetter { 5241784a5fbSDaniel Vetter unsigned int aperture_size; 5251784a5fbSDaniel Vetter 526820647b9SDaniel Vetter if (INTEL_GTT_GEN == 1) { 527820647b9SDaniel Vetter u32 smram_miscc; 528820647b9SDaniel Vetter 529820647b9SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, 530820647b9SDaniel Vetter I810_SMRAM_MISCC, &smram_miscc); 531820647b9SDaniel Vetter 532820647b9SDaniel Vetter if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) 533820647b9SDaniel Vetter == I810_GFX_MEM_WIN_32M) 534820647b9SDaniel Vetter aperture_size = MB(32); 535820647b9SDaniel Vetter else 536820647b9SDaniel Vetter aperture_size = MB(64); 537820647b9SDaniel Vetter } else if (INTEL_GTT_GEN == 2) { 538b1c5b0f8SChris Wilson u16 gmch_ctrl; 5391784a5fbSDaniel Vetter 5401784a5fbSDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 5411784a5fbSDaniel Vetter I830_GMCH_CTRL, &gmch_ctrl); 5421784a5fbSDaniel Vetter 5431784a5fbSDaniel Vetter if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) 544b1c5b0f8SChris Wilson aperture_size = MB(64); 5451784a5fbSDaniel Vetter else 546b1c5b0f8SChris Wilson aperture_size = MB(128); 547239918f7SDaniel Vetter } else { 5481784a5fbSDaniel Vetter /* 9xx supports large sizes, just look at the length */ 5491784a5fbSDaniel Vetter aperture_size = pci_resource_len(intel_private.pcidev, 2); 5501784a5fbSDaniel Vetter } 5511784a5fbSDaniel Vetter 5521784a5fbSDaniel Vetter return aperture_size >> PAGE_SHIFT; 5531784a5fbSDaniel Vetter } 5541784a5fbSDaniel Vetter 5550e87d2b0SDaniel Vetter static void intel_gtt_teardown_scratch_page(void) 5560e87d2b0SDaniel Vetter { 5570e87d2b0SDaniel Vetter set_pages_wb(intel_private.scratch_page, 1); 5589c61a32dSBen Widawsky pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, 5590e87d2b0SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 5600e87d2b0SDaniel Vetter put_page(intel_private.scratch_page); 5610e87d2b0SDaniel Vetter __free_page(intel_private.scratch_page); 5620e87d2b0SDaniel Vetter } 5630e87d2b0SDaniel Vetter 5640e87d2b0SDaniel Vetter static void intel_gtt_cleanup(void) 5650e87d2b0SDaniel Vetter { 566ae83dd5cSDaniel Vetter intel_private.driver->cleanup(); 567ae83dd5cSDaniel Vetter 5680e87d2b0SDaniel Vetter iounmap(intel_private.gtt); 5690e87d2b0SDaniel Vetter iounmap(intel_private.registers); 5700e87d2b0SDaniel Vetter 5710e87d2b0SDaniel Vetter intel_gtt_teardown_scratch_page(); 5720e87d2b0SDaniel Vetter } 5730e87d2b0SDaniel Vetter 574da88a5f7SChris Wilson /* Certain Gen5 chipsets require require idling the GPU before 575da88a5f7SChris Wilson * unmapping anything from the GTT when VT-d is enabled. 576da88a5f7SChris Wilson */ 577da88a5f7SChris Wilson static inline int needs_ilk_vtd_wa(void) 578da88a5f7SChris Wilson { 579da88a5f7SChris Wilson #ifdef CONFIG_INTEL_IOMMU 580da88a5f7SChris Wilson const unsigned short gpu_devid = intel_private.pcidev->device; 581da88a5f7SChris Wilson 582da88a5f7SChris Wilson /* Query intel_iommu to see if we need the workaround. Presumably that 583da88a5f7SChris Wilson * was loaded first. 584da88a5f7SChris Wilson */ 585da88a5f7SChris Wilson if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || 586da88a5f7SChris Wilson gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) && 587da88a5f7SChris Wilson intel_iommu_gfx_mapped) 588da88a5f7SChris Wilson return 1; 589da88a5f7SChris Wilson #endif 590da88a5f7SChris Wilson return 0; 591da88a5f7SChris Wilson } 592da88a5f7SChris Wilson 593da88a5f7SChris Wilson static bool intel_gtt_can_wc(void) 594da88a5f7SChris Wilson { 595da88a5f7SChris Wilson if (INTEL_GTT_GEN <= 2) 596da88a5f7SChris Wilson return false; 597da88a5f7SChris Wilson 598da88a5f7SChris Wilson if (INTEL_GTT_GEN >= 6) 599da88a5f7SChris Wilson return false; 600da88a5f7SChris Wilson 601da88a5f7SChris Wilson /* Reports of major corruption with ILK vt'd enabled */ 602da88a5f7SChris Wilson if (needs_ilk_vtd_wa()) 603da88a5f7SChris Wilson return false; 604da88a5f7SChris Wilson 605da88a5f7SChris Wilson return true; 606da88a5f7SChris Wilson } 607da88a5f7SChris Wilson 6081784a5fbSDaniel Vetter static int intel_gtt_init(void) 6091784a5fbSDaniel Vetter { 610f67eab66SDaniel Vetter u32 gtt_map_size; 611545b0a74SYinghai Lu int ret, bar; 6123b15a9d7SDaniel Vetter 6133b15a9d7SDaniel Vetter ret = intel_private.driver->setup(); 6143b15a9d7SDaniel Vetter if (ret != 0) 6153b15a9d7SDaniel Vetter return ret; 616f67eab66SDaniel Vetter 617a54c0c27SBen Widawsky intel_private.gtt_mappable_entries = intel_gtt_mappable_entries(); 618a54c0c27SBen Widawsky intel_private.gtt_total_entries = intel_gtt_total_entries(); 619f67eab66SDaniel Vetter 620b3eafc5aSDaniel Vetter /* save the PGETBL reg for resume */ 621b3eafc5aSDaniel Vetter intel_private.PGETBL_save = 622b3eafc5aSDaniel Vetter readl(intel_private.registers+I810_PGETBL_CTL) 623b3eafc5aSDaniel Vetter & ~I810_PGETBL_ENABLED; 624100519e2SChris Wilson /* we only ever restore the register when enabling the PGTBL... */ 625100519e2SChris Wilson if (HAS_PGTBL_EN) 626100519e2SChris Wilson intel_private.PGETBL_save |= I810_PGETBL_ENABLED; 627b3eafc5aSDaniel Vetter 6280af9e92eSDaniel Vetter dev_info(&intel_private.bridge_dev->dev, 6290af9e92eSDaniel Vetter "detected gtt size: %dK total, %dK mappable\n", 630a54c0c27SBen Widawsky intel_private.gtt_total_entries * 4, 631a54c0c27SBen Widawsky intel_private.gtt_mappable_entries * 4); 6320af9e92eSDaniel Vetter 633a54c0c27SBen Widawsky gtt_map_size = intel_private.gtt_total_entries * 4; 634f67eab66SDaniel Vetter 635edef7e68SChris Wilson intel_private.gtt = NULL; 636da88a5f7SChris Wilson if (intel_gtt_can_wc()) 6375acc4ce4SBjorn Helgaas intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr, 638edef7e68SChris Wilson gtt_map_size); 639edef7e68SChris Wilson if (intel_private.gtt == NULL) 6405acc4ce4SBjorn Helgaas intel_private.gtt = ioremap(intel_private.gtt_phys_addr, 641f67eab66SDaniel Vetter gtt_map_size); 642edef7e68SChris Wilson if (intel_private.gtt == NULL) { 643ae83dd5cSDaniel Vetter intel_private.driver->cleanup(); 644f67eab66SDaniel Vetter iounmap(intel_private.registers); 645f67eab66SDaniel Vetter return -ENOMEM; 646f67eab66SDaniel Vetter } 647f67eab66SDaniel Vetter 648f67eab66SDaniel Vetter global_cache_flush(); /* FIXME: ? */ 649f67eab66SDaniel Vetter 650a54c0c27SBen Widawsky intel_private.stolen_size = intel_gtt_stolen_size(); 6511784a5fbSDaniel Vetter 6528d2e6308SBen Widawsky intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; 653a46f3108SDave Airlie 6540e87d2b0SDaniel Vetter ret = intel_gtt_setup_scratch_page(); 6550e87d2b0SDaniel Vetter if (ret != 0) { 6560e87d2b0SDaniel Vetter intel_gtt_cleanup(); 6570e87d2b0SDaniel Vetter return ret; 6580e87d2b0SDaniel Vetter } 6590e87d2b0SDaniel Vetter 66032e3cd6eSDaniel Vetter if (INTEL_GTT_GEN <= 2) 661545b0a74SYinghai Lu bar = I810_GMADR_BAR; 66232e3cd6eSDaniel Vetter else 663545b0a74SYinghai Lu bar = I915_GMADR_BAR; 66432e3cd6eSDaniel Vetter 665545b0a74SYinghai Lu intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar); 6661784a5fbSDaniel Vetter return 0; 6671784a5fbSDaniel Vetter } 6681784a5fbSDaniel Vetter 6693e921f98SDaniel Vetter static int intel_fake_agp_fetch_size(void) 6703e921f98SDaniel Vetter { 6719e76e7b8SChris Wilson int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); 6723e921f98SDaniel Vetter unsigned int aper_size; 6733e921f98SDaniel Vetter int i; 6743e921f98SDaniel Vetter 675a54c0c27SBen Widawsky aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1); 6763e921f98SDaniel Vetter 6773e921f98SDaniel Vetter for (i = 0; i < num_sizes; i++) { 678ffdd7510SDaniel Vetter if (aper_size == intel_fake_agp_sizes[i].size) { 6799e76e7b8SChris Wilson agp_bridge->current_size = 6809e76e7b8SChris Wilson (void *) (intel_fake_agp_sizes + i); 6813e921f98SDaniel Vetter return aper_size; 6823e921f98SDaniel Vetter } 6833e921f98SDaniel Vetter } 6843e921f98SDaniel Vetter 6853e921f98SDaniel Vetter return 0; 6863e921f98SDaniel Vetter } 6873e921f98SDaniel Vetter 688ae83dd5cSDaniel Vetter static void i830_cleanup(void) 689f51b7662SDaniel Vetter { 690f51b7662SDaniel Vetter } 691f51b7662SDaniel Vetter 692f51b7662SDaniel Vetter /* The chipset_flush interface needs to get data that has already been 693f51b7662SDaniel Vetter * flushed out of the CPU all the way out to main memory, because the GPU 694f51b7662SDaniel Vetter * doesn't snoop those buffers. 695f51b7662SDaniel Vetter * 696f51b7662SDaniel Vetter * The 8xx series doesn't have the same lovely interface for flushing the 697f51b7662SDaniel Vetter * chipset write buffers that the later chips do. According to the 865 698f51b7662SDaniel Vetter * specs, it's 64 octwords, or 1KB. So, to get those previous things in 699f51b7662SDaniel Vetter * that buffer out, we just fill 1KB and clflush it out, on the assumption 700f51b7662SDaniel Vetter * that it'll push whatever was in there out. It appears to work. 701f51b7662SDaniel Vetter */ 7021b263f24SDaniel Vetter static void i830_chipset_flush(void) 703f51b7662SDaniel Vetter { 704bdb8b975SChris Wilson unsigned long timeout = jiffies + msecs_to_jiffies(1000); 705f51b7662SDaniel Vetter 706bdb8b975SChris Wilson /* Forcibly evict everything from the CPU write buffers. 707bdb8b975SChris Wilson * clflush appears to be insufficient. 708bdb8b975SChris Wilson */ 709bdb8b975SChris Wilson wbinvd_on_all_cpus(); 710f51b7662SDaniel Vetter 711bdb8b975SChris Wilson /* Now we've only seen documents for this magic bit on 855GM, 712bdb8b975SChris Wilson * we hope it exists for the other gen2 chipsets... 713bdb8b975SChris Wilson * 714bdb8b975SChris Wilson * Also works as advertised on my 845G. 715bdb8b975SChris Wilson */ 716bdb8b975SChris Wilson writel(readl(intel_private.registers+I830_HIC) | (1<<31), 717bdb8b975SChris Wilson intel_private.registers+I830_HIC); 718bdb8b975SChris Wilson 719bdb8b975SChris Wilson while (readl(intel_private.registers+I830_HIC) & (1<<31)) { 720bdb8b975SChris Wilson if (time_after(jiffies, timeout)) 721bdb8b975SChris Wilson break; 722bdb8b975SChris Wilson 723bdb8b975SChris Wilson udelay(50); 724bdb8b975SChris Wilson } 725f51b7662SDaniel Vetter } 726f51b7662SDaniel Vetter 727351bb278SDaniel Vetter static void i830_write_entry(dma_addr_t addr, unsigned int entry, 728351bb278SDaniel Vetter unsigned int flags) 729351bb278SDaniel Vetter { 730351bb278SDaniel Vetter u32 pte_flags = I810_PTE_VALID; 731351bb278SDaniel Vetter 732b47cf66fSDaniel Vetter if (flags == AGP_USER_CACHED_MEMORY) 733351bb278SDaniel Vetter pte_flags |= I830_PTE_SYSTEM_CACHED; 734351bb278SDaniel Vetter 735351bb278SDaniel Vetter writel(addr | pte_flags, intel_private.gtt + entry); 736351bb278SDaniel Vetter } 737351bb278SDaniel Vetter 7388ecd1a66SDaniel Vetter bool intel_enable_gtt(void) 73973800422SDaniel Vetter { 740e380f60bSChris Wilson u8 __iomem *reg; 74173800422SDaniel Vetter 742100519e2SChris Wilson if (INTEL_GTT_GEN == 2) { 743100519e2SChris Wilson u16 gmch_ctrl; 744100519e2SChris Wilson 745e380f60bSChris Wilson pci_read_config_word(intel_private.bridge_dev, 746e380f60bSChris Wilson I830_GMCH_CTRL, &gmch_ctrl); 747e380f60bSChris Wilson gmch_ctrl |= I830_GMCH_ENABLED; 748e380f60bSChris Wilson pci_write_config_word(intel_private.bridge_dev, 749e380f60bSChris Wilson I830_GMCH_CTRL, gmch_ctrl); 750e380f60bSChris Wilson 751e380f60bSChris Wilson pci_read_config_word(intel_private.bridge_dev, 752e380f60bSChris Wilson I830_GMCH_CTRL, &gmch_ctrl); 753e380f60bSChris Wilson if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { 754e380f60bSChris Wilson dev_err(&intel_private.pcidev->dev, 755e380f60bSChris Wilson "failed to enable the GTT: GMCH_CTRL=%x\n", 756e380f60bSChris Wilson gmch_ctrl); 757e380f60bSChris Wilson return false; 758e380f60bSChris Wilson } 759100519e2SChris Wilson } 760e380f60bSChris Wilson 761c97689d8SChris Wilson /* On the resume path we may be adjusting the PGTBL value, so 762c97689d8SChris Wilson * be paranoid and flush all chipset write buffers... 763c97689d8SChris Wilson */ 764c97689d8SChris Wilson if (INTEL_GTT_GEN >= 3) 765c97689d8SChris Wilson writel(0, intel_private.registers+GFX_FLSH_CNTL); 766c97689d8SChris Wilson 767e380f60bSChris Wilson reg = intel_private.registers+I810_PGETBL_CTL; 768100519e2SChris Wilson writel(intel_private.PGETBL_save, reg); 769100519e2SChris Wilson if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { 770e380f60bSChris Wilson dev_err(&intel_private.pcidev->dev, 771100519e2SChris Wilson "failed to enable the GTT: PGETBL=%x [expected %x]\n", 772e380f60bSChris Wilson readl(reg), intel_private.PGETBL_save); 773e380f60bSChris Wilson return false; 774e380f60bSChris Wilson } 775e380f60bSChris Wilson 776c97689d8SChris Wilson if (INTEL_GTT_GEN >= 3) 777c97689d8SChris Wilson writel(0, intel_private.registers+GFX_FLSH_CNTL); 778c97689d8SChris Wilson 779e380f60bSChris Wilson return true; 78073800422SDaniel Vetter } 7818ecd1a66SDaniel Vetter EXPORT_SYMBOL(intel_enable_gtt); 78273800422SDaniel Vetter 78373800422SDaniel Vetter static int i830_setup(void) 78473800422SDaniel Vetter { 785*d3572532SBjorn Helgaas phys_addr_t reg_addr; 78673800422SDaniel Vetter 787*d3572532SBjorn Helgaas reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); 78873800422SDaniel Vetter 78973800422SDaniel Vetter intel_private.registers = ioremap(reg_addr, KB(64)); 79073800422SDaniel Vetter if (!intel_private.registers) 79173800422SDaniel Vetter return -ENOMEM; 79273800422SDaniel Vetter 7935acc4ce4SBjorn Helgaas intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; 79473800422SDaniel Vetter 79573800422SDaniel Vetter return 0; 79673800422SDaniel Vetter } 79773800422SDaniel Vetter 7983b15a9d7SDaniel Vetter static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) 799f51b7662SDaniel Vetter { 80073800422SDaniel Vetter agp_bridge->gatt_table_real = NULL; 801f51b7662SDaniel Vetter agp_bridge->gatt_table = NULL; 80273800422SDaniel Vetter agp_bridge->gatt_bus_addr = 0; 803f51b7662SDaniel Vetter 804f51b7662SDaniel Vetter return 0; 805f51b7662SDaniel Vetter } 806f51b7662SDaniel Vetter 807ffdd7510SDaniel Vetter static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) 808f51b7662SDaniel Vetter { 809f51b7662SDaniel Vetter return 0; 810f51b7662SDaniel Vetter } 811f51b7662SDaniel Vetter 812351bb278SDaniel Vetter static int intel_fake_agp_configure(void) 813f51b7662SDaniel Vetter { 814e380f60bSChris Wilson if (!intel_enable_gtt()) 815e380f60bSChris Wilson return -EIO; 816f51b7662SDaniel Vetter 817bee4a186SChris Wilson intel_private.clear_fake_agp = true; 818e5c65377SBen Widawsky agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 819f51b7662SDaniel Vetter 820f51b7662SDaniel Vetter return 0; 821f51b7662SDaniel Vetter } 822f51b7662SDaniel Vetter 8235cbecafcSDaniel Vetter static bool i830_check_flags(unsigned int flags) 824f51b7662SDaniel Vetter { 8255cbecafcSDaniel Vetter switch (flags) { 8265cbecafcSDaniel Vetter case 0: 8275cbecafcSDaniel Vetter case AGP_PHYS_MEMORY: 8285cbecafcSDaniel Vetter case AGP_USER_CACHED_MEMORY: 8295cbecafcSDaniel Vetter case AGP_USER_MEMORY: 8305cbecafcSDaniel Vetter return true; 8315cbecafcSDaniel Vetter } 8325cbecafcSDaniel Vetter 8335cbecafcSDaniel Vetter return false; 8345cbecafcSDaniel Vetter } 8355cbecafcSDaniel Vetter 8369da3da66SChris Wilson void intel_gtt_insert_sg_entries(struct sg_table *st, 837fefaa70fSDaniel Vetter unsigned int pg_start, 838fefaa70fSDaniel Vetter unsigned int flags) 839fefaa70fSDaniel Vetter { 840fefaa70fSDaniel Vetter struct scatterlist *sg; 841fefaa70fSDaniel Vetter unsigned int len, m; 842fefaa70fSDaniel Vetter int i, j; 843fefaa70fSDaniel Vetter 844fefaa70fSDaniel Vetter j = pg_start; 845fefaa70fSDaniel Vetter 846fefaa70fSDaniel Vetter /* sg may merge pages, but we have to separate 847fefaa70fSDaniel Vetter * per-page addr for GTT */ 8489da3da66SChris Wilson for_each_sg(st->sgl, sg, st->nents, i) { 849fefaa70fSDaniel Vetter len = sg_dma_len(sg) >> PAGE_SHIFT; 850fefaa70fSDaniel Vetter for (m = 0; m < len; m++) { 851fefaa70fSDaniel Vetter dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); 8529da3da66SChris Wilson intel_private.driver->write_entry(addr, j, flags); 853fefaa70fSDaniel Vetter j++; 854fefaa70fSDaniel Vetter } 855fefaa70fSDaniel Vetter } 856fefaa70fSDaniel Vetter readl(intel_private.gtt+j-1); 857fefaa70fSDaniel Vetter } 8584080775bSDaniel Vetter EXPORT_SYMBOL(intel_gtt_insert_sg_entries); 8594080775bSDaniel Vetter 8609da3da66SChris Wilson static void intel_gtt_insert_pages(unsigned int first_entry, 8619da3da66SChris Wilson unsigned int num_entries, 8629da3da66SChris Wilson struct page **pages, 8639da3da66SChris Wilson unsigned int flags) 8644080775bSDaniel Vetter { 8654080775bSDaniel Vetter int i, j; 8664080775bSDaniel Vetter 8674080775bSDaniel Vetter for (i = 0, j = first_entry; i < num_entries; i++, j++) { 8684080775bSDaniel Vetter dma_addr_t addr = page_to_phys(pages[i]); 8694080775bSDaniel Vetter intel_private.driver->write_entry(addr, 8704080775bSDaniel Vetter j, flags); 8714080775bSDaniel Vetter } 8724080775bSDaniel Vetter readl(intel_private.gtt+j-1); 8734080775bSDaniel Vetter } 874fefaa70fSDaniel Vetter 8755cbecafcSDaniel Vetter static int intel_fake_agp_insert_entries(struct agp_memory *mem, 8765cbecafcSDaniel Vetter off_t pg_start, int type) 8775cbecafcSDaniel Vetter { 878f51b7662SDaniel Vetter int ret = -EINVAL; 879f51b7662SDaniel Vetter 880bee4a186SChris Wilson if (intel_private.clear_fake_agp) { 881a54c0c27SBen Widawsky int start = intel_private.stolen_size / PAGE_SIZE; 882a54c0c27SBen Widawsky int end = intel_private.gtt_mappable_entries; 883bee4a186SChris Wilson intel_gtt_clear_range(start, end - start); 884bee4a186SChris Wilson intel_private.clear_fake_agp = false; 885bee4a186SChris Wilson } 886bee4a186SChris Wilson 887ff26860fSDaniel Vetter if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) 888ff26860fSDaniel Vetter return i810_insert_dcache_entries(mem, pg_start, type); 889ff26860fSDaniel Vetter 890f51b7662SDaniel Vetter if (mem->page_count == 0) 891f51b7662SDaniel Vetter goto out; 892f51b7662SDaniel Vetter 893a54c0c27SBen Widawsky if (pg_start + mem->page_count > intel_private.gtt_total_entries) 894f51b7662SDaniel Vetter goto out_err; 895f51b7662SDaniel Vetter 896f51b7662SDaniel Vetter if (type != mem->type) 897f51b7662SDaniel Vetter goto out_err; 898f51b7662SDaniel Vetter 8995cbecafcSDaniel Vetter if (!intel_private.driver->check_flags(type)) 900f51b7662SDaniel Vetter goto out_err; 901f51b7662SDaniel Vetter 902f51b7662SDaniel Vetter if (!mem->is_flushed) 903f51b7662SDaniel Vetter global_cache_flush(); 904f51b7662SDaniel Vetter 9058d2e6308SBen Widawsky if (intel_private.needs_dmar) { 9069da3da66SChris Wilson struct sg_table st; 9079da3da66SChris Wilson 9089da3da66SChris Wilson ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st); 909fefaa70fSDaniel Vetter if (ret != 0) 910fefaa70fSDaniel Vetter return ret; 911fefaa70fSDaniel Vetter 9129da3da66SChris Wilson intel_gtt_insert_sg_entries(&st, pg_start, type); 9139da3da66SChris Wilson mem->sg_list = st.sgl; 9149da3da66SChris Wilson mem->num_sg = st.nents; 9154080775bSDaniel Vetter } else 9164080775bSDaniel Vetter intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, 9174080775bSDaniel Vetter type); 918f51b7662SDaniel Vetter 919f51b7662SDaniel Vetter out: 920f51b7662SDaniel Vetter ret = 0; 921f51b7662SDaniel Vetter out_err: 922f51b7662SDaniel Vetter mem->is_flushed = true; 923f51b7662SDaniel Vetter return ret; 924f51b7662SDaniel Vetter } 925f51b7662SDaniel Vetter 9264080775bSDaniel Vetter void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) 927f51b7662SDaniel Vetter { 9284080775bSDaniel Vetter unsigned int i; 929f51b7662SDaniel Vetter 9304080775bSDaniel Vetter for (i = first_entry; i < (first_entry + num_entries); i++) { 9319c61a32dSBen Widawsky intel_private.driver->write_entry(intel_private.scratch_page_dma, 9325cbecafcSDaniel Vetter i, 0); 933f51b7662SDaniel Vetter } 934fdfb58a9SDaniel Vetter readl(intel_private.gtt+i-1); 9354080775bSDaniel Vetter } 9364080775bSDaniel Vetter EXPORT_SYMBOL(intel_gtt_clear_range); 9374080775bSDaniel Vetter 9384080775bSDaniel Vetter static int intel_fake_agp_remove_entries(struct agp_memory *mem, 9394080775bSDaniel Vetter off_t pg_start, int type) 9404080775bSDaniel Vetter { 9414080775bSDaniel Vetter if (mem->page_count == 0) 9424080775bSDaniel Vetter return 0; 9434080775bSDaniel Vetter 944d15eda5cSDave Airlie intel_gtt_clear_range(pg_start, mem->page_count); 945d15eda5cSDave Airlie 9468d2e6308SBen Widawsky if (intel_private.needs_dmar) { 9474080775bSDaniel Vetter intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); 9484080775bSDaniel Vetter mem->sg_list = NULL; 9494080775bSDaniel Vetter mem->num_sg = 0; 9504080775bSDaniel Vetter } 9514080775bSDaniel Vetter 952f51b7662SDaniel Vetter return 0; 953f51b7662SDaniel Vetter } 954f51b7662SDaniel Vetter 955ffdd7510SDaniel Vetter static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, 956ffdd7510SDaniel Vetter int type) 957f51b7662SDaniel Vetter { 958625dd9d3SDaniel Vetter struct agp_memory *new; 959625dd9d3SDaniel Vetter 960625dd9d3SDaniel Vetter if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { 961625dd9d3SDaniel Vetter if (pg_count != intel_private.num_dcache_entries) 962625dd9d3SDaniel Vetter return NULL; 963625dd9d3SDaniel Vetter 964625dd9d3SDaniel Vetter new = agp_create_memory(1); 965625dd9d3SDaniel Vetter if (new == NULL) 966625dd9d3SDaniel Vetter return NULL; 967625dd9d3SDaniel Vetter 968625dd9d3SDaniel Vetter new->type = AGP_DCACHE_MEMORY; 969625dd9d3SDaniel Vetter new->page_count = pg_count; 970625dd9d3SDaniel Vetter new->num_scratch_pages = 0; 971625dd9d3SDaniel Vetter agp_free_page_array(new); 972625dd9d3SDaniel Vetter return new; 973625dd9d3SDaniel Vetter } 974f51b7662SDaniel Vetter if (type == AGP_PHYS_MEMORY) 975f51b7662SDaniel Vetter return alloc_agpphysmem_i8xx(pg_count, type); 976f51b7662SDaniel Vetter /* always return NULL for other allocation types for now */ 977f51b7662SDaniel Vetter return NULL; 978f51b7662SDaniel Vetter } 979f51b7662SDaniel Vetter 980f51b7662SDaniel Vetter static int intel_alloc_chipset_flush_resource(void) 981f51b7662SDaniel Vetter { 982f51b7662SDaniel Vetter int ret; 983d7cca2f7SDaniel Vetter ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 984f51b7662SDaniel Vetter PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 985d7cca2f7SDaniel Vetter pcibios_align_resource, intel_private.bridge_dev); 986f51b7662SDaniel Vetter 987f51b7662SDaniel Vetter return ret; 988f51b7662SDaniel Vetter } 989f51b7662SDaniel Vetter 990f51b7662SDaniel Vetter static void intel_i915_setup_chipset_flush(void) 991f51b7662SDaniel Vetter { 992f51b7662SDaniel Vetter int ret; 993f51b7662SDaniel Vetter u32 temp; 994f51b7662SDaniel Vetter 995d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); 996f51b7662SDaniel Vetter if (!(temp & 0x1)) { 997f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 998f51b7662SDaniel Vetter intel_private.resource_valid = 1; 999d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1000f51b7662SDaniel Vetter } else { 1001f51b7662SDaniel Vetter temp &= ~1; 1002f51b7662SDaniel Vetter 1003f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1004f51b7662SDaniel Vetter intel_private.ifp_resource.start = temp; 1005f51b7662SDaniel Vetter intel_private.ifp_resource.end = temp + PAGE_SIZE; 1006f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1007f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 1008f51b7662SDaniel Vetter if (ret) 1009f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1010f51b7662SDaniel Vetter } 1011f51b7662SDaniel Vetter } 1012f51b7662SDaniel Vetter 1013f51b7662SDaniel Vetter static void intel_i965_g33_setup_chipset_flush(void) 1014f51b7662SDaniel Vetter { 1015f51b7662SDaniel Vetter u32 temp_hi, temp_lo; 1016f51b7662SDaniel Vetter int ret; 1017f51b7662SDaniel Vetter 1018d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); 1019d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); 1020f51b7662SDaniel Vetter 1021f51b7662SDaniel Vetter if (!(temp_lo & 0x1)) { 1022f51b7662SDaniel Vetter 1023f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 1024f51b7662SDaniel Vetter 1025f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1026d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, 1027f51b7662SDaniel Vetter upper_32_bits(intel_private.ifp_resource.start)); 1028d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1029f51b7662SDaniel Vetter } else { 1030f51b7662SDaniel Vetter u64 l64; 1031f51b7662SDaniel Vetter 1032f51b7662SDaniel Vetter temp_lo &= ~0x1; 1033f51b7662SDaniel Vetter l64 = ((u64)temp_hi << 32) | temp_lo; 1034f51b7662SDaniel Vetter 1035f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1036f51b7662SDaniel Vetter intel_private.ifp_resource.start = l64; 1037f51b7662SDaniel Vetter intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1038f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1039f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 1040f51b7662SDaniel Vetter if (ret) 1041f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1042f51b7662SDaniel Vetter } 1043f51b7662SDaniel Vetter } 1044f51b7662SDaniel Vetter 1045f51b7662SDaniel Vetter static void intel_i9xx_setup_flush(void) 1046f51b7662SDaniel Vetter { 1047f51b7662SDaniel Vetter /* return if already configured */ 1048f51b7662SDaniel Vetter if (intel_private.ifp_resource.start) 1049f51b7662SDaniel Vetter return; 1050f51b7662SDaniel Vetter 10511a997ff2SDaniel Vetter if (INTEL_GTT_GEN == 6) 1052f51b7662SDaniel Vetter return; 1053f51b7662SDaniel Vetter 1054f51b7662SDaniel Vetter /* setup a resource for this object */ 1055f51b7662SDaniel Vetter intel_private.ifp_resource.name = "Intel Flush Page"; 1056f51b7662SDaniel Vetter intel_private.ifp_resource.flags = IORESOURCE_MEM; 1057f51b7662SDaniel Vetter 1058f51b7662SDaniel Vetter /* Setup chipset flush for 915 */ 10591a997ff2SDaniel Vetter if (IS_G33 || INTEL_GTT_GEN >= 4) { 1060f51b7662SDaniel Vetter intel_i965_g33_setup_chipset_flush(); 1061f51b7662SDaniel Vetter } else { 1062f51b7662SDaniel Vetter intel_i915_setup_chipset_flush(); 1063f51b7662SDaniel Vetter } 1064f51b7662SDaniel Vetter 1065df51e7aaSChris Wilson if (intel_private.ifp_resource.start) 1066f51b7662SDaniel Vetter intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1067f51b7662SDaniel Vetter if (!intel_private.i9xx_flush_page) 1068df51e7aaSChris Wilson dev_err(&intel_private.pcidev->dev, 1069df51e7aaSChris Wilson "can't ioremap flush page - no chipset flushing\n"); 1070f51b7662SDaniel Vetter } 1071f51b7662SDaniel Vetter 1072ae83dd5cSDaniel Vetter static void i9xx_cleanup(void) 1073ae83dd5cSDaniel Vetter { 1074ae83dd5cSDaniel Vetter if (intel_private.i9xx_flush_page) 1075ae83dd5cSDaniel Vetter iounmap(intel_private.i9xx_flush_page); 1076ae83dd5cSDaniel Vetter if (intel_private.resource_valid) 1077ae83dd5cSDaniel Vetter release_resource(&intel_private.ifp_resource); 1078ae83dd5cSDaniel Vetter intel_private.ifp_resource.start = 0; 1079ae83dd5cSDaniel Vetter intel_private.resource_valid = 0; 1080ae83dd5cSDaniel Vetter } 1081ae83dd5cSDaniel Vetter 10821b263f24SDaniel Vetter static void i9xx_chipset_flush(void) 1083f51b7662SDaniel Vetter { 1084f51b7662SDaniel Vetter if (intel_private.i9xx_flush_page) 1085f51b7662SDaniel Vetter writel(1, intel_private.i9xx_flush_page); 1086f51b7662SDaniel Vetter } 1087f51b7662SDaniel Vetter 108871f45660SChris Wilson static void i965_write_entry(dma_addr_t addr, 108971f45660SChris Wilson unsigned int entry, 1090a6963596SDaniel Vetter unsigned int flags) 1091a6963596SDaniel Vetter { 109271f45660SChris Wilson u32 pte_flags; 109371f45660SChris Wilson 109471f45660SChris Wilson pte_flags = I810_PTE_VALID; 109571f45660SChris Wilson if (flags == AGP_USER_CACHED_MEMORY) 109671f45660SChris Wilson pte_flags |= I830_PTE_SYSTEM_CACHED; 109771f45660SChris Wilson 1098a6963596SDaniel Vetter /* Shift high bits down */ 1099a6963596SDaniel Vetter addr |= (addr >> 28) & 0xf0; 110071f45660SChris Wilson writel(addr | pte_flags, intel_private.gtt + entry); 1101a6963596SDaniel Vetter } 1102a6963596SDaniel Vetter 11032d2430cfSDaniel Vetter static int i9xx_setup(void) 11042d2430cfSDaniel Vetter { 1105*d3572532SBjorn Helgaas phys_addr_t reg_addr; 11064b60d29eSJesse Barnes int size = KB(512); 11072d2430cfSDaniel Vetter 1108*d3572532SBjorn Helgaas reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR); 11092d2430cfSDaniel Vetter 11104b60d29eSJesse Barnes intel_private.registers = ioremap(reg_addr, size); 11112d2430cfSDaniel Vetter if (!intel_private.registers) 11122d2430cfSDaniel Vetter return -ENOMEM; 11132d2430cfSDaniel Vetter 1114009946f8SBen Widawsky switch (INTEL_GTT_GEN) { 1115009946f8SBen Widawsky case 3: 1116b5e350f9SBjorn Helgaas intel_private.gtt_phys_addr = 1117*d3572532SBjorn Helgaas pci_resource_start(intel_private.pcidev, I915_PTE_BAR); 1118009946f8SBen Widawsky break; 11192d2430cfSDaniel Vetter case 5: 11205acc4ce4SBjorn Helgaas intel_private.gtt_phys_addr = reg_addr + MB(2); 11212d2430cfSDaniel Vetter break; 11222d2430cfSDaniel Vetter default: 11235acc4ce4SBjorn Helgaas intel_private.gtt_phys_addr = reg_addr + KB(512); 11242d2430cfSDaniel Vetter break; 11252d2430cfSDaniel Vetter } 11262d2430cfSDaniel Vetter 11272d2430cfSDaniel Vetter intel_i9xx_setup_flush(); 11282d2430cfSDaniel Vetter 11292d2430cfSDaniel Vetter return 0; 11302d2430cfSDaniel Vetter } 11312d2430cfSDaniel Vetter 1132e9b1cc81SDaniel Vetter static const struct agp_bridge_driver intel_fake_agp_driver = { 1133f51b7662SDaniel Vetter .owner = THIS_MODULE, 1134f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 11359e76e7b8SChris Wilson .aperture_sizes = intel_fake_agp_sizes, 11369e76e7b8SChris Wilson .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1137a6963596SDaniel Vetter .configure = intel_fake_agp_configure, 11383e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1139fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1140ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1141f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 11423b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1143ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1144450f2b3dSDaniel Vetter .insert_memory = intel_fake_agp_insert_entries, 1145450f2b3dSDaniel Vetter .remove_memory = intel_fake_agp_remove_entries, 1146ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1147f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1148f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1149f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1150f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1151f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1152f51b7662SDaniel Vetter }; 115302c026ceSDaniel Vetter 1154bdd30729SDaniel Vetter static const struct intel_gtt_driver i81x_gtt_driver = { 1155bdd30729SDaniel Vetter .gen = 1, 1156820647b9SDaniel Vetter .has_pgtbl_enable = 1, 115722533b49SDaniel Vetter .dma_mask_size = 32, 1158820647b9SDaniel Vetter .setup = i810_setup, 1159820647b9SDaniel Vetter .cleanup = i810_cleanup, 1160625dd9d3SDaniel Vetter .check_flags = i830_check_flags, 1161625dd9d3SDaniel Vetter .write_entry = i810_write_entry, 1162bdd30729SDaniel Vetter }; 11631a997ff2SDaniel Vetter static const struct intel_gtt_driver i8xx_gtt_driver = { 11641a997ff2SDaniel Vetter .gen = 2, 1165100519e2SChris Wilson .has_pgtbl_enable = 1, 116673800422SDaniel Vetter .setup = i830_setup, 1167ae83dd5cSDaniel Vetter .cleanup = i830_cleanup, 1168351bb278SDaniel Vetter .write_entry = i830_write_entry, 116922533b49SDaniel Vetter .dma_mask_size = 32, 11705cbecafcSDaniel Vetter .check_flags = i830_check_flags, 11711b263f24SDaniel Vetter .chipset_flush = i830_chipset_flush, 11721a997ff2SDaniel Vetter }; 11731a997ff2SDaniel Vetter static const struct intel_gtt_driver i915_gtt_driver = { 11741a997ff2SDaniel Vetter .gen = 3, 1175100519e2SChris Wilson .has_pgtbl_enable = 1, 11762d2430cfSDaniel Vetter .setup = i9xx_setup, 1177ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1178351bb278SDaniel Vetter /* i945 is the last gpu to need phys mem (for overlay and cursors). */ 1179351bb278SDaniel Vetter .write_entry = i830_write_entry, 118022533b49SDaniel Vetter .dma_mask_size = 32, 1181fefaa70fSDaniel Vetter .check_flags = i830_check_flags, 11821b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 11831a997ff2SDaniel Vetter }; 11841a997ff2SDaniel Vetter static const struct intel_gtt_driver g33_gtt_driver = { 11851a997ff2SDaniel Vetter .gen = 3, 11861a997ff2SDaniel Vetter .is_g33 = 1, 11872d2430cfSDaniel Vetter .setup = i9xx_setup, 1188ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1189a6963596SDaniel Vetter .write_entry = i965_write_entry, 119022533b49SDaniel Vetter .dma_mask_size = 36, 1191450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 11921b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 11931a997ff2SDaniel Vetter }; 11941a997ff2SDaniel Vetter static const struct intel_gtt_driver pineview_gtt_driver = { 11951a997ff2SDaniel Vetter .gen = 3, 11961a997ff2SDaniel Vetter .is_pineview = 1, .is_g33 = 1, 11972d2430cfSDaniel Vetter .setup = i9xx_setup, 1198ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1199a6963596SDaniel Vetter .write_entry = i965_write_entry, 120022533b49SDaniel Vetter .dma_mask_size = 36, 1201450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 12021b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 12031a997ff2SDaniel Vetter }; 12041a997ff2SDaniel Vetter static const struct intel_gtt_driver i965_gtt_driver = { 12051a997ff2SDaniel Vetter .gen = 4, 1206100519e2SChris Wilson .has_pgtbl_enable = 1, 12072d2430cfSDaniel Vetter .setup = i9xx_setup, 1208ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1209a6963596SDaniel Vetter .write_entry = i965_write_entry, 121022533b49SDaniel Vetter .dma_mask_size = 36, 1211450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 12121b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 12131a997ff2SDaniel Vetter }; 12141a997ff2SDaniel Vetter static const struct intel_gtt_driver g4x_gtt_driver = { 12151a997ff2SDaniel Vetter .gen = 5, 12162d2430cfSDaniel Vetter .setup = i9xx_setup, 1217ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1218a6963596SDaniel Vetter .write_entry = i965_write_entry, 121922533b49SDaniel Vetter .dma_mask_size = 36, 1220450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 12211b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 12221a997ff2SDaniel Vetter }; 12231a997ff2SDaniel Vetter static const struct intel_gtt_driver ironlake_gtt_driver = { 12241a997ff2SDaniel Vetter .gen = 5, 12251a997ff2SDaniel Vetter .is_ironlake = 1, 12262d2430cfSDaniel Vetter .setup = i9xx_setup, 1227ae83dd5cSDaniel Vetter .cleanup = i9xx_cleanup, 1228a6963596SDaniel Vetter .write_entry = i965_write_entry, 122922533b49SDaniel Vetter .dma_mask_size = 36, 1230450f2b3dSDaniel Vetter .check_flags = i830_check_flags, 12311b263f24SDaniel Vetter .chipset_flush = i9xx_chipset_flush, 12321a997ff2SDaniel Vetter }; 12331a997ff2SDaniel Vetter 123402c026ceSDaniel Vetter /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 123502c026ceSDaniel Vetter * driver and gmch_driver must be non-null, and find_gmch will determine 123602c026ceSDaniel Vetter * which one should be used if a gmch_chip_id is present. 123702c026ceSDaniel Vetter */ 123802c026ceSDaniel Vetter static const struct intel_gtt_driver_description { 123902c026ceSDaniel Vetter unsigned int gmch_chip_id; 124002c026ceSDaniel Vetter char *name; 12411a997ff2SDaniel Vetter const struct intel_gtt_driver *gtt_driver; 124202c026ceSDaniel Vetter } intel_gtt_chipsets[] = { 1243ff26860fSDaniel Vetter { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", 1244bdd30729SDaniel Vetter &i81x_gtt_driver}, 1245ff26860fSDaniel Vetter { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", 1246bdd30729SDaniel Vetter &i81x_gtt_driver}, 1247ff26860fSDaniel Vetter { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", 1248bdd30729SDaniel Vetter &i81x_gtt_driver}, 1249ff26860fSDaniel Vetter { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", 1250bdd30729SDaniel Vetter &i81x_gtt_driver}, 12511a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 1252ff26860fSDaniel Vetter &i8xx_gtt_driver}, 125353371edaSOswald Buddenhagen { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", 1254ff26860fSDaniel Vetter &i8xx_gtt_driver}, 12551a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82854_IG, "854", 1256ff26860fSDaniel Vetter &i8xx_gtt_driver}, 12571a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", 1258ff26860fSDaniel Vetter &i8xx_gtt_driver}, 12591a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82865_IG, "865", 1260ff26860fSDaniel Vetter &i8xx_gtt_driver}, 12611a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", 1262ff26860fSDaniel Vetter &i915_gtt_driver }, 12631a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", 1264ff26860fSDaniel Vetter &i915_gtt_driver }, 12651a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", 1266ff26860fSDaniel Vetter &i915_gtt_driver }, 12671a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", 1268ff26860fSDaniel Vetter &i915_gtt_driver }, 12691a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", 1270ff26860fSDaniel Vetter &i915_gtt_driver }, 12711a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", 1272ff26860fSDaniel Vetter &i915_gtt_driver }, 12731a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", 1274ff26860fSDaniel Vetter &i965_gtt_driver }, 12751a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", 1276ff26860fSDaniel Vetter &i965_gtt_driver }, 12771a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", 1278ff26860fSDaniel Vetter &i965_gtt_driver }, 12791a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", 1280ff26860fSDaniel Vetter &i965_gtt_driver }, 12811a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", 1282ff26860fSDaniel Vetter &i965_gtt_driver }, 12831a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", 1284ff26860fSDaniel Vetter &i965_gtt_driver }, 12851a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G33_IG, "G33", 1286ff26860fSDaniel Vetter &g33_gtt_driver }, 12871a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", 1288ff26860fSDaniel Vetter &g33_gtt_driver }, 12891a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", 1290ff26860fSDaniel Vetter &g33_gtt_driver }, 12911a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", 1292ff26860fSDaniel Vetter &pineview_gtt_driver }, 12931a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", 1294ff26860fSDaniel Vetter &pineview_gtt_driver }, 12951a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", 1296ff26860fSDaniel Vetter &g4x_gtt_driver }, 12971a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", 1298ff26860fSDaniel Vetter &g4x_gtt_driver }, 12991a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", 1300ff26860fSDaniel Vetter &g4x_gtt_driver }, 13011a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", 1302ff26860fSDaniel Vetter &g4x_gtt_driver }, 13031a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_B43_IG, "B43", 1304ff26860fSDaniel Vetter &g4x_gtt_driver }, 1305e9e5f8e8SChris Wilson { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", 1306ff26860fSDaniel Vetter &g4x_gtt_driver }, 13071a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G41_IG, "G41", 1308ff26860fSDaniel Vetter &g4x_gtt_driver }, 130902c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 1310ff26860fSDaniel Vetter "HD Graphics", &ironlake_gtt_driver }, 131102c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 1312ff26860fSDaniel Vetter "HD Graphics", &ironlake_gtt_driver }, 131302c026ceSDaniel Vetter { 0, NULL, NULL } 131402c026ceSDaniel Vetter }; 131502c026ceSDaniel Vetter 131602c026ceSDaniel Vetter static int find_gmch(u16 device) 131702c026ceSDaniel Vetter { 131802c026ceSDaniel Vetter struct pci_dev *gmch_device; 131902c026ceSDaniel Vetter 132002c026ceSDaniel Vetter gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 132102c026ceSDaniel Vetter if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 132202c026ceSDaniel Vetter gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 132302c026ceSDaniel Vetter device, gmch_device); 132402c026ceSDaniel Vetter } 132502c026ceSDaniel Vetter 132602c026ceSDaniel Vetter if (!gmch_device) 132702c026ceSDaniel Vetter return 0; 132802c026ceSDaniel Vetter 132902c026ceSDaniel Vetter intel_private.pcidev = gmch_device; 133002c026ceSDaniel Vetter return 1; 133102c026ceSDaniel Vetter } 133202c026ceSDaniel Vetter 133314be93ddSDaniel Vetter int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, 133402c026ceSDaniel Vetter struct agp_bridge_data *bridge) 133502c026ceSDaniel Vetter { 133602c026ceSDaniel Vetter int i, mask; 133714be93ddSDaniel Vetter 133814be93ddSDaniel Vetter /* 133914be93ddSDaniel Vetter * Can be called from the fake agp driver but also directly from 134014be93ddSDaniel Vetter * drm/i915.ko. Hence we need to check whether everything is set up 134114be93ddSDaniel Vetter * already. 134214be93ddSDaniel Vetter */ 134314be93ddSDaniel Vetter if (intel_private.driver) { 134414be93ddSDaniel Vetter intel_private.refcount++; 134514be93ddSDaniel Vetter return 1; 134614be93ddSDaniel Vetter } 134702c026ceSDaniel Vetter 134802c026ceSDaniel Vetter for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { 134914be93ddSDaniel Vetter if (gpu_pdev) { 135014be93ddSDaniel Vetter if (gpu_pdev->device == 135114be93ddSDaniel Vetter intel_gtt_chipsets[i].gmch_chip_id) { 135214be93ddSDaniel Vetter intel_private.pcidev = pci_dev_get(gpu_pdev); 135314be93ddSDaniel Vetter intel_private.driver = 135414be93ddSDaniel Vetter intel_gtt_chipsets[i].gtt_driver; 135514be93ddSDaniel Vetter 135614be93ddSDaniel Vetter break; 135714be93ddSDaniel Vetter } 135814be93ddSDaniel Vetter } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { 13591a997ff2SDaniel Vetter intel_private.driver = 13601a997ff2SDaniel Vetter intel_gtt_chipsets[i].gtt_driver; 136102c026ceSDaniel Vetter break; 136202c026ceSDaniel Vetter } 136302c026ceSDaniel Vetter } 136402c026ceSDaniel Vetter 1365ff26860fSDaniel Vetter if (!intel_private.driver) 136602c026ceSDaniel Vetter return 0; 136702c026ceSDaniel Vetter 136814be93ddSDaniel Vetter intel_private.refcount++; 136914be93ddSDaniel Vetter 13707e8f6306SDaniel Vetter if (bridge) { 1371ff26860fSDaniel Vetter bridge->driver = &intel_fake_agp_driver; 137202c026ceSDaniel Vetter bridge->dev_private_data = &intel_private; 137314be93ddSDaniel Vetter bridge->dev = bridge_pdev; 13747e8f6306SDaniel Vetter } 137502c026ceSDaniel Vetter 137614be93ddSDaniel Vetter intel_private.bridge_dev = pci_dev_get(bridge_pdev); 1377d7cca2f7SDaniel Vetter 137814be93ddSDaniel Vetter dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); 137902c026ceSDaniel Vetter 138022533b49SDaniel Vetter mask = intel_private.driver->dma_mask_size; 138102c026ceSDaniel Vetter if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) 138202c026ceSDaniel Vetter dev_err(&intel_private.pcidev->dev, 138302c026ceSDaniel Vetter "set gfx device dma mask %d-bit failed!\n", mask); 138402c026ceSDaniel Vetter else 138502c026ceSDaniel Vetter pci_set_consistent_dma_mask(intel_private.pcidev, 138602c026ceSDaniel Vetter DMA_BIT_MASK(mask)); 138702c026ceSDaniel Vetter 138814be93ddSDaniel Vetter if (intel_gtt_init() != 0) { 138914be93ddSDaniel Vetter intel_gmch_remove(); 139014be93ddSDaniel Vetter 13913b15a9d7SDaniel Vetter return 0; 139214be93ddSDaniel Vetter } 13931784a5fbSDaniel Vetter 139402c026ceSDaniel Vetter return 1; 139502c026ceSDaniel Vetter } 1396e2404e7cSDaniel Vetter EXPORT_SYMBOL(intel_gmch_probe); 139702c026ceSDaniel Vetter 139841907ddcSBen Widawsky void intel_gtt_get(size_t *gtt_total, size_t *stolen_size, 139941907ddcSBen Widawsky phys_addr_t *mappable_base, unsigned long *mappable_end) 140019966754SDaniel Vetter { 1401a54c0c27SBen Widawsky *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT; 1402a54c0c27SBen Widawsky *stolen_size = intel_private.stolen_size; 140341907ddcSBen Widawsky *mappable_base = intel_private.gma_bus_addr; 140441907ddcSBen Widawsky *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT; 140519966754SDaniel Vetter } 140619966754SDaniel Vetter EXPORT_SYMBOL(intel_gtt_get); 140719966754SDaniel Vetter 140840ce6575SDaniel Vetter void intel_gtt_chipset_flush(void) 140940ce6575SDaniel Vetter { 141040ce6575SDaniel Vetter if (intel_private.driver->chipset_flush) 141140ce6575SDaniel Vetter intel_private.driver->chipset_flush(); 141240ce6575SDaniel Vetter } 141340ce6575SDaniel Vetter EXPORT_SYMBOL(intel_gtt_chipset_flush); 141440ce6575SDaniel Vetter 141514be93ddSDaniel Vetter void intel_gmch_remove(void) 141602c026ceSDaniel Vetter { 141714be93ddSDaniel Vetter if (--intel_private.refcount) 141814be93ddSDaniel Vetter return; 141914be93ddSDaniel Vetter 142002c026ceSDaniel Vetter if (intel_private.pcidev) 142102c026ceSDaniel Vetter pci_dev_put(intel_private.pcidev); 1422d7cca2f7SDaniel Vetter if (intel_private.bridge_dev) 1423d7cca2f7SDaniel Vetter pci_dev_put(intel_private.bridge_dev); 142414be93ddSDaniel Vetter intel_private.driver = NULL; 142502c026ceSDaniel Vetter } 1426e2404e7cSDaniel Vetter EXPORT_SYMBOL(intel_gmch_remove); 1427e2404e7cSDaniel Vetter 1428e2404e7cSDaniel Vetter MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 1429e2404e7cSDaniel Vetter MODULE_LICENSE("GPL and additional rights"); 1430