1f51b7662SDaniel Vetter /* 2f51b7662SDaniel Vetter * Intel GTT (Graphics Translation Table) routines 3f51b7662SDaniel Vetter * 4f51b7662SDaniel Vetter * Caveat: This driver implements the linux agp interface, but this is far from 5f51b7662SDaniel Vetter * a agp driver! GTT support ended up here for purely historical reasons: The 6f51b7662SDaniel Vetter * old userspace intel graphics drivers needed an interface to map memory into 7f51b7662SDaniel Vetter * the GTT. And the drm provides a default interface for graphic devices sitting 8f51b7662SDaniel Vetter * on an agp port. So it made sense to fake the GTT support as an agp port to 9f51b7662SDaniel Vetter * avoid having to create a new api. 10f51b7662SDaniel Vetter * 11f51b7662SDaniel Vetter * With gem this does not make much sense anymore, just needlessly complicates 12f51b7662SDaniel Vetter * the code. But as long as the old graphics stack is still support, it's stuck 13f51b7662SDaniel Vetter * here. 14f51b7662SDaniel Vetter * 15f51b7662SDaniel Vetter * /fairy-tale-mode off 16f51b7662SDaniel Vetter */ 17f51b7662SDaniel Vetter 18e2404e7cSDaniel Vetter #include <linux/module.h> 19e2404e7cSDaniel Vetter #include <linux/pci.h> 20e2404e7cSDaniel Vetter #include <linux/init.h> 21e2404e7cSDaniel Vetter #include <linux/kernel.h> 22e2404e7cSDaniel Vetter #include <linux/pagemap.h> 23e2404e7cSDaniel Vetter #include <linux/agp_backend.h> 24e2404e7cSDaniel Vetter #include <asm/smp.h> 25e2404e7cSDaniel Vetter #include "agp.h" 26e2404e7cSDaniel Vetter #include "intel-agp.h" 27e2404e7cSDaniel Vetter #include <linux/intel-gtt.h> 280ade6386SDaniel Vetter #include <drm/intel-gtt.h> 29e2404e7cSDaniel Vetter 30f51b7662SDaniel Vetter /* 31f51b7662SDaniel Vetter * If we have Intel graphics, we're not going to have anything other than 32f51b7662SDaniel Vetter * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 33f51b7662SDaniel Vetter * on the Intel IOMMU support (CONFIG_DMAR). 34f51b7662SDaniel Vetter * Only newer chipsets need to bother with this, of course. 35f51b7662SDaniel Vetter */ 36f51b7662SDaniel Vetter #ifdef CONFIG_DMAR 37f51b7662SDaniel Vetter #define USE_PCI_DMA_API 1 380e87d2b0SDaniel Vetter #else 390e87d2b0SDaniel Vetter #define USE_PCI_DMA_API 0 40f51b7662SDaniel Vetter #endif 41f51b7662SDaniel Vetter 42d1d6ca73SJesse Barnes /* Max amount of stolen space, anything above will be returned to Linux */ 43d1d6ca73SJesse Barnes int intel_max_stolen = 32 * 1024 * 1024; 44d1d6ca73SJesse Barnes EXPORT_SYMBOL(intel_max_stolen); 45d1d6ca73SJesse Barnes 46f51b7662SDaniel Vetter static const struct aper_size_info_fixed intel_i810_sizes[] = 47f51b7662SDaniel Vetter { 48f51b7662SDaniel Vetter {64, 16384, 4}, 49f51b7662SDaniel Vetter /* The 32M mode still requires a 64k gatt */ 50f51b7662SDaniel Vetter {32, 8192, 4} 51f51b7662SDaniel Vetter }; 52f51b7662SDaniel Vetter 53f51b7662SDaniel Vetter #define AGP_DCACHE_MEMORY 1 54f51b7662SDaniel Vetter #define AGP_PHYS_MEMORY 2 55f51b7662SDaniel Vetter #define INTEL_AGP_CACHED_MEMORY 3 56f51b7662SDaniel Vetter 57f51b7662SDaniel Vetter static struct gatt_mask intel_i810_masks[] = 58f51b7662SDaniel Vetter { 59f51b7662SDaniel Vetter {.mask = I810_PTE_VALID, .type = 0}, 60f51b7662SDaniel Vetter {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 61f51b7662SDaniel Vetter {.mask = I810_PTE_VALID, .type = 0}, 62f51b7662SDaniel Vetter {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, 63f51b7662SDaniel Vetter .type = INTEL_AGP_CACHED_MEMORY} 64f51b7662SDaniel Vetter }; 65f51b7662SDaniel Vetter 66f8f235e5SZhenyu Wang #define INTEL_AGP_UNCACHED_MEMORY 0 67f8f235e5SZhenyu Wang #define INTEL_AGP_CACHED_MEMORY_LLC 1 68f8f235e5SZhenyu Wang #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2 69f8f235e5SZhenyu Wang #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3 70f8f235e5SZhenyu Wang #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4 71f8f235e5SZhenyu Wang 72f8f235e5SZhenyu Wang static struct gatt_mask intel_gen6_masks[] = 73f8f235e5SZhenyu Wang { 74f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED, 75f8f235e5SZhenyu Wang .type = INTEL_AGP_UNCACHED_MEMORY }, 76f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_LLC, 77f8f235e5SZhenyu Wang .type = INTEL_AGP_CACHED_MEMORY_LLC }, 78f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT, 79f8f235e5SZhenyu Wang .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT }, 80f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC, 81f8f235e5SZhenyu Wang .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC }, 82f8f235e5SZhenyu Wang {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT, 83f8f235e5SZhenyu Wang .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT }, 84f8f235e5SZhenyu Wang }; 85f8f235e5SZhenyu Wang 861a997ff2SDaniel Vetter struct intel_gtt_driver { 871a997ff2SDaniel Vetter unsigned int gen : 8; 881a997ff2SDaniel Vetter unsigned int is_g33 : 1; 891a997ff2SDaniel Vetter unsigned int is_pineview : 1; 901a997ff2SDaniel Vetter unsigned int is_ironlake : 1; 9173800422SDaniel Vetter /* Chipset specific GTT setup */ 9273800422SDaniel Vetter int (*setup)(void); 93*351bb278SDaniel Vetter void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); 94*351bb278SDaniel Vetter /* Flags is a more or less chipset specific opaque value. 95*351bb278SDaniel Vetter * For chipsets that need to support old ums (non-gem) code, this 96*351bb278SDaniel Vetter * needs to be identical to the various supported agp memory types! */ 971a997ff2SDaniel Vetter }; 981a997ff2SDaniel Vetter 99f51b7662SDaniel Vetter static struct _intel_private { 1000ade6386SDaniel Vetter struct intel_gtt base; 1011a997ff2SDaniel Vetter const struct intel_gtt_driver *driver; 102f51b7662SDaniel Vetter struct pci_dev *pcidev; /* device one */ 103d7cca2f7SDaniel Vetter struct pci_dev *bridge_dev; 104f51b7662SDaniel Vetter u8 __iomem *registers; 105f67eab66SDaniel Vetter phys_addr_t gtt_bus_addr; 10673800422SDaniel Vetter phys_addr_t gma_bus_addr; 1073f08e4efSChris Wilson phys_addr_t pte_bus_addr; 108f51b7662SDaniel Vetter u32 __iomem *gtt; /* I915G */ 109f51b7662SDaniel Vetter int num_dcache_entries; 110f51b7662SDaniel Vetter union { 111f51b7662SDaniel Vetter void __iomem *i9xx_flush_page; 112f51b7662SDaniel Vetter void *i8xx_flush_page; 113f51b7662SDaniel Vetter }; 114f51b7662SDaniel Vetter struct page *i8xx_page; 115f51b7662SDaniel Vetter struct resource ifp_resource; 116f51b7662SDaniel Vetter int resource_valid; 1170e87d2b0SDaniel Vetter struct page *scratch_page; 1180e87d2b0SDaniel Vetter dma_addr_t scratch_page_dma; 119f51b7662SDaniel Vetter } intel_private; 120f51b7662SDaniel Vetter 1211a997ff2SDaniel Vetter #define INTEL_GTT_GEN intel_private.driver->gen 1221a997ff2SDaniel Vetter #define IS_G33 intel_private.driver->is_g33 1231a997ff2SDaniel Vetter #define IS_PINEVIEW intel_private.driver->is_pineview 1241a997ff2SDaniel Vetter #define IS_IRONLAKE intel_private.driver->is_ironlake 1251a997ff2SDaniel Vetter 1260e87d2b0SDaniel Vetter #if USE_PCI_DMA_API 127f51b7662SDaniel Vetter static int intel_agp_map_page(struct page *page, dma_addr_t *ret) 128f51b7662SDaniel Vetter { 129f51b7662SDaniel Vetter *ret = pci_map_page(intel_private.pcidev, page, 0, 130f51b7662SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 131f51b7662SDaniel Vetter if (pci_dma_mapping_error(intel_private.pcidev, *ret)) 132f51b7662SDaniel Vetter return -EINVAL; 133f51b7662SDaniel Vetter return 0; 134f51b7662SDaniel Vetter } 135f51b7662SDaniel Vetter 136f51b7662SDaniel Vetter static void intel_agp_unmap_page(struct page *page, dma_addr_t dma) 137f51b7662SDaniel Vetter { 138f51b7662SDaniel Vetter pci_unmap_page(intel_private.pcidev, dma, 139f51b7662SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 140f51b7662SDaniel Vetter } 141f51b7662SDaniel Vetter 142f51b7662SDaniel Vetter static void intel_agp_free_sglist(struct agp_memory *mem) 143f51b7662SDaniel Vetter { 144f51b7662SDaniel Vetter struct sg_table st; 145f51b7662SDaniel Vetter 146f51b7662SDaniel Vetter st.sgl = mem->sg_list; 147f51b7662SDaniel Vetter st.orig_nents = st.nents = mem->page_count; 148f51b7662SDaniel Vetter 149f51b7662SDaniel Vetter sg_free_table(&st); 150f51b7662SDaniel Vetter 151f51b7662SDaniel Vetter mem->sg_list = NULL; 152f51b7662SDaniel Vetter mem->num_sg = 0; 153f51b7662SDaniel Vetter } 154f51b7662SDaniel Vetter 155f51b7662SDaniel Vetter static int intel_agp_map_memory(struct agp_memory *mem) 156f51b7662SDaniel Vetter { 157f51b7662SDaniel Vetter struct sg_table st; 158f51b7662SDaniel Vetter struct scatterlist *sg; 159f51b7662SDaniel Vetter int i; 160f51b7662SDaniel Vetter 161f51b7662SDaniel Vetter DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); 162f51b7662SDaniel Vetter 163f51b7662SDaniel Vetter if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) 164831cd445SChris Wilson goto err; 165f51b7662SDaniel Vetter 166f51b7662SDaniel Vetter mem->sg_list = sg = st.sgl; 167f51b7662SDaniel Vetter 168f51b7662SDaniel Vetter for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) 169f51b7662SDaniel Vetter sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); 170f51b7662SDaniel Vetter 171f51b7662SDaniel Vetter mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, 172f51b7662SDaniel Vetter mem->page_count, PCI_DMA_BIDIRECTIONAL); 173831cd445SChris Wilson if (unlikely(!mem->num_sg)) 174831cd445SChris Wilson goto err; 175831cd445SChris Wilson 176f51b7662SDaniel Vetter return 0; 177831cd445SChris Wilson 178831cd445SChris Wilson err: 179831cd445SChris Wilson sg_free_table(&st); 180831cd445SChris Wilson return -ENOMEM; 181f51b7662SDaniel Vetter } 182f51b7662SDaniel Vetter 183f51b7662SDaniel Vetter static void intel_agp_unmap_memory(struct agp_memory *mem) 184f51b7662SDaniel Vetter { 185f51b7662SDaniel Vetter DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 186f51b7662SDaniel Vetter 187f51b7662SDaniel Vetter pci_unmap_sg(intel_private.pcidev, mem->sg_list, 188f51b7662SDaniel Vetter mem->page_count, PCI_DMA_BIDIRECTIONAL); 189f51b7662SDaniel Vetter intel_agp_free_sglist(mem); 190f51b7662SDaniel Vetter } 191f51b7662SDaniel Vetter 192f51b7662SDaniel Vetter static void intel_agp_insert_sg_entries(struct agp_memory *mem, 193f51b7662SDaniel Vetter off_t pg_start, int mask_type) 194f51b7662SDaniel Vetter { 195f51b7662SDaniel Vetter struct scatterlist *sg; 196f51b7662SDaniel Vetter int i, j; 197f51b7662SDaniel Vetter 198f51b7662SDaniel Vetter j = pg_start; 199f51b7662SDaniel Vetter 200f51b7662SDaniel Vetter WARN_ON(!mem->num_sg); 201f51b7662SDaniel Vetter 202f51b7662SDaniel Vetter if (mem->num_sg == mem->page_count) { 203f51b7662SDaniel Vetter for_each_sg(mem->sg_list, sg, mem->page_count, i) { 204f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 205f51b7662SDaniel Vetter sg_dma_address(sg), mask_type), 206f51b7662SDaniel Vetter intel_private.gtt+j); 207f51b7662SDaniel Vetter j++; 208f51b7662SDaniel Vetter } 209f51b7662SDaniel Vetter } else { 210f51b7662SDaniel Vetter /* sg may merge pages, but we have to separate 211f51b7662SDaniel Vetter * per-page addr for GTT */ 212f51b7662SDaniel Vetter unsigned int len, m; 213f51b7662SDaniel Vetter 214f51b7662SDaniel Vetter for_each_sg(mem->sg_list, sg, mem->num_sg, i) { 215f51b7662SDaniel Vetter len = sg_dma_len(sg) / PAGE_SIZE; 216f51b7662SDaniel Vetter for (m = 0; m < len; m++) { 217f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 218f51b7662SDaniel Vetter sg_dma_address(sg) + m * PAGE_SIZE, 219f51b7662SDaniel Vetter mask_type), 220f51b7662SDaniel Vetter intel_private.gtt+j); 221f51b7662SDaniel Vetter j++; 222f51b7662SDaniel Vetter } 223f51b7662SDaniel Vetter } 224f51b7662SDaniel Vetter } 225f51b7662SDaniel Vetter readl(intel_private.gtt+j-1); 226f51b7662SDaniel Vetter } 227f51b7662SDaniel Vetter 228f51b7662SDaniel Vetter #else 229f51b7662SDaniel Vetter 230f51b7662SDaniel Vetter static void intel_agp_insert_sg_entries(struct agp_memory *mem, 231f51b7662SDaniel Vetter off_t pg_start, int mask_type) 232f51b7662SDaniel Vetter { 233f51b7662SDaniel Vetter int i, j; 234f51b7662SDaniel Vetter 235f51b7662SDaniel Vetter for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 236f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 237f51b7662SDaniel Vetter page_to_phys(mem->pages[i]), mask_type), 238f51b7662SDaniel Vetter intel_private.gtt+j); 239f51b7662SDaniel Vetter } 240f51b7662SDaniel Vetter 241f51b7662SDaniel Vetter readl(intel_private.gtt+j-1); 242f51b7662SDaniel Vetter } 243f51b7662SDaniel Vetter 244f51b7662SDaniel Vetter #endif 245f51b7662SDaniel Vetter 246f51b7662SDaniel Vetter static int intel_i810_fetch_size(void) 247f51b7662SDaniel Vetter { 248f51b7662SDaniel Vetter u32 smram_miscc; 249f51b7662SDaniel Vetter struct aper_size_info_fixed *values; 250f51b7662SDaniel Vetter 251d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, 252d7cca2f7SDaniel Vetter I810_SMRAM_MISCC, &smram_miscc); 253f51b7662SDaniel Vetter values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 254f51b7662SDaniel Vetter 255f51b7662SDaniel Vetter if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 256d7cca2f7SDaniel Vetter dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n"); 257f51b7662SDaniel Vetter return 0; 258f51b7662SDaniel Vetter } 259f51b7662SDaniel Vetter if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 260f51b7662SDaniel Vetter agp_bridge->current_size = (void *) (values + 1); 261f51b7662SDaniel Vetter agp_bridge->aperture_size_idx = 1; 262f51b7662SDaniel Vetter return values[1].size; 263f51b7662SDaniel Vetter } else { 264f51b7662SDaniel Vetter agp_bridge->current_size = (void *) (values); 265f51b7662SDaniel Vetter agp_bridge->aperture_size_idx = 0; 266f51b7662SDaniel Vetter return values[0].size; 267f51b7662SDaniel Vetter } 268f51b7662SDaniel Vetter 269f51b7662SDaniel Vetter return 0; 270f51b7662SDaniel Vetter } 271f51b7662SDaniel Vetter 272f51b7662SDaniel Vetter static int intel_i810_configure(void) 273f51b7662SDaniel Vetter { 274f51b7662SDaniel Vetter struct aper_size_info_fixed *current_size; 275f51b7662SDaniel Vetter u32 temp; 276f51b7662SDaniel Vetter int i; 277f51b7662SDaniel Vetter 278f51b7662SDaniel Vetter current_size = A_SIZE_FIX(agp_bridge->current_size); 279f51b7662SDaniel Vetter 280f51b7662SDaniel Vetter if (!intel_private.registers) { 281f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); 282f51b7662SDaniel Vetter temp &= 0xfff80000; 283f51b7662SDaniel Vetter 284f51b7662SDaniel Vetter intel_private.registers = ioremap(temp, 128 * 4096); 285f51b7662SDaniel Vetter if (!intel_private.registers) { 286f51b7662SDaniel Vetter dev_err(&intel_private.pcidev->dev, 287f51b7662SDaniel Vetter "can't remap memory\n"); 288f51b7662SDaniel Vetter return -ENOMEM; 289f51b7662SDaniel Vetter } 290f51b7662SDaniel Vetter } 291f51b7662SDaniel Vetter 292f51b7662SDaniel Vetter if ((readl(intel_private.registers+I810_DRAM_CTL) 293f51b7662SDaniel Vetter & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 294f51b7662SDaniel Vetter /* This will need to be dynamically assigned */ 295f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 296f51b7662SDaniel Vetter "detected 4MB dedicated video ram\n"); 297f51b7662SDaniel Vetter intel_private.num_dcache_entries = 1024; 298f51b7662SDaniel Vetter } 299f51b7662SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); 300f51b7662SDaniel Vetter agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 301f51b7662SDaniel Vetter writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); 302f51b7662SDaniel Vetter readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 303f51b7662SDaniel Vetter 304f51b7662SDaniel Vetter if (agp_bridge->driver->needs_scratch_page) { 305f51b7662SDaniel Vetter for (i = 0; i < current_size->num_entries; i++) { 306f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 307f51b7662SDaniel Vetter } 308f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ 309f51b7662SDaniel Vetter } 310f51b7662SDaniel Vetter global_cache_flush(); 311f51b7662SDaniel Vetter return 0; 312f51b7662SDaniel Vetter } 313f51b7662SDaniel Vetter 314f51b7662SDaniel Vetter static void intel_i810_cleanup(void) 315f51b7662SDaniel Vetter { 316f51b7662SDaniel Vetter writel(0, intel_private.registers+I810_PGETBL_CTL); 317f51b7662SDaniel Vetter readl(intel_private.registers); /* PCI Posting. */ 318f51b7662SDaniel Vetter iounmap(intel_private.registers); 319f51b7662SDaniel Vetter } 320f51b7662SDaniel Vetter 321ffdd7510SDaniel Vetter static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) 322f51b7662SDaniel Vetter { 323f51b7662SDaniel Vetter return; 324f51b7662SDaniel Vetter } 325f51b7662SDaniel Vetter 326f51b7662SDaniel Vetter /* Exists to support ARGB cursors */ 327f51b7662SDaniel Vetter static struct page *i8xx_alloc_pages(void) 328f51b7662SDaniel Vetter { 329f51b7662SDaniel Vetter struct page *page; 330f51b7662SDaniel Vetter 331f51b7662SDaniel Vetter page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 332f51b7662SDaniel Vetter if (page == NULL) 333f51b7662SDaniel Vetter return NULL; 334f51b7662SDaniel Vetter 335f51b7662SDaniel Vetter if (set_pages_uc(page, 4) < 0) { 336f51b7662SDaniel Vetter set_pages_wb(page, 4); 337f51b7662SDaniel Vetter __free_pages(page, 2); 338f51b7662SDaniel Vetter return NULL; 339f51b7662SDaniel Vetter } 340f51b7662SDaniel Vetter get_page(page); 341f51b7662SDaniel Vetter atomic_inc(&agp_bridge->current_memory_agp); 342f51b7662SDaniel Vetter return page; 343f51b7662SDaniel Vetter } 344f51b7662SDaniel Vetter 345f51b7662SDaniel Vetter static void i8xx_destroy_pages(struct page *page) 346f51b7662SDaniel Vetter { 347f51b7662SDaniel Vetter if (page == NULL) 348f51b7662SDaniel Vetter return; 349f51b7662SDaniel Vetter 350f51b7662SDaniel Vetter set_pages_wb(page, 4); 351f51b7662SDaniel Vetter put_page(page); 352f51b7662SDaniel Vetter __free_pages(page, 2); 353f51b7662SDaniel Vetter atomic_dec(&agp_bridge->current_memory_agp); 354f51b7662SDaniel Vetter } 355f51b7662SDaniel Vetter 356f51b7662SDaniel Vetter static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 357f51b7662SDaniel Vetter int type) 358f51b7662SDaniel Vetter { 359f51b7662SDaniel Vetter if (type < AGP_USER_TYPES) 360f51b7662SDaniel Vetter return type; 361f51b7662SDaniel Vetter else if (type == AGP_USER_CACHED_MEMORY) 362f51b7662SDaniel Vetter return INTEL_AGP_CACHED_MEMORY; 363f51b7662SDaniel Vetter else 364f51b7662SDaniel Vetter return 0; 365f51b7662SDaniel Vetter } 366f51b7662SDaniel Vetter 367f8f235e5SZhenyu Wang static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge, 368f8f235e5SZhenyu Wang int type) 369f8f235e5SZhenyu Wang { 370f8f235e5SZhenyu Wang unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT; 371f8f235e5SZhenyu Wang unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT; 372f8f235e5SZhenyu Wang 373f8f235e5SZhenyu Wang if (type_mask == AGP_USER_UNCACHED_MEMORY) 374f8f235e5SZhenyu Wang return INTEL_AGP_UNCACHED_MEMORY; 375f8f235e5SZhenyu Wang else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) 376f8f235e5SZhenyu Wang return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT : 377f8f235e5SZhenyu Wang INTEL_AGP_CACHED_MEMORY_LLC_MLC; 378f8f235e5SZhenyu Wang else /* set 'normal'/'cached' to LLC by default */ 379f8f235e5SZhenyu Wang return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT : 380f8f235e5SZhenyu Wang INTEL_AGP_CACHED_MEMORY_LLC; 381f8f235e5SZhenyu Wang } 382f8f235e5SZhenyu Wang 383f8f235e5SZhenyu Wang 384f51b7662SDaniel Vetter static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 385f51b7662SDaniel Vetter int type) 386f51b7662SDaniel Vetter { 387f51b7662SDaniel Vetter int i, j, num_entries; 388f51b7662SDaniel Vetter void *temp; 389f51b7662SDaniel Vetter int ret = -EINVAL; 390f51b7662SDaniel Vetter int mask_type; 391f51b7662SDaniel Vetter 392f51b7662SDaniel Vetter if (mem->page_count == 0) 393f51b7662SDaniel Vetter goto out; 394f51b7662SDaniel Vetter 395f51b7662SDaniel Vetter temp = agp_bridge->current_size; 396f51b7662SDaniel Vetter num_entries = A_SIZE_FIX(temp)->num_entries; 397f51b7662SDaniel Vetter 398f51b7662SDaniel Vetter if ((pg_start + mem->page_count) > num_entries) 399f51b7662SDaniel Vetter goto out_err; 400f51b7662SDaniel Vetter 401f51b7662SDaniel Vetter 402f51b7662SDaniel Vetter for (j = pg_start; j < (pg_start + mem->page_count); j++) { 403f51b7662SDaniel Vetter if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 404f51b7662SDaniel Vetter ret = -EBUSY; 405f51b7662SDaniel Vetter goto out_err; 406f51b7662SDaniel Vetter } 407f51b7662SDaniel Vetter } 408f51b7662SDaniel Vetter 409f51b7662SDaniel Vetter if (type != mem->type) 410f51b7662SDaniel Vetter goto out_err; 411f51b7662SDaniel Vetter 412f51b7662SDaniel Vetter mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 413f51b7662SDaniel Vetter 414f51b7662SDaniel Vetter switch (mask_type) { 415f51b7662SDaniel Vetter case AGP_DCACHE_MEMORY: 416f51b7662SDaniel Vetter if (!mem->is_flushed) 417f51b7662SDaniel Vetter global_cache_flush(); 418f51b7662SDaniel Vetter for (i = pg_start; i < (pg_start + mem->page_count); i++) { 419f51b7662SDaniel Vetter writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, 420f51b7662SDaniel Vetter intel_private.registers+I810_PTE_BASE+(i*4)); 421f51b7662SDaniel Vetter } 422f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 423f51b7662SDaniel Vetter break; 424f51b7662SDaniel Vetter case AGP_PHYS_MEMORY: 425f51b7662SDaniel Vetter case AGP_NORMAL_MEMORY: 426f51b7662SDaniel Vetter if (!mem->is_flushed) 427f51b7662SDaniel Vetter global_cache_flush(); 428f51b7662SDaniel Vetter for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 429f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 430f51b7662SDaniel Vetter page_to_phys(mem->pages[i]), mask_type), 431f51b7662SDaniel Vetter intel_private.registers+I810_PTE_BASE+(j*4)); 432f51b7662SDaniel Vetter } 433f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); 434f51b7662SDaniel Vetter break; 435f51b7662SDaniel Vetter default: 436f51b7662SDaniel Vetter goto out_err; 437f51b7662SDaniel Vetter } 438f51b7662SDaniel Vetter 439f51b7662SDaniel Vetter out: 440f51b7662SDaniel Vetter ret = 0; 441f51b7662SDaniel Vetter out_err: 442f51b7662SDaniel Vetter mem->is_flushed = true; 443f51b7662SDaniel Vetter return ret; 444f51b7662SDaniel Vetter } 445f51b7662SDaniel Vetter 446f51b7662SDaniel Vetter static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 447f51b7662SDaniel Vetter int type) 448f51b7662SDaniel Vetter { 449f51b7662SDaniel Vetter int i; 450f51b7662SDaniel Vetter 451f51b7662SDaniel Vetter if (mem->page_count == 0) 452f51b7662SDaniel Vetter return 0; 453f51b7662SDaniel Vetter 454f51b7662SDaniel Vetter for (i = pg_start; i < (mem->page_count + pg_start); i++) { 455f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); 456f51b7662SDaniel Vetter } 457f51b7662SDaniel Vetter readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); 458f51b7662SDaniel Vetter 459f51b7662SDaniel Vetter return 0; 460f51b7662SDaniel Vetter } 461f51b7662SDaniel Vetter 462f51b7662SDaniel Vetter /* 463f51b7662SDaniel Vetter * The i810/i830 requires a physical address to program its mouse 464f51b7662SDaniel Vetter * pointer into hardware. 465f51b7662SDaniel Vetter * However the Xserver still writes to it through the agp aperture. 466f51b7662SDaniel Vetter */ 467f51b7662SDaniel Vetter static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 468f51b7662SDaniel Vetter { 469f51b7662SDaniel Vetter struct agp_memory *new; 470f51b7662SDaniel Vetter struct page *page; 471f51b7662SDaniel Vetter 472f51b7662SDaniel Vetter switch (pg_count) { 473f51b7662SDaniel Vetter case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 474f51b7662SDaniel Vetter break; 475f51b7662SDaniel Vetter case 4: 476f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 477f51b7662SDaniel Vetter page = i8xx_alloc_pages(); 478f51b7662SDaniel Vetter break; 479f51b7662SDaniel Vetter default: 480f51b7662SDaniel Vetter return NULL; 481f51b7662SDaniel Vetter } 482f51b7662SDaniel Vetter 483f51b7662SDaniel Vetter if (page == NULL) 484f51b7662SDaniel Vetter return NULL; 485f51b7662SDaniel Vetter 486f51b7662SDaniel Vetter new = agp_create_memory(pg_count); 487f51b7662SDaniel Vetter if (new == NULL) 488f51b7662SDaniel Vetter return NULL; 489f51b7662SDaniel Vetter 490f51b7662SDaniel Vetter new->pages[0] = page; 491f51b7662SDaniel Vetter if (pg_count == 4) { 492f51b7662SDaniel Vetter /* kludge to get 4 physical pages for ARGB cursor */ 493f51b7662SDaniel Vetter new->pages[1] = new->pages[0] + 1; 494f51b7662SDaniel Vetter new->pages[2] = new->pages[1] + 1; 495f51b7662SDaniel Vetter new->pages[3] = new->pages[2] + 1; 496f51b7662SDaniel Vetter } 497f51b7662SDaniel Vetter new->page_count = pg_count; 498f51b7662SDaniel Vetter new->num_scratch_pages = pg_count; 499f51b7662SDaniel Vetter new->type = AGP_PHYS_MEMORY; 500f51b7662SDaniel Vetter new->physical = page_to_phys(new->pages[0]); 501f51b7662SDaniel Vetter return new; 502f51b7662SDaniel Vetter } 503f51b7662SDaniel Vetter 504f51b7662SDaniel Vetter static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 505f51b7662SDaniel Vetter { 506f51b7662SDaniel Vetter struct agp_memory *new; 507f51b7662SDaniel Vetter 508f51b7662SDaniel Vetter if (type == AGP_DCACHE_MEMORY) { 509f51b7662SDaniel Vetter if (pg_count != intel_private.num_dcache_entries) 510f51b7662SDaniel Vetter return NULL; 511f51b7662SDaniel Vetter 512f51b7662SDaniel Vetter new = agp_create_memory(1); 513f51b7662SDaniel Vetter if (new == NULL) 514f51b7662SDaniel Vetter return NULL; 515f51b7662SDaniel Vetter 516f51b7662SDaniel Vetter new->type = AGP_DCACHE_MEMORY; 517f51b7662SDaniel Vetter new->page_count = pg_count; 518f51b7662SDaniel Vetter new->num_scratch_pages = 0; 519f51b7662SDaniel Vetter agp_free_page_array(new); 520f51b7662SDaniel Vetter return new; 521f51b7662SDaniel Vetter } 522f51b7662SDaniel Vetter if (type == AGP_PHYS_MEMORY) 523f51b7662SDaniel Vetter return alloc_agpphysmem_i8xx(pg_count, type); 524f51b7662SDaniel Vetter return NULL; 525f51b7662SDaniel Vetter } 526f51b7662SDaniel Vetter 527f51b7662SDaniel Vetter static void intel_i810_free_by_type(struct agp_memory *curr) 528f51b7662SDaniel Vetter { 529f51b7662SDaniel Vetter agp_free_key(curr->key); 530f51b7662SDaniel Vetter if (curr->type == AGP_PHYS_MEMORY) { 531f51b7662SDaniel Vetter if (curr->page_count == 4) 532f51b7662SDaniel Vetter i8xx_destroy_pages(curr->pages[0]); 533f51b7662SDaniel Vetter else { 534f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 535f51b7662SDaniel Vetter AGP_PAGE_DESTROY_UNMAP); 536f51b7662SDaniel Vetter agp_bridge->driver->agp_destroy_page(curr->pages[0], 537f51b7662SDaniel Vetter AGP_PAGE_DESTROY_FREE); 538f51b7662SDaniel Vetter } 539f51b7662SDaniel Vetter agp_free_page_array(curr); 540f51b7662SDaniel Vetter } 541f51b7662SDaniel Vetter kfree(curr); 542f51b7662SDaniel Vetter } 543f51b7662SDaniel Vetter 544f51b7662SDaniel Vetter static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 545f51b7662SDaniel Vetter dma_addr_t addr, int type) 546f51b7662SDaniel Vetter { 547f51b7662SDaniel Vetter /* Type checking must be done elsewhere */ 548f51b7662SDaniel Vetter return addr | bridge->driver->masks[type].mask; 549f51b7662SDaniel Vetter } 550f51b7662SDaniel Vetter 5510e87d2b0SDaniel Vetter static int intel_gtt_setup_scratch_page(void) 5520e87d2b0SDaniel Vetter { 5530e87d2b0SDaniel Vetter struct page *page; 5540e87d2b0SDaniel Vetter dma_addr_t dma_addr; 5550e87d2b0SDaniel Vetter 5560e87d2b0SDaniel Vetter page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); 5570e87d2b0SDaniel Vetter if (page == NULL) 5580e87d2b0SDaniel Vetter return -ENOMEM; 5590e87d2b0SDaniel Vetter get_page(page); 5600e87d2b0SDaniel Vetter set_pages_uc(page, 1); 5610e87d2b0SDaniel Vetter 5620e87d2b0SDaniel Vetter if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) { 5630e87d2b0SDaniel Vetter dma_addr = pci_map_page(intel_private.pcidev, page, 0, 5640e87d2b0SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 5650e87d2b0SDaniel Vetter if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) 5660e87d2b0SDaniel Vetter return -EINVAL; 5670e87d2b0SDaniel Vetter 5680e87d2b0SDaniel Vetter intel_private.scratch_page_dma = dma_addr; 5690e87d2b0SDaniel Vetter } else 5700e87d2b0SDaniel Vetter intel_private.scratch_page_dma = page_to_phys(page); 5710e87d2b0SDaniel Vetter 5720e87d2b0SDaniel Vetter intel_private.scratch_page = page; 5730e87d2b0SDaniel Vetter 5740e87d2b0SDaniel Vetter return 0; 5750e87d2b0SDaniel Vetter } 5760e87d2b0SDaniel Vetter 5779e76e7b8SChris Wilson static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = { 578f51b7662SDaniel Vetter {128, 32768, 5}, 579f51b7662SDaniel Vetter /* The 64M mode still requires a 128k gatt */ 580f51b7662SDaniel Vetter {64, 16384, 5}, 581f51b7662SDaniel Vetter {256, 65536, 6}, 582f51b7662SDaniel Vetter {512, 131072, 7}, 583f51b7662SDaniel Vetter }; 584f51b7662SDaniel Vetter 585bfde067bSDaniel Vetter static unsigned int intel_gtt_stolen_entries(void) 586f51b7662SDaniel Vetter { 587f51b7662SDaniel Vetter u16 gmch_ctrl; 588f51b7662SDaniel Vetter u8 rdct; 589f51b7662SDaniel Vetter int local = 0; 590f51b7662SDaniel Vetter static const int ddt[4] = { 0, 16, 32, 64 }; 591d8d9abcdSDaniel Vetter unsigned int overhead_entries, stolen_entries; 592d8d9abcdSDaniel Vetter unsigned int stolen_size = 0; 593f51b7662SDaniel Vetter 594d7cca2f7SDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 595d7cca2f7SDaniel Vetter I830_GMCH_CTRL, &gmch_ctrl); 596f51b7662SDaniel Vetter 5971a997ff2SDaniel Vetter if (INTEL_GTT_GEN > 4 || IS_PINEVIEW) 598fbe40783SDaniel Vetter overhead_entries = 0; 599fbe40783SDaniel Vetter else 600fbe40783SDaniel Vetter overhead_entries = intel_private.base.gtt_mappable_entries 601fbe40783SDaniel Vetter / 1024; 602f51b7662SDaniel Vetter 603fbe40783SDaniel Vetter overhead_entries += 1; /* BIOS popup */ 604d8d9abcdSDaniel Vetter 605d7cca2f7SDaniel Vetter if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 606d7cca2f7SDaniel Vetter intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 607f51b7662SDaniel Vetter switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 608f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_512: 609d8d9abcdSDaniel Vetter stolen_size = KB(512); 610f51b7662SDaniel Vetter break; 611f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_1024: 612d8d9abcdSDaniel Vetter stolen_size = MB(1); 613f51b7662SDaniel Vetter break; 614f51b7662SDaniel Vetter case I830_GMCH_GMS_STOLEN_8192: 615d8d9abcdSDaniel Vetter stolen_size = MB(8); 616f51b7662SDaniel Vetter break; 617f51b7662SDaniel Vetter case I830_GMCH_GMS_LOCAL: 618f51b7662SDaniel Vetter rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 619d8d9abcdSDaniel Vetter stolen_size = (I830_RDRAM_ND(rdct) + 1) * 620f51b7662SDaniel Vetter MB(ddt[I830_RDRAM_DDT(rdct)]); 621f51b7662SDaniel Vetter local = 1; 622f51b7662SDaniel Vetter break; 623f51b7662SDaniel Vetter default: 624d8d9abcdSDaniel Vetter stolen_size = 0; 625f51b7662SDaniel Vetter break; 626f51b7662SDaniel Vetter } 6271a997ff2SDaniel Vetter } else if (INTEL_GTT_GEN == 6) { 628f51b7662SDaniel Vetter /* 629f51b7662SDaniel Vetter * SandyBridge has new memory control reg at 0x50.w 630f51b7662SDaniel Vetter */ 631f51b7662SDaniel Vetter u16 snb_gmch_ctl; 632f51b7662SDaniel Vetter pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 633f51b7662SDaniel Vetter switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { 634f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_32M: 635d8d9abcdSDaniel Vetter stolen_size = MB(32); 636f51b7662SDaniel Vetter break; 637f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_64M: 638d8d9abcdSDaniel Vetter stolen_size = MB(64); 639f51b7662SDaniel Vetter break; 640f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_96M: 641d8d9abcdSDaniel Vetter stolen_size = MB(96); 642f51b7662SDaniel Vetter break; 643f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_128M: 644d8d9abcdSDaniel Vetter stolen_size = MB(128); 645f51b7662SDaniel Vetter break; 646f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_160M: 647d8d9abcdSDaniel Vetter stolen_size = MB(160); 648f51b7662SDaniel Vetter break; 649f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_192M: 650d8d9abcdSDaniel Vetter stolen_size = MB(192); 651f51b7662SDaniel Vetter break; 652f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_224M: 653d8d9abcdSDaniel Vetter stolen_size = MB(224); 654f51b7662SDaniel Vetter break; 655f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_256M: 656d8d9abcdSDaniel Vetter stolen_size = MB(256); 657f51b7662SDaniel Vetter break; 658f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_288M: 659d8d9abcdSDaniel Vetter stolen_size = MB(288); 660f51b7662SDaniel Vetter break; 661f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_320M: 662d8d9abcdSDaniel Vetter stolen_size = MB(320); 663f51b7662SDaniel Vetter break; 664f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_352M: 665d8d9abcdSDaniel Vetter stolen_size = MB(352); 666f51b7662SDaniel Vetter break; 667f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_384M: 668d8d9abcdSDaniel Vetter stolen_size = MB(384); 669f51b7662SDaniel Vetter break; 670f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_416M: 671d8d9abcdSDaniel Vetter stolen_size = MB(416); 672f51b7662SDaniel Vetter break; 673f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_448M: 674d8d9abcdSDaniel Vetter stolen_size = MB(448); 675f51b7662SDaniel Vetter break; 676f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_480M: 677d8d9abcdSDaniel Vetter stolen_size = MB(480); 678f51b7662SDaniel Vetter break; 679f51b7662SDaniel Vetter case SNB_GMCH_GMS_STOLEN_512M: 680d8d9abcdSDaniel Vetter stolen_size = MB(512); 681f51b7662SDaniel Vetter break; 682f51b7662SDaniel Vetter } 683f51b7662SDaniel Vetter } else { 684f51b7662SDaniel Vetter switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 685f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_1M: 686d8d9abcdSDaniel Vetter stolen_size = MB(1); 687f51b7662SDaniel Vetter break; 688f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_4M: 689d8d9abcdSDaniel Vetter stolen_size = MB(4); 690f51b7662SDaniel Vetter break; 691f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_8M: 692d8d9abcdSDaniel Vetter stolen_size = MB(8); 693f51b7662SDaniel Vetter break; 694f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_16M: 695d8d9abcdSDaniel Vetter stolen_size = MB(16); 696f51b7662SDaniel Vetter break; 697f51b7662SDaniel Vetter case I855_GMCH_GMS_STOLEN_32M: 698d8d9abcdSDaniel Vetter stolen_size = MB(32); 699f51b7662SDaniel Vetter break; 700f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_48M: 701d8d9abcdSDaniel Vetter stolen_size = MB(48); 702f51b7662SDaniel Vetter break; 703f51b7662SDaniel Vetter case I915_GMCH_GMS_STOLEN_64M: 704d8d9abcdSDaniel Vetter stolen_size = MB(64); 705f51b7662SDaniel Vetter break; 706f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_128M: 707d8d9abcdSDaniel Vetter stolen_size = MB(128); 708f51b7662SDaniel Vetter break; 709f51b7662SDaniel Vetter case G33_GMCH_GMS_STOLEN_256M: 710d8d9abcdSDaniel Vetter stolen_size = MB(256); 711f51b7662SDaniel Vetter break; 712f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_96M: 713d8d9abcdSDaniel Vetter stolen_size = MB(96); 714f51b7662SDaniel Vetter break; 715f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_160M: 716d8d9abcdSDaniel Vetter stolen_size = MB(160); 717f51b7662SDaniel Vetter break; 718f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_224M: 719d8d9abcdSDaniel Vetter stolen_size = MB(224); 720f51b7662SDaniel Vetter break; 721f51b7662SDaniel Vetter case INTEL_GMCH_GMS_STOLEN_352M: 722d8d9abcdSDaniel Vetter stolen_size = MB(352); 723f51b7662SDaniel Vetter break; 724f51b7662SDaniel Vetter default: 725d8d9abcdSDaniel Vetter stolen_size = 0; 726f51b7662SDaniel Vetter break; 727f51b7662SDaniel Vetter } 728f51b7662SDaniel Vetter } 7291784a5fbSDaniel Vetter 730d8d9abcdSDaniel Vetter if (!local && stolen_size > intel_max_stolen) { 731d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, 732d1d6ca73SJesse Barnes "detected %dK stolen memory, trimming to %dK\n", 733d8d9abcdSDaniel Vetter stolen_size / KB(1), intel_max_stolen / KB(1)); 734d8d9abcdSDaniel Vetter stolen_size = intel_max_stolen; 735d8d9abcdSDaniel Vetter } else if (stolen_size > 0) { 736d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", 737d8d9abcdSDaniel Vetter stolen_size / KB(1), local ? "local" : "stolen"); 738f51b7662SDaniel Vetter } else { 739d7cca2f7SDaniel Vetter dev_info(&intel_private.bridge_dev->dev, 740f51b7662SDaniel Vetter "no pre-allocated video memory detected\n"); 741d8d9abcdSDaniel Vetter stolen_size = 0; 742f51b7662SDaniel Vetter } 743f51b7662SDaniel Vetter 744d8d9abcdSDaniel Vetter stolen_entries = stolen_size/KB(4) - overhead_entries; 745d8d9abcdSDaniel Vetter 746d8d9abcdSDaniel Vetter return stolen_entries; 747f51b7662SDaniel Vetter } 748f51b7662SDaniel Vetter 749fbe40783SDaniel Vetter static unsigned int intel_gtt_total_entries(void) 750fbe40783SDaniel Vetter { 751fbe40783SDaniel Vetter int size; 752fbe40783SDaniel Vetter 753210b23c2SDaniel Vetter if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) { 754fbe40783SDaniel Vetter u32 pgetbl_ctl; 755fbe40783SDaniel Vetter pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 756fbe40783SDaniel Vetter 757fbe40783SDaniel Vetter switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 758fbe40783SDaniel Vetter case I965_PGETBL_SIZE_128KB: 759e5e408fcSDaniel Vetter size = KB(128); 760fbe40783SDaniel Vetter break; 761fbe40783SDaniel Vetter case I965_PGETBL_SIZE_256KB: 762e5e408fcSDaniel Vetter size = KB(256); 763fbe40783SDaniel Vetter break; 764fbe40783SDaniel Vetter case I965_PGETBL_SIZE_512KB: 765e5e408fcSDaniel Vetter size = KB(512); 766fbe40783SDaniel Vetter break; 767fbe40783SDaniel Vetter case I965_PGETBL_SIZE_1MB: 768e5e408fcSDaniel Vetter size = KB(1024); 769fbe40783SDaniel Vetter break; 770fbe40783SDaniel Vetter case I965_PGETBL_SIZE_2MB: 771e5e408fcSDaniel Vetter size = KB(2048); 772fbe40783SDaniel Vetter break; 773fbe40783SDaniel Vetter case I965_PGETBL_SIZE_1_5MB: 774e5e408fcSDaniel Vetter size = KB(1024 + 512); 775fbe40783SDaniel Vetter break; 776fbe40783SDaniel Vetter default: 777fbe40783SDaniel Vetter dev_info(&intel_private.pcidev->dev, 778fbe40783SDaniel Vetter "unknown page table size, assuming 512KB\n"); 779e5e408fcSDaniel Vetter size = KB(512); 780fbe40783SDaniel Vetter } 781e5e408fcSDaniel Vetter 782e5e408fcSDaniel Vetter return size/4; 783210b23c2SDaniel Vetter } else if (INTEL_GTT_GEN == 6) { 784210b23c2SDaniel Vetter u16 snb_gmch_ctl; 785210b23c2SDaniel Vetter 786210b23c2SDaniel Vetter pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 787210b23c2SDaniel Vetter switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { 788210b23c2SDaniel Vetter default: 789210b23c2SDaniel Vetter case SNB_GTT_SIZE_0M: 790210b23c2SDaniel Vetter printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); 791210b23c2SDaniel Vetter size = MB(0); 792210b23c2SDaniel Vetter break; 793210b23c2SDaniel Vetter case SNB_GTT_SIZE_1M: 794210b23c2SDaniel Vetter size = MB(1); 795210b23c2SDaniel Vetter break; 796210b23c2SDaniel Vetter case SNB_GTT_SIZE_2M: 797210b23c2SDaniel Vetter size = MB(2); 798210b23c2SDaniel Vetter break; 799210b23c2SDaniel Vetter } 800210b23c2SDaniel Vetter return size/4; 801fbe40783SDaniel Vetter } else { 802fbe40783SDaniel Vetter /* On previous hardware, the GTT size was just what was 803fbe40783SDaniel Vetter * required to map the aperture. 804fbe40783SDaniel Vetter */ 805e5e408fcSDaniel Vetter return intel_private.base.gtt_mappable_entries; 806fbe40783SDaniel Vetter } 807fbe40783SDaniel Vetter } 808fbe40783SDaniel Vetter 8091784a5fbSDaniel Vetter static unsigned int intel_gtt_mappable_entries(void) 8101784a5fbSDaniel Vetter { 8111784a5fbSDaniel Vetter unsigned int aperture_size; 8121784a5fbSDaniel Vetter 813b1c5b0f8SChris Wilson if (INTEL_GTT_GEN == 2) { 814b1c5b0f8SChris Wilson u16 gmch_ctrl; 8151784a5fbSDaniel Vetter 8161784a5fbSDaniel Vetter pci_read_config_word(intel_private.bridge_dev, 8171784a5fbSDaniel Vetter I830_GMCH_CTRL, &gmch_ctrl); 8181784a5fbSDaniel Vetter 8191784a5fbSDaniel Vetter if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) 820b1c5b0f8SChris Wilson aperture_size = MB(64); 8211784a5fbSDaniel Vetter else 822b1c5b0f8SChris Wilson aperture_size = MB(128); 823239918f7SDaniel Vetter } else { 8241784a5fbSDaniel Vetter /* 9xx supports large sizes, just look at the length */ 8251784a5fbSDaniel Vetter aperture_size = pci_resource_len(intel_private.pcidev, 2); 8261784a5fbSDaniel Vetter } 8271784a5fbSDaniel Vetter 8281784a5fbSDaniel Vetter return aperture_size >> PAGE_SHIFT; 8291784a5fbSDaniel Vetter } 8301784a5fbSDaniel Vetter 8310e87d2b0SDaniel Vetter static void intel_gtt_teardown_scratch_page(void) 8320e87d2b0SDaniel Vetter { 8330e87d2b0SDaniel Vetter set_pages_wb(intel_private.scratch_page, 1); 8340e87d2b0SDaniel Vetter pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, 8350e87d2b0SDaniel Vetter PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 8360e87d2b0SDaniel Vetter put_page(intel_private.scratch_page); 8370e87d2b0SDaniel Vetter __free_page(intel_private.scratch_page); 8380e87d2b0SDaniel Vetter } 8390e87d2b0SDaniel Vetter 8400e87d2b0SDaniel Vetter static void intel_gtt_cleanup(void) 8410e87d2b0SDaniel Vetter { 8420e87d2b0SDaniel Vetter if (intel_private.i9xx_flush_page) 8430e87d2b0SDaniel Vetter iounmap(intel_private.i9xx_flush_page); 8440e87d2b0SDaniel Vetter if (intel_private.resource_valid) 8450e87d2b0SDaniel Vetter release_resource(&intel_private.ifp_resource); 8460e87d2b0SDaniel Vetter intel_private.ifp_resource.start = 0; 8470e87d2b0SDaniel Vetter intel_private.resource_valid = 0; 8480e87d2b0SDaniel Vetter iounmap(intel_private.gtt); 8490e87d2b0SDaniel Vetter iounmap(intel_private.registers); 8500e87d2b0SDaniel Vetter 8510e87d2b0SDaniel Vetter intel_gtt_teardown_scratch_page(); 8520e87d2b0SDaniel Vetter } 8530e87d2b0SDaniel Vetter 8541784a5fbSDaniel Vetter static int intel_gtt_init(void) 8551784a5fbSDaniel Vetter { 856f67eab66SDaniel Vetter u32 gtt_map_size; 8573b15a9d7SDaniel Vetter int ret; 8583b15a9d7SDaniel Vetter 8593b15a9d7SDaniel Vetter ret = intel_private.driver->setup(); 8603b15a9d7SDaniel Vetter if (ret != 0) 8613b15a9d7SDaniel Vetter return ret; 862f67eab66SDaniel Vetter 863f67eab66SDaniel Vetter intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); 864f67eab66SDaniel Vetter intel_private.base.gtt_total_entries = intel_gtt_total_entries(); 865f67eab66SDaniel Vetter 866f67eab66SDaniel Vetter gtt_map_size = intel_private.base.gtt_total_entries * 4; 867f67eab66SDaniel Vetter 868f67eab66SDaniel Vetter intel_private.gtt = ioremap(intel_private.gtt_bus_addr, 869f67eab66SDaniel Vetter gtt_map_size); 870f67eab66SDaniel Vetter if (!intel_private.gtt) { 871f67eab66SDaniel Vetter iounmap(intel_private.registers); 872f67eab66SDaniel Vetter return -ENOMEM; 873f67eab66SDaniel Vetter } 874f67eab66SDaniel Vetter 875f67eab66SDaniel Vetter global_cache_flush(); /* FIXME: ? */ 876f67eab66SDaniel Vetter 8771784a5fbSDaniel Vetter /* we have to call this as early as possible after the MMIO base address is known */ 8781784a5fbSDaniel Vetter intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries(); 8791784a5fbSDaniel Vetter if (intel_private.base.gtt_stolen_entries == 0) { 8801784a5fbSDaniel Vetter iounmap(intel_private.registers); 881f67eab66SDaniel Vetter iounmap(intel_private.gtt); 8821784a5fbSDaniel Vetter return -ENOMEM; 8831784a5fbSDaniel Vetter } 8841784a5fbSDaniel Vetter 8850e87d2b0SDaniel Vetter ret = intel_gtt_setup_scratch_page(); 8860e87d2b0SDaniel Vetter if (ret != 0) { 8870e87d2b0SDaniel Vetter intel_gtt_cleanup(); 8880e87d2b0SDaniel Vetter return ret; 8890e87d2b0SDaniel Vetter } 8900e87d2b0SDaniel Vetter 8911784a5fbSDaniel Vetter return 0; 8921784a5fbSDaniel Vetter } 8931784a5fbSDaniel Vetter 8943e921f98SDaniel Vetter static int intel_fake_agp_fetch_size(void) 8953e921f98SDaniel Vetter { 8969e76e7b8SChris Wilson int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); 8973e921f98SDaniel Vetter unsigned int aper_size; 8983e921f98SDaniel Vetter int i; 8993e921f98SDaniel Vetter 9003e921f98SDaniel Vetter aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) 9013e921f98SDaniel Vetter / MB(1); 9023e921f98SDaniel Vetter 9033e921f98SDaniel Vetter for (i = 0; i < num_sizes; i++) { 904ffdd7510SDaniel Vetter if (aper_size == intel_fake_agp_sizes[i].size) { 9059e76e7b8SChris Wilson agp_bridge->current_size = 9069e76e7b8SChris Wilson (void *) (intel_fake_agp_sizes + i); 9073e921f98SDaniel Vetter return aper_size; 9083e921f98SDaniel Vetter } 9093e921f98SDaniel Vetter } 9103e921f98SDaniel Vetter 9113e921f98SDaniel Vetter return 0; 9123e921f98SDaniel Vetter } 9133e921f98SDaniel Vetter 914f51b7662SDaniel Vetter static void intel_i830_fini_flush(void) 915f51b7662SDaniel Vetter { 916f51b7662SDaniel Vetter kunmap(intel_private.i8xx_page); 917f51b7662SDaniel Vetter intel_private.i8xx_flush_page = NULL; 918f51b7662SDaniel Vetter unmap_page_from_agp(intel_private.i8xx_page); 919f51b7662SDaniel Vetter 920f51b7662SDaniel Vetter __free_page(intel_private.i8xx_page); 921f51b7662SDaniel Vetter intel_private.i8xx_page = NULL; 922f51b7662SDaniel Vetter } 923f51b7662SDaniel Vetter 924f51b7662SDaniel Vetter static void intel_i830_setup_flush(void) 925f51b7662SDaniel Vetter { 926f51b7662SDaniel Vetter /* return if we've already set the flush mechanism up */ 927f51b7662SDaniel Vetter if (intel_private.i8xx_page) 928f51b7662SDaniel Vetter return; 929f51b7662SDaniel Vetter 930f51b7662SDaniel Vetter intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); 931f51b7662SDaniel Vetter if (!intel_private.i8xx_page) 932f51b7662SDaniel Vetter return; 933f51b7662SDaniel Vetter 934f51b7662SDaniel Vetter intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); 935f51b7662SDaniel Vetter if (!intel_private.i8xx_flush_page) 936f51b7662SDaniel Vetter intel_i830_fini_flush(); 937f51b7662SDaniel Vetter } 938f51b7662SDaniel Vetter 939f51b7662SDaniel Vetter /* The chipset_flush interface needs to get data that has already been 940f51b7662SDaniel Vetter * flushed out of the CPU all the way out to main memory, because the GPU 941f51b7662SDaniel Vetter * doesn't snoop those buffers. 942f51b7662SDaniel Vetter * 943f51b7662SDaniel Vetter * The 8xx series doesn't have the same lovely interface for flushing the 944f51b7662SDaniel Vetter * chipset write buffers that the later chips do. According to the 865 945f51b7662SDaniel Vetter * specs, it's 64 octwords, or 1KB. So, to get those previous things in 946f51b7662SDaniel Vetter * that buffer out, we just fill 1KB and clflush it out, on the assumption 947f51b7662SDaniel Vetter * that it'll push whatever was in there out. It appears to work. 948f51b7662SDaniel Vetter */ 949f51b7662SDaniel Vetter static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) 950f51b7662SDaniel Vetter { 951f51b7662SDaniel Vetter unsigned int *pg = intel_private.i8xx_flush_page; 952f51b7662SDaniel Vetter 953f51b7662SDaniel Vetter memset(pg, 0, 1024); 954f51b7662SDaniel Vetter 955f51b7662SDaniel Vetter if (cpu_has_clflush) 956f51b7662SDaniel Vetter clflush_cache_range(pg, 1024); 957f51b7662SDaniel Vetter else if (wbinvd_on_all_cpus() != 0) 958f51b7662SDaniel Vetter printk(KERN_ERR "Timed out waiting for cache flush.\n"); 959f51b7662SDaniel Vetter } 960f51b7662SDaniel Vetter 961*351bb278SDaniel Vetter static void i830_write_entry(dma_addr_t addr, unsigned int entry, 962*351bb278SDaniel Vetter unsigned int flags) 963*351bb278SDaniel Vetter { 964*351bb278SDaniel Vetter u32 pte_flags = I810_PTE_VALID; 965*351bb278SDaniel Vetter 966*351bb278SDaniel Vetter switch (flags) { 967*351bb278SDaniel Vetter case AGP_DCACHE_MEMORY: 968*351bb278SDaniel Vetter pte_flags |= I810_PTE_LOCAL; 969*351bb278SDaniel Vetter break; 970*351bb278SDaniel Vetter case AGP_USER_CACHED_MEMORY: 971*351bb278SDaniel Vetter pte_flags |= I830_PTE_SYSTEM_CACHED; 972*351bb278SDaniel Vetter break; 973*351bb278SDaniel Vetter } 974*351bb278SDaniel Vetter 975*351bb278SDaniel Vetter writel(addr | pte_flags, intel_private.gtt + entry); 976*351bb278SDaniel Vetter } 977*351bb278SDaniel Vetter 97873800422SDaniel Vetter static void intel_enable_gtt(void) 97973800422SDaniel Vetter { 9803f08e4efSChris Wilson u32 gma_addr; 98173800422SDaniel Vetter u16 gmch_ctrl; 98273800422SDaniel Vetter 9832d2430cfSDaniel Vetter if (INTEL_GTT_GEN == 2) 9842d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_GMADDR, 9852d2430cfSDaniel Vetter &gma_addr); 9862d2430cfSDaniel Vetter else 9872d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_GMADDR, 9882d2430cfSDaniel Vetter &gma_addr); 9892d2430cfSDaniel Vetter 99073800422SDaniel Vetter intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); 99173800422SDaniel Vetter 99273800422SDaniel Vetter pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl); 99373800422SDaniel Vetter gmch_ctrl |= I830_GMCH_ENABLED; 99473800422SDaniel Vetter pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl); 99573800422SDaniel Vetter 9963f08e4efSChris Wilson writel(intel_private.pte_bus_addr|I810_PGETBL_ENABLED, 9973f08e4efSChris Wilson intel_private.registers+I810_PGETBL_CTL); 99873800422SDaniel Vetter readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 99973800422SDaniel Vetter } 100073800422SDaniel Vetter 100173800422SDaniel Vetter static int i830_setup(void) 100273800422SDaniel Vetter { 100373800422SDaniel Vetter u32 reg_addr; 100473800422SDaniel Vetter 100573800422SDaniel Vetter pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 100673800422SDaniel Vetter reg_addr &= 0xfff80000; 100773800422SDaniel Vetter 100873800422SDaniel Vetter intel_private.registers = ioremap(reg_addr, KB(64)); 100973800422SDaniel Vetter if (!intel_private.registers) 101073800422SDaniel Vetter return -ENOMEM; 101173800422SDaniel Vetter 101273800422SDaniel Vetter intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 10133f08e4efSChris Wilson intel_private.pte_bus_addr = 10143f08e4efSChris Wilson readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 101573800422SDaniel Vetter 101673800422SDaniel Vetter intel_i830_setup_flush(); 101773800422SDaniel Vetter 101873800422SDaniel Vetter return 0; 101973800422SDaniel Vetter } 102073800422SDaniel Vetter 10213b15a9d7SDaniel Vetter static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) 1022f51b7662SDaniel Vetter { 102373800422SDaniel Vetter agp_bridge->gatt_table_real = NULL; 1024f51b7662SDaniel Vetter agp_bridge->gatt_table = NULL; 102573800422SDaniel Vetter agp_bridge->gatt_bus_addr = 0; 1026f51b7662SDaniel Vetter 1027f51b7662SDaniel Vetter return 0; 1028f51b7662SDaniel Vetter } 1029f51b7662SDaniel Vetter 1030ffdd7510SDaniel Vetter static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) 1031f51b7662SDaniel Vetter { 1032f51b7662SDaniel Vetter return 0; 1033f51b7662SDaniel Vetter } 1034f51b7662SDaniel Vetter 1035*351bb278SDaniel Vetter static int intel_fake_agp_configure(void) 1036f51b7662SDaniel Vetter { 1037f51b7662SDaniel Vetter int i; 1038f51b7662SDaniel Vetter 103973800422SDaniel Vetter intel_enable_gtt(); 1040f51b7662SDaniel Vetter 104173800422SDaniel Vetter agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 1042f51b7662SDaniel Vetter 104373800422SDaniel Vetter for (i = intel_private.base.gtt_stolen_entries; 104473800422SDaniel Vetter i < intel_private.base.gtt_total_entries; i++) { 1045*351bb278SDaniel Vetter intel_private.driver->write_entry(intel_private.scratch_page_dma, 1046*351bb278SDaniel Vetter i, 0); 1047f51b7662SDaniel Vetter } 1048fdfb58a9SDaniel Vetter readl(intel_private.gtt+i-1); /* PCI Posting. */ 1049f51b7662SDaniel Vetter 1050f51b7662SDaniel Vetter global_cache_flush(); 1051f51b7662SDaniel Vetter 1052f51b7662SDaniel Vetter return 0; 1053f51b7662SDaniel Vetter } 1054f51b7662SDaniel Vetter 1055f51b7662SDaniel Vetter static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, 1056f51b7662SDaniel Vetter int type) 1057f51b7662SDaniel Vetter { 1058f51b7662SDaniel Vetter int i, j, num_entries; 1059f51b7662SDaniel Vetter void *temp; 1060f51b7662SDaniel Vetter int ret = -EINVAL; 1061f51b7662SDaniel Vetter int mask_type; 1062f51b7662SDaniel Vetter 1063f51b7662SDaniel Vetter if (mem->page_count == 0) 1064f51b7662SDaniel Vetter goto out; 1065f51b7662SDaniel Vetter 1066f51b7662SDaniel Vetter temp = agp_bridge->current_size; 1067f51b7662SDaniel Vetter num_entries = A_SIZE_FIX(temp)->num_entries; 1068f51b7662SDaniel Vetter 10690ade6386SDaniel Vetter if (pg_start < intel_private.base.gtt_stolen_entries) { 1070f51b7662SDaniel Vetter dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 10710ade6386SDaniel Vetter "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n", 10720ade6386SDaniel Vetter pg_start, intel_private.base.gtt_stolen_entries); 1073f51b7662SDaniel Vetter 1074f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1075f51b7662SDaniel Vetter "trying to insert into local/stolen memory\n"); 1076f51b7662SDaniel Vetter goto out_err; 1077f51b7662SDaniel Vetter } 1078f51b7662SDaniel Vetter 1079f51b7662SDaniel Vetter if ((pg_start + mem->page_count) > num_entries) 1080f51b7662SDaniel Vetter goto out_err; 1081f51b7662SDaniel Vetter 1082f51b7662SDaniel Vetter /* The i830 can't check the GTT for entries since its read only, 1083f51b7662SDaniel Vetter * depend on the caller to make the correct offset decisions. 1084f51b7662SDaniel Vetter */ 1085f51b7662SDaniel Vetter 1086f51b7662SDaniel Vetter if (type != mem->type) 1087f51b7662SDaniel Vetter goto out_err; 1088f51b7662SDaniel Vetter 1089f51b7662SDaniel Vetter mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1090f51b7662SDaniel Vetter 1091f51b7662SDaniel Vetter if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 1092f51b7662SDaniel Vetter mask_type != INTEL_AGP_CACHED_MEMORY) 1093f51b7662SDaniel Vetter goto out_err; 1094f51b7662SDaniel Vetter 1095f51b7662SDaniel Vetter if (!mem->is_flushed) 1096f51b7662SDaniel Vetter global_cache_flush(); 1097f51b7662SDaniel Vetter 1098f51b7662SDaniel Vetter for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 1099f51b7662SDaniel Vetter writel(agp_bridge->driver->mask_memory(agp_bridge, 1100f51b7662SDaniel Vetter page_to_phys(mem->pages[i]), mask_type), 1101fdfb58a9SDaniel Vetter intel_private.gtt+j); 1102f51b7662SDaniel Vetter } 1103fdfb58a9SDaniel Vetter readl(intel_private.gtt+j-1); 1104f51b7662SDaniel Vetter 1105f51b7662SDaniel Vetter out: 1106f51b7662SDaniel Vetter ret = 0; 1107f51b7662SDaniel Vetter out_err: 1108f51b7662SDaniel Vetter mem->is_flushed = true; 1109f51b7662SDaniel Vetter return ret; 1110f51b7662SDaniel Vetter } 1111f51b7662SDaniel Vetter 1112f51b7662SDaniel Vetter static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, 1113f51b7662SDaniel Vetter int type) 1114f51b7662SDaniel Vetter { 1115f51b7662SDaniel Vetter int i; 1116f51b7662SDaniel Vetter 1117f51b7662SDaniel Vetter if (mem->page_count == 0) 1118f51b7662SDaniel Vetter return 0; 1119f51b7662SDaniel Vetter 11200ade6386SDaniel Vetter if (pg_start < intel_private.base.gtt_stolen_entries) { 1121f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1122f51b7662SDaniel Vetter "trying to disable local/stolen memory\n"); 1123f51b7662SDaniel Vetter return -EINVAL; 1124f51b7662SDaniel Vetter } 1125f51b7662SDaniel Vetter 1126f51b7662SDaniel Vetter for (i = pg_start; i < (mem->page_count + pg_start); i++) { 1127fdfb58a9SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.gtt+i); 1128f51b7662SDaniel Vetter } 1129fdfb58a9SDaniel Vetter readl(intel_private.gtt+i-1); 1130f51b7662SDaniel Vetter 1131f51b7662SDaniel Vetter return 0; 1132f51b7662SDaniel Vetter } 1133f51b7662SDaniel Vetter 1134ffdd7510SDaniel Vetter static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, 1135ffdd7510SDaniel Vetter int type) 1136f51b7662SDaniel Vetter { 1137f51b7662SDaniel Vetter if (type == AGP_PHYS_MEMORY) 1138f51b7662SDaniel Vetter return alloc_agpphysmem_i8xx(pg_count, type); 1139f51b7662SDaniel Vetter /* always return NULL for other allocation types for now */ 1140f51b7662SDaniel Vetter return NULL; 1141f51b7662SDaniel Vetter } 1142f51b7662SDaniel Vetter 1143f51b7662SDaniel Vetter static int intel_alloc_chipset_flush_resource(void) 1144f51b7662SDaniel Vetter { 1145f51b7662SDaniel Vetter int ret; 1146d7cca2f7SDaniel Vetter ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 1147f51b7662SDaniel Vetter PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 1148d7cca2f7SDaniel Vetter pcibios_align_resource, intel_private.bridge_dev); 1149f51b7662SDaniel Vetter 1150f51b7662SDaniel Vetter return ret; 1151f51b7662SDaniel Vetter } 1152f51b7662SDaniel Vetter 1153f51b7662SDaniel Vetter static void intel_i915_setup_chipset_flush(void) 1154f51b7662SDaniel Vetter { 1155f51b7662SDaniel Vetter int ret; 1156f51b7662SDaniel Vetter u32 temp; 1157f51b7662SDaniel Vetter 1158d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); 1159f51b7662SDaniel Vetter if (!(temp & 0x1)) { 1160f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 1161f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1162d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1163f51b7662SDaniel Vetter } else { 1164f51b7662SDaniel Vetter temp &= ~1; 1165f51b7662SDaniel Vetter 1166f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1167f51b7662SDaniel Vetter intel_private.ifp_resource.start = temp; 1168f51b7662SDaniel Vetter intel_private.ifp_resource.end = temp + PAGE_SIZE; 1169f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1170f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 1171f51b7662SDaniel Vetter if (ret) 1172f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1173f51b7662SDaniel Vetter } 1174f51b7662SDaniel Vetter } 1175f51b7662SDaniel Vetter 1176f51b7662SDaniel Vetter static void intel_i965_g33_setup_chipset_flush(void) 1177f51b7662SDaniel Vetter { 1178f51b7662SDaniel Vetter u32 temp_hi, temp_lo; 1179f51b7662SDaniel Vetter int ret; 1180f51b7662SDaniel Vetter 1181d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); 1182d7cca2f7SDaniel Vetter pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); 1183f51b7662SDaniel Vetter 1184f51b7662SDaniel Vetter if (!(temp_lo & 0x1)) { 1185f51b7662SDaniel Vetter 1186f51b7662SDaniel Vetter intel_alloc_chipset_flush_resource(); 1187f51b7662SDaniel Vetter 1188f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1189d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, 1190f51b7662SDaniel Vetter upper_32_bits(intel_private.ifp_resource.start)); 1191d7cca2f7SDaniel Vetter pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1192f51b7662SDaniel Vetter } else { 1193f51b7662SDaniel Vetter u64 l64; 1194f51b7662SDaniel Vetter 1195f51b7662SDaniel Vetter temp_lo &= ~0x1; 1196f51b7662SDaniel Vetter l64 = ((u64)temp_hi << 32) | temp_lo; 1197f51b7662SDaniel Vetter 1198f51b7662SDaniel Vetter intel_private.resource_valid = 1; 1199f51b7662SDaniel Vetter intel_private.ifp_resource.start = l64; 1200f51b7662SDaniel Vetter intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1201f51b7662SDaniel Vetter ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1202f51b7662SDaniel Vetter /* some BIOSes reserve this area in a pnp some don't */ 1203f51b7662SDaniel Vetter if (ret) 1204f51b7662SDaniel Vetter intel_private.resource_valid = 0; 1205f51b7662SDaniel Vetter } 1206f51b7662SDaniel Vetter } 1207f51b7662SDaniel Vetter 1208f51b7662SDaniel Vetter static void intel_i9xx_setup_flush(void) 1209f51b7662SDaniel Vetter { 1210f51b7662SDaniel Vetter /* return if already configured */ 1211f51b7662SDaniel Vetter if (intel_private.ifp_resource.start) 1212f51b7662SDaniel Vetter return; 1213f51b7662SDaniel Vetter 12141a997ff2SDaniel Vetter if (INTEL_GTT_GEN == 6) 1215f51b7662SDaniel Vetter return; 1216f51b7662SDaniel Vetter 1217f51b7662SDaniel Vetter /* setup a resource for this object */ 1218f51b7662SDaniel Vetter intel_private.ifp_resource.name = "Intel Flush Page"; 1219f51b7662SDaniel Vetter intel_private.ifp_resource.flags = IORESOURCE_MEM; 1220f51b7662SDaniel Vetter 1221f51b7662SDaniel Vetter /* Setup chipset flush for 915 */ 12221a997ff2SDaniel Vetter if (IS_G33 || INTEL_GTT_GEN >= 4) { 1223f51b7662SDaniel Vetter intel_i965_g33_setup_chipset_flush(); 1224f51b7662SDaniel Vetter } else { 1225f51b7662SDaniel Vetter intel_i915_setup_chipset_flush(); 1226f51b7662SDaniel Vetter } 1227f51b7662SDaniel Vetter 1228df51e7aaSChris Wilson if (intel_private.ifp_resource.start) 1229f51b7662SDaniel Vetter intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1230f51b7662SDaniel Vetter if (!intel_private.i9xx_flush_page) 1231df51e7aaSChris Wilson dev_err(&intel_private.pcidev->dev, 1232df51e7aaSChris Wilson "can't ioremap flush page - no chipset flushing\n"); 1233f51b7662SDaniel Vetter } 1234f51b7662SDaniel Vetter 1235f1befe71SChris Wilson static int intel_i9xx_configure(void) 1236f51b7662SDaniel Vetter { 1237f51b7662SDaniel Vetter int i; 1238f51b7662SDaniel Vetter 12392d2430cfSDaniel Vetter intel_enable_gtt(); 1240f51b7662SDaniel Vetter 12412d2430cfSDaniel Vetter agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 1242f51b7662SDaniel Vetter 1243f51b7662SDaniel Vetter if (agp_bridge->driver->needs_scratch_page) { 12440ade6386SDaniel Vetter for (i = intel_private.base.gtt_stolen_entries; i < 12450ade6386SDaniel Vetter intel_private.base.gtt_total_entries; i++) { 1246f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.gtt+i); 1247f51b7662SDaniel Vetter } 1248f51b7662SDaniel Vetter readl(intel_private.gtt+i-1); /* PCI Posting. */ 1249f51b7662SDaniel Vetter } 1250f51b7662SDaniel Vetter 1251f51b7662SDaniel Vetter global_cache_flush(); 1252f51b7662SDaniel Vetter 1253f51b7662SDaniel Vetter return 0; 1254f51b7662SDaniel Vetter } 1255f51b7662SDaniel Vetter 1256f51b7662SDaniel Vetter static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) 1257f51b7662SDaniel Vetter { 1258f51b7662SDaniel Vetter if (intel_private.i9xx_flush_page) 1259f51b7662SDaniel Vetter writel(1, intel_private.i9xx_flush_page); 1260f51b7662SDaniel Vetter } 1261f51b7662SDaniel Vetter 1262f51b7662SDaniel Vetter static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, 1263f51b7662SDaniel Vetter int type) 1264f51b7662SDaniel Vetter { 1265f51b7662SDaniel Vetter int num_entries; 1266f51b7662SDaniel Vetter void *temp; 1267f51b7662SDaniel Vetter int ret = -EINVAL; 1268f51b7662SDaniel Vetter int mask_type; 1269f51b7662SDaniel Vetter 1270f51b7662SDaniel Vetter if (mem->page_count == 0) 1271f51b7662SDaniel Vetter goto out; 1272f51b7662SDaniel Vetter 1273f51b7662SDaniel Vetter temp = agp_bridge->current_size; 1274f51b7662SDaniel Vetter num_entries = A_SIZE_FIX(temp)->num_entries; 1275f51b7662SDaniel Vetter 12760ade6386SDaniel Vetter if (pg_start < intel_private.base.gtt_stolen_entries) { 1277f51b7662SDaniel Vetter dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, 12780ade6386SDaniel Vetter "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n", 12790ade6386SDaniel Vetter pg_start, intel_private.base.gtt_stolen_entries); 1280f51b7662SDaniel Vetter 1281f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1282f51b7662SDaniel Vetter "trying to insert into local/stolen memory\n"); 1283f51b7662SDaniel Vetter goto out_err; 1284f51b7662SDaniel Vetter } 1285f51b7662SDaniel Vetter 1286f51b7662SDaniel Vetter if ((pg_start + mem->page_count) > num_entries) 1287f51b7662SDaniel Vetter goto out_err; 1288f51b7662SDaniel Vetter 1289f51b7662SDaniel Vetter /* The i915 can't check the GTT for entries since it's read only; 1290f51b7662SDaniel Vetter * depend on the caller to make the correct offset decisions. 1291f51b7662SDaniel Vetter */ 1292f51b7662SDaniel Vetter 1293f51b7662SDaniel Vetter if (type != mem->type) 1294f51b7662SDaniel Vetter goto out_err; 1295f51b7662SDaniel Vetter 1296f51b7662SDaniel Vetter mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 1297f51b7662SDaniel Vetter 12981a997ff2SDaniel Vetter if (INTEL_GTT_GEN != 6 && mask_type != 0 && 12991a997ff2SDaniel Vetter mask_type != AGP_PHYS_MEMORY && 1300f51b7662SDaniel Vetter mask_type != INTEL_AGP_CACHED_MEMORY) 1301f51b7662SDaniel Vetter goto out_err; 1302f51b7662SDaniel Vetter 1303f51b7662SDaniel Vetter if (!mem->is_flushed) 1304f51b7662SDaniel Vetter global_cache_flush(); 1305f51b7662SDaniel Vetter 1306f51b7662SDaniel Vetter intel_agp_insert_sg_entries(mem, pg_start, mask_type); 1307f51b7662SDaniel Vetter 1308f51b7662SDaniel Vetter out: 1309f51b7662SDaniel Vetter ret = 0; 1310f51b7662SDaniel Vetter out_err: 1311f51b7662SDaniel Vetter mem->is_flushed = true; 1312f51b7662SDaniel Vetter return ret; 1313f51b7662SDaniel Vetter } 1314f51b7662SDaniel Vetter 1315f51b7662SDaniel Vetter static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, 1316f51b7662SDaniel Vetter int type) 1317f51b7662SDaniel Vetter { 1318f51b7662SDaniel Vetter int i; 1319f51b7662SDaniel Vetter 1320f51b7662SDaniel Vetter if (mem->page_count == 0) 1321f51b7662SDaniel Vetter return 0; 1322f51b7662SDaniel Vetter 13230ade6386SDaniel Vetter if (pg_start < intel_private.base.gtt_stolen_entries) { 1324f51b7662SDaniel Vetter dev_info(&intel_private.pcidev->dev, 1325f51b7662SDaniel Vetter "trying to disable local/stolen memory\n"); 1326f51b7662SDaniel Vetter return -EINVAL; 1327f51b7662SDaniel Vetter } 1328f51b7662SDaniel Vetter 1329f51b7662SDaniel Vetter for (i = pg_start; i < (mem->page_count + pg_start); i++) 1330f51b7662SDaniel Vetter writel(agp_bridge->scratch_page, intel_private.gtt+i); 1331f51b7662SDaniel Vetter 1332f51b7662SDaniel Vetter readl(intel_private.gtt+i-1); 1333f51b7662SDaniel Vetter 1334f51b7662SDaniel Vetter return 0; 1335f51b7662SDaniel Vetter } 1336f51b7662SDaniel Vetter 13372d2430cfSDaniel Vetter static int i9xx_setup(void) 13382d2430cfSDaniel Vetter { 13392d2430cfSDaniel Vetter u32 reg_addr; 13402d2430cfSDaniel Vetter 13412d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); 13422d2430cfSDaniel Vetter 13432d2430cfSDaniel Vetter reg_addr &= 0xfff80000; 13442d2430cfSDaniel Vetter 13452d2430cfSDaniel Vetter intel_private.registers = ioremap(reg_addr, 128 * 4096); 13462d2430cfSDaniel Vetter if (!intel_private.registers) 13472d2430cfSDaniel Vetter return -ENOMEM; 13482d2430cfSDaniel Vetter 13492d2430cfSDaniel Vetter if (INTEL_GTT_GEN == 3) { 13502d2430cfSDaniel Vetter u32 gtt_addr; 13513f08e4efSChris Wilson 13522d2430cfSDaniel Vetter pci_read_config_dword(intel_private.pcidev, 13532d2430cfSDaniel Vetter I915_PTEADDR, >t_addr); 13542d2430cfSDaniel Vetter intel_private.gtt_bus_addr = gtt_addr; 13552d2430cfSDaniel Vetter } else { 13562d2430cfSDaniel Vetter u32 gtt_offset; 13572d2430cfSDaniel Vetter 13582d2430cfSDaniel Vetter switch (INTEL_GTT_GEN) { 13592d2430cfSDaniel Vetter case 5: 13602d2430cfSDaniel Vetter case 6: 13612d2430cfSDaniel Vetter gtt_offset = MB(2); 13622d2430cfSDaniel Vetter break; 13632d2430cfSDaniel Vetter case 4: 13642d2430cfSDaniel Vetter default: 13652d2430cfSDaniel Vetter gtt_offset = KB(512); 13662d2430cfSDaniel Vetter break; 13672d2430cfSDaniel Vetter } 13682d2430cfSDaniel Vetter intel_private.gtt_bus_addr = reg_addr + gtt_offset; 13692d2430cfSDaniel Vetter } 13702d2430cfSDaniel Vetter 13713f08e4efSChris Wilson intel_private.pte_bus_addr = 13723f08e4efSChris Wilson readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; 13733f08e4efSChris Wilson 13742d2430cfSDaniel Vetter intel_i9xx_setup_flush(); 13752d2430cfSDaniel Vetter 13762d2430cfSDaniel Vetter return 0; 13772d2430cfSDaniel Vetter } 13782d2430cfSDaniel Vetter 1379f51b7662SDaniel Vetter /* 1380f51b7662SDaniel Vetter * The i965 supports 36-bit physical addresses, but to keep 1381f51b7662SDaniel Vetter * the format of the GTT the same, the bits that don't fit 1382f51b7662SDaniel Vetter * in a 32-bit word are shifted down to bits 4..7. 1383f51b7662SDaniel Vetter * 1384f51b7662SDaniel Vetter * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 1385f51b7662SDaniel Vetter * is always zero on 32-bit architectures, so no need to make 1386f51b7662SDaniel Vetter * this conditional. 1387f51b7662SDaniel Vetter */ 1388f51b7662SDaniel Vetter static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 1389f51b7662SDaniel Vetter dma_addr_t addr, int type) 1390f51b7662SDaniel Vetter { 1391f51b7662SDaniel Vetter /* Shift high bits down */ 1392f51b7662SDaniel Vetter addr |= (addr >> 28) & 0xf0; 1393f51b7662SDaniel Vetter 1394f51b7662SDaniel Vetter /* Type checking must be done elsewhere */ 1395f51b7662SDaniel Vetter return addr | bridge->driver->masks[type].mask; 1396f51b7662SDaniel Vetter } 1397f51b7662SDaniel Vetter 13983869d4a8SZhenyu Wang static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge, 13993869d4a8SZhenyu Wang dma_addr_t addr, int type) 14003869d4a8SZhenyu Wang { 14018dfc2b14SZhenyu Wang /* gen6 has bit11-4 for physical addr bit39-32 */ 14028dfc2b14SZhenyu Wang addr |= (addr >> 28) & 0xff0; 14033869d4a8SZhenyu Wang 14043869d4a8SZhenyu Wang /* Type checking must be done elsewhere */ 14053869d4a8SZhenyu Wang return addr | bridge->driver->masks[type].mask; 14063869d4a8SZhenyu Wang } 14073869d4a8SZhenyu Wang 1408f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_810_driver = { 1409f51b7662SDaniel Vetter .owner = THIS_MODULE, 1410f51b7662SDaniel Vetter .aperture_sizes = intel_i810_sizes, 1411f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 1412f51b7662SDaniel Vetter .num_aperture_sizes = 2, 1413f51b7662SDaniel Vetter .needs_scratch_page = true, 1414f51b7662SDaniel Vetter .configure = intel_i810_configure, 1415f51b7662SDaniel Vetter .fetch_size = intel_i810_fetch_size, 1416f51b7662SDaniel Vetter .cleanup = intel_i810_cleanup, 1417f51b7662SDaniel Vetter .mask_memory = intel_i810_mask_memory, 1418f51b7662SDaniel Vetter .masks = intel_i810_masks, 1419ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1420f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 1421f51b7662SDaniel Vetter .create_gatt_table = agp_generic_create_gatt_table, 1422f51b7662SDaniel Vetter .free_gatt_table = agp_generic_free_gatt_table, 1423f51b7662SDaniel Vetter .insert_memory = intel_i810_insert_entries, 1424f51b7662SDaniel Vetter .remove_memory = intel_i810_remove_entries, 1425f51b7662SDaniel Vetter .alloc_by_type = intel_i810_alloc_by_type, 1426f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1427f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1428f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1429f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1430f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1431f51b7662SDaniel Vetter .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1432f51b7662SDaniel Vetter }; 1433f51b7662SDaniel Vetter 1434f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_830_driver = { 1435f51b7662SDaniel Vetter .owner = THIS_MODULE, 1436f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 14379e76e7b8SChris Wilson .aperture_sizes = intel_fake_agp_sizes, 14389e76e7b8SChris Wilson .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1439f51b7662SDaniel Vetter .needs_scratch_page = true, 1440*351bb278SDaniel Vetter .configure = intel_fake_agp_configure, 14413e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1442fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1443f51b7662SDaniel Vetter .mask_memory = intel_i810_mask_memory, 1444f51b7662SDaniel Vetter .masks = intel_i810_masks, 1445ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1446f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 14473b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1448ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1449f51b7662SDaniel Vetter .insert_memory = intel_i830_insert_entries, 1450f51b7662SDaniel Vetter .remove_memory = intel_i830_remove_entries, 1451ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1452f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1453f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1454f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1455f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1456f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1457f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1458f51b7662SDaniel Vetter .chipset_flush = intel_i830_chipset_flush, 1459f51b7662SDaniel Vetter }; 1460f51b7662SDaniel Vetter 1461f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_915_driver = { 1462f51b7662SDaniel Vetter .owner = THIS_MODULE, 1463f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 14649e76e7b8SChris Wilson .aperture_sizes = intel_fake_agp_sizes, 14659e76e7b8SChris Wilson .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1466f51b7662SDaniel Vetter .needs_scratch_page = true, 1467*351bb278SDaniel Vetter .configure = intel_fake_agp_configure, 14683e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1469fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1470f51b7662SDaniel Vetter .mask_memory = intel_i810_mask_memory, 1471f51b7662SDaniel Vetter .masks = intel_i810_masks, 1472ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1473f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 14743b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1475ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1476f51b7662SDaniel Vetter .insert_memory = intel_i915_insert_entries, 1477f51b7662SDaniel Vetter .remove_memory = intel_i915_remove_entries, 1478ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1479f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1480f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1481f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1482f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1483f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1484f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1485f51b7662SDaniel Vetter .chipset_flush = intel_i915_chipset_flush, 14860e87d2b0SDaniel Vetter #if USE_PCI_DMA_API 1487f51b7662SDaniel Vetter .agp_map_page = intel_agp_map_page, 1488f51b7662SDaniel Vetter .agp_unmap_page = intel_agp_unmap_page, 1489f51b7662SDaniel Vetter .agp_map_memory = intel_agp_map_memory, 1490f51b7662SDaniel Vetter .agp_unmap_memory = intel_agp_unmap_memory, 1491f51b7662SDaniel Vetter #endif 1492f51b7662SDaniel Vetter }; 1493f51b7662SDaniel Vetter 1494f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_i965_driver = { 1495f51b7662SDaniel Vetter .owner = THIS_MODULE, 1496f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 14979e76e7b8SChris Wilson .aperture_sizes = intel_fake_agp_sizes, 14989e76e7b8SChris Wilson .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1499f51b7662SDaniel Vetter .needs_scratch_page = true, 1500f1befe71SChris Wilson .configure = intel_i9xx_configure, 15013e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1502fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1503f51b7662SDaniel Vetter .mask_memory = intel_i965_mask_memory, 1504f51b7662SDaniel Vetter .masks = intel_i810_masks, 1505ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1506f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 15073b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1508ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1509f51b7662SDaniel Vetter .insert_memory = intel_i915_insert_entries, 1510f51b7662SDaniel Vetter .remove_memory = intel_i915_remove_entries, 1511ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1512f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1513f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1514f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1515f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1516f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1517f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1518f51b7662SDaniel Vetter .chipset_flush = intel_i915_chipset_flush, 15190e87d2b0SDaniel Vetter #if USE_PCI_DMA_API 1520f51b7662SDaniel Vetter .agp_map_page = intel_agp_map_page, 1521f51b7662SDaniel Vetter .agp_unmap_page = intel_agp_unmap_page, 1522f51b7662SDaniel Vetter .agp_map_memory = intel_agp_map_memory, 1523f51b7662SDaniel Vetter .agp_unmap_memory = intel_agp_unmap_memory, 1524f51b7662SDaniel Vetter #endif 1525f51b7662SDaniel Vetter }; 1526f51b7662SDaniel Vetter 15273869d4a8SZhenyu Wang static const struct agp_bridge_driver intel_gen6_driver = { 15283869d4a8SZhenyu Wang .owner = THIS_MODULE, 15293869d4a8SZhenyu Wang .size_type = FIXED_APER_SIZE, 15309e76e7b8SChris Wilson .aperture_sizes = intel_fake_agp_sizes, 15319e76e7b8SChris Wilson .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 15323869d4a8SZhenyu Wang .needs_scratch_page = true, 15333869d4a8SZhenyu Wang .configure = intel_i9xx_configure, 15343e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1535fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 15363869d4a8SZhenyu Wang .mask_memory = intel_gen6_mask_memory, 1537f8f235e5SZhenyu Wang .masks = intel_gen6_masks, 1538ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 15393869d4a8SZhenyu Wang .cache_flush = global_cache_flush, 15403b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1541ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 15423869d4a8SZhenyu Wang .insert_memory = intel_i915_insert_entries, 15433869d4a8SZhenyu Wang .remove_memory = intel_i915_remove_entries, 1544ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 15453869d4a8SZhenyu Wang .free_by_type = intel_i810_free_by_type, 15463869d4a8SZhenyu Wang .agp_alloc_page = agp_generic_alloc_page, 15473869d4a8SZhenyu Wang .agp_alloc_pages = agp_generic_alloc_pages, 15483869d4a8SZhenyu Wang .agp_destroy_page = agp_generic_destroy_page, 15493869d4a8SZhenyu Wang .agp_destroy_pages = agp_generic_destroy_pages, 1550f8f235e5SZhenyu Wang .agp_type_to_mask_type = intel_gen6_type_to_mask_type, 15513869d4a8SZhenyu Wang .chipset_flush = intel_i915_chipset_flush, 15520e87d2b0SDaniel Vetter #if USE_PCI_DMA_API 15533869d4a8SZhenyu Wang .agp_map_page = intel_agp_map_page, 15543869d4a8SZhenyu Wang .agp_unmap_page = intel_agp_unmap_page, 15553869d4a8SZhenyu Wang .agp_map_memory = intel_agp_map_memory, 15563869d4a8SZhenyu Wang .agp_unmap_memory = intel_agp_unmap_memory, 15573869d4a8SZhenyu Wang #endif 15583869d4a8SZhenyu Wang }; 15593869d4a8SZhenyu Wang 1560f51b7662SDaniel Vetter static const struct agp_bridge_driver intel_g33_driver = { 1561f51b7662SDaniel Vetter .owner = THIS_MODULE, 1562f51b7662SDaniel Vetter .size_type = FIXED_APER_SIZE, 15639e76e7b8SChris Wilson .aperture_sizes = intel_fake_agp_sizes, 15649e76e7b8SChris Wilson .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1565f51b7662SDaniel Vetter .needs_scratch_page = true, 1566f1befe71SChris Wilson .configure = intel_i9xx_configure, 15673e921f98SDaniel Vetter .fetch_size = intel_fake_agp_fetch_size, 1568fdfb58a9SDaniel Vetter .cleanup = intel_gtt_cleanup, 1569f51b7662SDaniel Vetter .mask_memory = intel_i965_mask_memory, 1570f51b7662SDaniel Vetter .masks = intel_i810_masks, 1571ffdd7510SDaniel Vetter .agp_enable = intel_fake_agp_enable, 1572f51b7662SDaniel Vetter .cache_flush = global_cache_flush, 15733b15a9d7SDaniel Vetter .create_gatt_table = intel_fake_agp_create_gatt_table, 1574ffdd7510SDaniel Vetter .free_gatt_table = intel_fake_agp_free_gatt_table, 1575f51b7662SDaniel Vetter .insert_memory = intel_i915_insert_entries, 1576f51b7662SDaniel Vetter .remove_memory = intel_i915_remove_entries, 1577ffdd7510SDaniel Vetter .alloc_by_type = intel_fake_agp_alloc_by_type, 1578f51b7662SDaniel Vetter .free_by_type = intel_i810_free_by_type, 1579f51b7662SDaniel Vetter .agp_alloc_page = agp_generic_alloc_page, 1580f51b7662SDaniel Vetter .agp_alloc_pages = agp_generic_alloc_pages, 1581f51b7662SDaniel Vetter .agp_destroy_page = agp_generic_destroy_page, 1582f51b7662SDaniel Vetter .agp_destroy_pages = agp_generic_destroy_pages, 1583f51b7662SDaniel Vetter .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1584f51b7662SDaniel Vetter .chipset_flush = intel_i915_chipset_flush, 15850e87d2b0SDaniel Vetter #if USE_PCI_DMA_API 1586f51b7662SDaniel Vetter .agp_map_page = intel_agp_map_page, 1587f51b7662SDaniel Vetter .agp_unmap_page = intel_agp_unmap_page, 1588f51b7662SDaniel Vetter .agp_map_memory = intel_agp_map_memory, 1589f51b7662SDaniel Vetter .agp_unmap_memory = intel_agp_unmap_memory, 1590f51b7662SDaniel Vetter #endif 1591f51b7662SDaniel Vetter }; 159202c026ceSDaniel Vetter 15931a997ff2SDaniel Vetter static const struct intel_gtt_driver i8xx_gtt_driver = { 15941a997ff2SDaniel Vetter .gen = 2, 159573800422SDaniel Vetter .setup = i830_setup, 1596*351bb278SDaniel Vetter .write_entry = i830_write_entry, 15971a997ff2SDaniel Vetter }; 15981a997ff2SDaniel Vetter static const struct intel_gtt_driver i915_gtt_driver = { 15991a997ff2SDaniel Vetter .gen = 3, 16002d2430cfSDaniel Vetter .setup = i9xx_setup, 1601*351bb278SDaniel Vetter /* i945 is the last gpu to need phys mem (for overlay and cursors). */ 1602*351bb278SDaniel Vetter .write_entry = i830_write_entry, 16031a997ff2SDaniel Vetter }; 16041a997ff2SDaniel Vetter static const struct intel_gtt_driver g33_gtt_driver = { 16051a997ff2SDaniel Vetter .gen = 3, 16061a997ff2SDaniel Vetter .is_g33 = 1, 16072d2430cfSDaniel Vetter .setup = i9xx_setup, 16081a997ff2SDaniel Vetter }; 16091a997ff2SDaniel Vetter static const struct intel_gtt_driver pineview_gtt_driver = { 16101a997ff2SDaniel Vetter .gen = 3, 16111a997ff2SDaniel Vetter .is_pineview = 1, .is_g33 = 1, 16122d2430cfSDaniel Vetter .setup = i9xx_setup, 16131a997ff2SDaniel Vetter }; 16141a997ff2SDaniel Vetter static const struct intel_gtt_driver i965_gtt_driver = { 16151a997ff2SDaniel Vetter .gen = 4, 16162d2430cfSDaniel Vetter .setup = i9xx_setup, 16171a997ff2SDaniel Vetter }; 16181a997ff2SDaniel Vetter static const struct intel_gtt_driver g4x_gtt_driver = { 16191a997ff2SDaniel Vetter .gen = 5, 16202d2430cfSDaniel Vetter .setup = i9xx_setup, 16211a997ff2SDaniel Vetter }; 16221a997ff2SDaniel Vetter static const struct intel_gtt_driver ironlake_gtt_driver = { 16231a997ff2SDaniel Vetter .gen = 5, 16241a997ff2SDaniel Vetter .is_ironlake = 1, 16252d2430cfSDaniel Vetter .setup = i9xx_setup, 16261a997ff2SDaniel Vetter }; 16271a997ff2SDaniel Vetter static const struct intel_gtt_driver sandybridge_gtt_driver = { 16281a997ff2SDaniel Vetter .gen = 6, 16292d2430cfSDaniel Vetter .setup = i9xx_setup, 16301a997ff2SDaniel Vetter }; 16311a997ff2SDaniel Vetter 163202c026ceSDaniel Vetter /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 163302c026ceSDaniel Vetter * driver and gmch_driver must be non-null, and find_gmch will determine 163402c026ceSDaniel Vetter * which one should be used if a gmch_chip_id is present. 163502c026ceSDaniel Vetter */ 163602c026ceSDaniel Vetter static const struct intel_gtt_driver_description { 163702c026ceSDaniel Vetter unsigned int gmch_chip_id; 163802c026ceSDaniel Vetter char *name; 163902c026ceSDaniel Vetter const struct agp_bridge_driver *gmch_driver; 16401a997ff2SDaniel Vetter const struct intel_gtt_driver *gtt_driver; 164102c026ceSDaniel Vetter } intel_gtt_chipsets[] = { 16421a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver , NULL}, 16431a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver , NULL}, 16441a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver , NULL}, 16451a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver , NULL}, 16461a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 16471a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 16481a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82845G_IG, "830M", 16491a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 16501a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82854_IG, "854", 16511a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 16521a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", 16531a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 16541a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82865_IG, "865", 16551a997ff2SDaniel Vetter &intel_830_driver , &i8xx_gtt_driver}, 16561a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", 16571a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 16581a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", 16591a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 16601a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", 16611a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 16621a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", 16631a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 16641a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", 16651a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 16661a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", 16671a997ff2SDaniel Vetter &intel_915_driver , &i915_gtt_driver }, 16681a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", 16691a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16701a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", 16711a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16721a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", 16731a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16741a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", 16751a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16761a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", 16771a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16781a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", 16791a997ff2SDaniel Vetter &intel_i965_driver , &i965_gtt_driver }, 16801a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G33_IG, "G33", 16811a997ff2SDaniel Vetter &intel_g33_driver , &g33_gtt_driver }, 16821a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", 16831a997ff2SDaniel Vetter &intel_g33_driver , &g33_gtt_driver }, 16841a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", 16851a997ff2SDaniel Vetter &intel_g33_driver , &g33_gtt_driver }, 16861a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", 16871a997ff2SDaniel Vetter &intel_g33_driver , &pineview_gtt_driver }, 16881a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", 16891a997ff2SDaniel Vetter &intel_g33_driver , &pineview_gtt_driver }, 16901a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", 16911a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 16921a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", 16931a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 16941a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", 16951a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 16961a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", 16971a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 16981a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_B43_IG, "B43", 16991a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 1700e9e5f8e8SChris Wilson { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", 1701e9e5f8e8SChris Wilson &intel_i965_driver , &g4x_gtt_driver }, 17021a997ff2SDaniel Vetter { PCI_DEVICE_ID_INTEL_G41_IG, "G41", 17031a997ff2SDaniel Vetter &intel_i965_driver , &g4x_gtt_driver }, 170402c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 17051a997ff2SDaniel Vetter "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver }, 170602c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 17071a997ff2SDaniel Vetter "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver }, 170802c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, 17091a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 171002c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, 17111a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 171202c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, 17131a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 171402c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, 17151a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 171602c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, 17171a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 171802c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, 17191a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 172002c026ceSDaniel Vetter { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, 17211a997ff2SDaniel Vetter "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, 172202c026ceSDaniel Vetter { 0, NULL, NULL } 172302c026ceSDaniel Vetter }; 172402c026ceSDaniel Vetter 172502c026ceSDaniel Vetter static int find_gmch(u16 device) 172602c026ceSDaniel Vetter { 172702c026ceSDaniel Vetter struct pci_dev *gmch_device; 172802c026ceSDaniel Vetter 172902c026ceSDaniel Vetter gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 173002c026ceSDaniel Vetter if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 173102c026ceSDaniel Vetter gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 173202c026ceSDaniel Vetter device, gmch_device); 173302c026ceSDaniel Vetter } 173402c026ceSDaniel Vetter 173502c026ceSDaniel Vetter if (!gmch_device) 173602c026ceSDaniel Vetter return 0; 173702c026ceSDaniel Vetter 173802c026ceSDaniel Vetter intel_private.pcidev = gmch_device; 173902c026ceSDaniel Vetter return 1; 174002c026ceSDaniel Vetter } 174102c026ceSDaniel Vetter 1742e2404e7cSDaniel Vetter int intel_gmch_probe(struct pci_dev *pdev, 174302c026ceSDaniel Vetter struct agp_bridge_data *bridge) 174402c026ceSDaniel Vetter { 174502c026ceSDaniel Vetter int i, mask; 174602c026ceSDaniel Vetter bridge->driver = NULL; 174702c026ceSDaniel Vetter 174802c026ceSDaniel Vetter for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { 174902c026ceSDaniel Vetter if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { 175002c026ceSDaniel Vetter bridge->driver = 175102c026ceSDaniel Vetter intel_gtt_chipsets[i].gmch_driver; 17521a997ff2SDaniel Vetter intel_private.driver = 17531a997ff2SDaniel Vetter intel_gtt_chipsets[i].gtt_driver; 175402c026ceSDaniel Vetter break; 175502c026ceSDaniel Vetter } 175602c026ceSDaniel Vetter } 175702c026ceSDaniel Vetter 175802c026ceSDaniel Vetter if (!bridge->driver) 175902c026ceSDaniel Vetter return 0; 176002c026ceSDaniel Vetter 176102c026ceSDaniel Vetter bridge->dev_private_data = &intel_private; 176202c026ceSDaniel Vetter bridge->dev = pdev; 176302c026ceSDaniel Vetter 1764d7cca2f7SDaniel Vetter intel_private.bridge_dev = pci_dev_get(pdev); 1765d7cca2f7SDaniel Vetter 176602c026ceSDaniel Vetter dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); 176702c026ceSDaniel Vetter 176802c026ceSDaniel Vetter if (bridge->driver->mask_memory == intel_gen6_mask_memory) 176902c026ceSDaniel Vetter mask = 40; 177002c026ceSDaniel Vetter else if (bridge->driver->mask_memory == intel_i965_mask_memory) 177102c026ceSDaniel Vetter mask = 36; 177202c026ceSDaniel Vetter else 177302c026ceSDaniel Vetter mask = 32; 177402c026ceSDaniel Vetter 177502c026ceSDaniel Vetter if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) 177602c026ceSDaniel Vetter dev_err(&intel_private.pcidev->dev, 177702c026ceSDaniel Vetter "set gfx device dma mask %d-bit failed!\n", mask); 177802c026ceSDaniel Vetter else 177902c026ceSDaniel Vetter pci_set_consistent_dma_mask(intel_private.pcidev, 178002c026ceSDaniel Vetter DMA_BIT_MASK(mask)); 178102c026ceSDaniel Vetter 17821784a5fbSDaniel Vetter if (bridge->driver == &intel_810_driver) 17831784a5fbSDaniel Vetter return 1; 17841784a5fbSDaniel Vetter 17853b15a9d7SDaniel Vetter if (intel_gtt_init() != 0) 17863b15a9d7SDaniel Vetter return 0; 17871784a5fbSDaniel Vetter 178802c026ceSDaniel Vetter return 1; 178902c026ceSDaniel Vetter } 1790e2404e7cSDaniel Vetter EXPORT_SYMBOL(intel_gmch_probe); 179102c026ceSDaniel Vetter 179219966754SDaniel Vetter struct intel_gtt *intel_gtt_get(void) 179319966754SDaniel Vetter { 179419966754SDaniel Vetter return &intel_private.base; 179519966754SDaniel Vetter } 179619966754SDaniel Vetter EXPORT_SYMBOL(intel_gtt_get); 179719966754SDaniel Vetter 1798e2404e7cSDaniel Vetter void intel_gmch_remove(struct pci_dev *pdev) 179902c026ceSDaniel Vetter { 180002c026ceSDaniel Vetter if (intel_private.pcidev) 180102c026ceSDaniel Vetter pci_dev_put(intel_private.pcidev); 1802d7cca2f7SDaniel Vetter if (intel_private.bridge_dev) 1803d7cca2f7SDaniel Vetter pci_dev_put(intel_private.bridge_dev); 180402c026ceSDaniel Vetter } 1805e2404e7cSDaniel Vetter EXPORT_SYMBOL(intel_gmch_remove); 1806e2404e7cSDaniel Vetter 1807e2404e7cSDaniel Vetter MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 1808e2404e7cSDaniel Vetter MODULE_LICENSE("GPL and additional rights"); 1809