1 /* 2 * Intel AGPGART routines. 3 */ 4 5 /* 6 * Intel(R) 855GM/852GM and 865G support added by David Dawes 7 * <dawes@tungstengraphics.com>. 8 * 9 * Intel(R) 915G/915GM support added by Alan Hourihane 10 * <alanh@tungstengraphics.com>. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/init.h> 16 #include <linux/pagemap.h> 17 #include <linux/agp_backend.h> 18 #include "agp.h" 19 20 /* Intel 815 register */ 21 #define INTEL_815_APCONT 0x51 22 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 23 24 /* Intel i820 registers */ 25 #define INTEL_I820_RDCR 0x51 26 #define INTEL_I820_ERRSTS 0xc8 27 28 /* Intel i840 registers */ 29 #define INTEL_I840_MCHCFG 0x50 30 #define INTEL_I840_ERRSTS 0xc8 31 32 /* Intel i850 registers */ 33 #define INTEL_I850_MCHCFG 0x50 34 #define INTEL_I850_ERRSTS 0xc8 35 36 /* intel 915G registers */ 37 #define I915_GMADDR 0x18 38 #define I915_MMADDR 0x10 39 #define I915_PTEADDR 0x1C 40 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 41 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 42 43 44 /* Intel 7505 registers */ 45 #define INTEL_I7505_APSIZE 0x74 46 #define INTEL_I7505_NCAPID 0x60 47 #define INTEL_I7505_NISTAT 0x6c 48 #define INTEL_I7505_ATTBASE 0x78 49 #define INTEL_I7505_ERRSTS 0x42 50 #define INTEL_I7505_AGPCTRL 0x70 51 #define INTEL_I7505_MCHCFG 0x50 52 53 static struct aper_size_info_fixed intel_i810_sizes[] = 54 { 55 {64, 16384, 4}, 56 /* The 32M mode still requires a 64k gatt */ 57 {32, 8192, 4} 58 }; 59 60 #define AGP_DCACHE_MEMORY 1 61 #define AGP_PHYS_MEMORY 2 62 63 static struct gatt_mask intel_i810_masks[] = 64 { 65 {.mask = I810_PTE_VALID, .type = 0}, 66 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 67 {.mask = I810_PTE_VALID, .type = 0} 68 }; 69 70 static struct _intel_i810_private { 71 struct pci_dev *i810_dev; /* device one */ 72 volatile u8 __iomem *registers; 73 int num_dcache_entries; 74 } intel_i810_private; 75 76 static int intel_i810_fetch_size(void) 77 { 78 u32 smram_miscc; 79 struct aper_size_info_fixed *values; 80 81 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 82 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 83 84 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 85 printk(KERN_WARNING PFX "i810 is disabled\n"); 86 return 0; 87 } 88 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 89 agp_bridge->previous_size = 90 agp_bridge->current_size = (void *) (values + 1); 91 agp_bridge->aperture_size_idx = 1; 92 return values[1].size; 93 } else { 94 agp_bridge->previous_size = 95 agp_bridge->current_size = (void *) (values); 96 agp_bridge->aperture_size_idx = 0; 97 return values[0].size; 98 } 99 100 return 0; 101 } 102 103 static int intel_i810_configure(void) 104 { 105 struct aper_size_info_fixed *current_size; 106 u32 temp; 107 int i; 108 109 current_size = A_SIZE_FIX(agp_bridge->current_size); 110 111 pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp); 112 temp &= 0xfff80000; 113 114 intel_i810_private.registers = ioremap(temp, 128 * 4096); 115 if (!intel_i810_private.registers) { 116 printk(KERN_ERR PFX "Unable to remap memory.\n"); 117 return -ENOMEM; 118 } 119 120 if ((readl(intel_i810_private.registers+I810_DRAM_CTL) 121 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 122 /* This will need to be dynamically assigned */ 123 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n"); 124 intel_i810_private.num_dcache_entries = 1024; 125 } 126 pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp); 127 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 128 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_i810_private.registers+I810_PGETBL_CTL); 129 readl(intel_i810_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 130 131 if (agp_bridge->driver->needs_scratch_page) { 132 for (i = 0; i < current_size->num_entries; i++) { 133 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4)); 134 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */ 135 } 136 } 137 global_cache_flush(); 138 return 0; 139 } 140 141 static void intel_i810_cleanup(void) 142 { 143 writel(0, intel_i810_private.registers+I810_PGETBL_CTL); 144 readl(intel_i810_private.registers); /* PCI Posting. */ 145 iounmap(intel_i810_private.registers); 146 } 147 148 static void intel_i810_tlbflush(struct agp_memory *mem) 149 { 150 return; 151 } 152 153 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 154 { 155 return; 156 } 157 158 /* Exists to support ARGB cursors */ 159 static void *i8xx_alloc_pages(void) 160 { 161 struct page * page; 162 163 page = alloc_pages(GFP_KERNEL, 2); 164 if (page == NULL) 165 return NULL; 166 167 if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) { 168 global_flush_tlb(); 169 __free_page(page); 170 return NULL; 171 } 172 global_flush_tlb(); 173 get_page(page); 174 SetPageLocked(page); 175 atomic_inc(&agp_bridge->current_memory_agp); 176 return page_address(page); 177 } 178 179 static void i8xx_destroy_pages(void *addr) 180 { 181 struct page *page; 182 183 if (addr == NULL) 184 return; 185 186 page = virt_to_page(addr); 187 change_page_attr(page, 4, PAGE_KERNEL); 188 global_flush_tlb(); 189 put_page(page); 190 unlock_page(page); 191 free_pages((unsigned long)addr, 2); 192 atomic_dec(&agp_bridge->current_memory_agp); 193 } 194 195 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 196 int type) 197 { 198 int i, j, num_entries; 199 void *temp; 200 201 temp = agp_bridge->current_size; 202 num_entries = A_SIZE_FIX(temp)->num_entries; 203 204 if ((pg_start + mem->page_count) > num_entries) { 205 return -EINVAL; 206 } 207 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 208 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) 209 return -EBUSY; 210 } 211 212 if (type != 0 || mem->type != 0) { 213 if ((type == AGP_DCACHE_MEMORY) && (mem->type == AGP_DCACHE_MEMORY)) { 214 /* special insert */ 215 global_cache_flush(); 216 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 217 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, intel_i810_private.registers+I810_PTE_BASE+(i*4)); 218 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ 219 } 220 global_cache_flush(); 221 agp_bridge->driver->tlb_flush(mem); 222 return 0; 223 } 224 if((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY)) 225 goto insert; 226 return -EINVAL; 227 } 228 229 insert: 230 global_cache_flush(); 231 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 232 writel(agp_bridge->driver->mask_memory(agp_bridge, 233 mem->memory[i], mem->type), 234 intel_i810_private.registers+I810_PTE_BASE+(j*4)); 235 readl(intel_i810_private.registers+I810_PTE_BASE+(j*4)); /* PCI Posting. */ 236 } 237 global_cache_flush(); 238 239 agp_bridge->driver->tlb_flush(mem); 240 return 0; 241 } 242 243 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 244 int type) 245 { 246 int i; 247 248 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 249 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4)); 250 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ 251 } 252 253 global_cache_flush(); 254 agp_bridge->driver->tlb_flush(mem); 255 return 0; 256 } 257 258 /* 259 * The i810/i830 requires a physical address to program its mouse 260 * pointer into hardware. 261 * However the Xserver still writes to it through the agp aperture. 262 */ 263 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 264 { 265 struct agp_memory *new; 266 void *addr; 267 268 if (pg_count != 1 && pg_count != 4) 269 return NULL; 270 271 switch (pg_count) { 272 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge); 273 break; 274 case 4: 275 /* kludge to get 4 physical pages for ARGB cursor */ 276 addr = i8xx_alloc_pages(); 277 break; 278 default: 279 return NULL; 280 } 281 282 if (addr == NULL) 283 return NULL; 284 285 new = agp_create_memory(pg_count); 286 if (new == NULL) 287 return NULL; 288 289 new->memory[0] = virt_to_gart(addr); 290 if (pg_count == 4) { 291 /* kludge to get 4 physical pages for ARGB cursor */ 292 new->memory[1] = new->memory[0] + PAGE_SIZE; 293 new->memory[2] = new->memory[1] + PAGE_SIZE; 294 new->memory[3] = new->memory[2] + PAGE_SIZE; 295 } 296 new->page_count = pg_count; 297 new->num_scratch_pages = pg_count; 298 new->type = AGP_PHYS_MEMORY; 299 new->physical = new->memory[0]; 300 return new; 301 } 302 303 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 304 { 305 struct agp_memory *new; 306 307 if (type == AGP_DCACHE_MEMORY) { 308 if (pg_count != intel_i810_private.num_dcache_entries) 309 return NULL; 310 311 new = agp_create_memory(1); 312 if (new == NULL) 313 return NULL; 314 315 new->type = AGP_DCACHE_MEMORY; 316 new->page_count = pg_count; 317 new->num_scratch_pages = 0; 318 vfree(new->memory); 319 return new; 320 } 321 if (type == AGP_PHYS_MEMORY) 322 return alloc_agpphysmem_i8xx(pg_count, type); 323 324 return NULL; 325 } 326 327 static void intel_i810_free_by_type(struct agp_memory *curr) 328 { 329 agp_free_key(curr->key); 330 if(curr->type == AGP_PHYS_MEMORY) { 331 if (curr->page_count == 4) 332 i8xx_destroy_pages(gart_to_virt(curr->memory[0])); 333 else 334 agp_bridge->driver->agp_destroy_page( 335 gart_to_virt(curr->memory[0])); 336 vfree(curr->memory); 337 } 338 kfree(curr); 339 } 340 341 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 342 unsigned long addr, int type) 343 { 344 /* Type checking must be done elsewhere */ 345 return addr | bridge->driver->masks[type].mask; 346 } 347 348 static struct aper_size_info_fixed intel_i830_sizes[] = 349 { 350 {128, 32768, 5}, 351 /* The 64M mode still requires a 128k gatt */ 352 {64, 16384, 5}, 353 {256, 65536, 6}, 354 }; 355 356 static struct _intel_i830_private { 357 struct pci_dev *i830_dev; /* device one */ 358 volatile u8 __iomem *registers; 359 volatile u32 __iomem *gtt; /* I915G */ 360 int gtt_entries; 361 } intel_i830_private; 362 363 static void intel_i830_init_gtt_entries(void) 364 { 365 u16 gmch_ctrl; 366 int gtt_entries; 367 u8 rdct; 368 int local = 0; 369 static const int ddt[4] = { 0, 16, 32, 64 }; 370 int size; 371 372 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 373 374 /* We obtain the size of the GTT, which is also stored (for some 375 * reason) at the top of stolen memory. Then we add 4KB to that 376 * for the video BIOS popup, which is also stored in there. */ 377 size = agp_bridge->driver->fetch_size() + 4; 378 379 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 380 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 381 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 382 case I830_GMCH_GMS_STOLEN_512: 383 gtt_entries = KB(512) - KB(size); 384 break; 385 case I830_GMCH_GMS_STOLEN_1024: 386 gtt_entries = MB(1) - KB(size); 387 break; 388 case I830_GMCH_GMS_STOLEN_8192: 389 gtt_entries = MB(8) - KB(size); 390 break; 391 case I830_GMCH_GMS_LOCAL: 392 rdct = readb(intel_i830_private.registers+I830_RDRAM_CHANNEL_TYPE); 393 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 394 MB(ddt[I830_RDRAM_DDT(rdct)]); 395 local = 1; 396 break; 397 default: 398 gtt_entries = 0; 399 break; 400 } 401 } else { 402 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 403 case I855_GMCH_GMS_STOLEN_1M: 404 gtt_entries = MB(1) - KB(size); 405 break; 406 case I855_GMCH_GMS_STOLEN_4M: 407 gtt_entries = MB(4) - KB(size); 408 break; 409 case I855_GMCH_GMS_STOLEN_8M: 410 gtt_entries = MB(8) - KB(size); 411 break; 412 case I855_GMCH_GMS_STOLEN_16M: 413 gtt_entries = MB(16) - KB(size); 414 break; 415 case I855_GMCH_GMS_STOLEN_32M: 416 gtt_entries = MB(32) - KB(size); 417 break; 418 case I915_GMCH_GMS_STOLEN_48M: 419 /* Check it's really I915G */ 420 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || 421 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || 422 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB) 423 gtt_entries = MB(48) - KB(size); 424 else 425 gtt_entries = 0; 426 break; 427 case I915_GMCH_GMS_STOLEN_64M: 428 /* Check it's really I915G */ 429 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || 430 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || 431 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB) 432 gtt_entries = MB(64) - KB(size); 433 else 434 gtt_entries = 0; 435 default: 436 gtt_entries = 0; 437 break; 438 } 439 } 440 if (gtt_entries > 0) 441 printk(KERN_INFO PFX "Detected %dK %s memory.\n", 442 gtt_entries / KB(1), local ? "local" : "stolen"); 443 else 444 printk(KERN_INFO PFX 445 "No pre-allocated video memory detected.\n"); 446 gtt_entries /= KB(4); 447 448 intel_i830_private.gtt_entries = gtt_entries; 449 } 450 451 /* The intel i830 automatically initializes the agp aperture during POST. 452 * Use the memory already set aside for in the GTT. 453 */ 454 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) 455 { 456 int page_order; 457 struct aper_size_info_fixed *size; 458 int num_entries; 459 u32 temp; 460 461 size = agp_bridge->current_size; 462 page_order = size->page_order; 463 num_entries = size->num_entries; 464 agp_bridge->gatt_table_real = NULL; 465 466 pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp); 467 temp &= 0xfff80000; 468 469 intel_i830_private.registers = ioremap(temp,128 * 4096); 470 if (!intel_i830_private.registers) 471 return -ENOMEM; 472 473 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; 474 global_cache_flush(); /* FIXME: ?? */ 475 476 /* we have to call this as early as possible after the MMIO base address is known */ 477 intel_i830_init_gtt_entries(); 478 479 agp_bridge->gatt_table = NULL; 480 481 agp_bridge->gatt_bus_addr = temp; 482 483 return 0; 484 } 485 486 /* Return the gatt table to a sane state. Use the top of stolen 487 * memory for the GTT. 488 */ 489 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) 490 { 491 return 0; 492 } 493 494 static int intel_i830_fetch_size(void) 495 { 496 u16 gmch_ctrl; 497 struct aper_size_info_fixed *values; 498 499 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 500 501 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 502 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 503 /* 855GM/852GM/865G has 128MB aperture size */ 504 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 505 agp_bridge->aperture_size_idx = 0; 506 return values[0].size; 507 } 508 509 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 510 511 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 512 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 513 agp_bridge->aperture_size_idx = 0; 514 return values[0].size; 515 } else { 516 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); 517 agp_bridge->aperture_size_idx = 1; 518 return values[1].size; 519 } 520 521 return 0; 522 } 523 524 static int intel_i830_configure(void) 525 { 526 struct aper_size_info_fixed *current_size; 527 u32 temp; 528 u16 gmch_ctrl; 529 int i; 530 531 current_size = A_SIZE_FIX(agp_bridge->current_size); 532 533 pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp); 534 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 535 536 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 537 gmch_ctrl |= I830_GMCH_ENABLED; 538 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); 539 540 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL); 541 readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 542 543 if (agp_bridge->driver->needs_scratch_page) { 544 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) { 545 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4)); 546 readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ 547 } 548 } 549 550 global_cache_flush(); 551 return 0; 552 } 553 554 static void intel_i830_cleanup(void) 555 { 556 iounmap(intel_i830_private.registers); 557 } 558 559 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type) 560 { 561 int i,j,num_entries; 562 void *temp; 563 564 temp = agp_bridge->current_size; 565 num_entries = A_SIZE_FIX(temp)->num_entries; 566 567 if (pg_start < intel_i830_private.gtt_entries) { 568 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n", 569 pg_start,intel_i830_private.gtt_entries); 570 571 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); 572 return -EINVAL; 573 } 574 575 if ((pg_start + mem->page_count) > num_entries) 576 return -EINVAL; 577 578 /* The i830 can't check the GTT for entries since its read only, 579 * depend on the caller to make the correct offset decisions. 580 */ 581 582 if ((type != 0 && type != AGP_PHYS_MEMORY) || 583 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY)) 584 return -EINVAL; 585 586 global_cache_flush(); /* FIXME: Necessary ?*/ 587 588 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 589 writel(agp_bridge->driver->mask_memory(agp_bridge, 590 mem->memory[i], mem->type), 591 intel_i830_private.registers+I810_PTE_BASE+(j*4)); 592 readl(intel_i830_private.registers+I810_PTE_BASE+(j*4)); /* PCI Posting. */ 593 } 594 595 global_cache_flush(); 596 agp_bridge->driver->tlb_flush(mem); 597 return 0; 598 } 599 600 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start, 601 int type) 602 { 603 int i; 604 605 global_cache_flush(); 606 607 if (pg_start < intel_i830_private.gtt_entries) { 608 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); 609 return -EINVAL; 610 } 611 612 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 613 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4)); 614 readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ 615 } 616 617 global_cache_flush(); 618 agp_bridge->driver->tlb_flush(mem); 619 return 0; 620 } 621 622 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type) 623 { 624 if (type == AGP_PHYS_MEMORY) 625 return alloc_agpphysmem_i8xx(pg_count, type); 626 627 /* always return NULL for other allocation types for now */ 628 return NULL; 629 } 630 631 static int intel_i915_configure(void) 632 { 633 struct aper_size_info_fixed *current_size; 634 u32 temp; 635 u16 gmch_ctrl; 636 int i; 637 638 current_size = A_SIZE_FIX(agp_bridge->current_size); 639 640 pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp); 641 642 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 643 644 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 645 gmch_ctrl |= I830_GMCH_ENABLED; 646 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); 647 648 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL); 649 readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 650 651 if (agp_bridge->driver->needs_scratch_page) { 652 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) { 653 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i); 654 readl(intel_i830_private.gtt+i); /* PCI Posting. */ 655 } 656 } 657 658 global_cache_flush(); 659 return 0; 660 } 661 662 static void intel_i915_cleanup(void) 663 { 664 iounmap(intel_i830_private.gtt); 665 iounmap(intel_i830_private.registers); 666 } 667 668 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start, 669 int type) 670 { 671 int i,j,num_entries; 672 void *temp; 673 674 temp = agp_bridge->current_size; 675 num_entries = A_SIZE_FIX(temp)->num_entries; 676 677 if (pg_start < intel_i830_private.gtt_entries) { 678 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n", 679 pg_start,intel_i830_private.gtt_entries); 680 681 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); 682 return -EINVAL; 683 } 684 685 if ((pg_start + mem->page_count) > num_entries) 686 return -EINVAL; 687 688 /* The i830 can't check the GTT for entries since its read only, 689 * depend on the caller to make the correct offset decisions. 690 */ 691 692 if ((type != 0 && type != AGP_PHYS_MEMORY) || 693 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY)) 694 return -EINVAL; 695 696 global_cache_flush(); 697 698 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 699 writel(agp_bridge->driver->mask_memory(agp_bridge, 700 mem->memory[i], mem->type), intel_i830_private.gtt+j); 701 readl(intel_i830_private.gtt+j); /* PCI Posting. */ 702 } 703 704 global_cache_flush(); 705 agp_bridge->driver->tlb_flush(mem); 706 return 0; 707 } 708 709 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start, 710 int type) 711 { 712 int i; 713 714 global_cache_flush(); 715 716 if (pg_start < intel_i830_private.gtt_entries) { 717 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); 718 return -EINVAL; 719 } 720 721 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 722 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i); 723 readl(intel_i830_private.gtt+i); 724 } 725 726 global_cache_flush(); 727 agp_bridge->driver->tlb_flush(mem); 728 return 0; 729 } 730 731 static int intel_i915_fetch_size(void) 732 { 733 struct aper_size_info_fixed *values; 734 u32 temp, offset = 0; 735 736 #define I915_256MB_ADDRESS_MASK (1<<27) 737 738 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 739 740 pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp); 741 if (temp & I915_256MB_ADDRESS_MASK) 742 offset = 0; /* 128MB aperture */ 743 else 744 offset = 2; /* 256MB aperture */ 745 agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset); 746 return values[offset].size; 747 } 748 749 /* The intel i915 automatically initializes the agp aperture during POST. 750 * Use the memory already set aside for in the GTT. 751 */ 752 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 753 { 754 int page_order; 755 struct aper_size_info_fixed *size; 756 int num_entries; 757 u32 temp, temp2; 758 759 size = agp_bridge->current_size; 760 page_order = size->page_order; 761 num_entries = size->num_entries; 762 agp_bridge->gatt_table_real = NULL; 763 764 pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp); 765 pci_read_config_dword(intel_i830_private.i830_dev, I915_PTEADDR,&temp2); 766 767 intel_i830_private.gtt = ioremap(temp2, 256 * 1024); 768 if (!intel_i830_private.gtt) 769 return -ENOMEM; 770 771 temp &= 0xfff80000; 772 773 intel_i830_private.registers = ioremap(temp,128 * 4096); 774 if (!intel_i830_private.registers) 775 return -ENOMEM; 776 777 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; 778 global_cache_flush(); /* FIXME: ? */ 779 780 /* we have to call this as early as possible after the MMIO base address is known */ 781 intel_i830_init_gtt_entries(); 782 783 agp_bridge->gatt_table = NULL; 784 785 agp_bridge->gatt_bus_addr = temp; 786 787 return 0; 788 } 789 790 static int intel_fetch_size(void) 791 { 792 int i; 793 u16 temp; 794 struct aper_size_info_16 *values; 795 796 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 797 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 798 799 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 800 if (temp == values[i].size_value) { 801 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 802 agp_bridge->aperture_size_idx = i; 803 return values[i].size; 804 } 805 } 806 807 return 0; 808 } 809 810 static int __intel_8xx_fetch_size(u8 temp) 811 { 812 int i; 813 struct aper_size_info_8 *values; 814 815 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 816 817 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 818 if (temp == values[i].size_value) { 819 agp_bridge->previous_size = 820 agp_bridge->current_size = (void *) (values + i); 821 agp_bridge->aperture_size_idx = i; 822 return values[i].size; 823 } 824 } 825 return 0; 826 } 827 828 static int intel_8xx_fetch_size(void) 829 { 830 u8 temp; 831 832 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 833 return __intel_8xx_fetch_size(temp); 834 } 835 836 static int intel_815_fetch_size(void) 837 { 838 u8 temp; 839 840 /* Intel 815 chipsets have a _weird_ APSIZE register with only 841 * one non-reserved bit, so mask the others out ... */ 842 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 843 temp &= (1 << 3); 844 845 return __intel_8xx_fetch_size(temp); 846 } 847 848 static void intel_tlbflush(struct agp_memory *mem) 849 { 850 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 851 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 852 } 853 854 855 static void intel_8xx_tlbflush(struct agp_memory *mem) 856 { 857 u32 temp; 858 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 859 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); 860 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 861 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); 862 } 863 864 865 static void intel_cleanup(void) 866 { 867 u16 temp; 868 struct aper_size_info_16 *previous_size; 869 870 previous_size = A_SIZE_16(agp_bridge->previous_size); 871 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 872 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 873 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 874 } 875 876 877 static void intel_8xx_cleanup(void) 878 { 879 u16 temp; 880 struct aper_size_info_8 *previous_size; 881 882 previous_size = A_SIZE_8(agp_bridge->previous_size); 883 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 884 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 885 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 886 } 887 888 889 static int intel_configure(void) 890 { 891 u32 temp; 892 u16 temp2; 893 struct aper_size_info_16 *current_size; 894 895 current_size = A_SIZE_16(agp_bridge->current_size); 896 897 /* aperture size */ 898 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 899 900 /* address to map to */ 901 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 902 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 903 904 /* attbase - aperture base */ 905 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 906 907 /* agpctrl */ 908 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 909 910 /* paccfg/nbxcfg */ 911 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 912 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 913 (temp2 & ~(1 << 10)) | (1 << 9)); 914 /* clear any possible error conditions */ 915 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 916 return 0; 917 } 918 919 static int intel_815_configure(void) 920 { 921 u32 temp, addr; 922 u8 temp2; 923 struct aper_size_info_8 *current_size; 924 925 /* attbase - aperture base */ 926 /* the Intel 815 chipset spec. says that bits 29-31 in the 927 * ATTBASE register are reserved -> try not to write them */ 928 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { 929 printk (KERN_EMERG PFX "gatt bus addr too high"); 930 return -EINVAL; 931 } 932 933 current_size = A_SIZE_8(agp_bridge->current_size); 934 935 /* aperture size */ 936 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 937 current_size->size_value); 938 939 /* address to map to */ 940 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 941 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 942 943 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 944 addr &= INTEL_815_ATTBASE_MASK; 945 addr |= agp_bridge->gatt_bus_addr; 946 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); 947 948 /* agpctrl */ 949 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 950 951 /* apcont */ 952 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); 953 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); 954 955 /* clear any possible error conditions */ 956 /* Oddness : this chipset seems to have no ERRSTS register ! */ 957 return 0; 958 } 959 960 static void intel_820_tlbflush(struct agp_memory *mem) 961 { 962 return; 963 } 964 965 static void intel_820_cleanup(void) 966 { 967 u8 temp; 968 struct aper_size_info_8 *previous_size; 969 970 previous_size = A_SIZE_8(agp_bridge->previous_size); 971 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); 972 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, 973 temp & ~(1 << 1)); 974 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 975 previous_size->size_value); 976 } 977 978 979 static int intel_820_configure(void) 980 { 981 u32 temp; 982 u8 temp2; 983 struct aper_size_info_8 *current_size; 984 985 current_size = A_SIZE_8(agp_bridge->current_size); 986 987 /* aperture size */ 988 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 989 990 /* address to map to */ 991 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 992 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 993 994 /* attbase - aperture base */ 995 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 996 997 /* agpctrl */ 998 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 999 1000 /* global enable aperture access */ 1001 /* This flag is not accessed through MCHCFG register as in */ 1002 /* i850 chipset. */ 1003 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); 1004 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); 1005 /* clear any possible AGP-related error conditions */ 1006 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); 1007 return 0; 1008 } 1009 1010 static int intel_840_configure(void) 1011 { 1012 u32 temp; 1013 u16 temp2; 1014 struct aper_size_info_8 *current_size; 1015 1016 current_size = A_SIZE_8(agp_bridge->current_size); 1017 1018 /* aperture size */ 1019 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1020 1021 /* address to map to */ 1022 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1023 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1024 1025 /* attbase - aperture base */ 1026 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1027 1028 /* agpctrl */ 1029 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1030 1031 /* mcgcfg */ 1032 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); 1033 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); 1034 /* clear any possible error conditions */ 1035 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); 1036 return 0; 1037 } 1038 1039 static int intel_845_configure(void) 1040 { 1041 u32 temp; 1042 u8 temp2; 1043 struct aper_size_info_8 *current_size; 1044 1045 current_size = A_SIZE_8(agp_bridge->current_size); 1046 1047 /* aperture size */ 1048 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1049 1050 if (agp_bridge->apbase_config != 0) { 1051 pci_write_config_dword(agp_bridge->dev, AGP_APBASE, 1052 agp_bridge->apbase_config); 1053 } else { 1054 /* address to map to */ 1055 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1056 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1057 agp_bridge->apbase_config = temp; 1058 } 1059 1060 /* attbase - aperture base */ 1061 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1062 1063 /* agpctrl */ 1064 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1065 1066 /* agpm */ 1067 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); 1068 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 1069 /* clear any possible error conditions */ 1070 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 1071 return 0; 1072 } 1073 1074 static int intel_850_configure(void) 1075 { 1076 u32 temp; 1077 u16 temp2; 1078 struct aper_size_info_8 *current_size; 1079 1080 current_size = A_SIZE_8(agp_bridge->current_size); 1081 1082 /* aperture size */ 1083 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1084 1085 /* address to map to */ 1086 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1087 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1088 1089 /* attbase - aperture base */ 1090 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1091 1092 /* agpctrl */ 1093 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1094 1095 /* mcgcfg */ 1096 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); 1097 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); 1098 /* clear any possible AGP-related error conditions */ 1099 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); 1100 return 0; 1101 } 1102 1103 static int intel_860_configure(void) 1104 { 1105 u32 temp; 1106 u16 temp2; 1107 struct aper_size_info_8 *current_size; 1108 1109 current_size = A_SIZE_8(agp_bridge->current_size); 1110 1111 /* aperture size */ 1112 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1113 1114 /* address to map to */ 1115 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1116 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1117 1118 /* attbase - aperture base */ 1119 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1120 1121 /* agpctrl */ 1122 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1123 1124 /* mcgcfg */ 1125 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); 1126 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); 1127 /* clear any possible AGP-related error conditions */ 1128 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); 1129 return 0; 1130 } 1131 1132 static int intel_830mp_configure(void) 1133 { 1134 u32 temp; 1135 u16 temp2; 1136 struct aper_size_info_8 *current_size; 1137 1138 current_size = A_SIZE_8(agp_bridge->current_size); 1139 1140 /* aperture size */ 1141 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1142 1143 /* address to map to */ 1144 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1145 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1146 1147 /* attbase - aperture base */ 1148 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1149 1150 /* agpctrl */ 1151 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1152 1153 /* gmch */ 1154 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1155 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); 1156 /* clear any possible AGP-related error conditions */ 1157 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); 1158 return 0; 1159 } 1160 1161 static int intel_7505_configure(void) 1162 { 1163 u32 temp; 1164 u16 temp2; 1165 struct aper_size_info_8 *current_size; 1166 1167 current_size = A_SIZE_8(agp_bridge->current_size); 1168 1169 /* aperture size */ 1170 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1171 1172 /* address to map to */ 1173 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1174 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1175 1176 /* attbase - aperture base */ 1177 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1178 1179 /* agpctrl */ 1180 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1181 1182 /* mchcfg */ 1183 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); 1184 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); 1185 1186 return 0; 1187 } 1188 1189 /* Setup function */ 1190 static struct gatt_mask intel_generic_masks[] = 1191 { 1192 {.mask = 0x00000017, .type = 0} 1193 }; 1194 1195 static struct aper_size_info_8 intel_815_sizes[2] = 1196 { 1197 {64, 16384, 4, 0}, 1198 {32, 8192, 3, 8}, 1199 }; 1200 1201 static struct aper_size_info_8 intel_8xx_sizes[7] = 1202 { 1203 {256, 65536, 6, 0}, 1204 {128, 32768, 5, 32}, 1205 {64, 16384, 4, 48}, 1206 {32, 8192, 3, 56}, 1207 {16, 4096, 2, 60}, 1208 {8, 2048, 1, 62}, 1209 {4, 1024, 0, 63} 1210 }; 1211 1212 static struct aper_size_info_16 intel_generic_sizes[7] = 1213 { 1214 {256, 65536, 6, 0}, 1215 {128, 32768, 5, 32}, 1216 {64, 16384, 4, 48}, 1217 {32, 8192, 3, 56}, 1218 {16, 4096, 2, 60}, 1219 {8, 2048, 1, 62}, 1220 {4, 1024, 0, 63} 1221 }; 1222 1223 static struct aper_size_info_8 intel_830mp_sizes[4] = 1224 { 1225 {256, 65536, 6, 0}, 1226 {128, 32768, 5, 32}, 1227 {64, 16384, 4, 48}, 1228 {32, 8192, 3, 56} 1229 }; 1230 1231 static struct agp_bridge_driver intel_generic_driver = { 1232 .owner = THIS_MODULE, 1233 .aperture_sizes = intel_generic_sizes, 1234 .size_type = U16_APER_SIZE, 1235 .num_aperture_sizes = 7, 1236 .configure = intel_configure, 1237 .fetch_size = intel_fetch_size, 1238 .cleanup = intel_cleanup, 1239 .tlb_flush = intel_tlbflush, 1240 .mask_memory = agp_generic_mask_memory, 1241 .masks = intel_generic_masks, 1242 .agp_enable = agp_generic_enable, 1243 .cache_flush = global_cache_flush, 1244 .create_gatt_table = agp_generic_create_gatt_table, 1245 .free_gatt_table = agp_generic_free_gatt_table, 1246 .insert_memory = agp_generic_insert_memory, 1247 .remove_memory = agp_generic_remove_memory, 1248 .alloc_by_type = agp_generic_alloc_by_type, 1249 .free_by_type = agp_generic_free_by_type, 1250 .agp_alloc_page = agp_generic_alloc_page, 1251 .agp_destroy_page = agp_generic_destroy_page, 1252 }; 1253 1254 static struct agp_bridge_driver intel_810_driver = { 1255 .owner = THIS_MODULE, 1256 .aperture_sizes = intel_i810_sizes, 1257 .size_type = FIXED_APER_SIZE, 1258 .num_aperture_sizes = 2, 1259 .needs_scratch_page = TRUE, 1260 .configure = intel_i810_configure, 1261 .fetch_size = intel_i810_fetch_size, 1262 .cleanup = intel_i810_cleanup, 1263 .tlb_flush = intel_i810_tlbflush, 1264 .mask_memory = intel_i810_mask_memory, 1265 .masks = intel_i810_masks, 1266 .agp_enable = intel_i810_agp_enable, 1267 .cache_flush = global_cache_flush, 1268 .create_gatt_table = agp_generic_create_gatt_table, 1269 .free_gatt_table = agp_generic_free_gatt_table, 1270 .insert_memory = intel_i810_insert_entries, 1271 .remove_memory = intel_i810_remove_entries, 1272 .alloc_by_type = intel_i810_alloc_by_type, 1273 .free_by_type = intel_i810_free_by_type, 1274 .agp_alloc_page = agp_generic_alloc_page, 1275 .agp_destroy_page = agp_generic_destroy_page, 1276 }; 1277 1278 static struct agp_bridge_driver intel_815_driver = { 1279 .owner = THIS_MODULE, 1280 .aperture_sizes = intel_815_sizes, 1281 .size_type = U8_APER_SIZE, 1282 .num_aperture_sizes = 2, 1283 .configure = intel_815_configure, 1284 .fetch_size = intel_815_fetch_size, 1285 .cleanup = intel_8xx_cleanup, 1286 .tlb_flush = intel_8xx_tlbflush, 1287 .mask_memory = agp_generic_mask_memory, 1288 .masks = intel_generic_masks, 1289 .agp_enable = agp_generic_enable, 1290 .cache_flush = global_cache_flush, 1291 .create_gatt_table = agp_generic_create_gatt_table, 1292 .free_gatt_table = agp_generic_free_gatt_table, 1293 .insert_memory = agp_generic_insert_memory, 1294 .remove_memory = agp_generic_remove_memory, 1295 .alloc_by_type = agp_generic_alloc_by_type, 1296 .free_by_type = agp_generic_free_by_type, 1297 .agp_alloc_page = agp_generic_alloc_page, 1298 .agp_destroy_page = agp_generic_destroy_page, 1299 }; 1300 1301 static struct agp_bridge_driver intel_830_driver = { 1302 .owner = THIS_MODULE, 1303 .aperture_sizes = intel_i830_sizes, 1304 .size_type = FIXED_APER_SIZE, 1305 .num_aperture_sizes = 3, 1306 .needs_scratch_page = TRUE, 1307 .configure = intel_i830_configure, 1308 .fetch_size = intel_i830_fetch_size, 1309 .cleanup = intel_i830_cleanup, 1310 .tlb_flush = intel_i810_tlbflush, 1311 .mask_memory = intel_i810_mask_memory, 1312 .masks = intel_i810_masks, 1313 .agp_enable = intel_i810_agp_enable, 1314 .cache_flush = global_cache_flush, 1315 .create_gatt_table = intel_i830_create_gatt_table, 1316 .free_gatt_table = intel_i830_free_gatt_table, 1317 .insert_memory = intel_i830_insert_entries, 1318 .remove_memory = intel_i830_remove_entries, 1319 .alloc_by_type = intel_i830_alloc_by_type, 1320 .free_by_type = intel_i810_free_by_type, 1321 .agp_alloc_page = agp_generic_alloc_page, 1322 .agp_destroy_page = agp_generic_destroy_page, 1323 }; 1324 1325 static struct agp_bridge_driver intel_820_driver = { 1326 .owner = THIS_MODULE, 1327 .aperture_sizes = intel_8xx_sizes, 1328 .size_type = U8_APER_SIZE, 1329 .num_aperture_sizes = 7, 1330 .configure = intel_820_configure, 1331 .fetch_size = intel_8xx_fetch_size, 1332 .cleanup = intel_820_cleanup, 1333 .tlb_flush = intel_820_tlbflush, 1334 .mask_memory = agp_generic_mask_memory, 1335 .masks = intel_generic_masks, 1336 .agp_enable = agp_generic_enable, 1337 .cache_flush = global_cache_flush, 1338 .create_gatt_table = agp_generic_create_gatt_table, 1339 .free_gatt_table = agp_generic_free_gatt_table, 1340 .insert_memory = agp_generic_insert_memory, 1341 .remove_memory = agp_generic_remove_memory, 1342 .alloc_by_type = agp_generic_alloc_by_type, 1343 .free_by_type = agp_generic_free_by_type, 1344 .agp_alloc_page = agp_generic_alloc_page, 1345 .agp_destroy_page = agp_generic_destroy_page, 1346 }; 1347 1348 static struct agp_bridge_driver intel_830mp_driver = { 1349 .owner = THIS_MODULE, 1350 .aperture_sizes = intel_830mp_sizes, 1351 .size_type = U8_APER_SIZE, 1352 .num_aperture_sizes = 4, 1353 .configure = intel_830mp_configure, 1354 .fetch_size = intel_8xx_fetch_size, 1355 .cleanup = intel_8xx_cleanup, 1356 .tlb_flush = intel_8xx_tlbflush, 1357 .mask_memory = agp_generic_mask_memory, 1358 .masks = intel_generic_masks, 1359 .agp_enable = agp_generic_enable, 1360 .cache_flush = global_cache_flush, 1361 .create_gatt_table = agp_generic_create_gatt_table, 1362 .free_gatt_table = agp_generic_free_gatt_table, 1363 .insert_memory = agp_generic_insert_memory, 1364 .remove_memory = agp_generic_remove_memory, 1365 .alloc_by_type = agp_generic_alloc_by_type, 1366 .free_by_type = agp_generic_free_by_type, 1367 .agp_alloc_page = agp_generic_alloc_page, 1368 .agp_destroy_page = agp_generic_destroy_page, 1369 }; 1370 1371 static struct agp_bridge_driver intel_840_driver = { 1372 .owner = THIS_MODULE, 1373 .aperture_sizes = intel_8xx_sizes, 1374 .size_type = U8_APER_SIZE, 1375 .num_aperture_sizes = 7, 1376 .configure = intel_840_configure, 1377 .fetch_size = intel_8xx_fetch_size, 1378 .cleanup = intel_8xx_cleanup, 1379 .tlb_flush = intel_8xx_tlbflush, 1380 .mask_memory = agp_generic_mask_memory, 1381 .masks = intel_generic_masks, 1382 .agp_enable = agp_generic_enable, 1383 .cache_flush = global_cache_flush, 1384 .create_gatt_table = agp_generic_create_gatt_table, 1385 .free_gatt_table = agp_generic_free_gatt_table, 1386 .insert_memory = agp_generic_insert_memory, 1387 .remove_memory = agp_generic_remove_memory, 1388 .alloc_by_type = agp_generic_alloc_by_type, 1389 .free_by_type = agp_generic_free_by_type, 1390 .agp_alloc_page = agp_generic_alloc_page, 1391 .agp_destroy_page = agp_generic_destroy_page, 1392 }; 1393 1394 static struct agp_bridge_driver intel_845_driver = { 1395 .owner = THIS_MODULE, 1396 .aperture_sizes = intel_8xx_sizes, 1397 .size_type = U8_APER_SIZE, 1398 .num_aperture_sizes = 7, 1399 .configure = intel_845_configure, 1400 .fetch_size = intel_8xx_fetch_size, 1401 .cleanup = intel_8xx_cleanup, 1402 .tlb_flush = intel_8xx_tlbflush, 1403 .mask_memory = agp_generic_mask_memory, 1404 .masks = intel_generic_masks, 1405 .agp_enable = agp_generic_enable, 1406 .cache_flush = global_cache_flush, 1407 .create_gatt_table = agp_generic_create_gatt_table, 1408 .free_gatt_table = agp_generic_free_gatt_table, 1409 .insert_memory = agp_generic_insert_memory, 1410 .remove_memory = agp_generic_remove_memory, 1411 .alloc_by_type = agp_generic_alloc_by_type, 1412 .free_by_type = agp_generic_free_by_type, 1413 .agp_alloc_page = agp_generic_alloc_page, 1414 .agp_destroy_page = agp_generic_destroy_page, 1415 }; 1416 1417 static struct agp_bridge_driver intel_850_driver = { 1418 .owner = THIS_MODULE, 1419 .aperture_sizes = intel_8xx_sizes, 1420 .size_type = U8_APER_SIZE, 1421 .num_aperture_sizes = 7, 1422 .configure = intel_850_configure, 1423 .fetch_size = intel_8xx_fetch_size, 1424 .cleanup = intel_8xx_cleanup, 1425 .tlb_flush = intel_8xx_tlbflush, 1426 .mask_memory = agp_generic_mask_memory, 1427 .masks = intel_generic_masks, 1428 .agp_enable = agp_generic_enable, 1429 .cache_flush = global_cache_flush, 1430 .create_gatt_table = agp_generic_create_gatt_table, 1431 .free_gatt_table = agp_generic_free_gatt_table, 1432 .insert_memory = agp_generic_insert_memory, 1433 .remove_memory = agp_generic_remove_memory, 1434 .alloc_by_type = agp_generic_alloc_by_type, 1435 .free_by_type = agp_generic_free_by_type, 1436 .agp_alloc_page = agp_generic_alloc_page, 1437 .agp_destroy_page = agp_generic_destroy_page, 1438 }; 1439 1440 static struct agp_bridge_driver intel_860_driver = { 1441 .owner = THIS_MODULE, 1442 .aperture_sizes = intel_8xx_sizes, 1443 .size_type = U8_APER_SIZE, 1444 .num_aperture_sizes = 7, 1445 .configure = intel_860_configure, 1446 .fetch_size = intel_8xx_fetch_size, 1447 .cleanup = intel_8xx_cleanup, 1448 .tlb_flush = intel_8xx_tlbflush, 1449 .mask_memory = agp_generic_mask_memory, 1450 .masks = intel_generic_masks, 1451 .agp_enable = agp_generic_enable, 1452 .cache_flush = global_cache_flush, 1453 .create_gatt_table = agp_generic_create_gatt_table, 1454 .free_gatt_table = agp_generic_free_gatt_table, 1455 .insert_memory = agp_generic_insert_memory, 1456 .remove_memory = agp_generic_remove_memory, 1457 .alloc_by_type = agp_generic_alloc_by_type, 1458 .free_by_type = agp_generic_free_by_type, 1459 .agp_alloc_page = agp_generic_alloc_page, 1460 .agp_destroy_page = agp_generic_destroy_page, 1461 }; 1462 1463 static struct agp_bridge_driver intel_915_driver = { 1464 .owner = THIS_MODULE, 1465 .aperture_sizes = intel_i830_sizes, 1466 .size_type = FIXED_APER_SIZE, 1467 .num_aperture_sizes = 3, 1468 .needs_scratch_page = TRUE, 1469 .configure = intel_i915_configure, 1470 .fetch_size = intel_i915_fetch_size, 1471 .cleanup = intel_i915_cleanup, 1472 .tlb_flush = intel_i810_tlbflush, 1473 .mask_memory = intel_i810_mask_memory, 1474 .masks = intel_i810_masks, 1475 .agp_enable = intel_i810_agp_enable, 1476 .cache_flush = global_cache_flush, 1477 .create_gatt_table = intel_i915_create_gatt_table, 1478 .free_gatt_table = intel_i830_free_gatt_table, 1479 .insert_memory = intel_i915_insert_entries, 1480 .remove_memory = intel_i915_remove_entries, 1481 .alloc_by_type = intel_i830_alloc_by_type, 1482 .free_by_type = intel_i810_free_by_type, 1483 .agp_alloc_page = agp_generic_alloc_page, 1484 .agp_destroy_page = agp_generic_destroy_page, 1485 }; 1486 1487 1488 static struct agp_bridge_driver intel_7505_driver = { 1489 .owner = THIS_MODULE, 1490 .aperture_sizes = intel_8xx_sizes, 1491 .size_type = U8_APER_SIZE, 1492 .num_aperture_sizes = 7, 1493 .configure = intel_7505_configure, 1494 .fetch_size = intel_8xx_fetch_size, 1495 .cleanup = intel_8xx_cleanup, 1496 .tlb_flush = intel_8xx_tlbflush, 1497 .mask_memory = agp_generic_mask_memory, 1498 .masks = intel_generic_masks, 1499 .agp_enable = agp_generic_enable, 1500 .cache_flush = global_cache_flush, 1501 .create_gatt_table = agp_generic_create_gatt_table, 1502 .free_gatt_table = agp_generic_free_gatt_table, 1503 .insert_memory = agp_generic_insert_memory, 1504 .remove_memory = agp_generic_remove_memory, 1505 .alloc_by_type = agp_generic_alloc_by_type, 1506 .free_by_type = agp_generic_free_by_type, 1507 .agp_alloc_page = agp_generic_alloc_page, 1508 .agp_destroy_page = agp_generic_destroy_page, 1509 }; 1510 1511 static int find_i810(u16 device) 1512 { 1513 struct pci_dev *i810_dev; 1514 1515 i810_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1516 if (!i810_dev) 1517 return 0; 1518 intel_i810_private.i810_dev = i810_dev; 1519 return 1; 1520 } 1521 1522 static int find_i830(u16 device) 1523 { 1524 struct pci_dev *i830_dev; 1525 1526 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1527 if (i830_dev && PCI_FUNC(i830_dev->devfn) != 0) { 1528 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 1529 device, i830_dev); 1530 } 1531 1532 if (!i830_dev) 1533 return 0; 1534 1535 intel_i830_private.i830_dev = i830_dev; 1536 return 1; 1537 } 1538 1539 static int __devinit agp_intel_probe(struct pci_dev *pdev, 1540 const struct pci_device_id *ent) 1541 { 1542 struct agp_bridge_data *bridge; 1543 char *name = "(unknown)"; 1544 u8 cap_ptr = 0; 1545 struct resource *r; 1546 1547 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 1548 1549 bridge = agp_alloc_bridge(); 1550 if (!bridge) 1551 return -ENOMEM; 1552 1553 switch (pdev->device) { 1554 case PCI_DEVICE_ID_INTEL_82443LX_0: 1555 bridge->driver = &intel_generic_driver; 1556 name = "440LX"; 1557 break; 1558 case PCI_DEVICE_ID_INTEL_82443BX_0: 1559 bridge->driver = &intel_generic_driver; 1560 name = "440BX"; 1561 break; 1562 case PCI_DEVICE_ID_INTEL_82443GX_0: 1563 bridge->driver = &intel_generic_driver; 1564 name = "440GX"; 1565 break; 1566 case PCI_DEVICE_ID_INTEL_82810_MC1: 1567 name = "i810"; 1568 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG1)) 1569 goto fail; 1570 bridge->driver = &intel_810_driver; 1571 break; 1572 case PCI_DEVICE_ID_INTEL_82810_MC3: 1573 name = "i810 DC100"; 1574 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG3)) 1575 goto fail; 1576 bridge->driver = &intel_810_driver; 1577 break; 1578 case PCI_DEVICE_ID_INTEL_82810E_MC: 1579 name = "i810 E"; 1580 if (!find_i810(PCI_DEVICE_ID_INTEL_82810E_IG)) 1581 goto fail; 1582 bridge->driver = &intel_810_driver; 1583 break; 1584 case PCI_DEVICE_ID_INTEL_82815_MC: 1585 /* 1586 * The i815 can operate either as an i810 style 1587 * integrated device, or as an AGP4X motherboard. 1588 */ 1589 if (find_i810(PCI_DEVICE_ID_INTEL_82815_CGC)) 1590 bridge->driver = &intel_810_driver; 1591 else 1592 bridge->driver = &intel_815_driver; 1593 name = "i815"; 1594 break; 1595 case PCI_DEVICE_ID_INTEL_82820_HB: 1596 case PCI_DEVICE_ID_INTEL_82820_UP_HB: 1597 bridge->driver = &intel_820_driver; 1598 name = "i820"; 1599 break; 1600 case PCI_DEVICE_ID_INTEL_82830_HB: 1601 if (find_i830(PCI_DEVICE_ID_INTEL_82830_CGC)) { 1602 bridge->driver = &intel_830_driver; 1603 } else { 1604 bridge->driver = &intel_830mp_driver; 1605 } 1606 name = "830M"; 1607 break; 1608 case PCI_DEVICE_ID_INTEL_82840_HB: 1609 bridge->driver = &intel_840_driver; 1610 name = "i840"; 1611 break; 1612 case PCI_DEVICE_ID_INTEL_82845_HB: 1613 bridge->driver = &intel_845_driver; 1614 name = "i845"; 1615 break; 1616 case PCI_DEVICE_ID_INTEL_82845G_HB: 1617 if (find_i830(PCI_DEVICE_ID_INTEL_82845G_IG)) { 1618 bridge->driver = &intel_830_driver; 1619 } else { 1620 bridge->driver = &intel_845_driver; 1621 } 1622 name = "845G"; 1623 break; 1624 case PCI_DEVICE_ID_INTEL_82850_HB: 1625 bridge->driver = &intel_850_driver; 1626 name = "i850"; 1627 break; 1628 case PCI_DEVICE_ID_INTEL_82855PM_HB: 1629 bridge->driver = &intel_845_driver; 1630 name = "855PM"; 1631 break; 1632 case PCI_DEVICE_ID_INTEL_82855GM_HB: 1633 if (find_i830(PCI_DEVICE_ID_INTEL_82855GM_IG)) { 1634 bridge->driver = &intel_830_driver; 1635 name = "855"; 1636 } else { 1637 bridge->driver = &intel_845_driver; 1638 name = "855GM"; 1639 } 1640 break; 1641 case PCI_DEVICE_ID_INTEL_82860_HB: 1642 bridge->driver = &intel_860_driver; 1643 name = "i860"; 1644 break; 1645 case PCI_DEVICE_ID_INTEL_82865_HB: 1646 if (find_i830(PCI_DEVICE_ID_INTEL_82865_IG)) { 1647 bridge->driver = &intel_830_driver; 1648 } else { 1649 bridge->driver = &intel_845_driver; 1650 } 1651 name = "865"; 1652 break; 1653 case PCI_DEVICE_ID_INTEL_82875_HB: 1654 bridge->driver = &intel_845_driver; 1655 name = "i875"; 1656 break; 1657 case PCI_DEVICE_ID_INTEL_82915G_HB: 1658 if (find_i830(PCI_DEVICE_ID_INTEL_82915G_IG)) { 1659 bridge->driver = &intel_915_driver; 1660 } else { 1661 bridge->driver = &intel_845_driver; 1662 } 1663 name = "915G"; 1664 break; 1665 case PCI_DEVICE_ID_INTEL_82915GM_HB: 1666 if (find_i830(PCI_DEVICE_ID_INTEL_82915GM_IG)) { 1667 bridge->driver = &intel_915_driver; 1668 } else { 1669 bridge->driver = &intel_845_driver; 1670 } 1671 name = "915GM"; 1672 break; 1673 case PCI_DEVICE_ID_INTEL_82945G_HB: 1674 if (find_i830(PCI_DEVICE_ID_INTEL_82945G_IG)) { 1675 bridge->driver = &intel_915_driver; 1676 } else { 1677 bridge->driver = &intel_845_driver; 1678 } 1679 name = "945G"; 1680 break; 1681 case PCI_DEVICE_ID_INTEL_7505_0: 1682 bridge->driver = &intel_7505_driver; 1683 name = "E7505"; 1684 break; 1685 case PCI_DEVICE_ID_INTEL_7205_0: 1686 bridge->driver = &intel_7505_driver; 1687 name = "E7205"; 1688 break; 1689 default: 1690 if (cap_ptr) 1691 printk(KERN_WARNING PFX "Unsupported Intel chipset (device id: %04x)\n", 1692 pdev->device); 1693 agp_put_bridge(bridge); 1694 return -ENODEV; 1695 }; 1696 1697 bridge->dev = pdev; 1698 bridge->capndx = cap_ptr; 1699 1700 if (bridge->driver == &intel_810_driver) 1701 bridge->dev_private_data = &intel_i810_private; 1702 else if (bridge->driver == &intel_830_driver) 1703 bridge->dev_private_data = &intel_i830_private; 1704 1705 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", name); 1706 1707 /* 1708 * The following fixes the case where the BIOS has "forgotten" to 1709 * provide an address range for the GART. 1710 * 20030610 - hamish@zot.org 1711 */ 1712 r = &pdev->resource[0]; 1713 if (!r->start && r->end) { 1714 if(pci_assign_resource(pdev, 0)) { 1715 printk(KERN_ERR PFX "could not assign resource 0\n"); 1716 agp_put_bridge(bridge); 1717 return -ENODEV; 1718 } 1719 } 1720 1721 /* 1722 * If the device has not been properly setup, the following will catch 1723 * the problem and should stop the system from crashing. 1724 * 20030610 - hamish@zot.org 1725 */ 1726 if (pci_enable_device(pdev)) { 1727 printk(KERN_ERR PFX "Unable to Enable PCI device\n"); 1728 agp_put_bridge(bridge); 1729 return -ENODEV; 1730 } 1731 1732 /* Fill in the mode register */ 1733 if (cap_ptr) { 1734 pci_read_config_dword(pdev, 1735 bridge->capndx+PCI_AGP_STATUS, 1736 &bridge->mode); 1737 } 1738 1739 pci_set_drvdata(pdev, bridge); 1740 return agp_add_bridge(bridge); 1741 1742 fail: 1743 printk(KERN_ERR PFX "Detected an Intel %s chipset, " 1744 "but could not find the secondary device.\n", name); 1745 agp_put_bridge(bridge); 1746 return -ENODEV; 1747 } 1748 1749 static void __devexit agp_intel_remove(struct pci_dev *pdev) 1750 { 1751 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 1752 1753 agp_remove_bridge(bridge); 1754 1755 if (intel_i810_private.i810_dev) 1756 pci_dev_put(intel_i810_private.i810_dev); 1757 if (intel_i830_private.i830_dev) 1758 pci_dev_put(intel_i830_private.i830_dev); 1759 1760 agp_put_bridge(bridge); 1761 } 1762 1763 static int agp_intel_resume(struct pci_dev *pdev) 1764 { 1765 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 1766 1767 pci_restore_state(pdev); 1768 1769 if (bridge->driver == &intel_generic_driver) 1770 intel_configure(); 1771 else if (bridge->driver == &intel_850_driver) 1772 intel_850_configure(); 1773 else if (bridge->driver == &intel_845_driver) 1774 intel_845_configure(); 1775 else if (bridge->driver == &intel_830mp_driver) 1776 intel_830mp_configure(); 1777 else if (bridge->driver == &intel_915_driver) 1778 intel_i915_configure(); 1779 else if (bridge->driver == &intel_830_driver) 1780 intel_i830_configure(); 1781 else if (bridge->driver == &intel_810_driver) 1782 intel_i810_configure(); 1783 1784 return 0; 1785 } 1786 1787 static struct pci_device_id agp_intel_pci_table[] = { 1788 #define ID(x) \ 1789 { \ 1790 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 1791 .class_mask = ~0, \ 1792 .vendor = PCI_VENDOR_ID_INTEL, \ 1793 .device = x, \ 1794 .subvendor = PCI_ANY_ID, \ 1795 .subdevice = PCI_ANY_ID, \ 1796 } 1797 ID(PCI_DEVICE_ID_INTEL_82443LX_0), 1798 ID(PCI_DEVICE_ID_INTEL_82443BX_0), 1799 ID(PCI_DEVICE_ID_INTEL_82443GX_0), 1800 ID(PCI_DEVICE_ID_INTEL_82810_MC1), 1801 ID(PCI_DEVICE_ID_INTEL_82810_MC3), 1802 ID(PCI_DEVICE_ID_INTEL_82810E_MC), 1803 ID(PCI_DEVICE_ID_INTEL_82815_MC), 1804 ID(PCI_DEVICE_ID_INTEL_82820_HB), 1805 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), 1806 ID(PCI_DEVICE_ID_INTEL_82830_HB), 1807 ID(PCI_DEVICE_ID_INTEL_82840_HB), 1808 ID(PCI_DEVICE_ID_INTEL_82845_HB), 1809 ID(PCI_DEVICE_ID_INTEL_82845G_HB), 1810 ID(PCI_DEVICE_ID_INTEL_82850_HB), 1811 ID(PCI_DEVICE_ID_INTEL_82855PM_HB), 1812 ID(PCI_DEVICE_ID_INTEL_82855GM_HB), 1813 ID(PCI_DEVICE_ID_INTEL_82860_HB), 1814 ID(PCI_DEVICE_ID_INTEL_82865_HB), 1815 ID(PCI_DEVICE_ID_INTEL_82875_HB), 1816 ID(PCI_DEVICE_ID_INTEL_7505_0), 1817 ID(PCI_DEVICE_ID_INTEL_7205_0), 1818 ID(PCI_DEVICE_ID_INTEL_82915G_HB), 1819 ID(PCI_DEVICE_ID_INTEL_82915GM_HB), 1820 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 1821 { } 1822 }; 1823 1824 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); 1825 1826 static struct pci_driver agp_intel_pci_driver = { 1827 .name = "agpgart-intel", 1828 .id_table = agp_intel_pci_table, 1829 .probe = agp_intel_probe, 1830 .remove = __devexit_p(agp_intel_remove), 1831 .resume = agp_intel_resume, 1832 }; 1833 1834 static int __init agp_intel_init(void) 1835 { 1836 if (agp_off) 1837 return -EINVAL; 1838 return pci_register_driver(&agp_intel_pci_driver); 1839 } 1840 1841 static void __exit agp_intel_cleanup(void) 1842 { 1843 pci_unregister_driver(&agp_intel_pci_driver); 1844 } 1845 1846 module_init(agp_intel_init); 1847 module_exit(agp_intel_cleanup); 1848 1849 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>"); 1850 MODULE_LICENSE("GPL and additional rights"); 1851