1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * 4 * Bluetooth support for Intel PCIe devices 5 * 6 * Copyright (C) 2024 Intel Corporation 7 */ 8 9 /* Control and Status Register(BTINTEL_PCIE_CSR) */ 10 #define BTINTEL_PCIE_CSR_BASE (0x000) 11 #define BTINTEL_PCIE_CSR_FUNC_CTRL_REG (BTINTEL_PCIE_CSR_BASE + 0x024) 12 #define BTINTEL_PCIE_CSR_HW_REV_REG (BTINTEL_PCIE_CSR_BASE + 0x028) 13 #define BTINTEL_PCIE_CSR_RF_ID_REG (BTINTEL_PCIE_CSR_BASE + 0x09C) 14 #define BTINTEL_PCIE_CSR_BOOT_STAGE_REG (BTINTEL_PCIE_CSR_BASE + 0x108) 15 #define BTINTEL_PCIE_CSR_IPC_CONTROL_REG (BTINTEL_PCIE_CSR_BASE + 0x10C) 16 #define BTINTEL_PCIE_CSR_IPC_STATUS_REG (BTINTEL_PCIE_CSR_BASE + 0x110) 17 #define BTINTEL_PCIE_CSR_IPC_SLEEP_CTL_REG (BTINTEL_PCIE_CSR_BASE + 0x114) 18 #define BTINTEL_PCIE_CSR_CI_ADDR_LSB_REG (BTINTEL_PCIE_CSR_BASE + 0x118) 19 #define BTINTEL_PCIE_CSR_CI_ADDR_MSB_REG (BTINTEL_PCIE_CSR_BASE + 0x11C) 20 #define BTINTEL_PCIE_CSR_IMG_RESPONSE_REG (BTINTEL_PCIE_CSR_BASE + 0x12C) 21 #define BTINTEL_PCIE_CSR_MBOX_1_REG (BTINTEL_PCIE_CSR_BASE + 0x170) 22 #define BTINTEL_PCIE_CSR_MBOX_2_REG (BTINTEL_PCIE_CSR_BASE + 0x174) 23 #define BTINTEL_PCIE_CSR_MBOX_3_REG (BTINTEL_PCIE_CSR_BASE + 0x178) 24 #define BTINTEL_PCIE_CSR_MBOX_4_REG (BTINTEL_PCIE_CSR_BASE + 0x17C) 25 #define BTINTEL_PCIE_CSR_MBOX_STATUS_REG (BTINTEL_PCIE_CSR_BASE + 0x180) 26 #define BTINTEL_PCIE_PRPH_DEV_ADDR_REG (BTINTEL_PCIE_CSR_BASE + 0x440) 27 #define BTINTEL_PCIE_PRPH_DEV_RD_REG (BTINTEL_PCIE_CSR_BASE + 0x458) 28 #define BTINTEL_PCIE_CSR_HBUS_TARG_WRPTR (BTINTEL_PCIE_CSR_BASE + 0x460) 29 30 /* BTINTEL_PCIE_CSR Function Control Register */ 31 #define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA (BIT(0)) 32 #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT (BIT(6)) 33 #define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT (BIT(7)) 34 #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS (BIT(20)) 35 36 #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ (BIT(21)) 37 38 #define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_STS (BIT(28)) 39 #define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_DISCON (BIT(29)) 40 #define BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET (BIT(31)) 41 42 /* Value for BTINTEL_PCIE_CSR_BOOT_STAGE register */ 43 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM (BIT(0)) 44 #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML (BIT(1)) 45 #define BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW (BIT(2)) 46 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM_LOCKDOWN (BIT(10)) 47 #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML_LOCKDOWN (BIT(11)) 48 #define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_WARNING (BIT(12)) 49 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ABORT_HANDLER (BIT(13)) 50 #define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_HALTED (BIT(14)) 51 #define BTINTEL_PCIE_CSR_BOOT_STAGE_MAC_ACCESS_ON (BIT(16)) 52 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ALIVE (BIT(23)) 53 #define BTINTEL_PCIE_CSR_BOOT_STAGE_D3_STATE_READY (BIT(24)) 54 55 /* Registers for MSI-X */ 56 #define BTINTEL_PCIE_CSR_MSIX_BASE (0x2000) 57 #define BTINTEL_PCIE_CSR_MSIX_FH_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0800) 58 #define BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0804) 59 #define BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0808) 60 #define BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x080C) 61 #define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_ST (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0810) 62 #define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_EN (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0814) 63 #define BTINTEL_PCIE_CSR_MSIX_IVAR_BASE (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0880) 64 #define BTINTEL_PCIE_CSR_MSIX_IVAR(cause) (BTINTEL_PCIE_CSR_MSIX_IVAR_BASE + (cause)) 65 66 /* IOSF Debug Register */ 67 #define BTINTEL_PCIE_DBGC_BASE_ADDR (0xf3800300) 68 #define BTINTEL_PCIE_DBGC_CUR_DBGBUFF_STATUS (BTINTEL_PCIE_DBGC_BASE_ADDR + 0x1C) 69 #define BTINTEL_PCIE_DBGC_DBGBUFF_WRAP_ARND (BTINTEL_PCIE_DBGC_BASE_ADDR + 0x2C) 70 71 #define BTINTEL_PCIE_DBG_IDX_BIT_MASK 0x0F 72 #define BTINTEL_PCIE_DBGC_DBG_BUF_IDX(data) (((data) >> 24) & BTINTEL_PCIE_DBG_IDX_BIT_MASK) 73 #define BTINTEL_PCIE_DBG_OFFSET_BIT_MASK 0xFFFFFF 74 75 /* The DRAM buffer count, each buffer size, and 76 * fragment buffer size 77 */ 78 #define BTINTEL_PCIE_DBGC_BUFFER_COUNT 16 79 #define BTINTEL_PCIE_DBGC_BUFFER_SIZE (256 * 1024) /* 256 KB */ 80 81 #define BTINTEL_PCIE_DBGC_FRAG_VERSION 1 82 #define BTINTEL_PCIE_DBGC_FRAG_BUFFER_COUNT BTINTEL_PCIE_DBGC_BUFFER_COUNT 83 84 /* Magic number(4), version(4), size of payload length(4) */ 85 #define BTINTEL_PCIE_DBGC_FRAG_HEADER_SIZE 12 86 87 /* Num of alloc Dbg buff (4) + (LSB(4), MSB(4), Size(4)) for each buffer */ 88 #define BTINTEL_PCIE_DBGC_FRAG_PAYLOAD_SIZE 196 89 90 /* Causes for the FH register interrupts */ 91 enum msix_fh_int_causes { 92 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_0 = BIT(0), /* cause 0 */ 93 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_1 = BIT(1), /* cause 1 */ 94 }; 95 96 /* Causes for the HW register interrupts */ 97 enum msix_hw_int_causes { 98 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0 = BIT(0), /* cause 32 */ 99 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP1 = BIT(1), /* cause 33 */ 100 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_HWEXP = BIT(3), /* cause 35 */ 101 }; 102 103 /* PCIe device states 104 * Host-Device interface is active 105 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD) 106 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD) 107 */ 108 enum { 109 BTINTEL_PCIE_STATE_D0 = 0, 110 BTINTEL_PCIE_STATE_D3_HOT = 2, 111 BTINTEL_PCIE_STATE_D3_COLD = 3, 112 }; 113 114 enum { 115 BTINTEL_PCIE_CORE_HALTED, 116 BTINTEL_PCIE_HWEXP_INPROGRESS, 117 BTINTEL_PCIE_COREDUMP_INPROGRESS, 118 BTINTEL_PCIE_RECOVERY_IN_PROGRESS, 119 BTINTEL_PCIE_SETUP_DONE 120 }; 121 122 enum btintel_pcie_tlv_type { 123 BTINTEL_CNVI_BT, 124 BTINTEL_WRITE_PTR, 125 BTINTEL_WRAP_CTR, 126 BTINTEL_TRIGGER_REASON, 127 BTINTEL_FW_SHA, 128 BTINTEL_CNVR_TOP, 129 BTINTEL_CNVI_TOP, 130 BTINTEL_DUMP_TIME, 131 BTINTEL_FW_BUILD, 132 BTINTEL_VENDOR, 133 BTINTEL_DRIVER 134 }; 135 136 /* causes for the MBOX interrupts */ 137 enum msix_mbox_int_causes { 138 BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX1 = BIT(0), /* cause MBOX1 */ 139 BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX2 = BIT(1), /* cause MBOX2 */ 140 BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX3 = BIT(2), /* cause MBOX3 */ 141 BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX4 = BIT(3), /* cause MBOX4 */ 142 }; 143 144 #define BTINTEL_PCIE_MSIX_NON_AUTO_CLEAR_CAUSE BIT(7) 145 146 /* Minimum and Maximum number of MSI-X Vector 147 * Intel Bluetooth PCIe support only 1 vector 148 */ 149 #define BTINTEL_PCIE_MSIX_VEC_MAX 1 150 #define BTINTEL_PCIE_MSIX_VEC_MIN 1 151 152 /* Default poll time for MAC access during init */ 153 #define BTINTEL_DEFAULT_MAC_ACCESS_TIMEOUT_US 200000 154 155 /* Default interrupt timeout in msec */ 156 #define BTINTEL_DEFAULT_INTR_TIMEOUT_MS 3000 157 158 #define BTINTEL_PCIE_DX_TRANSITION_MAX_RETRIES 3 159 160 /* The number of descriptors in TX queues */ 161 #define BTINTEL_PCIE_TX_DESCS_COUNT 32 162 163 /* The number of descriptors in RX queues */ 164 #define BTINTEL_PCIE_RX_DESCS_COUNT 64 165 166 /* Number of Queue for TX and RX 167 * It indicates the index of the IA(Index Array) 168 */ 169 enum { 170 BTINTEL_PCIE_TXQ_NUM = 0, 171 BTINTEL_PCIE_RXQ_NUM = 1, 172 BTINTEL_PCIE_NUM_QUEUES = 2, 173 }; 174 175 /* The size of DMA buffer for TX and RX in bytes */ 176 #define BTINTEL_PCIE_BUFFER_SIZE 4096 177 178 #define BTINTEL_PCIE_TX_WAIT_TIMEOUT_MS 500 179 180 /* Doorbell vector for TFD */ 181 #define BTINTEL_PCIE_TX_DB_VEC 0 182 183 /* Doorbell vector for FRBD */ 184 #define BTINTEL_PCIE_RX_DB_VEC 513 185 186 /* RBD buffer size mapping */ 187 #define BTINTEL_PCIE_RBD_SIZE_4K 0x04 188 189 /* 190 * Struct for Context Information (v2) 191 * 192 * All members are write-only for host and read-only for device. 193 * 194 * @version: Version of context information 195 * @size: Size of context information 196 * @config: Config with which host wants peripheral to execute 197 * Subset of capability register published by device 198 * @addr_tr_hia: Address of TR Head Index Array 199 * @addr_tr_tia: Address of TR Tail Index Array 200 * @addr_cr_hia: Address of CR Head Index Array 201 * @addr_cr_tia: Address of CR Tail Index Array 202 * @num_tr_ia: Number of entries in TR Index Arrays 203 * @num_cr_ia: Number of entries in CR Index Arrays 204 * @rbd_siz: RBD Size { 0x4=4K } 205 * @addr_tfdq: Address of TFD Queue(tx) 206 * @addr_urbdq0: Address of URBD Queue(tx) 207 * @num_tfdq: Number of TFD in TFD Queue(tx) 208 * @num_urbdq0: Number of URBD in URBD Queue(tx) 209 * @tfdq_db_vec: Queue number of TFD 210 * @urbdq0_db_vec: Queue number of URBD 211 * @addr_frbdq: Address of FRBD Queue(rx) 212 * @addr_urbdq1: Address of URBD Queue(rx) 213 * @num_frbdq: Number of FRBD in FRBD Queue(rx) 214 * @frbdq_db_vec: Queue number of FRBD 215 * @num_urbdq1: Number of URBD in URBD Queue(rx) 216 * @urbdq_db_vec: Queue number of URBDQ1 217 * @tr_msi_vec: Transfer Ring MSI-X Vector 218 * @cr_msi_vec: Completion Ring MSI-X Vector 219 * @dbgc_addr: DBGC first fragment address 220 * @dbgc_size: DBGC buffer size 221 * @early_enable: Enarly debug enable 222 * @dbg_output_mode: Debug output mode 223 * Bit[4] DBGC O/P { 0=SRAM, 1=DRAM(not relevant for NPK) } 224 * Bit[5] DBGC I/P { 0=BDBG, 1=DBGI } 225 * Bits[6:7] DBGI O/P(relevant if bit[5] = 1) 226 * 0=BT DBGC, 1=WiFi DBGC, 2=NPK } 227 * @dbg_preset: Debug preset 228 * @ext_addr: Address of context information extension 229 * @ext_size: Size of context information part 230 * 231 * Total 38 DWords 232 */ 233 struct ctx_info { 234 u16 version; 235 u16 size; 236 u32 config; 237 u32 reserved_dw02; 238 u32 reserved_dw03; 239 u64 addr_tr_hia; 240 u64 addr_tr_tia; 241 u64 addr_cr_hia; 242 u64 addr_cr_tia; 243 u16 num_tr_ia; 244 u16 num_cr_ia; 245 u32 rbd_size:4, 246 reserved_dw13:28; 247 u64 addr_tfdq; 248 u64 addr_urbdq0; 249 u16 num_tfdq; 250 u16 num_urbdq0; 251 u16 tfdq_db_vec; 252 u16 urbdq0_db_vec; 253 u64 addr_frbdq; 254 u64 addr_urbdq1; 255 u16 num_frbdq; 256 u16 frbdq_db_vec; 257 u16 num_urbdq1; 258 u16 urbdq_db_vec; 259 u16 tr_msi_vec; 260 u16 cr_msi_vec; 261 u32 reserved_dw27; 262 u64 dbgc_addr; 263 u32 dbgc_size; 264 u32 early_enable:1, 265 reserved_dw31:3, 266 dbg_output_mode:4, 267 dbg_preset:8, 268 reserved2_dw31:16; 269 u64 ext_addr; 270 u32 ext_size; 271 u32 test_param; 272 u32 reserved_dw36; 273 u32 reserved_dw37; 274 } __packed; 275 276 /* Transfer Descriptor for TX 277 * @type: Not in use. Set to 0x0 278 * @size: Size of data in the buffer 279 * @addr: DMA Address of buffer 280 */ 281 struct tfd { 282 u8 type; 283 u16 size; 284 u8 reserved; 285 u64 addr; 286 u32 reserved1; 287 } __packed; 288 289 /* URB Descriptor for TX 290 * @tfd_index: Index of TFD in TFDQ + 1 291 * @num_txq: Queue index of TFD Queue 292 * @cmpl_count: Completion count. Always 0x01 293 * @immediate_cmpl: Immediate completion flag: Always 0x01 294 */ 295 struct urbd0 { 296 u32 tfd_index:16, 297 num_txq:8, 298 cmpl_count:4, 299 reserved:3, 300 immediate_cmpl:1; 301 } __packed; 302 303 /* FRB Descriptor for RX 304 * @tag: RX buffer tag (index of RX buffer queue) 305 * @addr: Address of buffer 306 */ 307 struct frbd { 308 u32 tag:16, 309 reserved:16; 310 u32 reserved2; 311 u64 addr; 312 } __packed; 313 314 /* URB Descriptor for RX 315 * @frbd_tag: Tag from FRBD 316 * @status: Status 317 */ 318 struct urbd1 { 319 u32 frbd_tag:16, 320 status:1, 321 reserved:14, 322 fixed:1; 323 } __packed; 324 325 /* RFH header in RX packet 326 * @packet_len: Length of the data in the buffer 327 * @rxq: RX Queue number 328 * @cmd_id: Command ID. Not in Use 329 */ 330 struct rfh_hdr { 331 u64 packet_len:16, 332 rxq:6, 333 reserved:10, 334 cmd_id:16, 335 reserved1:16; 336 } __packed; 337 338 /* Internal data buffer 339 * @data: pointer to the data buffer 340 * @p_addr: physical address of data buffer 341 */ 342 struct data_buf { 343 u8 *data; 344 dma_addr_t data_p_addr; 345 }; 346 347 /* Index Array */ 348 struct ia { 349 dma_addr_t tr_hia_p_addr; 350 u16 *tr_hia; 351 dma_addr_t tr_tia_p_addr; 352 u16 *tr_tia; 353 dma_addr_t cr_hia_p_addr; 354 u16 *cr_hia; 355 dma_addr_t cr_tia_p_addr; 356 u16 *cr_tia; 357 }; 358 359 /* Structure for TX Queue 360 * @count: Number of descriptors 361 * @tfds: Array of TFD 362 * @urbd0s: Array of URBD0 363 * @buf: Array of data_buf structure 364 */ 365 struct txq { 366 u16 count; 367 368 dma_addr_t tfds_p_addr; 369 struct tfd *tfds; 370 371 dma_addr_t urbd0s_p_addr; 372 struct urbd0 *urbd0s; 373 374 dma_addr_t buf_p_addr; 375 void *buf_v_addr; 376 struct data_buf *bufs; 377 }; 378 379 /* Structure for RX Queue 380 * @count: Number of descriptors 381 * @frbds: Array of FRBD 382 * @urbd1s: Array of URBD1 383 * @buf: Array of data_buf structure 384 */ 385 struct rxq { 386 u16 count; 387 388 dma_addr_t frbds_p_addr; 389 struct frbd *frbds; 390 391 dma_addr_t urbd1s_p_addr; 392 struct urbd1 *urbd1s; 393 394 dma_addr_t buf_p_addr; 395 void *buf_v_addr; 396 struct data_buf *bufs; 397 }; 398 399 /* Structure for DRAM Buffer 400 * @count: Number of descriptors 401 * @buf: Array of data_buf structure 402 */ 403 struct btintel_pcie_dbgc { 404 u16 count; 405 406 void *frag_v_addr; 407 dma_addr_t frag_p_addr; 408 u16 frag_size; 409 410 dma_addr_t buf_p_addr; 411 void *buf_v_addr; 412 struct data_buf *bufs; 413 }; 414 415 struct btintel_pcie_dump_header { 416 const char *driver_name; 417 u32 cnvi_top; 418 u32 cnvr_top; 419 u16 fw_timestamp; 420 u8 fw_build_type; 421 u32 fw_build_num; 422 u32 fw_git_sha1; 423 u32 cnvi_bt; 424 u32 write_ptr; 425 u32 wrap_ctr; 426 u16 trigger_reason; 427 int state; 428 }; 429 430 /* struct btintel_pcie_data 431 * @pdev: pci device 432 * @hdev: hdev device 433 * @flags: driver state 434 * @irq_lock: spinlock for MSI-X 435 * @hci_rx_lock: spinlock for HCI RX flow 436 * @base_addr: pci base address (from BAR) 437 * @msix_entries: array of MSI-X entries 438 * @msix_enabled: true if MSI-X is enabled; 439 * @alloc_vecs: number of interrupt vectors allocated 440 * @def_irq: default irq for all causes 441 * @fh_init_mask: initial unmasked rxq causes 442 * @hw_init_mask: initial unmaksed hw causes 443 * @boot_stage_cache: cached value of boot stage register 444 * @img_resp_cache: cached value of image response register 445 * @cnvi: CNVi register value 446 * @cnvr: CNVr register value 447 * @gp0_received: condition for gp0 interrupt 448 * @gp0_wait_q: wait_q for gp0 interrupt 449 * @tx_wait_done: condition for tx interrupt 450 * @tx_wait_q: wait_q for tx interrupt 451 * @workqueue: workqueue for RX work 452 * @rx_skb_q: SKB queue for RX packet 453 * @rx_work: RX work struct to process the RX packet in @rx_skb_q 454 * @dma_pool: DMA pool for descriptors, index array and ci 455 * @dma_p_addr: DMA address for pool 456 * @dma_v_addr: address of pool 457 * @ci_p_addr: DMA address for CI struct 458 * @ci: CI struct 459 * @ia: Index Array struct 460 * @txq: TX Queue struct 461 * @rxq: RX Queue struct 462 * @alive_intr_ctxt: Alive interrupt context 463 * @pm_sx_event: PM event on which system got suspended 464 */ 465 struct btintel_pcie_data { 466 struct pci_dev *pdev; 467 struct hci_dev *hdev; 468 469 unsigned long flags; 470 /* lock used in MSI-X interrupt */ 471 spinlock_t irq_lock; 472 /* lock to serialize rx events */ 473 spinlock_t hci_rx_lock; 474 475 void __iomem *base_addr; 476 477 struct msix_entry msix_entries[BTINTEL_PCIE_MSIX_VEC_MAX]; 478 bool msix_enabled; 479 u32 alloc_vecs; 480 u32 def_irq; 481 482 u32 fh_init_mask; 483 u32 hw_init_mask; 484 485 u32 boot_stage_cache; 486 u32 img_resp_cache; 487 488 u32 cnvi; 489 u32 cnvr; 490 491 bool gp0_received; 492 wait_queue_head_t gp0_wait_q; 493 494 bool tx_wait_done; 495 wait_queue_head_t tx_wait_q; 496 497 struct workqueue_struct *workqueue; 498 struct sk_buff_head rx_skb_q; 499 struct work_struct rx_work; 500 501 struct dma_pool *dma_pool; 502 dma_addr_t dma_p_addr; 503 void *dma_v_addr; 504 505 dma_addr_t ci_p_addr; 506 struct ctx_info *ci; 507 struct ia ia; 508 struct txq txq; 509 struct rxq rxq; 510 u32 alive_intr_ctxt; 511 struct btintel_pcie_dbgc dbgc; 512 struct btintel_pcie_dump_header dmp_hdr; 513 u8 pm_sx_event; 514 }; 515 516 static inline u32 btintel_pcie_rd_reg32(struct btintel_pcie_data *data, 517 u32 offset) 518 { 519 return ioread32(data->base_addr + offset); 520 } 521 522 static inline void btintel_pcie_wr_reg8(struct btintel_pcie_data *data, 523 u32 offset, u8 val) 524 { 525 iowrite8(val, data->base_addr + offset); 526 } 527 528 static inline void btintel_pcie_wr_reg32(struct btintel_pcie_data *data, 529 u32 offset, u32 val) 530 { 531 iowrite32(val, data->base_addr + offset); 532 } 533 534 static inline void btintel_pcie_set_reg_bits(struct btintel_pcie_data *data, 535 u32 offset, u32 bits) 536 { 537 u32 r; 538 539 r = ioread32(data->base_addr + offset); 540 r |= bits; 541 iowrite32(r, data->base_addr + offset); 542 } 543 544 static inline void btintel_pcie_clr_reg_bits(struct btintel_pcie_data *data, 545 u32 offset, u32 bits) 546 { 547 u32 r; 548 549 r = ioread32(data->base_addr + offset); 550 r &= ~bits; 551 iowrite32(r, data->base_addr + offset); 552 } 553 554 static inline u32 btintel_pcie_rd_dev_mem(struct btintel_pcie_data *data, 555 u32 addr) 556 { 557 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_PRPH_DEV_ADDR_REG, addr); 558 return btintel_pcie_rd_reg32(data, BTINTEL_PCIE_PRPH_DEV_RD_REG); 559 } 560 561