19352f69cSRafał Miłecki /* 29352f69cSRafał Miłecki * Broadcom specific AMBA 39352f69cSRafał Miłecki * PCI Core in hostmode 49352f69cSRafał Miłecki * 549dc9577SHauke Mehrtens * Copyright 2005 - 2011, Broadcom Corporation 649dc9577SHauke Mehrtens * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 749dc9577SHauke Mehrtens * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> 849dc9577SHauke Mehrtens * 99352f69cSRafał Miłecki * Licensed under the GNU/GPL. See COPYING for details. 109352f69cSRafał Miłecki */ 119352f69cSRafał Miłecki 129352f69cSRafał Miłecki #include "bcma_private.h" 1358f743eeSPaul Gortmaker #include <linux/pci.h> 142264fc85SRafał Miłecki #include <linux/slab.h> 1549dc9577SHauke Mehrtens #include <linux/export.h> 169352f69cSRafał Miłecki #include <linux/bcma/bcma.h> 1749dc9577SHauke Mehrtens #include <asm/paccess.h> 1849dc9577SHauke Mehrtens 1949dc9577SHauke Mehrtens /* Probe a 32bit value on the bus and catch bus exceptions. 2049dc9577SHauke Mehrtens * Returns nonzero on a bus exception. 2149dc9577SHauke Mehrtens * This is MIPS specific */ 2249dc9577SHauke Mehrtens #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) 2349dc9577SHauke Mehrtens 2449dc9577SHauke Mehrtens /* Assume one-hot slot wiring */ 2549dc9577SHauke Mehrtens #define BCMA_PCI_SLOT_MAX 16 2649dc9577SHauke Mehrtens #define PCI_CONFIG_SPACE_SIZE 256 2749dc9577SHauke Mehrtens 280f58a01dSGreg Kroah-Hartman bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) 2949dc9577SHauke Mehrtens { 3049dc9577SHauke Mehrtens struct bcma_bus *bus = pc->core->bus; 3149dc9577SHauke Mehrtens u16 chipid_top; 3249dc9577SHauke Mehrtens u32 tmp; 3349dc9577SHauke Mehrtens 3449dc9577SHauke Mehrtens chipid_top = (bus->chipinfo.id & 0xFF00); 3549dc9577SHauke Mehrtens if (chipid_top != 0x4700 && 3649dc9577SHauke Mehrtens chipid_top != 0x5300) 3749dc9577SHauke Mehrtens return false; 3849dc9577SHauke Mehrtens 3949dc9577SHauke Mehrtens bcma_core_enable(pc->core, 0); 4049dc9577SHauke Mehrtens 4149dc9577SHauke Mehrtens return !mips_busprobe32(tmp, pc->core->io_addr); 4249dc9577SHauke Mehrtens } 4349dc9577SHauke Mehrtens 4449dc9577SHauke Mehrtens static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address) 4549dc9577SHauke Mehrtens { 4649dc9577SHauke Mehrtens pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address); 4749dc9577SHauke Mehrtens pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR); 4849dc9577SHauke Mehrtens return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA); 4949dc9577SHauke Mehrtens } 5049dc9577SHauke Mehrtens 5149dc9577SHauke Mehrtens static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address, 5249dc9577SHauke Mehrtens u32 data) 5349dc9577SHauke Mehrtens { 5449dc9577SHauke Mehrtens pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address); 5549dc9577SHauke Mehrtens pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR); 5649dc9577SHauke Mehrtens pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data); 5749dc9577SHauke Mehrtens } 5849dc9577SHauke Mehrtens 5949dc9577SHauke Mehrtens static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev, 6049dc9577SHauke Mehrtens unsigned int func, unsigned int off) 6149dc9577SHauke Mehrtens { 6249dc9577SHauke Mehrtens u32 addr = 0; 6349dc9577SHauke Mehrtens 6449dc9577SHauke Mehrtens /* Issue config commands only when the data link is up (at least 6549dc9577SHauke Mehrtens * one external pcie device is present). 6649dc9577SHauke Mehrtens */ 6749dc9577SHauke Mehrtens if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG) 6849dc9577SHauke Mehrtens & BCMA_CORE_PCI_DLLP_LSREG_LINKUP)) 6949dc9577SHauke Mehrtens goto out; 7049dc9577SHauke Mehrtens 7149dc9577SHauke Mehrtens /* Type 0 transaction */ 7249dc9577SHauke Mehrtens /* Slide the PCI window to the appropriate slot */ 7349dc9577SHauke Mehrtens pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0); 7449dc9577SHauke Mehrtens /* Calculate the address */ 7549dc9577SHauke Mehrtens addr = pc->host_controller->host_cfg_addr; 7649dc9577SHauke Mehrtens addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT); 7749dc9577SHauke Mehrtens addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT); 7849dc9577SHauke Mehrtens addr |= (off & ~3); 7949dc9577SHauke Mehrtens 8049dc9577SHauke Mehrtens out: 8149dc9577SHauke Mehrtens return addr; 8249dc9577SHauke Mehrtens } 8349dc9577SHauke Mehrtens 8449dc9577SHauke Mehrtens static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev, 8549dc9577SHauke Mehrtens unsigned int func, unsigned int off, 8649dc9577SHauke Mehrtens void *buf, int len) 8749dc9577SHauke Mehrtens { 8849dc9577SHauke Mehrtens int err = -EINVAL; 8949dc9577SHauke Mehrtens u32 addr, val; 9049dc9577SHauke Mehrtens void __iomem *mmio = 0; 9149dc9577SHauke Mehrtens 9249dc9577SHauke Mehrtens WARN_ON(!pc->hostmode); 9349dc9577SHauke Mehrtens if (unlikely(len != 1 && len != 2 && len != 4)) 9449dc9577SHauke Mehrtens goto out; 9549dc9577SHauke Mehrtens if (dev == 0) { 9649dc9577SHauke Mehrtens /* we support only two functions on device 0 */ 9749dc9577SHauke Mehrtens if (func > 1) 98a35ab937SNathan Hintz goto out; 9949dc9577SHauke Mehrtens 10049dc9577SHauke Mehrtens /* accesses to config registers with offsets >= 256 10149dc9577SHauke Mehrtens * requires indirect access. 10249dc9577SHauke Mehrtens */ 10349dc9577SHauke Mehrtens if (off >= PCI_CONFIG_SPACE_SIZE) { 10449dc9577SHauke Mehrtens addr = (func << 12); 105b09e9abdSNathan Hintz addr |= (off & 0x0FFC); 10649dc9577SHauke Mehrtens val = bcma_pcie_read_config(pc, addr); 10749dc9577SHauke Mehrtens } else { 10849dc9577SHauke Mehrtens addr = BCMA_CORE_PCI_PCICFG0; 10949dc9577SHauke Mehrtens addr |= (func << 8); 110660b9caaSNathan Hintz addr |= (off & 0xFC); 11149dc9577SHauke Mehrtens val = pcicore_read32(pc, addr); 11249dc9577SHauke Mehrtens } 11349dc9577SHauke Mehrtens } else { 11449dc9577SHauke Mehrtens addr = bcma_get_cfgspace_addr(pc, dev, func, off); 11549dc9577SHauke Mehrtens if (unlikely(!addr)) 11649dc9577SHauke Mehrtens goto out; 11749dc9577SHauke Mehrtens err = -ENOMEM; 1184bdc0d67SChristoph Hellwig mmio = ioremap(addr, sizeof(val)); 11949dc9577SHauke Mehrtens if (!mmio) 12049dc9577SHauke Mehrtens goto out; 12149dc9577SHauke Mehrtens 12249dc9577SHauke Mehrtens if (mips_busprobe32(val, mmio)) { 123660b9caaSNathan Hintz val = 0xFFFFFFFF; 12449dc9577SHauke Mehrtens goto unmap; 12549dc9577SHauke Mehrtens } 12649dc9577SHauke Mehrtens } 12749dc9577SHauke Mehrtens val >>= (8 * (off & 3)); 12849dc9577SHauke Mehrtens 12949dc9577SHauke Mehrtens switch (len) { 13049dc9577SHauke Mehrtens case 1: 13149dc9577SHauke Mehrtens *((u8 *)buf) = (u8)val; 13249dc9577SHauke Mehrtens break; 13349dc9577SHauke Mehrtens case 2: 13449dc9577SHauke Mehrtens *((u16 *)buf) = (u16)val; 13549dc9577SHauke Mehrtens break; 13649dc9577SHauke Mehrtens case 4: 13749dc9577SHauke Mehrtens *((u32 *)buf) = (u32)val; 13849dc9577SHauke Mehrtens break; 13949dc9577SHauke Mehrtens } 14049dc9577SHauke Mehrtens err = 0; 14149dc9577SHauke Mehrtens unmap: 14249dc9577SHauke Mehrtens if (mmio) 14349dc9577SHauke Mehrtens iounmap(mmio); 14449dc9577SHauke Mehrtens out: 14549dc9577SHauke Mehrtens return err; 14649dc9577SHauke Mehrtens } 14749dc9577SHauke Mehrtens 14849dc9577SHauke Mehrtens static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev, 14949dc9577SHauke Mehrtens unsigned int func, unsigned int off, 15049dc9577SHauke Mehrtens const void *buf, int len) 15149dc9577SHauke Mehrtens { 15249dc9577SHauke Mehrtens int err = -EINVAL; 153447d7e25SNathan Hintz u32 addr, val; 15449dc9577SHauke Mehrtens void __iomem *mmio = 0; 15549dc9577SHauke Mehrtens u16 chipid = pc->core->bus->chipinfo.id; 15649dc9577SHauke Mehrtens 15749dc9577SHauke Mehrtens WARN_ON(!pc->hostmode); 15849dc9577SHauke Mehrtens if (unlikely(len != 1 && len != 2 && len != 4)) 15949dc9577SHauke Mehrtens goto out; 16049dc9577SHauke Mehrtens if (dev == 0) { 161a35ab937SNathan Hintz /* we support only two functions on device 0 */ 162a35ab937SNathan Hintz if (func > 1) 163a35ab937SNathan Hintz goto out; 164a35ab937SNathan Hintz 16549dc9577SHauke Mehrtens /* accesses to config registers with offsets >= 256 16649dc9577SHauke Mehrtens * requires indirect access. 16749dc9577SHauke Mehrtens */ 168b09e9abdSNathan Hintz if (off >= PCI_CONFIG_SPACE_SIZE) { 169b09e9abdSNathan Hintz addr = (func << 12); 170b09e9abdSNathan Hintz addr |= (off & 0x0FFC); 171b09e9abdSNathan Hintz val = bcma_pcie_read_config(pc, addr); 172b09e9abdSNathan Hintz } else { 173447d7e25SNathan Hintz addr = BCMA_CORE_PCI_PCICFG0; 17449dc9577SHauke Mehrtens addr |= (func << 8); 175660b9caaSNathan Hintz addr |= (off & 0xFC); 176447d7e25SNathan Hintz val = pcicore_read32(pc, addr); 17749dc9577SHauke Mehrtens } 17849dc9577SHauke Mehrtens } else { 17949dc9577SHauke Mehrtens addr = bcma_get_cfgspace_addr(pc, dev, func, off); 18049dc9577SHauke Mehrtens if (unlikely(!addr)) 18149dc9577SHauke Mehrtens goto out; 18249dc9577SHauke Mehrtens err = -ENOMEM; 1834bdc0d67SChristoph Hellwig mmio = ioremap(addr, sizeof(val)); 18449dc9577SHauke Mehrtens if (!mmio) 18549dc9577SHauke Mehrtens goto out; 18649dc9577SHauke Mehrtens 18749dc9577SHauke Mehrtens if (mips_busprobe32(val, mmio)) { 188660b9caaSNathan Hintz val = 0xFFFFFFFF; 18949dc9577SHauke Mehrtens goto unmap; 19049dc9577SHauke Mehrtens } 19149dc9577SHauke Mehrtens } 19249dc9577SHauke Mehrtens 19349dc9577SHauke Mehrtens switch (len) { 19449dc9577SHauke Mehrtens case 1: 19549dc9577SHauke Mehrtens val &= ~(0xFF << (8 * (off & 3))); 19649dc9577SHauke Mehrtens val |= *((const u8 *)buf) << (8 * (off & 3)); 19749dc9577SHauke Mehrtens break; 19849dc9577SHauke Mehrtens case 2: 19949dc9577SHauke Mehrtens val &= ~(0xFFFF << (8 * (off & 3))); 20049dc9577SHauke Mehrtens val |= *((const u16 *)buf) << (8 * (off & 3)); 20149dc9577SHauke Mehrtens break; 20249dc9577SHauke Mehrtens case 4: 20349dc9577SHauke Mehrtens val = *((const u32 *)buf); 20449dc9577SHauke Mehrtens break; 20549dc9577SHauke Mehrtens } 206447d7e25SNathan Hintz if (dev == 0) { 20749dc9577SHauke Mehrtens /* accesses to config registers with offsets >= 256 20849dc9577SHauke Mehrtens * requires indirect access. 20949dc9577SHauke Mehrtens */ 210b09e9abdSNathan Hintz if (off >= PCI_CONFIG_SPACE_SIZE) 21149dc9577SHauke Mehrtens bcma_pcie_write_config(pc, addr, val); 212b09e9abdSNathan Hintz else 213447d7e25SNathan Hintz pcicore_write32(pc, addr, val); 21449dc9577SHauke Mehrtens } else { 21549dc9577SHauke Mehrtens writel(val, mmio); 21649dc9577SHauke Mehrtens 2174b4f5be2SHauke Mehrtens if (chipid == BCMA_CHIP_ID_BCM4716 || 2184b4f5be2SHauke Mehrtens chipid == BCMA_CHIP_ID_BCM4748) 21949dc9577SHauke Mehrtens readl(mmio); 22049dc9577SHauke Mehrtens } 22149dc9577SHauke Mehrtens 22249dc9577SHauke Mehrtens err = 0; 22349dc9577SHauke Mehrtens unmap: 22449dc9577SHauke Mehrtens if (mmio) 22549dc9577SHauke Mehrtens iounmap(mmio); 22649dc9577SHauke Mehrtens out: 22749dc9577SHauke Mehrtens return err; 22849dc9577SHauke Mehrtens } 22949dc9577SHauke Mehrtens 23049dc9577SHauke Mehrtens static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus, 23149dc9577SHauke Mehrtens unsigned int devfn, 23249dc9577SHauke Mehrtens int reg, int size, u32 *val) 23349dc9577SHauke Mehrtens { 23449dc9577SHauke Mehrtens unsigned long flags; 23549dc9577SHauke Mehrtens int err; 23649dc9577SHauke Mehrtens struct bcma_drv_pci *pc; 23749dc9577SHauke Mehrtens struct bcma_drv_pci_host *pc_host; 23849dc9577SHauke Mehrtens 23949dc9577SHauke Mehrtens pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops); 24049dc9577SHauke Mehrtens pc = pc_host->pdev; 24149dc9577SHauke Mehrtens 24249dc9577SHauke Mehrtens spin_lock_irqsave(&pc_host->cfgspace_lock, flags); 24349dc9577SHauke Mehrtens err = bcma_extpci_read_config(pc, PCI_SLOT(devfn), 24449dc9577SHauke Mehrtens PCI_FUNC(devfn), reg, val, size); 24549dc9577SHauke Mehrtens spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags); 24649dc9577SHauke Mehrtens 24749dc9577SHauke Mehrtens return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 24849dc9577SHauke Mehrtens } 24949dc9577SHauke Mehrtens 25049dc9577SHauke Mehrtens static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus, 25149dc9577SHauke Mehrtens unsigned int devfn, 25249dc9577SHauke Mehrtens int reg, int size, u32 val) 25349dc9577SHauke Mehrtens { 25449dc9577SHauke Mehrtens unsigned long flags; 25549dc9577SHauke Mehrtens int err; 25649dc9577SHauke Mehrtens struct bcma_drv_pci *pc; 25749dc9577SHauke Mehrtens struct bcma_drv_pci_host *pc_host; 25849dc9577SHauke Mehrtens 25949dc9577SHauke Mehrtens pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops); 26049dc9577SHauke Mehrtens pc = pc_host->pdev; 26149dc9577SHauke Mehrtens 26249dc9577SHauke Mehrtens spin_lock_irqsave(&pc_host->cfgspace_lock, flags); 26349dc9577SHauke Mehrtens err = bcma_extpci_write_config(pc, PCI_SLOT(devfn), 26449dc9577SHauke Mehrtens PCI_FUNC(devfn), reg, &val, size); 26549dc9577SHauke Mehrtens spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags); 26649dc9577SHauke Mehrtens 26749dc9577SHauke Mehrtens return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 26849dc9577SHauke Mehrtens } 26949dc9577SHauke Mehrtens 27049dc9577SHauke Mehrtens /* return cap_offset if requested capability exists in the PCI config space */ 2710f58a01dSGreg Kroah-Hartman static u8 bcma_find_pci_capability(struct bcma_drv_pci *pc, unsigned int dev, 27249dc9577SHauke Mehrtens unsigned int func, u8 req_cap_id, 27349dc9577SHauke Mehrtens unsigned char *buf, u32 *buflen) 27449dc9577SHauke Mehrtens { 27549dc9577SHauke Mehrtens u8 cap_id; 27649dc9577SHauke Mehrtens u8 cap_ptr = 0; 27749dc9577SHauke Mehrtens u32 bufsize; 27849dc9577SHauke Mehrtens u8 byte_val; 27949dc9577SHauke Mehrtens 28049dc9577SHauke Mehrtens /* check for Header type 0 */ 28149dc9577SHauke Mehrtens bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val, 28249dc9577SHauke Mehrtens sizeof(u8)); 283ac586b84SIlpo Järvinen if ((byte_val & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_NORMAL) 28449dc9577SHauke Mehrtens return cap_ptr; 28549dc9577SHauke Mehrtens 28649dc9577SHauke Mehrtens /* check if the capability pointer field exists */ 28749dc9577SHauke Mehrtens bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val, 28849dc9577SHauke Mehrtens sizeof(u8)); 28949dc9577SHauke Mehrtens if (!(byte_val & PCI_STATUS_CAP_LIST)) 29049dc9577SHauke Mehrtens return cap_ptr; 29149dc9577SHauke Mehrtens 29249dc9577SHauke Mehrtens /* check if the capability pointer is 0x00 */ 29349dc9577SHauke Mehrtens bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr, 29449dc9577SHauke Mehrtens sizeof(u8)); 29549dc9577SHauke Mehrtens if (cap_ptr == 0x00) 29649dc9577SHauke Mehrtens return cap_ptr; 29749dc9577SHauke Mehrtens 298032931fdSTom Rix /* loop through the capability list and see if the requested capability 29949dc9577SHauke Mehrtens * exists */ 30049dc9577SHauke Mehrtens bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8)); 30149dc9577SHauke Mehrtens while (cap_id != req_cap_id) { 30249dc9577SHauke Mehrtens bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr, 30349dc9577SHauke Mehrtens sizeof(u8)); 30449dc9577SHauke Mehrtens if (cap_ptr == 0x00) 30549dc9577SHauke Mehrtens return cap_ptr; 30649dc9577SHauke Mehrtens bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, 30749dc9577SHauke Mehrtens sizeof(u8)); 30849dc9577SHauke Mehrtens } 30949dc9577SHauke Mehrtens 31049dc9577SHauke Mehrtens /* found the caller requested capability */ 31149dc9577SHauke Mehrtens if ((buf != NULL) && (buflen != NULL)) { 31249dc9577SHauke Mehrtens u8 cap_data; 31349dc9577SHauke Mehrtens 31449dc9577SHauke Mehrtens bufsize = *buflen; 31549dc9577SHauke Mehrtens if (!bufsize) 31649dc9577SHauke Mehrtens return cap_ptr; 31749dc9577SHauke Mehrtens 31849dc9577SHauke Mehrtens *buflen = 0; 31949dc9577SHauke Mehrtens 320032931fdSTom Rix /* copy the capability data excluding cap ID and next ptr */ 32149dc9577SHauke Mehrtens cap_data = cap_ptr + 2; 32249dc9577SHauke Mehrtens if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE) 32349dc9577SHauke Mehrtens bufsize = PCI_CONFIG_SPACE_SIZE - cap_data; 32449dc9577SHauke Mehrtens *buflen = bufsize; 32549dc9577SHauke Mehrtens while (bufsize--) { 32649dc9577SHauke Mehrtens bcma_extpci_read_config(pc, dev, func, cap_data, buf, 32749dc9577SHauke Mehrtens sizeof(u8)); 32849dc9577SHauke Mehrtens cap_data++; 32949dc9577SHauke Mehrtens buf++; 33049dc9577SHauke Mehrtens } 33149dc9577SHauke Mehrtens } 33249dc9577SHauke Mehrtens 33349dc9577SHauke Mehrtens return cap_ptr; 33449dc9577SHauke Mehrtens } 33549dc9577SHauke Mehrtens 33649dc9577SHauke Mehrtens /* If the root port is capable of returning Config Request 337*87f10fafSBjorn Helgaas * Retry Status (RRS) Completion Status to software then 33849dc9577SHauke Mehrtens * enable the feature. 33949dc9577SHauke Mehrtens */ 3400f58a01dSGreg Kroah-Hartman static void bcma_core_pci_enable_crs(struct bcma_drv_pci *pc) 34149dc9577SHauke Mehrtens { 3423d9d8af3SRafał Miłecki struct bcma_bus *bus = pc->core->bus; 34349dc9577SHauke Mehrtens u8 cap_ptr, root_ctrl, root_cap, dev; 34449dc9577SHauke Mehrtens u16 val16; 34549dc9577SHauke Mehrtens int i; 34649dc9577SHauke Mehrtens 34749dc9577SHauke Mehrtens cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL, 34849dc9577SHauke Mehrtens NULL); 34949dc9577SHauke Mehrtens root_cap = cap_ptr + PCI_EXP_RTCAP; 35049dc9577SHauke Mehrtens bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16)); 351*87f10fafSBjorn Helgaas if (val16 & BCMA_CORE_PCI_RC_RRS_VISIBILITY) { 352*87f10fafSBjorn Helgaas /* Enable Configuration RRS Software Visibility */ 35349dc9577SHauke Mehrtens root_ctrl = cap_ptr + PCI_EXP_RTCTL; 354*87f10fafSBjorn Helgaas val16 = PCI_EXP_RTCTL_RRS_SVE; 35549dc9577SHauke Mehrtens bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16, 35649dc9577SHauke Mehrtens sizeof(u16)); 35749dc9577SHauke Mehrtens 35849dc9577SHauke Mehrtens /* Initiate a configuration request to read the vendor id 35949dc9577SHauke Mehrtens * field of the device function's config space header after 36049dc9577SHauke Mehrtens * 100 ms wait time from the end of Reset. If the device is 36149dc9577SHauke Mehrtens * not done with its internal initialization, it must at 36249dc9577SHauke Mehrtens * least return a completion TLP, with a completion status 363*87f10fafSBjorn Helgaas * of "Configuration Request Retry Status (RRS)". The root 36449dc9577SHauke Mehrtens * complex must complete the request to the host by returning 36549dc9577SHauke Mehrtens * a read-data value of 0001h for the Vendor ID field and 36649dc9577SHauke Mehrtens * all 1s for any additional bytes included in the request. 36749dc9577SHauke Mehrtens * Poll using the config reads for max wait time of 1 sec or 36849dc9577SHauke Mehrtens * until we receive the successful completion status. Repeat 36949dc9577SHauke Mehrtens * the procedure for all the devices. 37049dc9577SHauke Mehrtens */ 37149dc9577SHauke Mehrtens for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) { 37249dc9577SHauke Mehrtens for (i = 0; i < 100000; i++) { 37349dc9577SHauke Mehrtens bcma_extpci_read_config(pc, dev, 0, 37449dc9577SHauke Mehrtens PCI_VENDOR_ID, &val16, 37549dc9577SHauke Mehrtens sizeof(val16)); 37649dc9577SHauke Mehrtens if (val16 != 0x1) 37749dc9577SHauke Mehrtens break; 37849dc9577SHauke Mehrtens udelay(10); 37949dc9577SHauke Mehrtens } 38049dc9577SHauke Mehrtens if (val16 == 0x1) 3813d9d8af3SRafał Miłecki bcma_err(bus, "PCI: Broken device in slot %d\n", 3823d9d8af3SRafał Miłecki dev); 38349dc9577SHauke Mehrtens } 38449dc9577SHauke Mehrtens } 38549dc9577SHauke Mehrtens } 3869352f69cSRafał Miłecki 3870f58a01dSGreg Kroah-Hartman void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) 3889352f69cSRafał Miłecki { 38949dc9577SHauke Mehrtens struct bcma_bus *bus = pc->core->bus; 39049dc9577SHauke Mehrtens struct bcma_drv_pci_host *pc_host; 39149dc9577SHauke Mehrtens u32 tmp; 39249dc9577SHauke Mehrtens u32 pci_membase_1G; 39349dc9577SHauke Mehrtens unsigned long io_map_base; 39449dc9577SHauke Mehrtens 3953d9d8af3SRafał Miłecki bcma_info(bus, "PCIEcore in host mode found\n"); 39649dc9577SHauke Mehrtens 3972b4766c3SHauke Mehrtens if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) { 3982b4766c3SHauke Mehrtens bcma_info(bus, "This PCIE core is disabled and not working\n"); 3992b4766c3SHauke Mehrtens return; 4002b4766c3SHauke Mehrtens } 4012b4766c3SHauke Mehrtens 40249dc9577SHauke Mehrtens pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL); 40349dc9577SHauke Mehrtens if (!pc_host) { 4043d9d8af3SRafał Miłecki bcma_err(bus, "can not allocate memory"); 40549dc9577SHauke Mehrtens return; 4069352f69cSRafał Miłecki } 40749dc9577SHauke Mehrtens 408f45dd363SHauke Mehrtens spin_lock_init(&pc_host->cfgspace_lock); 409f45dd363SHauke Mehrtens 41049dc9577SHauke Mehrtens pc->host_controller = pc_host; 41149dc9577SHauke Mehrtens pc_host->pci_controller.io_resource = &pc_host->io_resource; 41249dc9577SHauke Mehrtens pc_host->pci_controller.mem_resource = &pc_host->mem_resource; 41349dc9577SHauke Mehrtens pc_host->pci_controller.pci_ops = &pc_host->pci_ops; 41449dc9577SHauke Mehrtens pc_host->pdev = pc; 41549dc9577SHauke Mehrtens 41649dc9577SHauke Mehrtens pci_membase_1G = BCMA_SOC_PCI_DMA; 41749dc9577SHauke Mehrtens pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG; 41849dc9577SHauke Mehrtens 41949dc9577SHauke Mehrtens pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config; 42049dc9577SHauke Mehrtens pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config; 42149dc9577SHauke Mehrtens 422703314b2SJulia Lawall pc_host->mem_resource.name = "BCMA PCIcore external memory"; 42349dc9577SHauke Mehrtens pc_host->mem_resource.start = BCMA_SOC_PCI_DMA; 42449dc9577SHauke Mehrtens pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1; 42549dc9577SHauke Mehrtens pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED; 42649dc9577SHauke Mehrtens 427703314b2SJulia Lawall pc_host->io_resource.name = "BCMA PCIcore external I/O"; 42849dc9577SHauke Mehrtens pc_host->io_resource.start = 0x100; 42949dc9577SHauke Mehrtens pc_host->io_resource.end = 0x7FF; 43049dc9577SHauke Mehrtens pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED; 43149dc9577SHauke Mehrtens 43249dc9577SHauke Mehrtens /* Reset RC */ 4331fd41a65SRafał Miłecki usleep_range(3000, 5000); 43449dc9577SHauke Mehrtens pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE); 435990debe2SNathan Hintz msleep(50); 43649dc9577SHauke Mehrtens pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST | 43749dc9577SHauke Mehrtens BCMA_CORE_PCI_CTL_RST_OE); 43849dc9577SHauke Mehrtens 43949dc9577SHauke Mehrtens /* 64 MB I/O access window. On 4716, use 44049dc9577SHauke Mehrtens * sbtopcie0 to access the device registers. We 44149dc9577SHauke Mehrtens * can't use address match 2 (1 GB window) region 44249dc9577SHauke Mehrtens * as mips can't generate 64-bit address on the 44349dc9577SHauke Mehrtens * backplane. 44449dc9577SHauke Mehrtens */ 4454b4f5be2SHauke Mehrtens if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 || 4464b4f5be2SHauke Mehrtens bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) { 44749dc9577SHauke Mehrtens pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; 44849dc9577SHauke Mehrtens pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + 44949dc9577SHauke Mehrtens BCMA_SOC_PCI_MEM_SZ - 1; 45049dc9577SHauke Mehrtens pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, 45149dc9577SHauke Mehrtens BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM); 4524b4f5be2SHauke Mehrtens } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { 45349dc9577SHauke Mehrtens tmp = BCMA_CORE_PCI_SBTOPCI_MEM; 45449dc9577SHauke Mehrtens tmp |= BCMA_CORE_PCI_SBTOPCI_PREF; 45549dc9577SHauke Mehrtens tmp |= BCMA_CORE_PCI_SBTOPCI_BURST; 45649dc9577SHauke Mehrtens if (pc->core->core_unit == 0) { 45749dc9577SHauke Mehrtens pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; 45849dc9577SHauke Mehrtens pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + 45949dc9577SHauke Mehrtens BCMA_SOC_PCI_MEM_SZ - 1; 460dfae7143SHauke Mehrtens pc_host->io_resource.start = 0x100; 461dfae7143SHauke Mehrtens pc_host->io_resource.end = 0x47F; 46249dc9577SHauke Mehrtens pci_membase_1G = BCMA_SOC_PCIE_DMA_H32; 46349dc9577SHauke Mehrtens pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, 46449dc9577SHauke Mehrtens tmp | BCMA_SOC_PCI_MEM); 46549dc9577SHauke Mehrtens } else if (pc->core->core_unit == 1) { 46649dc9577SHauke Mehrtens pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM; 46749dc9577SHauke Mehrtens pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM + 46849dc9577SHauke Mehrtens BCMA_SOC_PCI_MEM_SZ - 1; 469dfae7143SHauke Mehrtens pc_host->io_resource.start = 0x480; 470dfae7143SHauke Mehrtens pc_host->io_resource.end = 0x7FF; 47149dc9577SHauke Mehrtens pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32; 47249dc9577SHauke Mehrtens pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG; 47349dc9577SHauke Mehrtens pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, 47449dc9577SHauke Mehrtens tmp | BCMA_SOC_PCI1_MEM); 47549dc9577SHauke Mehrtens } 47649dc9577SHauke Mehrtens } else 47749dc9577SHauke Mehrtens pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, 47849dc9577SHauke Mehrtens BCMA_CORE_PCI_SBTOPCI_IO); 47949dc9577SHauke Mehrtens 48049dc9577SHauke Mehrtens /* 64 MB configuration access window */ 48149dc9577SHauke Mehrtens pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0); 48249dc9577SHauke Mehrtens 48349dc9577SHauke Mehrtens /* 1 GB memory access window */ 48449dc9577SHauke Mehrtens pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2, 48549dc9577SHauke Mehrtens BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G); 48649dc9577SHauke Mehrtens 48749dc9577SHauke Mehrtens 48849dc9577SHauke Mehrtens /* As per PCI Express Base Spec 1.1 we need to wait for 48949dc9577SHauke Mehrtens * at least 100 ms from the end of a reset (cold/warm/hot) 49049dc9577SHauke Mehrtens * before issuing configuration requests to PCI Express 49149dc9577SHauke Mehrtens * devices. 49249dc9577SHauke Mehrtens */ 4931fd41a65SRafał Miłecki msleep(100); 49449dc9577SHauke Mehrtens 49549dc9577SHauke Mehrtens bcma_core_pci_enable_crs(pc); 49649dc9577SHauke Mehrtens 497990debe2SNathan Hintz if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 || 498990debe2SNathan Hintz bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) { 499990debe2SNathan Hintz u16 val16; 500990debe2SNathan Hintz bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL, 501990debe2SNathan Hintz &val16, sizeof(val16)); 502990debe2SNathan Hintz val16 |= (2 << 5); /* Max payload size of 512 */ 503990debe2SNathan Hintz val16 |= (2 << 12); /* MRRS 512 */ 504990debe2SNathan Hintz bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL, 505990debe2SNathan Hintz &val16, sizeof(val16)); 506990debe2SNathan Hintz } 507990debe2SNathan Hintz 50849dc9577SHauke Mehrtens /* Enable PCI bridge BAR0 memory & master access */ 50949dc9577SHauke Mehrtens tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 51049dc9577SHauke Mehrtens bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp)); 51149dc9577SHauke Mehrtens 51249dc9577SHauke Mehrtens /* Enable PCI interrupts */ 51349dc9577SHauke Mehrtens pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA); 51449dc9577SHauke Mehrtens 51549dc9577SHauke Mehrtens /* Ok, ready to run, register it to the system. 51649dc9577SHauke Mehrtens * The following needs change, if we want to port hostmode 51749dc9577SHauke Mehrtens * to non-MIPS platform. */ 5184bdc0d67SChristoph Hellwig io_map_base = (unsigned long)ioremap(pc_host->mem_resource.start, 5194acabf45SNathan Hintz resource_size(&pc_host->mem_resource)); 52049dc9577SHauke Mehrtens pc_host->pci_controller.io_map_base = io_map_base; 52149dc9577SHauke Mehrtens set_io_port_base(pc_host->pci_controller.io_map_base); 52249dc9577SHauke Mehrtens /* Give some time to the PCI controller to configure itself with the new 52349dc9577SHauke Mehrtens * values. Not waiting at this point causes crashes of the machine. */ 5241fd41a65SRafał Miłecki usleep_range(10000, 15000); 52549dc9577SHauke Mehrtens register_pci_controller(&pc_host->pci_controller); 52649dc9577SHauke Mehrtens return; 52749dc9577SHauke Mehrtens } 52849dc9577SHauke Mehrtens 52949dc9577SHauke Mehrtens /* Early PCI fixup for a device on the PCI-core bridge. */ 53049dc9577SHauke Mehrtens static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev) 53149dc9577SHauke Mehrtens { 53249dc9577SHauke Mehrtens if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { 53349dc9577SHauke Mehrtens /* This is not a device on the PCI-core bridge. */ 53449dc9577SHauke Mehrtens return; 53549dc9577SHauke Mehrtens } 53649dc9577SHauke Mehrtens if (PCI_SLOT(dev->devfn) != 0) 53749dc9577SHauke Mehrtens return; 53849dc9577SHauke Mehrtens 53949dc9577SHauke Mehrtens pr_info("PCI: Fixing up bridge %s\n", pci_name(dev)); 54049dc9577SHauke Mehrtens 54149dc9577SHauke Mehrtens /* Enable PCI bridge bus mastering and memory space */ 54249dc9577SHauke Mehrtens pci_set_master(dev); 54349dc9577SHauke Mehrtens if (pcibios_enable_device(dev, ~0) < 0) { 54449dc9577SHauke Mehrtens pr_err("PCI: BCMA bridge enable failed\n"); 54549dc9577SHauke Mehrtens return; 54649dc9577SHauke Mehrtens } 54749dc9577SHauke Mehrtens 54849dc9577SHauke Mehrtens /* Enable PCI bridge BAR1 prefetch and burst */ 54949dc9577SHauke Mehrtens pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3); 55049dc9577SHauke Mehrtens } 55149dc9577SHauke Mehrtens DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge); 55249dc9577SHauke Mehrtens 55349dc9577SHauke Mehrtens /* Early PCI fixup for all PCI-cores to set the correct memory address. */ 55449dc9577SHauke Mehrtens static void bcma_core_pci_fixup_addresses(struct pci_dev *dev) 55549dc9577SHauke Mehrtens { 55649dc9577SHauke Mehrtens struct resource *res; 5574a7267c9SHauke Mehrtens int pos, err; 55849dc9577SHauke Mehrtens 55949dc9577SHauke Mehrtens if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { 56049dc9577SHauke Mehrtens /* This is not a device on the PCI-core bridge. */ 56149dc9577SHauke Mehrtens return; 56249dc9577SHauke Mehrtens } 56349dc9577SHauke Mehrtens if (PCI_SLOT(dev->devfn) == 0) 56449dc9577SHauke Mehrtens return; 56549dc9577SHauke Mehrtens 56649dc9577SHauke Mehrtens pr_info("PCI: Fixing up addresses %s\n", pci_name(dev)); 56749dc9577SHauke Mehrtens 56849dc9577SHauke Mehrtens for (pos = 0; pos < 6; pos++) { 56949dc9577SHauke Mehrtens res = &dev->resource[pos]; 5704a7267c9SHauke Mehrtens if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) { 5714a7267c9SHauke Mehrtens err = pci_assign_resource(dev, pos); 5724a7267c9SHauke Mehrtens if (err) 5734a7267c9SHauke Mehrtens pr_err("PCI: Problem fixing up the addresses on %s\n", 5744a7267c9SHauke Mehrtens pci_name(dev)); 5754a7267c9SHauke Mehrtens } 57649dc9577SHauke Mehrtens } 57749dc9577SHauke Mehrtens } 57849dc9577SHauke Mehrtens DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses); 57949dc9577SHauke Mehrtens 58049dc9577SHauke Mehrtens /* This function is called when doing a pci_enable_device(). 58149dc9577SHauke Mehrtens * We must first check if the device is a device on the PCI-core bridge. */ 58249dc9577SHauke Mehrtens int bcma_core_pci_plat_dev_init(struct pci_dev *dev) 58349dc9577SHauke Mehrtens { 58449dc9577SHauke Mehrtens struct bcma_drv_pci_host *pc_host; 585f4a83e57SHauke Mehrtens int readrq; 58649dc9577SHauke Mehrtens 58749dc9577SHauke Mehrtens if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { 58849dc9577SHauke Mehrtens /* This is not a device on the PCI-core bridge. */ 58949dc9577SHauke Mehrtens return -ENODEV; 59049dc9577SHauke Mehrtens } 59149dc9577SHauke Mehrtens pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, 59249dc9577SHauke Mehrtens pci_ops); 59349dc9577SHauke Mehrtens 59449dc9577SHauke Mehrtens pr_info("PCI: Fixing up device %s\n", pci_name(dev)); 59549dc9577SHauke Mehrtens 59649dc9577SHauke Mehrtens /* Fix up interrupt lines */ 59785eb92e8SHauke Mehrtens dev->irq = bcma_core_irq(pc_host->pdev->core, 0); 59849dc9577SHauke Mehrtens pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 59949dc9577SHauke Mehrtens 600f4a83e57SHauke Mehrtens readrq = pcie_get_readrq(dev); 601f4a83e57SHauke Mehrtens if (readrq > 128) { 602f4a83e57SHauke Mehrtens pr_info("change PCIe max read request size from %i to 128\n", readrq); 603f4a83e57SHauke Mehrtens pcie_set_readrq(dev, 128); 604f4a83e57SHauke Mehrtens } 60549dc9577SHauke Mehrtens return 0; 60649dc9577SHauke Mehrtens } 60749dc9577SHauke Mehrtens EXPORT_SYMBOL(bcma_core_pci_plat_dev_init); 60849dc9577SHauke Mehrtens 60949dc9577SHauke Mehrtens /* PCI device IRQ mapping. */ 61049dc9577SHauke Mehrtens int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev) 61149dc9577SHauke Mehrtens { 61249dc9577SHauke Mehrtens struct bcma_drv_pci_host *pc_host; 61349dc9577SHauke Mehrtens 61449dc9577SHauke Mehrtens if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) { 61549dc9577SHauke Mehrtens /* This is not a device on the PCI-core bridge. */ 61649dc9577SHauke Mehrtens return -ENODEV; 61749dc9577SHauke Mehrtens } 61849dc9577SHauke Mehrtens 61949dc9577SHauke Mehrtens pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, 62049dc9577SHauke Mehrtens pci_ops); 62185eb92e8SHauke Mehrtens return bcma_core_irq(pc_host->pdev->core, 0); 62249dc9577SHauke Mehrtens } 62349dc9577SHauke Mehrtens EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq); 624