1 /* 2 * sata_sx4.c - Promise SATA 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2003-2004 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * Hardware documentation available under NDA. 30 * 31 */ 32 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <linux/init.h> 37 #include <linux/blkdev.h> 38 #include <linux/delay.h> 39 #include <linux/interrupt.h> 40 #include <linux/device.h> 41 #include <scsi/scsi_host.h> 42 #include <scsi/scsi_cmnd.h> 43 #include <linux/libata.h> 44 #include "sata_promise.h" 45 46 #define DRV_NAME "sata_sx4" 47 #define DRV_VERSION "0.10" 48 49 50 enum { 51 PDC_MMIO_BAR = 3, 52 PDC_DIMM_BAR = 4, 53 54 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */ 55 56 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ 57 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */ 58 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ 59 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */ 60 61 PDC_20621_SEQCTL = 0x400, 62 PDC_20621_SEQMASK = 0x480, 63 PDC_20621_GENERAL_CTL = 0x484, 64 PDC_20621_PAGE_SIZE = (32 * 1024), 65 66 /* chosen, not constant, values; we design our own DIMM mem map */ 67 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */ 68 PDC_20621_DIMM_BASE = 0x00200000, 69 PDC_20621_DIMM_DATA = (64 * 1024), 70 PDC_DIMM_DATA_STEP = (256 * 1024), 71 PDC_DIMM_WINDOW_STEP = (8 * 1024), 72 PDC_DIMM_HOST_PRD = (6 * 1024), 73 PDC_DIMM_HOST_PKT = (128 * 0), 74 PDC_DIMM_HPKT_PRD = (128 * 1), 75 PDC_DIMM_ATA_PKT = (128 * 2), 76 PDC_DIMM_APKT_PRD = (128 * 3), 77 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128, 78 PDC_PAGE_WINDOW = 0x40, 79 PDC_PAGE_DATA = PDC_PAGE_WINDOW + 80 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE), 81 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE, 82 83 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */ 84 85 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | 86 (1<<23), 87 88 board_20621 = 0, /* FastTrak S150 SX4 */ 89 90 PDC_RESET = (1 << 11), /* HDMA reset */ 91 92 PDC_MAX_HDMA = 32, 93 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1), 94 95 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50, 96 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51, 97 PDC_MAX_DIMM_MODULE = 0x02, 98 PDC_I2C_CONTROL_OFFSET = 0x48, 99 PDC_I2C_ADDR_DATA_OFFSET = 0x4C, 100 PDC_DIMM0_CONTROL_OFFSET = 0x80, 101 PDC_DIMM1_CONTROL_OFFSET = 0x84, 102 PDC_SDRAM_CONTROL_OFFSET = 0x88, 103 PDC_I2C_WRITE = 0x00000000, 104 PDC_I2C_READ = 0x00000040, 105 PDC_I2C_START = 0x00000080, 106 PDC_I2C_MASK_INT = 0x00000020, 107 PDC_I2C_COMPLETE = 0x00010000, 108 PDC_I2C_NO_ACK = 0x00100000, 109 PDC_DIMM_SPD_SUBADDRESS_START = 0x00, 110 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F, 111 PDC_DIMM_SPD_ROW_NUM = 3, 112 PDC_DIMM_SPD_COLUMN_NUM = 4, 113 PDC_DIMM_SPD_MODULE_ROW = 5, 114 PDC_DIMM_SPD_TYPE = 11, 115 PDC_DIMM_SPD_FRESH_RATE = 12, 116 PDC_DIMM_SPD_BANK_NUM = 17, 117 PDC_DIMM_SPD_CAS_LATENCY = 18, 118 PDC_DIMM_SPD_ATTRIBUTE = 21, 119 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27, 120 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28, 121 PDC_DIMM_SPD_RAS_CAS_DELAY = 29, 122 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30, 123 PDC_DIMM_SPD_SYSTEM_FREQ = 126, 124 PDC_CTL_STATUS = 0x08, 125 PDC_DIMM_WINDOW_CTLR = 0x0C, 126 PDC_TIME_CONTROL = 0x3C, 127 PDC_TIME_PERIOD = 0x40, 128 PDC_TIME_COUNTER = 0x44, 129 PDC_GENERAL_CTLR = 0x484, 130 PCI_PLL_INIT = 0x8A531824, 131 PCI_X_TCOUNT = 0xEE1E5CFF 132 }; 133 134 135 struct pdc_port_priv { 136 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512]; 137 u8 *pkt; 138 dma_addr_t pkt_dma; 139 }; 140 141 struct pdc_host_priv { 142 unsigned int doing_hdma; 143 unsigned int hdma_prod; 144 unsigned int hdma_cons; 145 struct { 146 struct ata_queued_cmd *qc; 147 unsigned int seq; 148 unsigned long pkt_ofs; 149 } hdma[32]; 150 }; 151 152 153 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 154 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance); 155 static void pdc_eng_timeout(struct ata_port *ap); 156 static void pdc_20621_phy_reset (struct ata_port *ap); 157 static int pdc_port_start(struct ata_port *ap); 158 static void pdc20621_qc_prep(struct ata_queued_cmd *qc); 159 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 160 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 161 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe); 162 static int pdc20621_detect_dimm(struct ata_probe_ent *pe); 163 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, 164 u32 device, u32 subaddr, u32 *pdata); 165 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe); 166 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe); 167 #ifdef ATA_VERBOSE_DEBUG 168 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, 169 void *psource, u32 offset, u32 size); 170 #endif 171 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, 172 void *psource, u32 offset, u32 size); 173 static void pdc20621_irq_clear(struct ata_port *ap); 174 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc); 175 176 177 static struct scsi_host_template pdc_sata_sht = { 178 .module = THIS_MODULE, 179 .name = DRV_NAME, 180 .ioctl = ata_scsi_ioctl, 181 .queuecommand = ata_scsi_queuecmd, 182 .can_queue = ATA_DEF_QUEUE, 183 .this_id = ATA_SHT_THIS_ID, 184 .sg_tablesize = LIBATA_MAX_PRD, 185 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 186 .emulated = ATA_SHT_EMULATED, 187 .use_clustering = ATA_SHT_USE_CLUSTERING, 188 .proc_name = DRV_NAME, 189 .dma_boundary = ATA_DMA_BOUNDARY, 190 .slave_configure = ata_scsi_slave_config, 191 .slave_destroy = ata_scsi_slave_destroy, 192 .bios_param = ata_std_bios_param, 193 }; 194 195 static const struct ata_port_operations pdc_20621_ops = { 196 .port_disable = ata_port_disable, 197 .tf_load = pdc_tf_load_mmio, 198 .tf_read = ata_tf_read, 199 .check_status = ata_check_status, 200 .exec_command = pdc_exec_command_mmio, 201 .dev_select = ata_std_dev_select, 202 .phy_reset = pdc_20621_phy_reset, 203 .qc_prep = pdc20621_qc_prep, 204 .qc_issue = pdc20621_qc_issue_prot, 205 .data_xfer = ata_data_xfer, 206 .eng_timeout = pdc_eng_timeout, 207 .irq_handler = pdc20621_interrupt, 208 .irq_clear = pdc20621_irq_clear, 209 .irq_on = ata_irq_on, 210 .irq_ack = ata_irq_ack, 211 .port_start = pdc_port_start, 212 }; 213 214 static const struct ata_port_info pdc_port_info[] = { 215 /* board_20621 */ 216 { 217 .sht = &pdc_sata_sht, 218 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 219 ATA_FLAG_SRST | ATA_FLAG_MMIO | 220 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING, 221 .pio_mask = 0x1f, /* pio0-4 */ 222 .mwdma_mask = 0x07, /* mwdma0-2 */ 223 .udma_mask = 0x7f, /* udma0-6 ; FIXME */ 224 .port_ops = &pdc_20621_ops, 225 }, 226 227 }; 228 229 static const struct pci_device_id pdc_sata_pci_tbl[] = { 230 { PCI_VDEVICE(PROMISE, 0x6622), board_20621 }, 231 232 { } /* terminate list */ 233 }; 234 235 static struct pci_driver pdc_sata_pci_driver = { 236 .name = DRV_NAME, 237 .id_table = pdc_sata_pci_tbl, 238 .probe = pdc_sata_init_one, 239 .remove = ata_pci_remove_one, 240 }; 241 242 243 static int pdc_port_start(struct ata_port *ap) 244 { 245 struct device *dev = ap->host->dev; 246 struct pdc_port_priv *pp; 247 int rc; 248 249 rc = ata_port_start(ap); 250 if (rc) 251 return rc; 252 253 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 254 if (!pp) 255 return -ENOMEM; 256 257 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); 258 if (!pp->pkt) 259 return -ENOMEM; 260 261 ap->private_data = pp; 262 263 return 0; 264 } 265 266 static void pdc_20621_phy_reset (struct ata_port *ap) 267 { 268 VPRINTK("ENTER\n"); 269 ap->cbl = ATA_CBL_SATA; 270 ata_port_probe(ap); 271 ata_bus_reset(ap); 272 } 273 274 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf, 275 unsigned int portno, 276 unsigned int total_len) 277 { 278 u32 addr; 279 unsigned int dw = PDC_DIMM_APKT_PRD >> 2; 280 u32 *buf32 = (u32 *) buf; 281 282 /* output ATA packet S/G table */ 283 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA + 284 (PDC_DIMM_DATA_STEP * portno); 285 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr); 286 buf32[dw] = cpu_to_le32(addr); 287 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT); 288 289 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n", 290 PDC_20621_DIMM_BASE + 291 (PDC_DIMM_WINDOW_STEP * portno) + 292 PDC_DIMM_APKT_PRD, 293 buf32[dw], buf32[dw + 1]); 294 } 295 296 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf, 297 unsigned int portno, 298 unsigned int total_len) 299 { 300 u32 addr; 301 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2; 302 u32 *buf32 = (u32 *) buf; 303 304 /* output Host DMA packet S/G table */ 305 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA + 306 (PDC_DIMM_DATA_STEP * portno); 307 308 buf32[dw] = cpu_to_le32(addr); 309 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT); 310 311 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n", 312 PDC_20621_DIMM_BASE + 313 (PDC_DIMM_WINDOW_STEP * portno) + 314 PDC_DIMM_HPKT_PRD, 315 buf32[dw], buf32[dw + 1]); 316 } 317 318 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf, 319 unsigned int devno, u8 *buf, 320 unsigned int portno) 321 { 322 unsigned int i, dw; 323 u32 *buf32 = (u32 *) buf; 324 u8 dev_reg; 325 326 unsigned int dimm_sg = PDC_20621_DIMM_BASE + 327 (PDC_DIMM_WINDOW_STEP * portno) + 328 PDC_DIMM_APKT_PRD; 329 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg); 330 331 i = PDC_DIMM_ATA_PKT; 332 333 /* 334 * Set up ATA packet 335 */ 336 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE))) 337 buf[i++] = PDC_PKT_READ; 338 else if (tf->protocol == ATA_PROT_NODATA) 339 buf[i++] = PDC_PKT_NODATA; 340 else 341 buf[i++] = 0; 342 buf[i++] = 0; /* reserved */ 343 buf[i++] = portno + 1; /* seq. id */ 344 buf[i++] = 0xff; /* delay seq. id */ 345 346 /* dimm dma S/G, and next-pkt */ 347 dw = i >> 2; 348 if (tf->protocol == ATA_PROT_NODATA) 349 buf32[dw] = 0; 350 else 351 buf32[dw] = cpu_to_le32(dimm_sg); 352 buf32[dw + 1] = 0; 353 i += 8; 354 355 if (devno == 0) 356 dev_reg = ATA_DEVICE_OBS; 357 else 358 dev_reg = ATA_DEVICE_OBS | ATA_DEV1; 359 360 /* select device */ 361 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE; 362 buf[i++] = dev_reg; 363 364 /* device control register */ 365 buf[i++] = (1 << 5) | PDC_REG_DEVCTL; 366 buf[i++] = tf->ctl; 367 368 return i; 369 } 370 371 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf, 372 unsigned int portno) 373 { 374 unsigned int dw; 375 u32 tmp, *buf32 = (u32 *) buf; 376 377 unsigned int host_sg = PDC_20621_DIMM_BASE + 378 (PDC_DIMM_WINDOW_STEP * portno) + 379 PDC_DIMM_HOST_PRD; 380 unsigned int dimm_sg = PDC_20621_DIMM_BASE + 381 (PDC_DIMM_WINDOW_STEP * portno) + 382 PDC_DIMM_HPKT_PRD; 383 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg); 384 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg); 385 386 dw = PDC_DIMM_HOST_PKT >> 2; 387 388 /* 389 * Set up Host DMA packet 390 */ 391 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE))) 392 tmp = PDC_PKT_READ; 393 else 394 tmp = 0; 395 tmp |= ((portno + 1 + 4) << 16); /* seq. id */ 396 tmp |= (0xff << 24); /* delay seq. id */ 397 buf32[dw + 0] = cpu_to_le32(tmp); 398 buf32[dw + 1] = cpu_to_le32(host_sg); 399 buf32[dw + 2] = cpu_to_le32(dimm_sg); 400 buf32[dw + 3] = 0; 401 402 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n", 403 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) + 404 PDC_DIMM_HOST_PKT, 405 buf32[dw + 0], 406 buf32[dw + 1], 407 buf32[dw + 2], 408 buf32[dw + 3]); 409 } 410 411 static void pdc20621_dma_prep(struct ata_queued_cmd *qc) 412 { 413 struct scatterlist *sg; 414 struct ata_port *ap = qc->ap; 415 struct pdc_port_priv *pp = ap->private_data; 416 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; 417 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR]; 418 unsigned int portno = ap->port_no; 419 unsigned int i, idx, total_len = 0, sgt_len; 420 u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ]; 421 422 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP)); 423 424 VPRINTK("ata%u: ENTER\n", ap->print_id); 425 426 /* hard-code chip #0 */ 427 mmio += PDC_CHIP0_OFS; 428 429 /* 430 * Build S/G table 431 */ 432 idx = 0; 433 ata_for_each_sg(sg, qc) { 434 buf[idx++] = cpu_to_le32(sg_dma_address(sg)); 435 buf[idx++] = cpu_to_le32(sg_dma_len(sg)); 436 total_len += sg_dma_len(sg); 437 } 438 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT); 439 sgt_len = idx * 4; 440 441 /* 442 * Build ATA, host DMA packets 443 */ 444 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len); 445 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno); 446 447 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len); 448 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno); 449 450 if (qc->tf.flags & ATA_TFLAG_LBA48) 451 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i); 452 else 453 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i); 454 455 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i); 456 457 /* copy three S/G tables and two packets to DIMM MMIO window */ 458 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP), 459 &pp->dimm_buf, PDC_DIMM_HEADER_SZ); 460 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) + 461 PDC_DIMM_HOST_PRD, 462 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len); 463 464 /* force host FIFO dump */ 465 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); 466 467 readl(dimm_mmio); /* MMIO PCI posting flush */ 468 469 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len); 470 } 471 472 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc) 473 { 474 struct ata_port *ap = qc->ap; 475 struct pdc_port_priv *pp = ap->private_data; 476 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; 477 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR]; 478 unsigned int portno = ap->port_no; 479 unsigned int i; 480 481 VPRINTK("ata%u: ENTER\n", ap->print_id); 482 483 /* hard-code chip #0 */ 484 mmio += PDC_CHIP0_OFS; 485 486 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno); 487 488 if (qc->tf.flags & ATA_TFLAG_LBA48) 489 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i); 490 else 491 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i); 492 493 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i); 494 495 /* copy three S/G tables and two packets to DIMM MMIO window */ 496 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP), 497 &pp->dimm_buf, PDC_DIMM_HEADER_SZ); 498 499 /* force host FIFO dump */ 500 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); 501 502 readl(dimm_mmio); /* MMIO PCI posting flush */ 503 504 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i); 505 } 506 507 static void pdc20621_qc_prep(struct ata_queued_cmd *qc) 508 { 509 switch (qc->tf.protocol) { 510 case ATA_PROT_DMA: 511 pdc20621_dma_prep(qc); 512 break; 513 case ATA_PROT_NODATA: 514 pdc20621_nodata_prep(qc); 515 break; 516 default: 517 break; 518 } 519 } 520 521 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc, 522 unsigned int seq, 523 u32 pkt_ofs) 524 { 525 struct ata_port *ap = qc->ap; 526 struct ata_host *host = ap->host; 527 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; 528 529 /* hard-code chip #0 */ 530 mmio += PDC_CHIP0_OFS; 531 532 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); 533 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ 534 535 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT); 536 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */ 537 } 538 539 static void pdc20621_push_hdma(struct ata_queued_cmd *qc, 540 unsigned int seq, 541 u32 pkt_ofs) 542 { 543 struct ata_port *ap = qc->ap; 544 struct pdc_host_priv *pp = ap->host->private_data; 545 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK; 546 547 if (!pp->doing_hdma) { 548 __pdc20621_push_hdma(qc, seq, pkt_ofs); 549 pp->doing_hdma = 1; 550 return; 551 } 552 553 pp->hdma[idx].qc = qc; 554 pp->hdma[idx].seq = seq; 555 pp->hdma[idx].pkt_ofs = pkt_ofs; 556 pp->hdma_prod++; 557 } 558 559 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc) 560 { 561 struct ata_port *ap = qc->ap; 562 struct pdc_host_priv *pp = ap->host->private_data; 563 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK; 564 565 /* if nothing on queue, we're done */ 566 if (pp->hdma_prod == pp->hdma_cons) { 567 pp->doing_hdma = 0; 568 return; 569 } 570 571 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq, 572 pp->hdma[idx].pkt_ofs); 573 pp->hdma_cons++; 574 } 575 576 #ifdef ATA_VERBOSE_DEBUG 577 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc) 578 { 579 struct ata_port *ap = qc->ap; 580 unsigned int port_no = ap->port_no; 581 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR]; 582 583 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP); 584 dimm_mmio += PDC_DIMM_HOST_PKT; 585 586 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio)); 587 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4)); 588 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8)); 589 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12)); 590 } 591 #else 592 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { } 593 #endif /* ATA_VERBOSE_DEBUG */ 594 595 static void pdc20621_packet_start(struct ata_queued_cmd *qc) 596 { 597 struct ata_port *ap = qc->ap; 598 struct ata_host *host = ap->host; 599 unsigned int port_no = ap->port_no; 600 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; 601 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 602 u8 seq = (u8) (port_no + 1); 603 unsigned int port_ofs; 604 605 /* hard-code chip #0 */ 606 mmio += PDC_CHIP0_OFS; 607 608 VPRINTK("ata%u: ENTER\n", ap->print_id); 609 610 wmb(); /* flush PRD, pkt writes */ 611 612 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no); 613 614 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */ 615 if (rw && qc->tf.protocol == ATA_PROT_DMA) { 616 seq += 4; 617 618 pdc20621_dump_hdma(qc); 619 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT); 620 VPRINTK("queued ofs 0x%x (%u), seq %u\n", 621 port_ofs + PDC_DIMM_HOST_PKT, 622 port_ofs + PDC_DIMM_HOST_PKT, 623 seq); 624 } else { 625 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); 626 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ 627 628 writel(port_ofs + PDC_DIMM_ATA_PKT, 629 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); 630 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); 631 VPRINTK("submitted ofs 0x%x (%u), seq %u\n", 632 port_ofs + PDC_DIMM_ATA_PKT, 633 port_ofs + PDC_DIMM_ATA_PKT, 634 seq); 635 } 636 } 637 638 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc) 639 { 640 switch (qc->tf.protocol) { 641 case ATA_PROT_DMA: 642 case ATA_PROT_NODATA: 643 pdc20621_packet_start(qc); 644 return 0; 645 646 case ATA_PROT_ATAPI_DMA: 647 BUG(); 648 break; 649 650 default: 651 break; 652 } 653 654 return ata_qc_issue_prot(qc); 655 } 656 657 static inline unsigned int pdc20621_host_intr( struct ata_port *ap, 658 struct ata_queued_cmd *qc, 659 unsigned int doing_hdma, 660 void __iomem *mmio) 661 { 662 unsigned int port_no = ap->port_no; 663 unsigned int port_ofs = 664 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no); 665 u8 status; 666 unsigned int handled = 0; 667 668 VPRINTK("ENTER\n"); 669 670 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */ 671 (!(qc->tf.flags & ATA_TFLAG_WRITE))) { 672 673 /* step two - DMA from DIMM to host */ 674 if (doing_hdma) { 675 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->print_id, 676 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); 677 /* get drive status; clear intr; complete txn */ 678 qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); 679 ata_qc_complete(qc); 680 pdc20621_pop_hdma(qc); 681 } 682 683 /* step one - exec ATA command */ 684 else { 685 u8 seq = (u8) (port_no + 1 + 4); 686 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->print_id, 687 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); 688 689 /* submit hdma pkt */ 690 pdc20621_dump_hdma(qc); 691 pdc20621_push_hdma(qc, seq, 692 port_ofs + PDC_DIMM_HOST_PKT); 693 } 694 handled = 1; 695 696 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */ 697 698 /* step one - DMA from host to DIMM */ 699 if (doing_hdma) { 700 u8 seq = (u8) (port_no + 1); 701 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->print_id, 702 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); 703 704 /* submit ata pkt */ 705 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); 706 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); 707 writel(port_ofs + PDC_DIMM_ATA_PKT, 708 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); 709 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); 710 } 711 712 /* step two - execute ATA command */ 713 else { 714 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->print_id, 715 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); 716 /* get drive status; clear intr; complete txn */ 717 qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); 718 ata_qc_complete(qc); 719 pdc20621_pop_hdma(qc); 720 } 721 handled = 1; 722 723 /* command completion, but no data xfer */ 724 } else if (qc->tf.protocol == ATA_PROT_NODATA) { 725 726 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); 727 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status); 728 qc->err_mask |= ac_err_mask(status); 729 ata_qc_complete(qc); 730 handled = 1; 731 732 } else { 733 ap->stats.idle_irq++; 734 } 735 736 return handled; 737 } 738 739 static void pdc20621_irq_clear(struct ata_port *ap) 740 { 741 struct ata_host *host = ap->host; 742 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; 743 744 mmio += PDC_CHIP0_OFS; 745 746 readl(mmio + PDC_20621_SEQMASK); 747 } 748 749 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance) 750 { 751 struct ata_host *host = dev_instance; 752 struct ata_port *ap; 753 u32 mask = 0; 754 unsigned int i, tmp, port_no; 755 unsigned int handled = 0; 756 void __iomem *mmio_base; 757 758 VPRINTK("ENTER\n"); 759 760 if (!host || !host->iomap[PDC_MMIO_BAR]) { 761 VPRINTK("QUICK EXIT\n"); 762 return IRQ_NONE; 763 } 764 765 mmio_base = host->iomap[PDC_MMIO_BAR]; 766 767 /* reading should also clear interrupts */ 768 mmio_base += PDC_CHIP0_OFS; 769 mask = readl(mmio_base + PDC_20621_SEQMASK); 770 VPRINTK("mask == 0x%x\n", mask); 771 772 if (mask == 0xffffffff) { 773 VPRINTK("QUICK EXIT 2\n"); 774 return IRQ_NONE; 775 } 776 mask &= 0xffff; /* only 16 tags possible */ 777 if (!mask) { 778 VPRINTK("QUICK EXIT 3\n"); 779 return IRQ_NONE; 780 } 781 782 spin_lock(&host->lock); 783 784 for (i = 1; i < 9; i++) { 785 port_no = i - 1; 786 if (port_no > 3) 787 port_no -= 4; 788 if (port_no >= host->n_ports) 789 ap = NULL; 790 else 791 ap = host->ports[port_no]; 792 tmp = mask & (1 << i); 793 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp); 794 if (tmp && ap && 795 !(ap->flags & ATA_FLAG_DISABLED)) { 796 struct ata_queued_cmd *qc; 797 798 qc = ata_qc_from_tag(ap, ap->active_tag); 799 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) 800 handled += pdc20621_host_intr(ap, qc, (i > 4), 801 mmio_base); 802 } 803 } 804 805 spin_unlock(&host->lock); 806 807 VPRINTK("mask == 0x%x\n", mask); 808 809 VPRINTK("EXIT\n"); 810 811 return IRQ_RETVAL(handled); 812 } 813 814 static void pdc_eng_timeout(struct ata_port *ap) 815 { 816 u8 drv_stat; 817 struct ata_host *host = ap->host; 818 struct ata_queued_cmd *qc; 819 unsigned long flags; 820 821 DPRINTK("ENTER\n"); 822 823 spin_lock_irqsave(&host->lock, flags); 824 825 qc = ata_qc_from_tag(ap, ap->active_tag); 826 827 switch (qc->tf.protocol) { 828 case ATA_PROT_DMA: 829 case ATA_PROT_NODATA: 830 ata_port_printk(ap, KERN_ERR, "command timeout\n"); 831 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap)); 832 break; 833 834 default: 835 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); 836 837 ata_port_printk(ap, KERN_ERR, 838 "unknown timeout, cmd 0x%x stat 0x%x\n", 839 qc->tf.command, drv_stat); 840 841 qc->err_mask |= ac_err_mask(drv_stat); 842 break; 843 } 844 845 spin_unlock_irqrestore(&host->lock, flags); 846 ata_eh_qc_complete(qc); 847 DPRINTK("EXIT\n"); 848 } 849 850 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) 851 { 852 WARN_ON (tf->protocol == ATA_PROT_DMA || 853 tf->protocol == ATA_PROT_NODATA); 854 ata_tf_load(ap, tf); 855 } 856 857 858 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) 859 { 860 WARN_ON (tf->protocol == ATA_PROT_DMA || 861 tf->protocol == ATA_PROT_NODATA); 862 ata_exec_command(ap, tf); 863 } 864 865 866 static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base) 867 { 868 port->cmd_addr = base; 869 port->data_addr = base; 870 port->feature_addr = 871 port->error_addr = base + 0x4; 872 port->nsect_addr = base + 0x8; 873 port->lbal_addr = base + 0xc; 874 port->lbam_addr = base + 0x10; 875 port->lbah_addr = base + 0x14; 876 port->device_addr = base + 0x18; 877 port->command_addr = 878 port->status_addr = base + 0x1c; 879 port->altstatus_addr = 880 port->ctl_addr = base + 0x38; 881 } 882 883 884 #ifdef ATA_VERBOSE_DEBUG 885 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource, 886 u32 offset, u32 size) 887 { 888 u32 window_size; 889 u16 idx; 890 u8 page_mask; 891 long dist; 892 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 893 void __iomem *dimm_mmio = pe->iomap[PDC_DIMM_BAR]; 894 895 /* hard-code chip #0 */ 896 mmio += PDC_CHIP0_OFS; 897 898 page_mask = 0x00; 899 window_size = 0x2000 * 4; /* 32K byte uchar size */ 900 idx = (u16) (offset / window_size); 901 902 writel(0x01, mmio + PDC_GENERAL_CTLR); 903 readl(mmio + PDC_GENERAL_CTLR); 904 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); 905 readl(mmio + PDC_DIMM_WINDOW_CTLR); 906 907 offset -= (idx * window_size); 908 idx++; 909 dist = ((long) (window_size - (offset + size))) >= 0 ? size : 910 (long) (window_size - offset); 911 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4), 912 dist); 913 914 psource += dist; 915 size -= dist; 916 for (; (long) size >= (long) window_size ;) { 917 writel(0x01, mmio + PDC_GENERAL_CTLR); 918 readl(mmio + PDC_GENERAL_CTLR); 919 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); 920 readl(mmio + PDC_DIMM_WINDOW_CTLR); 921 memcpy_fromio((char *) psource, (char *) (dimm_mmio), 922 window_size / 4); 923 psource += window_size; 924 size -= window_size; 925 idx ++; 926 } 927 928 if (size) { 929 writel(0x01, mmio + PDC_GENERAL_CTLR); 930 readl(mmio + PDC_GENERAL_CTLR); 931 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); 932 readl(mmio + PDC_DIMM_WINDOW_CTLR); 933 memcpy_fromio((char *) psource, (char *) (dimm_mmio), 934 size / 4); 935 } 936 } 937 #endif 938 939 940 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource, 941 u32 offset, u32 size) 942 { 943 u32 window_size; 944 u16 idx; 945 u8 page_mask; 946 long dist; 947 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 948 void __iomem *dimm_mmio = pe->iomap[PDC_DIMM_BAR]; 949 950 /* hard-code chip #0 */ 951 mmio += PDC_CHIP0_OFS; 952 953 page_mask = 0x00; 954 window_size = 0x2000 * 4; /* 32K byte uchar size */ 955 idx = (u16) (offset / window_size); 956 957 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); 958 readl(mmio + PDC_DIMM_WINDOW_CTLR); 959 offset -= (idx * window_size); 960 idx++; 961 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size : 962 (long) (window_size - offset); 963 memcpy_toio(dimm_mmio + offset / 4, psource, dist); 964 writel(0x01, mmio + PDC_GENERAL_CTLR); 965 readl(mmio + PDC_GENERAL_CTLR); 966 967 psource += dist; 968 size -= dist; 969 for (; (long) size >= (long) window_size ;) { 970 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); 971 readl(mmio + PDC_DIMM_WINDOW_CTLR); 972 memcpy_toio(dimm_mmio, psource, window_size / 4); 973 writel(0x01, mmio + PDC_GENERAL_CTLR); 974 readl(mmio + PDC_GENERAL_CTLR); 975 psource += window_size; 976 size -= window_size; 977 idx ++; 978 } 979 980 if (size) { 981 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); 982 readl(mmio + PDC_DIMM_WINDOW_CTLR); 983 memcpy_toio(dimm_mmio, psource, size / 4); 984 writel(0x01, mmio + PDC_GENERAL_CTLR); 985 readl(mmio + PDC_GENERAL_CTLR); 986 } 987 } 988 989 990 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device, 991 u32 subaddr, u32 *pdata) 992 { 993 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 994 u32 i2creg = 0; 995 u32 status; 996 u32 count =0; 997 998 /* hard-code chip #0 */ 999 mmio += PDC_CHIP0_OFS; 1000 1001 i2creg |= device << 24; 1002 i2creg |= subaddr << 16; 1003 1004 /* Set the device and subaddress */ 1005 writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET); 1006 readl(mmio + PDC_I2C_ADDR_DATA_OFFSET); 1007 1008 /* Write Control to perform read operation, mask int */ 1009 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT, 1010 mmio + PDC_I2C_CONTROL_OFFSET); 1011 1012 for (count = 0; count <= 1000; count ++) { 1013 status = readl(mmio + PDC_I2C_CONTROL_OFFSET); 1014 if (status & PDC_I2C_COMPLETE) { 1015 status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET); 1016 break; 1017 } else if (count == 1000) 1018 return 0; 1019 } 1020 1021 *pdata = (status >> 8) & 0x000000ff; 1022 return 1; 1023 } 1024 1025 1026 static int pdc20621_detect_dimm(struct ata_probe_ent *pe) 1027 { 1028 u32 data=0 ; 1029 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 1030 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) { 1031 if (data == 100) 1032 return 100; 1033 } else 1034 return 0; 1035 1036 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) { 1037 if(data <= 0x75) 1038 return 133; 1039 } else 1040 return 0; 1041 1042 return 0; 1043 } 1044 1045 1046 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe) 1047 { 1048 u32 spd0[50]; 1049 u32 data = 0; 1050 int size, i; 1051 u8 bdimmsize; 1052 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 1053 static const struct { 1054 unsigned int reg; 1055 unsigned int ofs; 1056 } pdc_i2c_read_data [] = { 1057 { PDC_DIMM_SPD_TYPE, 11 }, 1058 { PDC_DIMM_SPD_FRESH_RATE, 12 }, 1059 { PDC_DIMM_SPD_COLUMN_NUM, 4 }, 1060 { PDC_DIMM_SPD_ATTRIBUTE, 21 }, 1061 { PDC_DIMM_SPD_ROW_NUM, 3 }, 1062 { PDC_DIMM_SPD_BANK_NUM, 17 }, 1063 { PDC_DIMM_SPD_MODULE_ROW, 5 }, 1064 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 }, 1065 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 }, 1066 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 }, 1067 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 }, 1068 { PDC_DIMM_SPD_CAS_LATENCY, 18 }, 1069 }; 1070 1071 /* hard-code chip #0 */ 1072 mmio += PDC_CHIP0_OFS; 1073 1074 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++) 1075 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 1076 pdc_i2c_read_data[i].reg, 1077 &spd0[pdc_i2c_read_data[i].ofs]); 1078 1079 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4); 1080 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) | 1081 ((((spd0[27] + 9) / 10) - 1) << 8) ; 1082 data |= (((((spd0[29] > spd0[28]) 1083 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10; 1084 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12; 1085 1086 if (spd0[18] & 0x08) 1087 data |= ((0x03) << 14); 1088 else if (spd0[18] & 0x04) 1089 data |= ((0x02) << 14); 1090 else if (spd0[18] & 0x01) 1091 data |= ((0x01) << 14); 1092 else 1093 data |= (0 << 14); 1094 1095 /* 1096 Calculate the size of bDIMMSize (power of 2) and 1097 merge the DIMM size by program start/end address. 1098 */ 1099 1100 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3; 1101 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */ 1102 data |= (((size / 16) - 1) << 16); 1103 data |= (0 << 23); 1104 data |= 8; 1105 writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET); 1106 readl(mmio + PDC_DIMM0_CONTROL_OFFSET); 1107 return size; 1108 } 1109 1110 1111 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe) 1112 { 1113 u32 data, spd0; 1114 int error, i; 1115 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 1116 1117 /* hard-code chip #0 */ 1118 mmio += PDC_CHIP0_OFS; 1119 1120 /* 1121 Set To Default : DIMM Module Global Control Register (0x022259F1) 1122 DIMM Arbitration Disable (bit 20) 1123 DIMM Data/Control Output Driving Selection (bit12 - bit15) 1124 Refresh Enable (bit 17) 1125 */ 1126 1127 data = 0x022259F1; 1128 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET); 1129 readl(mmio + PDC_SDRAM_CONTROL_OFFSET); 1130 1131 /* Turn on for ECC */ 1132 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 1133 PDC_DIMM_SPD_TYPE, &spd0); 1134 if (spd0 == 0x02) { 1135 data |= (0x01 << 16); 1136 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET); 1137 readl(mmio + PDC_SDRAM_CONTROL_OFFSET); 1138 printk(KERN_ERR "Local DIMM ECC Enabled\n"); 1139 } 1140 1141 /* DIMM Initialization Select/Enable (bit 18/19) */ 1142 data &= (~(1<<18)); 1143 data |= (1<<19); 1144 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET); 1145 1146 error = 1; 1147 for (i = 1; i <= 10; i++) { /* polling ~5 secs */ 1148 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET); 1149 if (!(data & (1<<19))) { 1150 error = 0; 1151 break; 1152 } 1153 msleep(i*100); 1154 } 1155 return error; 1156 } 1157 1158 1159 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe) 1160 { 1161 int speed, size, length; 1162 u32 addr,spd0,pci_status; 1163 u32 tmp=0; 1164 u32 time_period=0; 1165 u32 tcount=0; 1166 u32 ticks=0; 1167 u32 clock=0; 1168 u32 fparam=0; 1169 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 1170 1171 /* hard-code chip #0 */ 1172 mmio += PDC_CHIP0_OFS; 1173 1174 /* Initialize PLL based upon PCI Bus Frequency */ 1175 1176 /* Initialize Time Period Register */ 1177 writel(0xffffffff, mmio + PDC_TIME_PERIOD); 1178 time_period = readl(mmio + PDC_TIME_PERIOD); 1179 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period); 1180 1181 /* Enable timer */ 1182 writel(0x00001a0, mmio + PDC_TIME_CONTROL); 1183 readl(mmio + PDC_TIME_CONTROL); 1184 1185 /* Wait 3 seconds */ 1186 msleep(3000); 1187 1188 /* 1189 When timer is enabled, counter is decreased every internal 1190 clock cycle. 1191 */ 1192 1193 tcount = readl(mmio + PDC_TIME_COUNTER); 1194 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount); 1195 1196 /* 1197 If SX4 is on PCI-X bus, after 3 seconds, the timer counter 1198 register should be >= (0xffffffff - 3x10^8). 1199 */ 1200 if(tcount >= PCI_X_TCOUNT) { 1201 ticks = (time_period - tcount); 1202 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks); 1203 1204 clock = (ticks / 300000); 1205 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock); 1206 1207 clock = (clock * 33); 1208 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock); 1209 1210 /* PLL F Param (bit 22:16) */ 1211 fparam = (1400000 / clock) - 2; 1212 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam); 1213 1214 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */ 1215 pci_status = (0x8a001824 | (fparam << 16)); 1216 } else 1217 pci_status = PCI_PLL_INIT; 1218 1219 /* Initialize PLL. */ 1220 VPRINTK("pci_status: 0x%x\n", pci_status); 1221 writel(pci_status, mmio + PDC_CTL_STATUS); 1222 readl(mmio + PDC_CTL_STATUS); 1223 1224 /* 1225 Read SPD of DIMM by I2C interface, 1226 and program the DIMM Module Controller. 1227 */ 1228 if (!(speed = pdc20621_detect_dimm(pe))) { 1229 printk(KERN_ERR "Detect Local DIMM Fail\n"); 1230 return 1; /* DIMM error */ 1231 } 1232 VPRINTK("Local DIMM Speed = %d\n", speed); 1233 1234 /* Programming DIMM0 Module Control Register (index_CID0:80h) */ 1235 size = pdc20621_prog_dimm0(pe); 1236 VPRINTK("Local DIMM Size = %dMB\n",size); 1237 1238 /* Programming DIMM Module Global Control Register (index_CID0:88h) */ 1239 if (pdc20621_prog_dimm_global(pe)) { 1240 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n"); 1241 return 1; 1242 } 1243 1244 #ifdef ATA_VERBOSE_DEBUG 1245 { 1246 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ', 1247 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ', 1248 '1','.','1','0', 1249 '9','8','0','3','1','6','1','2',0,0}; 1250 u8 test_parttern2[40] = {0}; 1251 1252 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40); 1253 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40); 1254 1255 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40); 1256 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40); 1257 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], 1258 test_parttern2[1], &(test_parttern2[2])); 1259 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040, 1260 40); 1261 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], 1262 test_parttern2[1], &(test_parttern2[2])); 1263 1264 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40); 1265 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40); 1266 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], 1267 test_parttern2[1], &(test_parttern2[2])); 1268 } 1269 #endif 1270 1271 /* ECC initiliazation. */ 1272 1273 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 1274 PDC_DIMM_SPD_TYPE, &spd0); 1275 if (spd0 == 0x02) { 1276 VPRINTK("Start ECC initialization\n"); 1277 addr = 0; 1278 length = size * 1024 * 1024; 1279 while (addr < length) { 1280 pdc20621_put_to_dimm(pe, (void *) &tmp, addr, 1281 sizeof(u32)); 1282 addr += sizeof(u32); 1283 } 1284 VPRINTK("Finish ECC initialization\n"); 1285 } 1286 return 0; 1287 } 1288 1289 1290 static void pdc_20621_init(struct ata_probe_ent *pe) 1291 { 1292 u32 tmp; 1293 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 1294 1295 /* hard-code chip #0 */ 1296 mmio += PDC_CHIP0_OFS; 1297 1298 /* 1299 * Select page 0x40 for our 32k DIMM window 1300 */ 1301 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000; 1302 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */ 1303 writel(tmp, mmio + PDC_20621_DIMM_WINDOW); 1304 1305 /* 1306 * Reset Host DMA 1307 */ 1308 tmp = readl(mmio + PDC_HDMA_CTLSTAT); 1309 tmp |= PDC_RESET; 1310 writel(tmp, mmio + PDC_HDMA_CTLSTAT); 1311 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */ 1312 1313 udelay(10); 1314 1315 tmp = readl(mmio + PDC_HDMA_CTLSTAT); 1316 tmp &= ~PDC_RESET; 1317 writel(tmp, mmio + PDC_HDMA_CTLSTAT); 1318 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */ 1319 } 1320 1321 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 1322 { 1323 static int printed_version; 1324 struct ata_probe_ent *probe_ent; 1325 void __iomem *base; 1326 struct pdc_host_priv *hpriv; 1327 unsigned int board_idx = (unsigned int) ent->driver_data; 1328 int rc; 1329 1330 if (!printed_version++) 1331 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1332 1333 rc = pcim_enable_device(pdev); 1334 if (rc) 1335 return rc; 1336 1337 rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR), 1338 DRV_NAME); 1339 if (rc == -EBUSY) 1340 pcim_pin_device(pdev); 1341 if (rc) 1342 return rc; 1343 1344 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 1345 if (rc) 1346 return rc; 1347 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 1348 if (rc) 1349 return rc; 1350 1351 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL); 1352 if (probe_ent == NULL) 1353 return -ENOMEM; 1354 1355 probe_ent->dev = pci_dev_to_dev(pdev); 1356 INIT_LIST_HEAD(&probe_ent->node); 1357 1358 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 1359 if (!hpriv) 1360 return -ENOMEM; 1361 1362 probe_ent->sht = pdc_port_info[board_idx].sht; 1363 probe_ent->port_flags = pdc_port_info[board_idx].flags; 1364 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; 1365 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; 1366 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; 1367 probe_ent->port_ops = pdc_port_info[board_idx].port_ops; 1368 1369 probe_ent->irq = pdev->irq; 1370 probe_ent->irq_flags = IRQF_SHARED; 1371 probe_ent->iomap = pcim_iomap_table(pdev); 1372 1373 probe_ent->private_data = hpriv; 1374 base = probe_ent->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS; 1375 1376 probe_ent->n_ports = 4; 1377 pdc_sata_setup_port(&probe_ent->port[0], base + 0x200); 1378 pdc_sata_setup_port(&probe_ent->port[1], base + 0x280); 1379 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300); 1380 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380); 1381 1382 pci_set_master(pdev); 1383 1384 /* initialize adapter */ 1385 /* initialize local dimm */ 1386 if (pdc20621_dimm_init(probe_ent)) 1387 return -ENOMEM; 1388 pdc_20621_init(probe_ent); 1389 1390 if (!ata_device_add(probe_ent)) 1391 return -ENODEV; 1392 1393 devm_kfree(&pdev->dev, probe_ent); 1394 return 0; 1395 } 1396 1397 1398 static int __init pdc_sata_init(void) 1399 { 1400 return pci_register_driver(&pdc_sata_pci_driver); 1401 } 1402 1403 1404 static void __exit pdc_sata_exit(void) 1405 { 1406 pci_unregister_driver(&pdc_sata_pci_driver); 1407 } 1408 1409 1410 MODULE_AUTHOR("Jeff Garzik"); 1411 MODULE_DESCRIPTION("Promise SATA low-level driver"); 1412 MODULE_LICENSE("GPL"); 1413 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl); 1414 MODULE_VERSION(DRV_VERSION); 1415 1416 module_init(pdc_sata_init); 1417 module_exit(pdc_sata_exit); 1418