1 /* 2 * pata_ns87415.c - NS87415 (non PARISC) PATA 3 * 4 * (C) 2005 Red Hat <alan@redhat.com> 5 * 6 * This is a fairly generic MWDMA controller. It has some limitations 7 * as it requires timing reloads on PIO/DMA transitions but it is otherwise 8 * fairly well designed. 9 * 10 * This driver assumes the firmware has left the chip in a valid ST506 11 * compliant state, either legacy IRQ 14/15 or native INTA shared. You 12 * may need to add platform code if your system fails to do this. 13 * 14 * The same cell appears in the 87560 controller used by some PARISC 15 * systems. This has its own special mountain of errata. 16 * 17 * TODO: 18 * Test PARISC SuperIO 19 * Get someone to test on SPARC 20 * Implement lazy pio/dma switching for better performance 21 * 8bit shared timing. 22 * See if we need to kill the FIFO for ATAPI 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include <linux/init.h> 29 #include <linux/blkdev.h> 30 #include <linux/delay.h> 31 #include <linux/device.h> 32 #include <scsi/scsi_host.h> 33 #include <linux/libata.h> 34 #include <linux/ata.h> 35 36 #define DRV_NAME "pata_ns87415" 37 #define DRV_VERSION "0.0.1" 38 39 /** 40 * ns87415_set_mode - Initialize host controller mode timings 41 * @ap: Port whose timings we are configuring 42 * @adev: Device whose timings we are configuring 43 * @mode: Mode to set 44 * 45 * Program the mode registers for this controller, channel and 46 * device. Because the chip is quite an old design we have to do this 47 * for PIO/DMA switches. 48 * 49 * LOCKING: 50 * None (inherited from caller). 51 */ 52 53 static void ns87415_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode) 54 { 55 struct pci_dev *dev = to_pci_dev(ap->host->dev); 56 int unit = 2 * ap->port_no + adev->devno; 57 int timing = 0x44 + 2 * unit; 58 unsigned long T = 1000000000 / 33333; /* PCI clocks */ 59 struct ata_timing t; 60 u16 clocking; 61 u8 iordy; 62 u8 status; 63 64 /* Timing register format is 17 - low nybble read timing with 65 the high nybble being 16 - x for recovery time in PCI clocks */ 66 67 ata_timing_compute(adev, adev->pio_mode, &t, T, 0); 68 69 clocking = 17 - FIT(t.active, 2, 17); 70 clocking |= (16 - FIT(t.recover, 1, 16)) << 4; 71 /* Use the same timing for read and write bytes */ 72 clocking |= (clocking << 8); 73 pci_write_config_word(dev, timing, clocking); 74 75 /* Set the IORDY enable versus DMA enable on or off properly */ 76 pci_read_config_byte(dev, 0x42, &iordy); 77 iordy &= ~(1 << (4 + unit)); 78 if (mode >= XFER_MW_DMA_0 || !ata_pio_need_iordy(adev)) 79 iordy |= (1 << (4 + unit)); 80 81 /* Paranoia: We shouldn't ever get here with busy write buffers 82 but if so wait */ 83 84 pci_read_config_byte(dev, 0x43, &status); 85 while (status & 0x03) { 86 udelay(1); 87 pci_read_config_byte(dev, 0x43, &status); 88 } 89 /* Flip the IORDY/DMA bits now we are sure the write buffers are 90 clear */ 91 pci_write_config_byte(dev, 0x42, iordy); 92 93 /* TODO: Set byte 54 command timing to the best 8bit 94 mode shared by all four devices */ 95 } 96 97 /** 98 * ns87415_set_piomode - Initialize host controller PATA PIO timings 99 * @ap: Port whose timings we are configuring 100 * @adev: Device to program 101 * 102 * Set PIO mode for device, in host controller PCI config space. 103 * 104 * LOCKING: 105 * None (inherited from caller). 106 */ 107 108 static void ns87415_set_piomode(struct ata_port *ap, struct ata_device *adev) 109 { 110 ns87415_set_mode(ap, adev, adev->pio_mode); 111 } 112 113 /** 114 * ns87415_bmdma_setup - Set up DMA 115 * @qc: Command block 116 * 117 * Set up for bus masterng DMA. We have to do this ourselves 118 * rather than use the helper due to a chip erratum 119 */ 120 121 static void ns87415_bmdma_setup(struct ata_queued_cmd *qc) 122 { 123 struct ata_port *ap = qc->ap; 124 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 125 u8 dmactl; 126 127 /* load PRD table addr. */ 128 mb(); /* make sure PRD table writes are visible to controller */ 129 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); 130 131 /* specify data direction, triple-check start bit is clear */ 132 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 133 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); 134 /* Due to an erratum we need to write these bits to the wrong 135 place - which does save us an I/O bizarrely */ 136 dmactl |= ATA_DMA_INTR | ATA_DMA_ERR; 137 if (!rw) 138 dmactl |= ATA_DMA_WR; 139 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 140 /* issue r/w command */ 141 ap->ops->exec_command(ap, &qc->tf); 142 } 143 144 /** 145 * ns87415_bmdma_start - Begin DMA transfer 146 * @qc: Command block 147 * 148 * Switch the timings for the chip and set up for a DMA transfer 149 * before the DMA burst begins. 150 * 151 * FIXME: We should do lazy switching on bmdma_start versus 152 * ata_pio_data_xfer for better performance. 153 */ 154 155 static void ns87415_bmdma_start(struct ata_queued_cmd *qc) 156 { 157 ns87415_set_mode(qc->ap, qc->dev, qc->dev->dma_mode); 158 ata_bmdma_start(qc); 159 } 160 161 /** 162 * ns87415_bmdma_stop - End DMA transfer 163 * @qc: Command block 164 * 165 * End DMA mode and switch the controller back into PIO mode 166 */ 167 168 static void ns87415_bmdma_stop(struct ata_queued_cmd *qc) 169 { 170 ata_bmdma_stop(qc); 171 ns87415_set_mode(qc->ap, qc->dev, qc->dev->pio_mode); 172 } 173 174 /** 175 * ns87415_bmdma_irq_clear - Clear interrupt 176 * @ap: Channel to clear 177 * 178 * Erratum: Due to a chip bug regisers 02 and 0A bit 1 and 2 (the 179 * error bits) are reset by writing to register 00 or 08. 180 */ 181 182 static void ns87415_bmdma_irq_clear(struct ata_port *ap) 183 { 184 void __iomem *mmio = ap->ioaddr.bmdma_addr; 185 186 if (!mmio) 187 return; 188 iowrite8((ioread8(mmio + ATA_DMA_CMD) | ATA_DMA_INTR | ATA_DMA_ERR), 189 mmio + ATA_DMA_CMD); 190 } 191 192 /** 193 * ns87415_check_atapi_dma - ATAPI DMA filter 194 * @qc: Command block 195 * 196 * Disable ATAPI DMA (for now). We may be able to do DMA if we 197 * kill the prefetching. This isn't clear. 198 */ 199 200 static int ns87415_check_atapi_dma(struct ata_queued_cmd *qc) 201 { 202 return -EOPNOTSUPP; 203 } 204 205 #if defined(CONFIG_SUPERIO) 206 207 /* SUPERIO 87560 is a PoS chip that NatSem denies exists. 208 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations 209 * which use the integrated NS87514 cell for CD-ROM support. 210 * i.e we have to support for CD-ROM installs. 211 * See drivers/parisc/superio.c for more gory details. 212 * 213 * Workarounds taken from drivers/ide/pci/ns87415.c 214 */ 215 216 #include <asm/superio.h> 217 218 /** 219 * ns87560_read_buggy - workaround buggy Super I/O chip 220 * @port: Port to read 221 * 222 * Work around chipset problems in the 87560 SuperIO chip 223 */ 224 225 static u8 ns87560_read_buggy(void __iomem *port) 226 { 227 u8 tmp; 228 int retries = SUPERIO_IDE_MAX_RETRIES; 229 do { 230 tmp = ioread8(port); 231 if (tmp != 0) 232 return tmp; 233 udelay(50); 234 } while(retries-- > 0); 235 return tmp; 236 } 237 238 /** 239 * ns87560_check_status 240 * @ap: channel to check 241 * 242 * Return the status of the channel working around the 243 * 87560 flaws. 244 */ 245 246 static u8 ns87560_check_status(struct ata_port *ap) 247 { 248 return ns87560_read_buggy(ap->ioaddr.status_addr); 249 } 250 251 /** 252 * ns87560_tf_read - input device's ATA taskfile shadow registers 253 * @ap: Port from which input is read 254 * @tf: ATA taskfile register set for storing input 255 * 256 * Reads ATA taskfile registers for currently-selected device 257 * into @tf. Work around the 87560 bugs. 258 * 259 * LOCKING: 260 * Inherited from caller. 261 */ 262 void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 263 { 264 struct ata_ioports *ioaddr = &ap->ioaddr; 265 266 tf->command = ns87560_check_status(ap); 267 tf->feature = ioread8(ioaddr->error_addr); 268 tf->nsect = ioread8(ioaddr->nsect_addr); 269 tf->lbal = ioread8(ioaddr->lbal_addr); 270 tf->lbam = ioread8(ioaddr->lbam_addr); 271 tf->lbah = ioread8(ioaddr->lbah_addr); 272 tf->device = ns87560_read_buggy(ioaddr->device_addr); 273 274 if (tf->flags & ATA_TFLAG_LBA48) { 275 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); 276 tf->hob_feature = ioread8(ioaddr->error_addr); 277 tf->hob_nsect = ioread8(ioaddr->nsect_addr); 278 tf->hob_lbal = ioread8(ioaddr->lbal_addr); 279 tf->hob_lbam = ioread8(ioaddr->lbam_addr); 280 tf->hob_lbah = ioread8(ioaddr->lbah_addr); 281 iowrite8(tf->ctl, ioaddr->ctl_addr); 282 ap->last_ctl = tf->ctl; 283 } 284 } 285 286 /** 287 * ns87560_bmdma_status 288 * @ap: channel to check 289 * 290 * Return the DMA status of the channel working around the 291 * 87560 flaws. 292 */ 293 294 static u8 ns87560_bmdma_status(struct ata_port *ap) 295 { 296 return ns87560_read_buggy(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 297 } 298 299 static const struct ata_port_operations ns87560_pata_ops = { 300 .set_piomode = ns87415_set_piomode, 301 .mode_filter = ata_pci_default_filter, 302 303 .tf_load = ata_tf_load, 304 .tf_read = ns87560_tf_read, 305 .check_status = ns87560_check_status, 306 .check_atapi_dma = ns87415_check_atapi_dma, 307 .exec_command = ata_exec_command, 308 .dev_select = ata_std_dev_select, 309 310 .freeze = ata_bmdma_freeze, 311 .thaw = ata_bmdma_thaw, 312 .error_handler = ata_bmdma_error_handler, 313 .post_internal_cmd = ata_bmdma_post_internal_cmd, 314 .cable_detect = ata_cable_40wire, 315 316 .bmdma_setup = ns87415_bmdma_setup, 317 .bmdma_start = ns87415_bmdma_start, 318 .bmdma_stop = ns87415_bmdma_stop, 319 .bmdma_status = ns87560_bmdma_status, 320 .qc_prep = ata_qc_prep, 321 .qc_issue = ata_qc_issue_prot, 322 .data_xfer = ata_data_xfer, 323 324 .irq_handler = ata_interrupt, 325 .irq_clear = ns87415_bmdma_irq_clear, 326 .irq_on = ata_irq_on, 327 328 .port_start = ata_sff_port_start, 329 }; 330 331 #endif /* 87560 SuperIO Support */ 332 333 334 static const struct ata_port_operations ns87415_pata_ops = { 335 .set_piomode = ns87415_set_piomode, 336 .mode_filter = ata_pci_default_filter, 337 338 .tf_load = ata_tf_load, 339 .tf_read = ata_tf_read, 340 .check_status = ata_check_status, 341 .check_atapi_dma = ns87415_check_atapi_dma, 342 .exec_command = ata_exec_command, 343 .dev_select = ata_std_dev_select, 344 345 .freeze = ata_bmdma_freeze, 346 .thaw = ata_bmdma_thaw, 347 .error_handler = ata_bmdma_error_handler, 348 .post_internal_cmd = ata_bmdma_post_internal_cmd, 349 .cable_detect = ata_cable_40wire, 350 351 .bmdma_setup = ns87415_bmdma_setup, 352 .bmdma_start = ns87415_bmdma_start, 353 .bmdma_stop = ns87415_bmdma_stop, 354 .bmdma_status = ata_bmdma_status, 355 .qc_prep = ata_qc_prep, 356 .qc_issue = ata_qc_issue_prot, 357 .data_xfer = ata_data_xfer, 358 359 .irq_handler = ata_interrupt, 360 .irq_clear = ns87415_bmdma_irq_clear, 361 .irq_on = ata_irq_on, 362 363 .port_start = ata_sff_port_start, 364 }; 365 366 static struct scsi_host_template ns87415_sht = { 367 .module = THIS_MODULE, 368 .name = DRV_NAME, 369 .ioctl = ata_scsi_ioctl, 370 .queuecommand = ata_scsi_queuecmd, 371 .can_queue = ATA_DEF_QUEUE, 372 .this_id = ATA_SHT_THIS_ID, 373 .sg_tablesize = LIBATA_MAX_PRD, 374 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 375 .emulated = ATA_SHT_EMULATED, 376 .use_clustering = ATA_SHT_USE_CLUSTERING, 377 .proc_name = DRV_NAME, 378 .dma_boundary = ATA_DMA_BOUNDARY, 379 .slave_configure = ata_scsi_slave_config, 380 .slave_destroy = ata_scsi_slave_destroy, 381 .bios_param = ata_std_bios_param, 382 }; 383 384 385 /** 386 * ns87415_init_one - Register 87415 ATA PCI device with kernel services 387 * @pdev: PCI device to register 388 * @ent: Entry in ns87415_pci_tbl matching with @pdev 389 * 390 * Called from kernel PCI layer. We probe for combined mode (sigh), 391 * and then hand over control to libata, for it to do the rest. 392 * 393 * LOCKING: 394 * Inherited from PCI layer (may sleep). 395 * 396 * RETURNS: 397 * Zero on success, or -ERRNO value. 398 */ 399 400 static int ns87415_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 401 { 402 static int printed_version; 403 static const struct ata_port_info info = { 404 .sht = &ns87415_sht, 405 .flags = ATA_FLAG_SLAVE_POSS, 406 .pio_mask = 0x1f, /* pio0-4 */ 407 .mwdma_mask = 0x07, /* mwdma0-2 */ 408 .port_ops = &ns87415_pata_ops, 409 }; 410 const struct ata_port_info *ppi[] = { &info, NULL }; 411 #if defined(CONFIG_SUPERIO) 412 static const struct ata_port_info info87560 = { 413 .sht = &ns87415_sht, 414 .flags = ATA_FLAG_SLAVE_POSS, 415 .pio_mask = 0x1f, /* pio0-4 */ 416 .mwdma_mask = 0x07, /* mwdma0-2 */ 417 .port_ops = &ns87560_pata_ops, 418 }; 419 420 if (PCI_SLOT(pdev->devfn) == 0x0E) 421 ppi[0] = &info87560; 422 #endif 423 if (!printed_version++) 424 dev_printk(KERN_DEBUG, &pdev->dev, 425 "version " DRV_VERSION "\n"); 426 /* Select 512 byte sectors */ 427 pci_write_config_byte(pdev, 0x55, 0xEE); 428 /* Select PIO0 8bit clocking */ 429 pci_write_config_byte(pdev, 0x54, 0xB7); 430 return ata_pci_init_one(pdev, ppi); 431 } 432 433 static const struct pci_device_id ns87415_pci_tbl[] = { 434 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), }, 435 436 { } /* terminate list */ 437 }; 438 439 static struct pci_driver ns87415_pci_driver = { 440 .name = DRV_NAME, 441 .id_table = ns87415_pci_tbl, 442 .probe = ns87415_init_one, 443 .remove = ata_pci_remove_one, 444 #ifdef CONFIG_PM 445 .suspend = ata_pci_device_suspend, 446 .resume = ata_pci_device_resume, 447 #endif 448 }; 449 450 static int __init ns87415_init(void) 451 { 452 return pci_register_driver(&ns87415_pci_driver); 453 } 454 455 static void __exit ns87415_exit(void) 456 { 457 pci_unregister_driver(&ns87415_pci_driver); 458 } 459 460 module_init(ns87415_init); 461 module_exit(ns87415_exit); 462 463 MODULE_AUTHOR("Alan Cox"); 464 MODULE_DESCRIPTION("ATA low-level driver for NS87415 controllers"); 465 MODULE_LICENSE("GPL"); 466 MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl); 467 MODULE_VERSION(DRV_VERSION); 468