1 /* 2 * pata-legacy.c - Legacy port PATA/SATA controller driver. 3 * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2, or (at your option) 8 * any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; see the file COPYING. If not, write to 17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * An ATA driver for the legacy ATA ports. 20 * 21 * Data Sources: 22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com 23 * HT6560 series: 24 * Promise 20230/20620: 25 * http://www.ryston.cz/petr/vlb/pdc20230b.html 26 * http://www.ryston.cz/petr/vlb/pdc20230c.html 27 * http://www.ryston.cz/petr/vlb/pdc20630.html 28 * 29 * Unsupported but docs exist: 30 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 31 * Winbond W83759A 32 * 33 * This driver handles legacy (that is "ISA/VLB side") IDE ports found 34 * on PC class systems. There are three hybrid devices that are exceptions 35 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and 36 * the MPIIX where the tuning is PCI side but the IDE is "ISA side". 37 * 38 * Specific support is included for the ht6560a/ht6560b/opti82c611a/ 39 * opti82c465mv/promise 20230c/20630 40 * 41 * Use the autospeed and pio_mask options with: 42 * Appian ADI/2 aka CLPD7220 or AIC25VL01. 43 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with 44 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, 45 * Winbond W83759A, Promise PDC20230-B 46 * 47 * For now use autospeed and pio_mask as above with the W83759A. This may 48 * change. 49 * 50 * TODO 51 * Merge existing pata_qdi driver 52 * 53 */ 54 55 #include <linux/kernel.h> 56 #include <linux/module.h> 57 #include <linux/pci.h> 58 #include <linux/init.h> 59 #include <linux/blkdev.h> 60 #include <linux/delay.h> 61 #include <scsi/scsi_host.h> 62 #include <linux/ata.h> 63 #include <linux/libata.h> 64 #include <linux/platform_device.h> 65 66 #define DRV_NAME "pata_legacy" 67 #define DRV_VERSION "0.5.5" 68 69 #define NR_HOST 6 70 71 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; 72 static int legacy_irq[NR_HOST] = { 14, 15, 11, 10, 8, 12 }; 73 74 struct legacy_data { 75 unsigned long timing; 76 u8 clock[2]; 77 u8 last; 78 int fast; 79 struct platform_device *platform_dev; 80 81 }; 82 83 static struct legacy_data legacy_data[NR_HOST]; 84 static struct ata_host *legacy_host[NR_HOST]; 85 static int nr_legacy_host; 86 87 88 static int probe_all; /* Set to check all ISA port ranges */ 89 static int ht6560a; /* HT 6560A on primary 1, secondary 2, both 3 */ 90 static int ht6560b; /* HT 6560A on primary 1, secondary 2, both 3 */ 91 static int opti82c611a; /* Opti82c611A on primary 1, secondary 2, both 3 */ 92 static int opti82c46x; /* Opti 82c465MV present (pri/sec autodetect) */ 93 static int autospeed; /* Chip present which snoops speed changes */ 94 static int pio_mask = 0x1F; /* PIO range for autospeed devices */ 95 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ 96 97 /** 98 * legacy_set_mode - mode setting 99 * @link: IDE link 100 * @unused: Device that failed when error is returned 101 * 102 * Use a non standard set_mode function. We don't want to be tuned. 103 * 104 * The BIOS configured everything. Our job is not to fiddle. Just use 105 * whatever PIO the hardware is using and leave it at that. When we 106 * get some kind of nice user driven API for control then we can 107 * expand on this as per hdparm in the base kernel. 108 */ 109 110 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) 111 { 112 struct ata_device *dev; 113 114 ata_link_for_each_dev(dev, link) { 115 if (ata_dev_enabled(dev)) { 116 ata_dev_printk(dev, KERN_INFO, "configured for PIO\n"); 117 dev->pio_mode = XFER_PIO_0; 118 dev->xfer_mode = XFER_PIO_0; 119 dev->xfer_shift = ATA_SHIFT_PIO; 120 dev->flags |= ATA_DFLAG_PIO; 121 } 122 } 123 return 0; 124 } 125 126 static struct scsi_host_template legacy_sht = { 127 .module = THIS_MODULE, 128 .name = DRV_NAME, 129 .ioctl = ata_scsi_ioctl, 130 .queuecommand = ata_scsi_queuecmd, 131 .can_queue = ATA_DEF_QUEUE, 132 .this_id = ATA_SHT_THIS_ID, 133 .sg_tablesize = LIBATA_MAX_PRD, 134 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 135 .emulated = ATA_SHT_EMULATED, 136 .use_clustering = ATA_SHT_USE_CLUSTERING, 137 .proc_name = DRV_NAME, 138 .dma_boundary = ATA_DMA_BOUNDARY, 139 .slave_configure = ata_scsi_slave_config, 140 .slave_destroy = ata_scsi_slave_destroy, 141 .bios_param = ata_std_bios_param, 142 }; 143 144 /* 145 * These ops are used if the user indicates the hardware 146 * snoops the commands to decide on the mode and handles the 147 * mode selection "magically" itself. Several legacy controllers 148 * do this. The mode range can be set if it is not 0x1F by setting 149 * pio_mask as well. 150 */ 151 152 static struct ata_port_operations simple_port_ops = { 153 .tf_load = ata_tf_load, 154 .tf_read = ata_tf_read, 155 .check_status = ata_check_status, 156 .exec_command = ata_exec_command, 157 .dev_select = ata_std_dev_select, 158 159 .freeze = ata_bmdma_freeze, 160 .thaw = ata_bmdma_thaw, 161 .error_handler = ata_bmdma_error_handler, 162 .post_internal_cmd = ata_bmdma_post_internal_cmd, 163 .cable_detect = ata_cable_40wire, 164 165 .qc_prep = ata_qc_prep, 166 .qc_issue = ata_qc_issue_prot, 167 168 .data_xfer = ata_data_xfer_noirq, 169 170 .irq_handler = ata_interrupt, 171 .irq_clear = ata_bmdma_irq_clear, 172 .irq_on = ata_irq_on, 173 174 .port_start = ata_port_start, 175 }; 176 177 static struct ata_port_operations legacy_port_ops = { 178 .set_mode = legacy_set_mode, 179 180 .tf_load = ata_tf_load, 181 .tf_read = ata_tf_read, 182 .check_status = ata_check_status, 183 .exec_command = ata_exec_command, 184 .dev_select = ata_std_dev_select, 185 .cable_detect = ata_cable_40wire, 186 187 .freeze = ata_bmdma_freeze, 188 .thaw = ata_bmdma_thaw, 189 .error_handler = ata_bmdma_error_handler, 190 .post_internal_cmd = ata_bmdma_post_internal_cmd, 191 192 .qc_prep = ata_qc_prep, 193 .qc_issue = ata_qc_issue_prot, 194 195 .data_xfer = ata_data_xfer_noirq, 196 197 .irq_handler = ata_interrupt, 198 .irq_clear = ata_bmdma_irq_clear, 199 .irq_on = ata_irq_on, 200 201 .port_start = ata_port_start, 202 }; 203 204 /* 205 * Promise 20230C and 20620 support 206 * 207 * This controller supports PIO0 to PIO2. We set PIO timings conservatively to 208 * allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to 209 * controller and PIO'd to the host and not supported. 210 */ 211 212 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) 213 { 214 int tries = 5; 215 int pio = adev->pio_mode - XFER_PIO_0; 216 u8 rt; 217 unsigned long flags; 218 219 /* Safe as UP only. Force I/Os to occur together */ 220 221 local_irq_save(flags); 222 223 /* Unlock the control interface */ 224 do 225 { 226 inb(0x1F5); 227 outb(inb(0x1F2) | 0x80, 0x1F2); 228 inb(0x1F2); 229 inb(0x3F6); 230 inb(0x3F6); 231 inb(0x1F2); 232 inb(0x1F2); 233 } 234 while((inb(0x1F2) & 0x80) && --tries); 235 236 local_irq_restore(flags); 237 238 outb(inb(0x1F4) & 0x07, 0x1F4); 239 240 rt = inb(0x1F3); 241 rt &= 0x07 << (3 * adev->devno); 242 if (pio) 243 rt |= (1 + 3 * pio) << (3 * adev->devno); 244 245 udelay(100); 246 outb(inb(0x1F2) | 0x01, 0x1F2); 247 udelay(100); 248 inb(0x1F5); 249 250 } 251 252 static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data) 253 { 254 struct ata_port *ap = adev->link->ap; 255 int slop = buflen & 3; 256 unsigned long flags; 257 258 if (ata_id_has_dword_io(adev->id)) { 259 local_irq_save(flags); 260 261 /* Perform the 32bit I/O synchronization sequence */ 262 ioread8(ap->ioaddr.nsect_addr); 263 ioread8(ap->ioaddr.nsect_addr); 264 ioread8(ap->ioaddr.nsect_addr); 265 266 /* Now the data */ 267 268 if (write_data) 269 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 270 else 271 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 272 273 if (unlikely(slop)) { 274 u32 pad; 275 if (write_data) { 276 memcpy(&pad, buf + buflen - slop, slop); 277 pad = le32_to_cpu(pad); 278 iowrite32(pad, ap->ioaddr.data_addr); 279 } else { 280 pad = ioread32(ap->ioaddr.data_addr); 281 pad = cpu_to_le16(pad); 282 memcpy(buf + buflen - slop, &pad, slop); 283 } 284 } 285 local_irq_restore(flags); 286 } 287 else 288 ata_data_xfer_noirq(adev, buf, buflen, write_data); 289 } 290 291 static struct ata_port_operations pdc20230_port_ops = { 292 .set_piomode = pdc20230_set_piomode, 293 294 .tf_load = ata_tf_load, 295 .tf_read = ata_tf_read, 296 .check_status = ata_check_status, 297 .exec_command = ata_exec_command, 298 .dev_select = ata_std_dev_select, 299 300 .freeze = ata_bmdma_freeze, 301 .thaw = ata_bmdma_thaw, 302 .error_handler = ata_bmdma_error_handler, 303 .post_internal_cmd = ata_bmdma_post_internal_cmd, 304 .cable_detect = ata_cable_40wire, 305 306 .qc_prep = ata_qc_prep, 307 .qc_issue = ata_qc_issue_prot, 308 309 .data_xfer = pdc_data_xfer_vlb, 310 311 .irq_handler = ata_interrupt, 312 .irq_clear = ata_bmdma_irq_clear, 313 .irq_on = ata_irq_on, 314 315 .port_start = ata_port_start, 316 }; 317 318 /* 319 * Holtek 6560A support 320 * 321 * This controller supports PIO0 to PIO2 (no IORDY even though higher timings 322 * can be loaded). 323 */ 324 325 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) 326 { 327 u8 active, recover; 328 struct ata_timing t; 329 330 /* Get the timing data in cycles. For now play safe at 50Mhz */ 331 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 332 333 active = FIT(t.active, 2, 15); 334 recover = FIT(t.recover, 4, 15); 335 336 inb(0x3E6); 337 inb(0x3E6); 338 inb(0x3E6); 339 inb(0x3E6); 340 341 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 342 ioread8(ap->ioaddr.status_addr); 343 } 344 345 static struct ata_port_operations ht6560a_port_ops = { 346 .set_piomode = ht6560a_set_piomode, 347 348 .tf_load = ata_tf_load, 349 .tf_read = ata_tf_read, 350 .check_status = ata_check_status, 351 .exec_command = ata_exec_command, 352 .dev_select = ata_std_dev_select, 353 354 .freeze = ata_bmdma_freeze, 355 .thaw = ata_bmdma_thaw, 356 .error_handler = ata_bmdma_error_handler, 357 .post_internal_cmd = ata_bmdma_post_internal_cmd, 358 .cable_detect = ata_cable_40wire, 359 360 .qc_prep = ata_qc_prep, 361 .qc_issue = ata_qc_issue_prot, 362 363 .data_xfer = ata_data_xfer, /* Check vlb/noirq */ 364 365 .irq_handler = ata_interrupt, 366 .irq_clear = ata_bmdma_irq_clear, 367 .irq_on = ata_irq_on, 368 369 .port_start = ata_port_start, 370 }; 371 372 /* 373 * Holtek 6560B support 374 * 375 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO setting 376 * unless we see an ATAPI device in which case we force it off. 377 * 378 * FIXME: need to implement 2nd channel support. 379 */ 380 381 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) 382 { 383 u8 active, recover; 384 struct ata_timing t; 385 386 /* Get the timing data in cycles. For now play safe at 50Mhz */ 387 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 388 389 active = FIT(t.active, 2, 15); 390 recover = FIT(t.recover, 2, 16); 391 recover &= 0x15; 392 393 inb(0x3E6); 394 inb(0x3E6); 395 inb(0x3E6); 396 inb(0x3E6); 397 398 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 399 400 if (adev->class != ATA_DEV_ATA) { 401 u8 rconf = inb(0x3E6); 402 if (rconf & 0x24) { 403 rconf &= ~ 0x24; 404 outb(rconf, 0x3E6); 405 } 406 } 407 ioread8(ap->ioaddr.status_addr); 408 } 409 410 static struct ata_port_operations ht6560b_port_ops = { 411 .set_piomode = ht6560b_set_piomode, 412 413 .tf_load = ata_tf_load, 414 .tf_read = ata_tf_read, 415 .check_status = ata_check_status, 416 .exec_command = ata_exec_command, 417 .dev_select = ata_std_dev_select, 418 419 .freeze = ata_bmdma_freeze, 420 .thaw = ata_bmdma_thaw, 421 .error_handler = ata_bmdma_error_handler, 422 .post_internal_cmd = ata_bmdma_post_internal_cmd, 423 .cable_detect = ata_cable_40wire, 424 425 .qc_prep = ata_qc_prep, 426 .qc_issue = ata_qc_issue_prot, 427 428 .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */ 429 430 .irq_handler = ata_interrupt, 431 .irq_clear = ata_bmdma_irq_clear, 432 .irq_on = ata_irq_on, 433 434 .port_start = ata_port_start, 435 }; 436 437 /* 438 * Opti core chipset helpers 439 */ 440 441 /** 442 * opti_syscfg - read OPTI chipset configuration 443 * @reg: Configuration register to read 444 * 445 * Returns the value of an OPTI system board configuration register. 446 */ 447 448 static u8 opti_syscfg(u8 reg) 449 { 450 unsigned long flags; 451 u8 r; 452 453 /* Uniprocessor chipset and must force cycles adjancent */ 454 local_irq_save(flags); 455 outb(reg, 0x22); 456 r = inb(0x24); 457 local_irq_restore(flags); 458 return r; 459 } 460 461 /* 462 * Opti 82C611A 463 * 464 * This controller supports PIO0 to PIO3. 465 */ 466 467 static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev) 468 { 469 u8 active, recover, setup; 470 struct ata_timing t; 471 struct ata_device *pair = ata_dev_pair(adev); 472 int clock; 473 int khz[4] = { 50000, 40000, 33000, 25000 }; 474 u8 rc; 475 476 /* Enter configuration mode */ 477 ioread16(ap->ioaddr.error_addr); 478 ioread16(ap->ioaddr.error_addr); 479 iowrite8(3, ap->ioaddr.nsect_addr); 480 481 /* Read VLB clock strapping */ 482 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; 483 484 /* Get the timing data in cycles */ 485 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 486 487 /* Setup timing is shared */ 488 if (pair) { 489 struct ata_timing tp; 490 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 491 492 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 493 } 494 495 active = FIT(t.active, 2, 17) - 2; 496 recover = FIT(t.recover, 1, 16) - 1; 497 setup = FIT(t.setup, 1, 4) - 1; 498 499 /* Select the right timing bank for write timing */ 500 rc = ioread8(ap->ioaddr.lbal_addr); 501 rc &= 0x7F; 502 rc |= (adev->devno << 7); 503 iowrite8(rc, ap->ioaddr.lbal_addr); 504 505 /* Write the timings */ 506 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 507 508 /* Select the right bank for read timings, also 509 load the shared timings for address */ 510 rc = ioread8(ap->ioaddr.device_addr); 511 rc &= 0xC0; 512 rc |= adev->devno; /* Index select */ 513 rc |= (setup << 4) | 0x04; 514 iowrite8(rc, ap->ioaddr.device_addr); 515 516 /* Load the read timings */ 517 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 518 519 /* Ensure the timing register mode is right */ 520 rc = ioread8(ap->ioaddr.lbal_addr); 521 rc &= 0x73; 522 rc |= 0x84; 523 iowrite8(rc, ap->ioaddr.lbal_addr); 524 525 /* Exit command mode */ 526 iowrite8(0x83, ap->ioaddr.nsect_addr); 527 } 528 529 530 static struct ata_port_operations opti82c611a_port_ops = { 531 .set_piomode = opti82c611a_set_piomode, 532 533 .tf_load = ata_tf_load, 534 .tf_read = ata_tf_read, 535 .check_status = ata_check_status, 536 .exec_command = ata_exec_command, 537 .dev_select = ata_std_dev_select, 538 539 .freeze = ata_bmdma_freeze, 540 .thaw = ata_bmdma_thaw, 541 .error_handler = ata_bmdma_error_handler, 542 .post_internal_cmd = ata_bmdma_post_internal_cmd, 543 .cable_detect = ata_cable_40wire, 544 545 .qc_prep = ata_qc_prep, 546 .qc_issue = ata_qc_issue_prot, 547 548 .data_xfer = ata_data_xfer, 549 550 .irq_handler = ata_interrupt, 551 .irq_clear = ata_bmdma_irq_clear, 552 .irq_on = ata_irq_on, 553 554 .port_start = ata_port_start, 555 }; 556 557 /* 558 * Opti 82C465MV 559 * 560 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB 561 * version is dual channel but doesn't have a lot of unique registers. 562 */ 563 564 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) 565 { 566 u8 active, recover, setup; 567 struct ata_timing t; 568 struct ata_device *pair = ata_dev_pair(adev); 569 int clock; 570 int khz[4] = { 50000, 40000, 33000, 25000 }; 571 u8 rc; 572 u8 sysclk; 573 574 /* Get the clock */ 575 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ 576 577 /* Enter configuration mode */ 578 ioread16(ap->ioaddr.error_addr); 579 ioread16(ap->ioaddr.error_addr); 580 iowrite8(3, ap->ioaddr.nsect_addr); 581 582 /* Read VLB clock strapping */ 583 clock = 1000000000 / khz[sysclk]; 584 585 /* Get the timing data in cycles */ 586 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 587 588 /* Setup timing is shared */ 589 if (pair) { 590 struct ata_timing tp; 591 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 592 593 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 594 } 595 596 active = FIT(t.active, 2, 17) - 2; 597 recover = FIT(t.recover, 1, 16) - 1; 598 setup = FIT(t.setup, 1, 4) - 1; 599 600 /* Select the right timing bank for write timing */ 601 rc = ioread8(ap->ioaddr.lbal_addr); 602 rc &= 0x7F; 603 rc |= (adev->devno << 7); 604 iowrite8(rc, ap->ioaddr.lbal_addr); 605 606 /* Write the timings */ 607 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 608 609 /* Select the right bank for read timings, also 610 load the shared timings for address */ 611 rc = ioread8(ap->ioaddr.device_addr); 612 rc &= 0xC0; 613 rc |= adev->devno; /* Index select */ 614 rc |= (setup << 4) | 0x04; 615 iowrite8(rc, ap->ioaddr.device_addr); 616 617 /* Load the read timings */ 618 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 619 620 /* Ensure the timing register mode is right */ 621 rc = ioread8(ap->ioaddr.lbal_addr); 622 rc &= 0x73; 623 rc |= 0x84; 624 iowrite8(rc, ap->ioaddr.lbal_addr); 625 626 /* Exit command mode */ 627 iowrite8(0x83, ap->ioaddr.nsect_addr); 628 629 /* We need to know this for quad device on the MVB */ 630 ap->host->private_data = ap; 631 } 632 633 /** 634 * opt82c465mv_qc_issue_prot - command issue 635 * @qc: command pending 636 * 637 * Called when the libata layer is about to issue a command. We wrap 638 * this interface so that we can load the correct ATA timings. The 639 * MVB has a single set of timing registers and these are shared 640 * across channels. As there are two registers we really ought to 641 * track the last two used values as a sort of register window. For 642 * now we just reload on a channel switch. On the single channel 643 * setup this condition never fires so we do nothing extra. 644 * 645 * FIXME: dual channel needs ->serialize support 646 */ 647 648 static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc) 649 { 650 struct ata_port *ap = qc->ap; 651 struct ata_device *adev = qc->dev; 652 653 /* If timings are set and for the wrong channel (2nd test is 654 due to a libata shortcoming and will eventually go I hope) */ 655 if (ap->host->private_data != ap->host 656 && ap->host->private_data != NULL) 657 opti82c46x_set_piomode(ap, adev); 658 659 return ata_qc_issue_prot(qc); 660 } 661 662 static struct ata_port_operations opti82c46x_port_ops = { 663 .set_piomode = opti82c46x_set_piomode, 664 665 .tf_load = ata_tf_load, 666 .tf_read = ata_tf_read, 667 .check_status = ata_check_status, 668 .exec_command = ata_exec_command, 669 .dev_select = ata_std_dev_select, 670 671 .freeze = ata_bmdma_freeze, 672 .thaw = ata_bmdma_thaw, 673 .error_handler = ata_bmdma_error_handler, 674 .post_internal_cmd = ata_bmdma_post_internal_cmd, 675 .cable_detect = ata_cable_40wire, 676 677 .qc_prep = ata_qc_prep, 678 .qc_issue = opti82c46x_qc_issue_prot, 679 680 .data_xfer = ata_data_xfer, 681 682 .irq_handler = ata_interrupt, 683 .irq_clear = ata_bmdma_irq_clear, 684 .irq_on = ata_irq_on, 685 686 .port_start = ata_port_start, 687 }; 688 689 690 /** 691 * legacy_init_one - attach a legacy interface 692 * @port: port number 693 * @io: I/O port start 694 * @ctrl: control port 695 * @irq: interrupt line 696 * 697 * Register an ISA bus IDE interface. Such interfaces are PIO and we 698 * assume do not support IRQ sharing. 699 */ 700 701 static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq) 702 { 703 struct legacy_data *ld = &legacy_data[nr_legacy_host]; 704 struct ata_host *host; 705 struct ata_port *ap; 706 struct platform_device *pdev; 707 struct ata_port_operations *ops = &legacy_port_ops; 708 void __iomem *io_addr, *ctrl_addr; 709 int pio_modes = pio_mask; 710 u32 mask = (1 << port); 711 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; 712 int ret; 713 714 pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0); 715 if (IS_ERR(pdev)) 716 return PTR_ERR(pdev); 717 718 ret = -EBUSY; 719 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || 720 devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL) 721 goto fail; 722 723 ret = -ENOMEM; 724 io_addr = devm_ioport_map(&pdev->dev, io, 8); 725 ctrl_addr = devm_ioport_map(&pdev->dev, ctrl, 1); 726 if (!io_addr || !ctrl_addr) 727 goto fail; 728 729 if (ht6560a & mask) { 730 ops = &ht6560a_port_ops; 731 pio_modes = 0x07; 732 iordy = ATA_FLAG_NO_IORDY; 733 } 734 if (ht6560b & mask) { 735 ops = &ht6560b_port_ops; 736 pio_modes = 0x1F; 737 } 738 if (opti82c611a & mask) { 739 ops = &opti82c611a_port_ops; 740 pio_modes = 0x0F; 741 } 742 if (opti82c46x & mask) { 743 ops = &opti82c46x_port_ops; 744 pio_modes = 0x0F; 745 } 746 747 /* Probe for automatically detectable controllers */ 748 749 if (io == 0x1F0 && ops == &legacy_port_ops) { 750 unsigned long flags; 751 752 local_irq_save(flags); 753 754 /* Probes */ 755 inb(0x1F5); 756 outb(inb(0x1F2) | 0x80, 0x1F2); 757 inb(0x1F2); 758 inb(0x3F6); 759 inb(0x3F6); 760 inb(0x1F2); 761 inb(0x1F2); 762 763 if ((inb(0x1F2) & 0x80) == 0) { 764 /* PDC20230c or 20630 ? */ 765 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n"); 766 pio_modes = 0x07; 767 ops = &pdc20230_port_ops; 768 iordy = ATA_FLAG_NO_IORDY; 769 udelay(100); 770 inb(0x1F5); 771 } else { 772 outb(0x55, 0x1F2); 773 inb(0x1F2); 774 inb(0x1F2); 775 if (inb(0x1F2) == 0x00) { 776 printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n"); 777 } 778 } 779 local_irq_restore(flags); 780 } 781 782 783 /* Chip does mode setting by command snooping */ 784 if (ops == &legacy_port_ops && (autospeed & mask)) 785 ops = &simple_port_ops; 786 787 ret = -ENOMEM; 788 host = ata_host_alloc(&pdev->dev, 1); 789 if (!host) 790 goto fail; 791 ap = host->ports[0]; 792 793 ap->ops = ops; 794 ap->pio_mask = pio_modes; 795 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; 796 ap->ioaddr.cmd_addr = io_addr; 797 ap->ioaddr.altstatus_addr = ctrl_addr; 798 ap->ioaddr.ctl_addr = ctrl_addr; 799 ata_std_ports(&ap->ioaddr); 800 ap->private_data = ld; 801 802 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, ctrl); 803 804 ret = ata_host_activate(host, irq, ata_interrupt, 0, &legacy_sht); 805 if (ret) 806 goto fail; 807 808 legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev); 809 ld->platform_dev = pdev; 810 return 0; 811 812 fail: 813 platform_device_unregister(pdev); 814 return ret; 815 } 816 817 /** 818 * legacy_check_special_cases - ATA special cases 819 * @p: PCI device to check 820 * @master: set this if we find an ATA master 821 * @master: set this if we find an ATA secondary 822 * 823 * A small number of vendors implemented early PCI ATA interfaces on bridge logic 824 * without the ATA interface being PCI visible. Where we have a matching PCI driver 825 * we must skip the relevant device here. If we don't know about it then the legacy 826 * driver is the right driver anyway. 827 */ 828 829 static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary) 830 { 831 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ 832 if (p->vendor == 0x1078 && p->device == 0x0000) { 833 *primary = *secondary = 1; 834 return; 835 } 836 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ 837 if (p->vendor == 0x1078 && p->device == 0x0002) { 838 *primary = *secondary = 1; 839 return; 840 } 841 /* Intel MPIIX - PIO ATA on non PCI side of bridge */ 842 if (p->vendor == 0x8086 && p->device == 0x1234) { 843 u16 r; 844 pci_read_config_word(p, 0x6C, &r); 845 if (r & 0x8000) { /* ATA port enabled */ 846 if (r & 0x4000) 847 *secondary = 1; 848 else 849 *primary = 1; 850 } 851 return; 852 } 853 } 854 855 856 /** 857 * legacy_init - attach legacy interfaces 858 * 859 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. 860 * Right now we do not scan the ide0 and ide1 address but should do so 861 * for non PCI systems or systems with no PCI IDE legacy mode devices. 862 * If you fix that note there are special cases to consider like VLB 863 * drivers and CS5510/20. 864 */ 865 866 static __init int legacy_init(void) 867 { 868 int i; 869 int ct = 0; 870 int primary = 0; 871 int secondary = 0; 872 int last_port = NR_HOST; 873 874 struct pci_dev *p = NULL; 875 876 for_each_pci_dev(p) { 877 int r; 878 /* Check for any overlap of the system ATA mappings. Native mode controllers 879 stuck on these addresses or some devices in 'raid' mode won't be found by 880 the storage class test */ 881 for (r = 0; r < 6; r++) { 882 if (pci_resource_start(p, r) == 0x1f0) 883 primary = 1; 884 if (pci_resource_start(p, r) == 0x170) 885 secondary = 1; 886 } 887 /* Check for special cases */ 888 legacy_check_special_cases(p, &primary, &secondary); 889 890 /* If PCI bus is present then don't probe for tertiary legacy ports */ 891 if (probe_all == 0) 892 last_port = 2; 893 } 894 895 /* If an OPTI 82C46X is present find out where the channels are */ 896 if (opti82c46x) { 897 static const char *optis[4] = { 898 "3/463MV", "5MV", 899 "5MVA", "5MVB" 900 }; 901 u8 chans = 1; 902 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; 903 904 opti82c46x = 3; /* Assume master and slave first */ 905 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]); 906 if (ctrl == 3) 907 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; 908 ctrl = opti_syscfg(0xAC); 909 /* Check enabled and this port is the 465MV port. On the 910 MVB we may have two channels */ 911 if (ctrl & 8) { 912 if (ctrl & 4) 913 opti82c46x = 2; /* Slave */ 914 else 915 opti82c46x = 1; /* Master */ 916 if (chans == 2) 917 opti82c46x = 3; /* Master and Slave */ 918 } /* Slave only */ 919 else if (chans == 1) 920 opti82c46x = 1; 921 } 922 923 for (i = 0; i < last_port; i++) { 924 /* Skip primary if we have seen a PCI one */ 925 if (i == 0 && primary == 1) 926 continue; 927 /* Skip secondary if we have seen a PCI one */ 928 if (i == 1 && secondary == 1) 929 continue; 930 if (legacy_init_one(i, legacy_port[i], 931 legacy_port[i] + 0x0206, 932 legacy_irq[i]) == 0) 933 ct++; 934 } 935 if (ct != 0) 936 return 0; 937 return -ENODEV; 938 } 939 940 static __exit void legacy_exit(void) 941 { 942 int i; 943 944 for (i = 0; i < nr_legacy_host; i++) { 945 struct legacy_data *ld = &legacy_data[i]; 946 947 ata_host_detach(legacy_host[i]); 948 platform_device_unregister(ld->platform_dev); 949 if (ld->timing) 950 release_region(ld->timing, 2); 951 } 952 } 953 954 MODULE_AUTHOR("Alan Cox"); 955 MODULE_DESCRIPTION("low-level driver for legacy ATA"); 956 MODULE_LICENSE("GPL"); 957 MODULE_VERSION(DRV_VERSION); 958 959 module_param(probe_all, int, 0); 960 module_param(autospeed, int, 0); 961 module_param(ht6560a, int, 0); 962 module_param(ht6560b, int, 0); 963 module_param(opti82c611a, int, 0); 964 module_param(opti82c46x, int, 0); 965 module_param(pio_mask, int, 0); 966 module_param(iordy_mask, int, 0); 967 968 module_init(legacy_init); 969 module_exit(legacy_exit); 970 971