1 /* 2 * ata-it821x.c - IT821x PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * based upon 7 * 8 * it821x.c 9 * 10 * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004 11 * 12 * Copyright (C) 2004 Red Hat <alan@redhat.com> 13 * 14 * May be copied or modified under the terms of the GNU General Public License 15 * Based in part on the ITE vendor provided SCSI driver. 16 * 17 * Documentation available from 18 * http://www.ite.com.tw/pc/IT8212F_V04.pdf 19 * Some other documents are NDA. 20 * 21 * The ITE8212 isn't exactly a standard IDE controller. It has two 22 * modes. In pass through mode then it is an IDE controller. In its smart 23 * mode its actually quite a capable hardware raid controller disguised 24 * as an IDE controller. Smart mode only understands DMA read/write and 25 * identify, none of the fancier commands apply. The IT8211 is identical 26 * in other respects but lacks the raid mode. 27 * 28 * Errata: 29 * o Rev 0x10 also requires master/slave hold the same DMA timings and 30 * cannot do ATAPI MWDMA. 31 * o The identify data for raid volumes lacks CHS info (technically ok) 32 * but also fails to set the LBA28 and other bits. We fix these in 33 * the IDE probe quirk code. 34 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode 35 * raid then the controller firmware dies 36 * o Smart mode without RAID doesn't clear all the necessary identify 37 * bits to reduce the command set to the one used 38 * 39 * This has a few impacts on the driver 40 * - In pass through mode we do all the work you would expect 41 * - In smart mode the clocking set up is done by the controller generally 42 * but we must watch the other limits and filter. 43 * - There are a few extra vendor commands that actually talk to the 44 * controller but only work PIO with no IRQ. 45 * 46 * Vendor areas of the identify block in smart mode are used for the 47 * timing and policy set up. Each HDD in raid mode also has a serial 48 * block on the disk. The hardware extra commands are get/set chip status, 49 * rebuild, get rebuild status. 50 * 51 * In Linux the driver supports pass through mode as if the device was 52 * just another IDE controller. If the smart mode is running then 53 * volumes are managed by the controller firmware and each IDE "disk" 54 * is a raid volume. Even more cute - the controller can do automated 55 * hotplug and rebuild. 56 * 57 * The pass through controller itself is a little demented. It has a 58 * flaw that it has a single set of PIO/MWDMA timings per channel so 59 * non UDMA devices restrict each others performance. It also has a 60 * single clock source per channel so mixed UDMA100/133 performance 61 * isn't perfect and we have to pick a clock. Thankfully none of this 62 * matters in smart mode. ATAPI DMA is not currently supported. 63 * 64 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not. 65 * 66 * TODO 67 * - ATAPI and other speed filtering 68 * - Command filter in smart mode 69 * - RAID configuration ioctls 70 */ 71 72 #include <linux/kernel.h> 73 #include <linux/module.h> 74 #include <linux/pci.h> 75 #include <linux/init.h> 76 #include <linux/blkdev.h> 77 #include <linux/delay.h> 78 #include <scsi/scsi_host.h> 79 #include <linux/libata.h> 80 81 82 #define DRV_NAME "pata_it821x" 83 #define DRV_VERSION "0.3.4" 84 85 struct it821x_dev 86 { 87 unsigned int smart:1, /* Are we in smart raid mode */ 88 timing10:1; /* Rev 0x10 */ 89 u8 clock_mode; /* 0, ATA_50 or ATA_66 */ 90 u8 want[2][2]; /* Mode/Pri log for master slave */ 91 /* We need these for switching the clock when DMA goes on/off 92 The high byte is the 66Mhz timing */ 93 u16 pio[2]; /* Cached PIO values */ 94 u16 mwdma[2]; /* Cached MWDMA values */ 95 u16 udma[2]; /* Cached UDMA values (per drive) */ 96 u16 last_device; /* Master or slave loaded ? */ 97 }; 98 99 #define ATA_66 0 100 #define ATA_50 1 101 #define ATA_ANY 2 102 103 #define UDMA_OFF 0 104 #define MWDMA_OFF 0 105 106 /* 107 * We allow users to force the card into non raid mode without 108 * flashing the alternative BIOS. This is also neccessary right now 109 * for embedded platforms that cannot run a PC BIOS but are using this 110 * device. 111 */ 112 113 static int it8212_noraid; 114 115 /** 116 * it821x_pre_reset - probe 117 * @ap: ATA port 118 * 119 * Set the cable type 120 */ 121 122 static int it821x_pre_reset(struct ata_port *ap) 123 { 124 ap->cbl = ATA_CBL_PATA80; 125 return ata_std_prereset(ap); 126 } 127 128 /** 129 * it821x_error_handler - probe/reset 130 * @ap: ATA port 131 * 132 * Set the cable type and trigger a probe 133 */ 134 135 static void it821x_error_handler(struct ata_port *ap) 136 { 137 return ata_bmdma_drive_eh(ap, it821x_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 138 } 139 140 /** 141 * it821x_program - program the PIO/MWDMA registers 142 * @ap: ATA port 143 * @adev: Device to program 144 * @timing: Timing value (66Mhz in top 8bits, 50 in the low 8) 145 * 146 * Program the PIO/MWDMA timing for this channel according to the 147 * current clock. These share the same register so are managed by 148 * the DMA start/stop sequence as with the old driver. 149 */ 150 151 static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing) 152 { 153 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 154 struct it821x_dev *itdev = ap->private_data; 155 int channel = ap->port_no; 156 u8 conf; 157 158 /* Program PIO/MWDMA timing bits */ 159 if (itdev->clock_mode == ATA_66) 160 conf = timing >> 8; 161 else 162 conf = timing & 0xFF; 163 pci_write_config_byte(pdev, 0x54 + 4 * channel, conf); 164 } 165 166 167 /** 168 * it821x_program_udma - program the UDMA registers 169 * @ap: ATA port 170 * @adev: ATA device to update 171 * @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz 172 * 173 * Program the UDMA timing for this drive according to the 174 * current clock. Handles the dual clocks and also knows about 175 * the errata on the 0x10 revision. The UDMA errata is partly handled 176 * here and partly in start_dma. 177 */ 178 179 static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing) 180 { 181 struct it821x_dev *itdev = ap->private_data; 182 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 183 int channel = ap->port_no; 184 int unit = adev->devno; 185 u8 conf; 186 187 /* Program UDMA timing bits */ 188 if (itdev->clock_mode == ATA_66) 189 conf = timing >> 8; 190 else 191 conf = timing & 0xFF; 192 if (itdev->timing10 == 0) 193 pci_write_config_byte(pdev, 0x56 + 4 * channel + unit, conf); 194 else { 195 /* Early revision must be programmed for both together */ 196 pci_write_config_byte(pdev, 0x56 + 4 * channel, conf); 197 pci_write_config_byte(pdev, 0x56 + 4 * channel + 1, conf); 198 } 199 } 200 201 /** 202 * it821x_clock_strategy 203 * @ap: ATA interface 204 * @adev: ATA device being updated 205 * 206 * Select between the 50 and 66Mhz base clocks to get the best 207 * results for this interface. 208 */ 209 210 static void it821x_clock_strategy(struct ata_port *ap, struct ata_device *adev) 211 { 212 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 213 struct it821x_dev *itdev = ap->private_data; 214 u8 unit = adev->devno; 215 struct ata_device *pair = ata_dev_pair(adev); 216 217 int clock, altclock; 218 u8 v; 219 int sel = 0; 220 221 /* Look for the most wanted clocking */ 222 if (itdev->want[0][0] > itdev->want[1][0]) { 223 clock = itdev->want[0][1]; 224 altclock = itdev->want[1][1]; 225 } else { 226 clock = itdev->want[1][1]; 227 altclock = itdev->want[0][1]; 228 } 229 230 /* Master doesn't care does the slave ? */ 231 if (clock == ATA_ANY) 232 clock = altclock; 233 234 /* Nobody cares - keep the same clock */ 235 if (clock == ATA_ANY) 236 return; 237 /* No change */ 238 if (clock == itdev->clock_mode) 239 return; 240 241 /* Load this into the controller */ 242 if (clock == ATA_66) 243 itdev->clock_mode = ATA_66; 244 else { 245 itdev->clock_mode = ATA_50; 246 sel = 1; 247 } 248 pci_read_config_byte(pdev, 0x50, &v); 249 v &= ~(1 << (1 + ap->port_no)); 250 v |= sel << (1 + ap->port_no); 251 pci_write_config_byte(pdev, 0x50, v); 252 253 /* 254 * Reprogram the UDMA/PIO of the pair drive for the switch 255 * MWDMA will be dealt with by the dma switcher 256 */ 257 if (pair && itdev->udma[1-unit] != UDMA_OFF) { 258 it821x_program_udma(ap, pair, itdev->udma[1-unit]); 259 it821x_program(ap, pair, itdev->pio[1-unit]); 260 } 261 /* 262 * Reprogram the UDMA/PIO of our drive for the switch. 263 * MWDMA will be dealt with by the dma switcher 264 */ 265 if (itdev->udma[unit] != UDMA_OFF) { 266 it821x_program_udma(ap, adev, itdev->udma[unit]); 267 it821x_program(ap, adev, itdev->pio[unit]); 268 } 269 } 270 271 /** 272 * it821x_passthru_set_piomode - set PIO mode data 273 * @ap: ATA interface 274 * @adev: ATA device 275 * 276 * Configure for PIO mode. This is complicated as the register is 277 * shared by PIO and MWDMA and for both channels. 278 */ 279 280 static void it821x_passthru_set_piomode(struct ata_port *ap, struct ata_device *adev) 281 { 282 /* Spec says 89 ref driver uses 88 */ 283 static const u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 }; 284 static const u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY }; 285 286 struct it821x_dev *itdev = ap->private_data; 287 int unit = adev->devno; 288 int mode_wanted = adev->pio_mode - XFER_PIO_0; 289 290 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */ 291 itdev->want[unit][1] = pio_want[mode_wanted]; 292 itdev->want[unit][0] = 1; /* PIO is lowest priority */ 293 itdev->pio[unit] = pio[mode_wanted]; 294 it821x_clock_strategy(ap, adev); 295 it821x_program(ap, adev, itdev->pio[unit]); 296 } 297 298 /** 299 * it821x_passthru_set_dmamode - set initial DMA mode data 300 * @ap: ATA interface 301 * @adev: ATA device 302 * 303 * Set up the DMA modes. The actions taken depend heavily on the mode 304 * to use. If UDMA is used as is hopefully the usual case then the 305 * timing register is private and we need only consider the clock. If 306 * we are using MWDMA then we have to manage the setting ourself as 307 * we switch devices and mode. 308 */ 309 310 static void it821x_passthru_set_dmamode(struct ata_port *ap, struct ata_device *adev) 311 { 312 static const u16 dma[] = { 0x8866, 0x3222, 0x3121 }; 313 static const u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY }; 314 static const u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 }; 315 static const u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 }; 316 317 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 318 struct it821x_dev *itdev = ap->private_data; 319 int channel = ap->port_no; 320 int unit = adev->devno; 321 u8 conf; 322 323 if (adev->dma_mode >= XFER_UDMA_0) { 324 int mode_wanted = adev->dma_mode - XFER_UDMA_0; 325 326 itdev->want[unit][1] = udma_want[mode_wanted]; 327 itdev->want[unit][0] = 3; /* UDMA is high priority */ 328 itdev->mwdma[unit] = MWDMA_OFF; 329 itdev->udma[unit] = udma[mode_wanted]; 330 if (mode_wanted >= 5) 331 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */ 332 333 /* UDMA on. Again revision 0x10 must do the pair */ 334 pci_read_config_byte(pdev, 0x50, &conf); 335 if (itdev->timing10) 336 conf &= channel ? 0x9F: 0xE7; 337 else 338 conf &= ~ (1 << (3 + 2 * channel + unit)); 339 pci_write_config_byte(pdev, 0x50, conf); 340 it821x_clock_strategy(ap, adev); 341 it821x_program_udma(ap, adev, itdev->udma[unit]); 342 } else { 343 int mode_wanted = adev->dma_mode - XFER_MW_DMA_0; 344 345 itdev->want[unit][1] = mwdma_want[mode_wanted]; 346 itdev->want[unit][0] = 2; /* MWDMA is low priority */ 347 itdev->mwdma[unit] = dma[mode_wanted]; 348 itdev->udma[unit] = UDMA_OFF; 349 350 /* UDMA bits off - Revision 0x10 do them in pairs */ 351 pci_read_config_byte(pdev, 0x50, &conf); 352 if (itdev->timing10) 353 conf |= channel ? 0x60: 0x18; 354 else 355 conf |= 1 << (3 + 2 * channel + unit); 356 pci_write_config_byte(pdev, 0x50, conf); 357 it821x_clock_strategy(ap, adev); 358 } 359 } 360 361 /** 362 * it821x_passthru_dma_start - DMA start callback 363 * @qc: Command in progress 364 * 365 * Usually drivers set the DMA timing at the point the set_dmamode call 366 * is made. IT821x however requires we load new timings on the 367 * transitions in some cases. 368 */ 369 370 static void it821x_passthru_bmdma_start(struct ata_queued_cmd *qc) 371 { 372 struct ata_port *ap = qc->ap; 373 struct ata_device *adev = qc->dev; 374 struct it821x_dev *itdev = ap->private_data; 375 int unit = adev->devno; 376 377 if (itdev->mwdma[unit] != MWDMA_OFF) 378 it821x_program(ap, adev, itdev->mwdma[unit]); 379 else if (itdev->udma[unit] != UDMA_OFF && itdev->timing10) 380 it821x_program_udma(ap, adev, itdev->udma[unit]); 381 ata_bmdma_start(qc); 382 } 383 384 /** 385 * it821x_passthru_dma_stop - DMA stop callback 386 * @qc: ATA command 387 * 388 * We loaded new timings in dma_start, as a result we need to restore 389 * the PIO timings in dma_stop so that the next command issue gets the 390 * right clock values. 391 */ 392 393 static void it821x_passthru_bmdma_stop(struct ata_queued_cmd *qc) 394 { 395 struct ata_port *ap = qc->ap; 396 struct ata_device *adev = qc->dev; 397 struct it821x_dev *itdev = ap->private_data; 398 int unit = adev->devno; 399 400 ata_bmdma_stop(qc); 401 if (itdev->mwdma[unit] != MWDMA_OFF) 402 it821x_program(ap, adev, itdev->pio[unit]); 403 } 404 405 406 /** 407 * it821x_passthru_dev_select - Select master/slave 408 * @ap: ATA port 409 * @device: Device number (not pointer) 410 * 411 * Device selection hook. If neccessary perform clock switching 412 */ 413 414 static void it821x_passthru_dev_select(struct ata_port *ap, 415 unsigned int device) 416 { 417 struct it821x_dev *itdev = ap->private_data; 418 if (itdev && device != itdev->last_device) { 419 struct ata_device *adev = &ap->device[device]; 420 it821x_program(ap, adev, itdev->pio[adev->devno]); 421 itdev->last_device = device; 422 } 423 ata_std_dev_select(ap, device); 424 } 425 426 /** 427 * it821x_smart_qc_issue_prot - wrap qc issue prot 428 * @qc: command 429 * 430 * Wrap the command issue sequence for the IT821x. We need to 431 * perform out own device selection timing loads before the 432 * usual happenings kick off 433 */ 434 435 static unsigned int it821x_smart_qc_issue_prot(struct ata_queued_cmd *qc) 436 { 437 switch(qc->tf.command) 438 { 439 /* Commands the firmware supports */ 440 case ATA_CMD_READ: 441 case ATA_CMD_READ_EXT: 442 case ATA_CMD_WRITE: 443 case ATA_CMD_WRITE_EXT: 444 case ATA_CMD_PIO_READ: 445 case ATA_CMD_PIO_READ_EXT: 446 case ATA_CMD_PIO_WRITE: 447 case ATA_CMD_PIO_WRITE_EXT: 448 case ATA_CMD_READ_MULTI: 449 case ATA_CMD_READ_MULTI_EXT: 450 case ATA_CMD_WRITE_MULTI: 451 case ATA_CMD_WRITE_MULTI_EXT: 452 case ATA_CMD_ID_ATA: 453 /* Arguably should just no-op this one */ 454 case ATA_CMD_SET_FEATURES: 455 return ata_qc_issue_prot(qc); 456 } 457 printk(KERN_DEBUG "it821x: can't process command 0x%02X\n", qc->tf.command); 458 return AC_ERR_INVALID; 459 } 460 461 /** 462 * it821x_passthru_qc_issue_prot - wrap qc issue prot 463 * @qc: command 464 * 465 * Wrap the command issue sequence for the IT821x. We need to 466 * perform out own device selection timing loads before the 467 * usual happenings kick off 468 */ 469 470 static unsigned int it821x_passthru_qc_issue_prot(struct ata_queued_cmd *qc) 471 { 472 it821x_passthru_dev_select(qc->ap, qc->dev->devno); 473 return ata_qc_issue_prot(qc); 474 } 475 476 /** 477 * it821x_smart_set_mode - mode setting 478 * @ap: interface to set up 479 * @unused: device that failed (error only) 480 * 481 * Use a non standard set_mode function. We don't want to be tuned. 482 * The BIOS configured everything. Our job is not to fiddle. We 483 * read the dma enabled bits from the PCI configuration of the device 484 * and respect them. 485 */ 486 487 static int it821x_smart_set_mode(struct ata_port *ap, struct ata_device **unused) 488 { 489 int dma_enabled = 0; 490 int i; 491 492 /* Bits 5 and 6 indicate if DMA is active on master/slave */ 493 /* It is possible that BMDMA isn't allocated */ 494 if (ap->ioaddr.bmdma_addr) 495 dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 496 497 for (i = 0; i < ATA_MAX_DEVICES; i++) { 498 struct ata_device *dev = &ap->device[i]; 499 if (ata_dev_enabled(dev)) { 500 /* We don't really care */ 501 dev->pio_mode = XFER_PIO_0; 502 dev->dma_mode = XFER_MW_DMA_0; 503 /* We do need the right mode information for DMA or PIO 504 and this comes from the current configuration flags */ 505 if (dma_enabled & (1 << (5 + i))) { 506 ata_dev_printk(dev, KERN_INFO, "configured for DMA\n"); 507 dev->xfer_mode = XFER_MW_DMA_0; 508 dev->xfer_shift = ATA_SHIFT_MWDMA; 509 dev->flags &= ~ATA_DFLAG_PIO; 510 } else { 511 ata_dev_printk(dev, KERN_INFO, "configured for PIO\n"); 512 dev->xfer_mode = XFER_PIO_0; 513 dev->xfer_shift = ATA_SHIFT_PIO; 514 dev->flags |= ATA_DFLAG_PIO; 515 } 516 } 517 } 518 return 0; 519 } 520 521 /** 522 * it821x_dev_config - Called each device identify 523 * @ap: ATA port 524 * @adev: Device that has just been identified 525 * 526 * Perform the initial setup needed for each device that is chip 527 * special. In our case we need to lock the sector count to avoid 528 * blowing the brains out of the firmware with large LBA48 requests 529 * 530 * FIXME: When FUA appears we need to block FUA too. And SMART and 531 * basically we need to filter commands for this chip. 532 */ 533 534 static void it821x_dev_config(struct ata_port *ap, struct ata_device *adev) 535 { 536 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 537 538 ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 539 540 if (adev->max_sectors > 255) 541 adev->max_sectors = 255; 542 543 if (strstr(model_num, "Integrated Technology Express")) { 544 /* RAID mode */ 545 printk(KERN_INFO "IT821x %sRAID%d volume", 546 adev->id[147]?"Bootable ":"", 547 adev->id[129]); 548 if (adev->id[129] != 1) 549 printk("(%dK stripe)", adev->id[146]); 550 printk(".\n"); 551 } 552 } 553 554 555 /** 556 * it821x_check_atapi_dma - ATAPI DMA handler 557 * @qc: Command we are about to issue 558 * 559 * Decide if this ATAPI command can be issued by DMA on this 560 * controller. Return 0 if it can be. 561 */ 562 563 static int it821x_check_atapi_dma(struct ata_queued_cmd *qc) 564 { 565 struct ata_port *ap = qc->ap; 566 struct it821x_dev *itdev = ap->private_data; 567 568 /* No ATAPI DMA in smart mode */ 569 if (itdev->smart) 570 return -EOPNOTSUPP; 571 /* No ATAPI DMA on rev 10 */ 572 if (itdev->timing10) 573 return -EOPNOTSUPP; 574 /* Cool */ 575 return 0; 576 } 577 578 579 /** 580 * it821x_port_start - port setup 581 * @ap: ATA port being set up 582 * 583 * The it821x needs to maintain private data structures and also to 584 * use the standard PCI interface which lacks support for this 585 * functionality. We instead set up the private data on the port 586 * start hook, and tear it down on port stop 587 */ 588 589 static int it821x_port_start(struct ata_port *ap) 590 { 591 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 592 struct it821x_dev *itdev; 593 u8 conf; 594 595 int ret = ata_port_start(ap); 596 if (ret < 0) 597 return ret; 598 599 itdev = devm_kzalloc(&pdev->dev, sizeof(struct it821x_dev), GFP_KERNEL); 600 if (itdev == NULL) 601 return -ENOMEM; 602 ap->private_data = itdev; 603 604 pci_read_config_byte(pdev, 0x50, &conf); 605 606 if (conf & 1) { 607 itdev->smart = 1; 608 /* Long I/O's although allowed in LBA48 space cause the 609 onboard firmware to enter the twighlight zone */ 610 /* No ATAPI DMA in this mode either */ 611 } 612 /* Pull the current clocks from 0x50 */ 613 if (conf & (1 << (1 + ap->port_no))) 614 itdev->clock_mode = ATA_50; 615 else 616 itdev->clock_mode = ATA_66; 617 618 itdev->want[0][1] = ATA_ANY; 619 itdev->want[1][1] = ATA_ANY; 620 itdev->last_device = -1; 621 622 pci_read_config_byte(pdev, PCI_REVISION_ID, &conf); 623 if (conf == 0x10) { 624 itdev->timing10 = 1; 625 /* Need to disable ATAPI DMA for this case */ 626 if (!itdev->smart) 627 printk(KERN_WARNING DRV_NAME": Revision 0x10, workarounds activated.\n"); 628 } 629 630 return 0; 631 } 632 633 static struct scsi_host_template it821x_sht = { 634 .module = THIS_MODULE, 635 .name = DRV_NAME, 636 .ioctl = ata_scsi_ioctl, 637 .queuecommand = ata_scsi_queuecmd, 638 .can_queue = ATA_DEF_QUEUE, 639 .this_id = ATA_SHT_THIS_ID, 640 .sg_tablesize = LIBATA_MAX_PRD, 641 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 642 .emulated = ATA_SHT_EMULATED, 643 .use_clustering = ATA_SHT_USE_CLUSTERING, 644 .proc_name = DRV_NAME, 645 .dma_boundary = ATA_DMA_BOUNDARY, 646 .slave_configure = ata_scsi_slave_config, 647 .slave_destroy = ata_scsi_slave_destroy, 648 .bios_param = ata_std_bios_param, 649 #ifdef CONFIG_PM 650 .resume = ata_scsi_device_resume, 651 .suspend = ata_scsi_device_suspend, 652 #endif 653 }; 654 655 static struct ata_port_operations it821x_smart_port_ops = { 656 .set_mode = it821x_smart_set_mode, 657 .port_disable = ata_port_disable, 658 .tf_load = ata_tf_load, 659 .tf_read = ata_tf_read, 660 .mode_filter = ata_pci_default_filter, 661 662 .check_status = ata_check_status, 663 .check_atapi_dma= it821x_check_atapi_dma, 664 .exec_command = ata_exec_command, 665 .dev_select = ata_std_dev_select, 666 .dev_config = it821x_dev_config, 667 668 .freeze = ata_bmdma_freeze, 669 .thaw = ata_bmdma_thaw, 670 .error_handler = it821x_error_handler, 671 .post_internal_cmd = ata_bmdma_post_internal_cmd, 672 673 .bmdma_setup = ata_bmdma_setup, 674 .bmdma_start = ata_bmdma_start, 675 .bmdma_stop = ata_bmdma_stop, 676 .bmdma_status = ata_bmdma_status, 677 678 .qc_prep = ata_qc_prep, 679 .qc_issue = it821x_smart_qc_issue_prot, 680 681 .data_xfer = ata_data_xfer, 682 683 .irq_handler = ata_interrupt, 684 .irq_clear = ata_bmdma_irq_clear, 685 .irq_on = ata_irq_on, 686 .irq_ack = ata_irq_ack, 687 688 .port_start = it821x_port_start, 689 }; 690 691 static struct ata_port_operations it821x_passthru_port_ops = { 692 .port_disable = ata_port_disable, 693 .set_piomode = it821x_passthru_set_piomode, 694 .set_dmamode = it821x_passthru_set_dmamode, 695 .mode_filter = ata_pci_default_filter, 696 697 .tf_load = ata_tf_load, 698 .tf_read = ata_tf_read, 699 .check_status = ata_check_status, 700 .exec_command = ata_exec_command, 701 .check_atapi_dma= it821x_check_atapi_dma, 702 .dev_select = it821x_passthru_dev_select, 703 704 .freeze = ata_bmdma_freeze, 705 .thaw = ata_bmdma_thaw, 706 .error_handler = it821x_error_handler, 707 .post_internal_cmd = ata_bmdma_post_internal_cmd, 708 709 .bmdma_setup = ata_bmdma_setup, 710 .bmdma_start = it821x_passthru_bmdma_start, 711 .bmdma_stop = it821x_passthru_bmdma_stop, 712 .bmdma_status = ata_bmdma_status, 713 714 .qc_prep = ata_qc_prep, 715 .qc_issue = it821x_passthru_qc_issue_prot, 716 717 .data_xfer = ata_data_xfer, 718 719 .irq_clear = ata_bmdma_irq_clear, 720 .irq_handler = ata_interrupt, 721 .irq_on = ata_irq_on, 722 .irq_ack = ata_irq_ack, 723 724 .port_start = it821x_port_start, 725 }; 726 727 static void __devinit it821x_disable_raid(struct pci_dev *pdev) 728 { 729 /* Reset local CPU, and set BIOS not ready */ 730 pci_write_config_byte(pdev, 0x5E, 0x01); 731 732 /* Set to bypass mode, and reset PCI bus */ 733 pci_write_config_byte(pdev, 0x50, 0x00); 734 pci_write_config_word(pdev, PCI_COMMAND, 735 PCI_COMMAND_PARITY | PCI_COMMAND_IO | 736 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 737 pci_write_config_word(pdev, 0x40, 0xA0F3); 738 739 pci_write_config_dword(pdev,0x4C, 0x02040204); 740 pci_write_config_byte(pdev, 0x42, 0x36); 741 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20); 742 } 743 744 745 static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 746 { 747 u8 conf; 748 749 static struct ata_port_info info_smart = { 750 .sht = &it821x_sht, 751 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 752 .pio_mask = 0x1f, 753 .mwdma_mask = 0x07, 754 .port_ops = &it821x_smart_port_ops 755 }; 756 static struct ata_port_info info_passthru = { 757 .sht = &it821x_sht, 758 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 759 .pio_mask = 0x1f, 760 .mwdma_mask = 0x07, 761 .udma_mask = 0x7f, 762 .port_ops = &it821x_passthru_port_ops 763 }; 764 static struct ata_port_info *port_info[2]; 765 766 static char *mode[2] = { "pass through", "smart" }; 767 768 /* Force the card into bypass mode if so requested */ 769 if (it8212_noraid) { 770 printk(KERN_INFO DRV_NAME ": forcing bypass mode.\n"); 771 it821x_disable_raid(pdev); 772 } 773 pci_read_config_byte(pdev, 0x50, &conf); 774 conf &= 1; 775 776 printk(KERN_INFO DRV_NAME ": controller in %s mode.\n", mode[conf]); 777 if (conf == 0) 778 port_info[0] = port_info[1] = &info_passthru; 779 else 780 port_info[0] = port_info[1] = &info_smart; 781 782 return ata_pci_init_one(pdev, port_info, 2); 783 } 784 785 #ifdef CONFIG_PM 786 static int it821x_reinit_one(struct pci_dev *pdev) 787 { 788 /* Resume - turn raid back off if need be */ 789 if (it8212_noraid) 790 it821x_disable_raid(pdev); 791 return ata_pci_device_resume(pdev); 792 } 793 #endif 794 795 static const struct pci_device_id it821x[] = { 796 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), }, 797 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), }, 798 799 { }, 800 }; 801 802 static struct pci_driver it821x_pci_driver = { 803 .name = DRV_NAME, 804 .id_table = it821x, 805 .probe = it821x_init_one, 806 .remove = ata_pci_remove_one, 807 #ifdef CONFIG_PM 808 .suspend = ata_pci_device_suspend, 809 .resume = it821x_reinit_one, 810 #endif 811 }; 812 813 static int __init it821x_init(void) 814 { 815 return pci_register_driver(&it821x_pci_driver); 816 } 817 818 static void __exit it821x_exit(void) 819 { 820 pci_unregister_driver(&it821x_pci_driver); 821 } 822 823 MODULE_AUTHOR("Alan Cox"); 824 MODULE_DESCRIPTION("low-level driver for the IT8211/IT8212 IDE RAID controller"); 825 MODULE_LICENSE("GPL"); 826 MODULE_DEVICE_TABLE(pci, it821x); 827 MODULE_VERSION(DRV_VERSION); 828 829 830 module_param_named(noraid, it8212_noraid, int, S_IRUGO); 831 MODULE_PARM_DESC(it8212_noraid, "Force card into bypass mode"); 832 833 module_init(it821x_init); 834 module_exit(it821x_exit); 835