1 /* 2 * IDE tuning and bus mastering support for the CS5510/CS5520 3 * chipsets 4 * 5 * The CS5510/CS5520 are slightly unusual devices. Unlike the 6 * typical IDE controllers they do bus mastering with the drive in 7 * PIO mode and smarter silicon. 8 * 9 * The practical upshot of this is that we must always tune the 10 * drive for the right PIO mode. We must also ignore all the blacklists 11 * and the drive bus mastering DMA information. Also to confuse matters 12 * further we can do DMA on PIO only drives. 13 * 14 * DMA on the 5510 also requires we disable_hlt() during DMA on early 15 * revisions. 16 * 17 * *** This driver is strictly experimental *** 18 * 19 * (c) Copyright Red Hat Inc 2002 20 * 21 * This program is free software; you can redistribute it and/or modify it 22 * under the terms of the GNU General Public License as published by the 23 * Free Software Foundation; either version 2, or (at your option) any 24 * later version. 25 * 26 * This program is distributed in the hope that it will be useful, but 27 * WITHOUT ANY WARRANTY; without even the implied warranty of 28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 29 * General Public License for more details. 30 * 31 * Documentation: 32 * Not publically available. 33 */ 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/init.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <scsi/scsi_host.h> 41 #include <linux/libata.h> 42 43 #define DRV_NAME "pata_cs5520" 44 #define DRV_VERSION "0.6.4" 45 46 struct pio_clocks 47 { 48 int address; 49 int assert; 50 int recovery; 51 }; 52 53 static const struct pio_clocks cs5520_pio_clocks[]={ 54 {3, 6, 11}, 55 {2, 5, 6}, 56 {1, 4, 3}, 57 {1, 3, 2}, 58 {1, 2, 1} 59 }; 60 61 /** 62 * cs5520_set_timings - program PIO timings 63 * @ap: ATA port 64 * @adev: ATA device 65 * 66 * Program the PIO mode timings for the controller according to the pio 67 * clocking table. 68 */ 69 70 static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio) 71 { 72 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 73 int slave = adev->devno; 74 75 pio -= XFER_PIO_0; 76 77 /* Channel command timing */ 78 pci_write_config_byte(pdev, 0x62 + ap->port_no, 79 (cs5520_pio_clocks[pio].recovery << 4) | 80 (cs5520_pio_clocks[pio].assert)); 81 /* FIXME: should these use address ? */ 82 /* Read command timing */ 83 pci_write_config_byte(pdev, 0x64 + 4*ap->port_no + slave, 84 (cs5520_pio_clocks[pio].recovery << 4) | 85 (cs5520_pio_clocks[pio].assert)); 86 /* Write command timing */ 87 pci_write_config_byte(pdev, 0x66 + 4*ap->port_no + slave, 88 (cs5520_pio_clocks[pio].recovery << 4) | 89 (cs5520_pio_clocks[pio].assert)); 90 } 91 92 /** 93 * cs5520_enable_dma - turn on DMA bits 94 * 95 * Turn on the DMA bits for this disk. Needed because the BIOS probably 96 * has not done the work for us. Belongs in the core SATA code. 97 */ 98 99 static void cs5520_enable_dma(struct ata_port *ap, struct ata_device *adev) 100 { 101 /* Set the DMA enable/disable flag */ 102 u8 reg = ioread8(ap->ioaddr.bmdma_addr + 0x02); 103 reg |= 1<<(adev->devno + 5); 104 iowrite8(reg, ap->ioaddr.bmdma_addr + 0x02); 105 } 106 107 /** 108 * cs5520_set_dmamode - program DMA timings 109 * @ap: ATA port 110 * @adev: ATA device 111 * 112 * Program the DMA mode timings for the controller according to the pio 113 * clocking table. Note that this device sets the DMA timings to PIO 114 * mode values. This may seem bizarre but the 5520 architecture talks 115 * PIO mode to the disk and DMA mode to the controller so the underlying 116 * transfers are PIO timed. 117 */ 118 119 static void cs5520_set_dmamode(struct ata_port *ap, struct ata_device *adev) 120 { 121 static const int dma_xlate[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 }; 122 cs5520_set_timings(ap, adev, dma_xlate[adev->dma_mode]); 123 cs5520_enable_dma(ap, adev); 124 } 125 126 /** 127 * cs5520_set_piomode - program PIO timings 128 * @ap: ATA port 129 * @adev: ATA device 130 * 131 * Program the PIO mode timings for the controller according to the pio 132 * clocking table. We know pio_mode will equal dma_mode because of the 133 * CS5520 architecture. At least once we turned DMA on and wrote a 134 * mode setter. 135 */ 136 137 static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev) 138 { 139 cs5520_set_timings(ap, adev, adev->pio_mode); 140 } 141 142 143 static int cs5520_pre_reset(struct ata_port *ap) 144 { 145 ap->cbl = ATA_CBL_PATA40; 146 return ata_std_prereset(ap); 147 } 148 149 static void cs5520_error_handler(struct ata_port *ap) 150 { 151 return ata_bmdma_drive_eh(ap, cs5520_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 152 } 153 154 static struct scsi_host_template cs5520_sht = { 155 .module = THIS_MODULE, 156 .name = DRV_NAME, 157 .ioctl = ata_scsi_ioctl, 158 .queuecommand = ata_scsi_queuecmd, 159 .can_queue = ATA_DEF_QUEUE, 160 .this_id = ATA_SHT_THIS_ID, 161 .sg_tablesize = LIBATA_MAX_PRD, 162 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 163 .emulated = ATA_SHT_EMULATED, 164 .use_clustering = ATA_SHT_USE_CLUSTERING, 165 .proc_name = DRV_NAME, 166 .dma_boundary = ATA_DMA_BOUNDARY, 167 .slave_configure = ata_scsi_slave_config, 168 .slave_destroy = ata_scsi_slave_destroy, 169 .bios_param = ata_std_bios_param, 170 #ifdef CONFIG_PM 171 .resume = ata_scsi_device_resume, 172 .suspend = ata_scsi_device_suspend, 173 #endif 174 }; 175 176 static struct ata_port_operations cs5520_port_ops = { 177 .port_disable = ata_port_disable, 178 .set_piomode = cs5520_set_piomode, 179 .set_dmamode = cs5520_set_dmamode, 180 181 .tf_load = ata_tf_load, 182 .tf_read = ata_tf_read, 183 .check_status = ata_check_status, 184 .exec_command = ata_exec_command, 185 .dev_select = ata_std_dev_select, 186 187 .freeze = ata_bmdma_freeze, 188 .thaw = ata_bmdma_thaw, 189 .error_handler = cs5520_error_handler, 190 .post_internal_cmd = ata_bmdma_post_internal_cmd, 191 192 .bmdma_setup = ata_bmdma_setup, 193 .bmdma_start = ata_bmdma_start, 194 .bmdma_stop = ata_bmdma_stop, 195 .bmdma_status = ata_bmdma_status, 196 .qc_prep = ata_qc_prep, 197 .qc_issue = ata_qc_issue_prot, 198 .data_xfer = ata_data_xfer, 199 200 .irq_handler = ata_interrupt, 201 .irq_clear = ata_bmdma_irq_clear, 202 .irq_on = ata_irq_on, 203 .irq_ack = ata_irq_ack, 204 205 .port_start = ata_port_start, 206 }; 207 208 static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id) 209 { 210 u8 pcicfg; 211 void *iomap[5]; 212 static struct ata_probe_ent probe[2]; 213 int ports = 0; 214 215 /* IDE port enable bits */ 216 pci_read_config_byte(dev, 0x60, &pcicfg); 217 218 /* Check if the ATA ports are enabled */ 219 if ((pcicfg & 3) == 0) 220 return -ENODEV; 221 222 if ((pcicfg & 0x40) == 0) { 223 printk(KERN_WARNING DRV_NAME ": DMA mode disabled. Enabling.\n"); 224 pci_write_config_byte(dev, 0x60, pcicfg | 0x40); 225 } 226 227 /* Perform set up for DMA */ 228 if (pci_enable_device_bars(dev, 1<<2)) { 229 printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n"); 230 return -ENODEV; 231 } 232 pci_set_master(dev); 233 if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { 234 printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n"); 235 return -ENODEV; 236 } 237 if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) { 238 printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n"); 239 return -ENODEV; 240 } 241 242 /* Map IO ports */ 243 iomap[0] = devm_ioport_map(&dev->dev, 0x1F0, 8); 244 iomap[1] = devm_ioport_map(&dev->dev, 0x3F6, 1); 245 iomap[2] = devm_ioport_map(&dev->dev, 0x170, 8); 246 iomap[3] = devm_ioport_map(&dev->dev, 0x376, 1); 247 iomap[4] = pcim_iomap(dev, 2, 0); 248 249 if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4]) 250 return -ENOMEM; 251 252 /* We have to do our own plumbing as the PCI setup for this 253 chipset is non-standard so we can't punt to the libata code */ 254 255 INIT_LIST_HEAD(&probe[0].node); 256 probe[0].dev = pci_dev_to_dev(dev); 257 probe[0].port_ops = &cs5520_port_ops; 258 probe[0].sht = &cs5520_sht; 259 probe[0].pio_mask = 0x1F; 260 probe[0].mwdma_mask = id->driver_data; 261 probe[0].irq = 14; 262 probe[0].irq_flags = 0; 263 probe[0].port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST; 264 probe[0].n_ports = 1; 265 probe[0].port[0].cmd_addr = iomap[0]; 266 probe[0].port[0].ctl_addr = iomap[1]; 267 probe[0].port[0].altstatus_addr = iomap[1]; 268 probe[0].port[0].bmdma_addr = iomap[4]; 269 270 /* The secondary lurks at different addresses but is otherwise 271 the same beastie */ 272 273 probe[1] = probe[0]; 274 INIT_LIST_HEAD(&probe[1].node); 275 probe[1].irq = 15; 276 probe[1].port[0].cmd_addr = iomap[2]; 277 probe[1].port[0].ctl_addr = iomap[3]; 278 probe[1].port[0].altstatus_addr = iomap[3]; 279 probe[1].port[0].bmdma_addr = iomap[4] + 8; 280 281 /* Let libata fill in the port details */ 282 ata_std_ports(&probe[0].port[0]); 283 ata_std_ports(&probe[1].port[0]); 284 285 /* Now add the ports that are active */ 286 if (pcicfg & 1) 287 ports += ata_device_add(&probe[0]); 288 if (pcicfg & 2) 289 ports += ata_device_add(&probe[1]); 290 if (ports) 291 return 0; 292 return -ENODEV; 293 } 294 295 /** 296 * cs5520_remove_one - device unload 297 * @pdev: PCI device being removed 298 * 299 * Handle an unplug/unload event for a PCI device. Unload the 300 * PCI driver but do not use the default handler as we manage 301 * resources ourself and *MUST NOT* disable the device as it has 302 * other functions. 303 */ 304 305 static void __devexit cs5520_remove_one(struct pci_dev *pdev) 306 { 307 struct device *dev = pci_dev_to_dev(pdev); 308 struct ata_host *host = dev_get_drvdata(dev); 309 310 ata_host_detach(host); 311 } 312 313 #ifdef CONFIG_PM 314 /** 315 * cs5520_reinit_one - device resume 316 * @pdev: PCI device 317 * 318 * Do any reconfiguration work needed by a resume from RAM. We need 319 * to restore DMA mode support on BIOSen which disabled it 320 */ 321 322 static int cs5520_reinit_one(struct pci_dev *pdev) 323 { 324 u8 pcicfg; 325 pci_read_config_byte(pdev, 0x60, &pcicfg); 326 if ((pcicfg & 0x40) == 0) 327 pci_write_config_byte(pdev, 0x60, pcicfg | 0x40); 328 return ata_pci_device_resume(pdev); 329 } 330 331 /** 332 * cs5520_pci_device_suspend - device suspend 333 * @pdev: PCI device 334 * 335 * We have to cut and waste bits from the standard method because 336 * the 5520 is a bit odd and not just a pure ATA device. As a result 337 * we must not disable it. The needed code is short and this avoids 338 * chip specific mess in the core code. 339 */ 340 341 static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 342 { 343 struct ata_host *host = dev_get_drvdata(&pdev->dev); 344 int rc = 0; 345 346 rc = ata_host_suspend(host, mesg); 347 if (rc) 348 return rc; 349 350 pci_save_state(pdev); 351 return 0; 352 } 353 #endif /* CONFIG_PM */ 354 355 /* For now keep DMA off. We can set it for all but A rev CS5510 once the 356 core ATA code can handle it */ 357 358 static const struct pci_device_id pata_cs5520[] = { 359 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), }, 360 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), }, 361 362 { }, 363 }; 364 365 static struct pci_driver cs5520_pci_driver = { 366 .name = DRV_NAME, 367 .id_table = pata_cs5520, 368 .probe = cs5520_init_one, 369 .remove = cs5520_remove_one, 370 #ifdef CONFIG_PM 371 .suspend = cs5520_pci_device_suspend, 372 .resume = cs5520_reinit_one, 373 #endif 374 }; 375 376 static int __init cs5520_init(void) 377 { 378 return pci_register_driver(&cs5520_pci_driver); 379 } 380 381 static void __exit cs5520_exit(void) 382 { 383 pci_unregister_driver(&cs5520_pci_driver); 384 } 385 386 MODULE_AUTHOR("Alan Cox"); 387 MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520"); 388 MODULE_LICENSE("GPL"); 389 MODULE_DEVICE_TABLE(pci, pata_cs5520); 390 MODULE_VERSION(DRV_VERSION); 391 392 module_init(cs5520_init); 393 module_exit(cs5520_exit); 394 395