1 /* 2 * pata_cmd64x.c - CMD64x PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * Based upon 7 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002 8 * 9 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. 10 * Note, this driver is not used at all on other systems because 11 * there the "BIOS" has done all of the following already. 12 * Due to massive hardware bugs, UltraDMA is only supported 13 * on the 646U2 and not on the 646U. 14 * 15 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 16 * Copyright (C) 1998 David S. Miller (davem@redhat.com) 17 * 18 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 19 * 20 * TODO 21 * Testing work 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 #include <linux/init.h> 28 #include <linux/blkdev.h> 29 #include <linux/delay.h> 30 #include <scsi/scsi_host.h> 31 #include <linux/libata.h> 32 33 #define DRV_NAME "pata_cmd64x" 34 #define DRV_VERSION "0.2.2" 35 36 /* 37 * CMD64x specific registers definition. 38 */ 39 40 enum { 41 CFR = 0x50, 42 CFR_INTR_CH0 = 0x02, 43 CNTRL = 0x51, 44 CNTRL_DIS_RA0 = 0x40, 45 CNTRL_DIS_RA1 = 0x80, 46 CNTRL_ENA_2ND = 0x08, 47 CMDTIM = 0x52, 48 ARTTIM0 = 0x53, 49 DRWTIM0 = 0x54, 50 ARTTIM1 = 0x55, 51 DRWTIM1 = 0x56, 52 ARTTIM23 = 0x57, 53 ARTTIM23_DIS_RA2 = 0x04, 54 ARTTIM23_DIS_RA3 = 0x08, 55 ARTTIM23_INTR_CH1 = 0x10, 56 ARTTIM2 = 0x57, 57 ARTTIM3 = 0x57, 58 DRWTIM23 = 0x58, 59 DRWTIM2 = 0x58, 60 BRST = 0x59, 61 DRWTIM3 = 0x5b, 62 BMIDECR0 = 0x70, 63 MRDMODE = 0x71, 64 MRDMODE_INTR_CH0 = 0x04, 65 MRDMODE_INTR_CH1 = 0x08, 66 MRDMODE_BLK_CH0 = 0x10, 67 MRDMODE_BLK_CH1 = 0x20, 68 BMIDESR0 = 0x72, 69 UDIDETCR0 = 0x73, 70 DTPR0 = 0x74, 71 BMIDECR1 = 0x78, 72 BMIDECSR = 0x79, 73 BMIDESR1 = 0x7A, 74 UDIDETCR1 = 0x7B, 75 DTPR1 = 0x7C 76 }; 77 78 static int cmd64x_pre_reset(struct ata_port *ap) 79 { 80 ap->cbl = ATA_CBL_PATA40; 81 return ata_std_prereset(ap); 82 } 83 84 static int cmd648_pre_reset(struct ata_port *ap) 85 { 86 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 87 u8 r; 88 89 /* Check cable detect bits */ 90 pci_read_config_byte(pdev, BMIDECSR, &r); 91 if (r & (1 << ap->port_no)) 92 ap->cbl = ATA_CBL_PATA80; 93 else 94 ap->cbl = ATA_CBL_PATA40; 95 96 return ata_std_prereset(ap); 97 } 98 99 static void cmd64x_error_handler(struct ata_port *ap) 100 { 101 return ata_bmdma_drive_eh(ap, cmd64x_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 102 } 103 104 static void cmd648_error_handler(struct ata_port *ap) 105 { 106 ata_bmdma_drive_eh(ap, cmd648_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 107 } 108 109 /** 110 * cmd64x_set_piomode - set initial PIO mode data 111 * @ap: ATA interface 112 * @adev: ATA device 113 * 114 * Called to do the PIO mode setup. 115 */ 116 117 static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) 118 { 119 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 120 struct ata_timing t; 121 const unsigned long T = 1000000 / 33; 122 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; 123 124 u8 reg; 125 126 /* Port layout is not logical so use a table */ 127 const u8 arttim_port[2][2] = { 128 { ARTTIM0, ARTTIM1 }, 129 { ARTTIM23, ARTTIM23 } 130 }; 131 const u8 drwtim_port[2][2] = { 132 { DRWTIM0, DRWTIM1 }, 133 { DRWTIM2, DRWTIM3 } 134 }; 135 136 int arttim = arttim_port[ap->port_no][adev->devno]; 137 int drwtim = drwtim_port[ap->port_no][adev->devno]; 138 139 140 if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) { 141 printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); 142 return; 143 } 144 if (ap->port_no) { 145 /* Slave has shared address setup */ 146 struct ata_device *pair = ata_dev_pair(adev); 147 148 if (pair) { 149 struct ata_timing tp; 150 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0); 151 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 152 } 153 } 154 155 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n", 156 t.active, t.recover, t.setup); 157 if (t.recover > 16) { 158 t.active += t.recover - 16; 159 t.recover = 16; 160 } 161 if (t.active > 16) 162 t.active = 16; 163 164 /* Now convert the clocks into values we can actually stuff into 165 the chip */ 166 167 if (t.recover > 1) 168 t.recover--; 169 else 170 t.recover = 15; 171 172 if (t.setup > 4) 173 t.setup = 0xC0; 174 else 175 t.setup = setup_data[t.setup]; 176 177 t.active &= 0x0F; /* 0 = 16 */ 178 179 /* Load setup timing */ 180 pci_read_config_byte(pdev, arttim, ®); 181 reg &= 0x3F; 182 reg |= t.setup; 183 pci_write_config_byte(pdev, arttim, reg); 184 185 /* Load active/recovery */ 186 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover); 187 } 188 189 /** 190 * cmd64x_set_dmamode - set initial DMA mode data 191 * @ap: ATA interface 192 * @adev: ATA device 193 * 194 * Called to do the DMA mode setup. 195 */ 196 197 static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev) 198 { 199 static const u8 udma_data[] = { 200 0x30, 0x20, 0x10, 0x20, 0x10, 0x00 201 }; 202 static const u8 mwdma_data[] = { 203 0x30, 0x20, 0x10 204 }; 205 206 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 207 u8 regU, regD; 208 209 int pciU = UDIDETCR0 + 8 * ap->port_no; 210 int pciD = BMIDESR0 + 8 * ap->port_no; 211 int shift = 2 * adev->devno; 212 213 pci_read_config_byte(pdev, pciD, ®D); 214 pci_read_config_byte(pdev, pciU, ®U); 215 216 /* DMA bits off */ 217 regD &= ~(0x20 << adev->devno); 218 /* DMA control bits */ 219 regU &= ~(0x30 << shift); 220 /* DMA timing bits */ 221 regU &= ~(0x05 << adev->devno); 222 223 if (adev->dma_mode >= XFER_UDMA_0) { 224 /* Merge thge timing value */ 225 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift; 226 /* Merge the control bits */ 227 regU |= 1 << adev->devno; /* UDMA on */ 228 if (adev->dma_mode > 2) /* 15nS timing */ 229 regU |= 4 << adev->devno; 230 } else 231 regD |= mwdma_data[adev->dma_mode - XFER_MW_DMA_0] << shift; 232 233 regD |= 0x20 << adev->devno; 234 235 pci_write_config_byte(pdev, pciU, regU); 236 pci_write_config_byte(pdev, pciD, regD); 237 } 238 239 /** 240 * cmd648_dma_stop - DMA stop callback 241 * @qc: Command in progress 242 * 243 * DMA has completed. 244 */ 245 246 static void cmd648_bmdma_stop(struct ata_queued_cmd *qc) 247 { 248 struct ata_port *ap = qc->ap; 249 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 250 u8 dma_intr; 251 int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; 252 int dma_reg = ap->port_no ? ARTTIM2 : CFR; 253 254 ata_bmdma_stop(qc); 255 256 pci_read_config_byte(pdev, dma_reg, &dma_intr); 257 pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask); 258 } 259 260 /** 261 * cmd646r1_dma_stop - DMA stop callback 262 * @qc: Command in progress 263 * 264 * Stub for now while investigating the r1 quirk in the old driver. 265 */ 266 267 static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc) 268 { 269 ata_bmdma_stop(qc); 270 } 271 272 static struct scsi_host_template cmd64x_sht = { 273 .module = THIS_MODULE, 274 .name = DRV_NAME, 275 .ioctl = ata_scsi_ioctl, 276 .queuecommand = ata_scsi_queuecmd, 277 .can_queue = ATA_DEF_QUEUE, 278 .this_id = ATA_SHT_THIS_ID, 279 .sg_tablesize = LIBATA_MAX_PRD, 280 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 281 .emulated = ATA_SHT_EMULATED, 282 .use_clustering = ATA_SHT_USE_CLUSTERING, 283 .proc_name = DRV_NAME, 284 .dma_boundary = ATA_DMA_BOUNDARY, 285 .slave_configure = ata_scsi_slave_config, 286 .slave_destroy = ata_scsi_slave_destroy, 287 .bios_param = ata_std_bios_param, 288 #ifdef CONFIG_PM 289 .resume = ata_scsi_device_resume, 290 .suspend = ata_scsi_device_suspend, 291 #endif 292 }; 293 294 static struct ata_port_operations cmd64x_port_ops = { 295 .port_disable = ata_port_disable, 296 .set_piomode = cmd64x_set_piomode, 297 .set_dmamode = cmd64x_set_dmamode, 298 .mode_filter = ata_pci_default_filter, 299 .tf_load = ata_tf_load, 300 .tf_read = ata_tf_read, 301 .check_status = ata_check_status, 302 .exec_command = ata_exec_command, 303 .dev_select = ata_std_dev_select, 304 305 .freeze = ata_bmdma_freeze, 306 .thaw = ata_bmdma_thaw, 307 .error_handler = cmd64x_error_handler, 308 .post_internal_cmd = ata_bmdma_post_internal_cmd, 309 310 .bmdma_setup = ata_bmdma_setup, 311 .bmdma_start = ata_bmdma_start, 312 .bmdma_stop = ata_bmdma_stop, 313 .bmdma_status = ata_bmdma_status, 314 315 .qc_prep = ata_qc_prep, 316 .qc_issue = ata_qc_issue_prot, 317 318 .data_xfer = ata_data_xfer, 319 320 .irq_handler = ata_interrupt, 321 .irq_clear = ata_bmdma_irq_clear, 322 .irq_on = ata_irq_on, 323 .irq_ack = ata_irq_ack, 324 325 .port_start = ata_port_start, 326 }; 327 328 static struct ata_port_operations cmd646r1_port_ops = { 329 .port_disable = ata_port_disable, 330 .set_piomode = cmd64x_set_piomode, 331 .set_dmamode = cmd64x_set_dmamode, 332 .mode_filter = ata_pci_default_filter, 333 .tf_load = ata_tf_load, 334 .tf_read = ata_tf_read, 335 .check_status = ata_check_status, 336 .exec_command = ata_exec_command, 337 .dev_select = ata_std_dev_select, 338 339 .freeze = ata_bmdma_freeze, 340 .thaw = ata_bmdma_thaw, 341 .error_handler = cmd64x_error_handler, 342 .post_internal_cmd = ata_bmdma_post_internal_cmd, 343 344 .bmdma_setup = ata_bmdma_setup, 345 .bmdma_start = ata_bmdma_start, 346 .bmdma_stop = cmd646r1_bmdma_stop, 347 .bmdma_status = ata_bmdma_status, 348 349 .qc_prep = ata_qc_prep, 350 .qc_issue = ata_qc_issue_prot, 351 352 .data_xfer = ata_data_xfer, 353 354 .irq_handler = ata_interrupt, 355 .irq_clear = ata_bmdma_irq_clear, 356 .irq_on = ata_irq_on, 357 .irq_ack = ata_irq_ack, 358 359 .port_start = ata_port_start, 360 }; 361 362 static struct ata_port_operations cmd648_port_ops = { 363 .port_disable = ata_port_disable, 364 .set_piomode = cmd64x_set_piomode, 365 .set_dmamode = cmd64x_set_dmamode, 366 .mode_filter = ata_pci_default_filter, 367 .tf_load = ata_tf_load, 368 .tf_read = ata_tf_read, 369 .check_status = ata_check_status, 370 .exec_command = ata_exec_command, 371 .dev_select = ata_std_dev_select, 372 373 .freeze = ata_bmdma_freeze, 374 .thaw = ata_bmdma_thaw, 375 .error_handler = cmd648_error_handler, 376 .post_internal_cmd = ata_bmdma_post_internal_cmd, 377 378 .bmdma_setup = ata_bmdma_setup, 379 .bmdma_start = ata_bmdma_start, 380 .bmdma_stop = cmd648_bmdma_stop, 381 .bmdma_status = ata_bmdma_status, 382 383 .qc_prep = ata_qc_prep, 384 .qc_issue = ata_qc_issue_prot, 385 386 .data_xfer = ata_data_xfer, 387 388 .irq_handler = ata_interrupt, 389 .irq_clear = ata_bmdma_irq_clear, 390 .irq_on = ata_irq_on, 391 .irq_ack = ata_irq_ack, 392 393 .port_start = ata_port_start, 394 }; 395 396 static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 397 { 398 u32 class_rev; 399 400 static struct ata_port_info cmd_info[6] = { 401 { /* CMD 643 - no UDMA */ 402 .sht = &cmd64x_sht, 403 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 404 .pio_mask = 0x1f, 405 .mwdma_mask = 0x07, 406 .port_ops = &cmd64x_port_ops 407 }, 408 { /* CMD 646 with broken UDMA */ 409 .sht = &cmd64x_sht, 410 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 411 .pio_mask = 0x1f, 412 .mwdma_mask = 0x07, 413 .port_ops = &cmd64x_port_ops 414 }, 415 { /* CMD 646 with working UDMA */ 416 .sht = &cmd64x_sht, 417 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 418 .pio_mask = 0x1f, 419 .mwdma_mask = 0x07, 420 .udma_mask = ATA_UDMA1, 421 .port_ops = &cmd64x_port_ops 422 }, 423 { /* CMD 646 rev 1 */ 424 .sht = &cmd64x_sht, 425 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 426 .pio_mask = 0x1f, 427 .mwdma_mask = 0x07, 428 .port_ops = &cmd646r1_port_ops 429 }, 430 { /* CMD 648 */ 431 .sht = &cmd64x_sht, 432 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 433 .pio_mask = 0x1f, 434 .mwdma_mask = 0x07, 435 .udma_mask = ATA_UDMA2, 436 .port_ops = &cmd648_port_ops 437 }, 438 { /* CMD 649 */ 439 .sht = &cmd64x_sht, 440 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 441 .pio_mask = 0x1f, 442 .mwdma_mask = 0x07, 443 .udma_mask = ATA_UDMA3, 444 .port_ops = &cmd648_port_ops 445 } 446 }; 447 static struct ata_port_info *port_info[2], *info; 448 u8 mrdmode; 449 450 info = &cmd_info[id->driver_data]; 451 452 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev); 453 class_rev &= 0xFF; 454 455 if (id->driver_data == 0) /* 643 */ 456 ata_pci_clear_simplex(pdev); 457 458 if (pdev->device == PCI_DEVICE_ID_CMD_646) { 459 /* Does UDMA work ? */ 460 if (class_rev > 4) 461 info = &cmd_info[2]; 462 /* Early rev with other problems ? */ 463 else if (class_rev == 1) 464 info = &cmd_info[3]; 465 } 466 467 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); 468 pci_read_config_byte(pdev, MRDMODE, &mrdmode); 469 mrdmode &= ~ 0x30; /* IRQ set up */ 470 mrdmode |= 0x02; /* Memory read line enable */ 471 pci_write_config_byte(pdev, MRDMODE, mrdmode); 472 473 /* Force PIO 0 here.. */ 474 475 /* PPC specific fixup copied from old driver */ 476 #ifdef CONFIG_PPC 477 pci_write_config_byte(pdev, UDIDETCR0, 0xF0); 478 #endif 479 480 port_info[0] = port_info[1] = info; 481 return ata_pci_init_one(pdev, port_info, 2); 482 } 483 484 #ifdef CONFIG_PM 485 static int cmd64x_reinit_one(struct pci_dev *pdev) 486 { 487 u8 mrdmode; 488 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); 489 pci_read_config_byte(pdev, MRDMODE, &mrdmode); 490 mrdmode &= ~ 0x30; /* IRQ set up */ 491 mrdmode |= 0x02; /* Memory read line enable */ 492 pci_write_config_byte(pdev, MRDMODE, mrdmode); 493 #ifdef CONFIG_PPC 494 pci_write_config_byte(pdev, UDIDETCR0, 0xF0); 495 #endif 496 return ata_pci_device_resume(pdev); 497 } 498 #endif 499 500 static const struct pci_device_id cmd64x[] = { 501 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, 502 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, 503 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 }, 504 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 }, 505 506 { }, 507 }; 508 509 static struct pci_driver cmd64x_pci_driver = { 510 .name = DRV_NAME, 511 .id_table = cmd64x, 512 .probe = cmd64x_init_one, 513 .remove = ata_pci_remove_one, 514 #ifdef CONFIG_PM 515 .suspend = ata_pci_device_suspend, 516 .resume = cmd64x_reinit_one, 517 #endif 518 }; 519 520 static int __init cmd64x_init(void) 521 { 522 return pci_register_driver(&cmd64x_pci_driver); 523 } 524 525 static void __exit cmd64x_exit(void) 526 { 527 pci_unregister_driver(&cmd64x_pci_driver); 528 } 529 530 MODULE_AUTHOR("Alan Cox"); 531 MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers"); 532 MODULE_LICENSE("GPL"); 533 MODULE_DEVICE_TABLE(pci, cmd64x); 534 MODULE_VERSION(DRV_VERSION); 535 536 module_init(cmd64x_init); 537 module_exit(cmd64x_exit); 538