1 /* 2 * ahci.c - AHCI SATA support 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/init.h> 39 #include <linux/blkdev.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/device.h> 44 #include <scsi/scsi_host.h> 45 #include <scsi/scsi_cmnd.h> 46 #include <linux/libata.h> 47 48 #define DRV_NAME "ahci" 49 #define DRV_VERSION "2.1" 50 51 52 enum { 53 AHCI_PCI_BAR = 5, 54 AHCI_MAX_PORTS = 32, 55 AHCI_MAX_SG = 168, /* hardware max is 64K */ 56 AHCI_DMA_BOUNDARY = 0xffffffff, 57 AHCI_USE_CLUSTERING = 0, 58 AHCI_MAX_CMDS = 32, 59 AHCI_CMD_SZ = 32, 60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, 61 AHCI_RX_FIS_SZ = 256, 62 AHCI_CMD_TBL_CDB = 0x40, 63 AHCI_CMD_TBL_HDR_SZ = 0x80, 64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), 65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, 66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + 67 AHCI_RX_FIS_SZ, 68 AHCI_IRQ_ON_SG = (1 << 31), 69 AHCI_CMD_ATAPI = (1 << 5), 70 AHCI_CMD_WRITE = (1 << 6), 71 AHCI_CMD_PREFETCH = (1 << 7), 72 AHCI_CMD_RESET = (1 << 8), 73 AHCI_CMD_CLR_BUSY = (1 << 10), 74 75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ 76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ 77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ 78 79 board_ahci = 0, 80 board_ahci_pi = 1, 81 board_ahci_vt8251 = 2, 82 board_ahci_ign_iferr = 3, 83 84 /* global controller registers */ 85 HOST_CAP = 0x00, /* host capabilities */ 86 HOST_CTL = 0x04, /* global host control */ 87 HOST_IRQ_STAT = 0x08, /* interrupt status */ 88 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ 89 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ 90 91 /* HOST_CTL bits */ 92 HOST_RESET = (1 << 0), /* reset controller; self-clear */ 93 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ 94 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ 95 96 /* HOST_CAP bits */ 97 HOST_CAP_SSC = (1 << 14), /* Slumber capable */ 98 HOST_CAP_CLO = (1 << 24), /* Command List Override support */ 99 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ 100 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ 101 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ 102 103 /* registers for each SATA port */ 104 PORT_LST_ADDR = 0x00, /* command list DMA addr */ 105 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ 106 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ 107 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ 108 PORT_IRQ_STAT = 0x10, /* interrupt status */ 109 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ 110 PORT_CMD = 0x18, /* port command */ 111 PORT_TFDATA = 0x20, /* taskfile data */ 112 PORT_SIG = 0x24, /* device TF signature */ 113 PORT_CMD_ISSUE = 0x38, /* command issue */ 114 PORT_SCR = 0x28, /* SATA phy register block */ 115 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ 116 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ 117 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ 118 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ 119 120 /* PORT_IRQ_{STAT,MASK} bits */ 121 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ 122 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ 123 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ 124 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ 125 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ 126 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ 127 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ 128 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ 129 130 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ 131 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ 132 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ 133 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ 134 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ 135 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ 136 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ 137 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ 138 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ 139 140 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | 141 PORT_IRQ_IF_ERR | 142 PORT_IRQ_CONNECT | 143 PORT_IRQ_PHYRDY | 144 PORT_IRQ_UNK_FIS, 145 PORT_IRQ_ERROR = PORT_IRQ_FREEZE | 146 PORT_IRQ_TF_ERR | 147 PORT_IRQ_HBUS_DATA_ERR, 148 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | 149 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | 150 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, 151 152 /* PORT_CMD bits */ 153 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ 154 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ 155 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ 156 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ 157 PORT_CMD_CLO = (1 << 3), /* Command list override */ 158 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ 159 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ 160 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ 161 162 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ 163 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ 164 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ 165 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ 166 167 /* ap->flags bits */ 168 AHCI_FLAG_NO_NCQ = (1 << 24), 169 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */ 170 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */ 171 }; 172 173 struct ahci_cmd_hdr { 174 u32 opts; 175 u32 status; 176 u32 tbl_addr; 177 u32 tbl_addr_hi; 178 u32 reserved[4]; 179 }; 180 181 struct ahci_sg { 182 u32 addr; 183 u32 addr_hi; 184 u32 reserved; 185 u32 flags_size; 186 }; 187 188 struct ahci_host_priv { 189 u32 cap; /* cache of HOST_CAP register */ 190 u32 port_map; /* cache of HOST_PORTS_IMPL reg */ 191 }; 192 193 struct ahci_port_priv { 194 struct ahci_cmd_hdr *cmd_slot; 195 dma_addr_t cmd_slot_dma; 196 void *cmd_tbl; 197 dma_addr_t cmd_tbl_dma; 198 void *rx_fis; 199 dma_addr_t rx_fis_dma; 200 /* for NCQ spurious interrupt analysis */ 201 unsigned int ncq_saw_d2h:1; 202 unsigned int ncq_saw_dmas:1; 203 unsigned int ncq_saw_sdb:1; 204 }; 205 206 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); 207 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); 208 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 209 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 210 static irqreturn_t ahci_interrupt (int irq, void *dev_instance); 211 static void ahci_irq_clear(struct ata_port *ap); 212 static int ahci_port_start(struct ata_port *ap); 213 static void ahci_port_stop(struct ata_port *ap); 214 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); 215 static void ahci_qc_prep(struct ata_queued_cmd *qc); 216 static u8 ahci_check_status(struct ata_port *ap); 217 static void ahci_freeze(struct ata_port *ap); 218 static void ahci_thaw(struct ata_port *ap); 219 static void ahci_error_handler(struct ata_port *ap); 220 static void ahci_vt8251_error_handler(struct ata_port *ap); 221 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 222 #ifdef CONFIG_PM 223 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 224 static int ahci_port_resume(struct ata_port *ap); 225 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 226 static int ahci_pci_device_resume(struct pci_dev *pdev); 227 #endif 228 229 static struct scsi_host_template ahci_sht = { 230 .module = THIS_MODULE, 231 .name = DRV_NAME, 232 .ioctl = ata_scsi_ioctl, 233 .queuecommand = ata_scsi_queuecmd, 234 .change_queue_depth = ata_scsi_change_queue_depth, 235 .can_queue = AHCI_MAX_CMDS - 1, 236 .this_id = ATA_SHT_THIS_ID, 237 .sg_tablesize = AHCI_MAX_SG, 238 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 239 .emulated = ATA_SHT_EMULATED, 240 .use_clustering = AHCI_USE_CLUSTERING, 241 .proc_name = DRV_NAME, 242 .dma_boundary = AHCI_DMA_BOUNDARY, 243 .slave_configure = ata_scsi_slave_config, 244 .slave_destroy = ata_scsi_slave_destroy, 245 .bios_param = ata_std_bios_param, 246 #ifdef CONFIG_PM 247 .suspend = ata_scsi_device_suspend, 248 .resume = ata_scsi_device_resume, 249 #endif 250 }; 251 252 static const struct ata_port_operations ahci_ops = { 253 .port_disable = ata_port_disable, 254 255 .check_status = ahci_check_status, 256 .check_altstatus = ahci_check_status, 257 .dev_select = ata_noop_dev_select, 258 259 .tf_read = ahci_tf_read, 260 261 .qc_prep = ahci_qc_prep, 262 .qc_issue = ahci_qc_issue, 263 264 .irq_handler = ahci_interrupt, 265 .irq_clear = ahci_irq_clear, 266 .irq_on = ata_dummy_irq_on, 267 .irq_ack = ata_dummy_irq_ack, 268 269 .scr_read = ahci_scr_read, 270 .scr_write = ahci_scr_write, 271 272 .freeze = ahci_freeze, 273 .thaw = ahci_thaw, 274 275 .error_handler = ahci_error_handler, 276 .post_internal_cmd = ahci_post_internal_cmd, 277 278 #ifdef CONFIG_PM 279 .port_suspend = ahci_port_suspend, 280 .port_resume = ahci_port_resume, 281 #endif 282 283 .port_start = ahci_port_start, 284 .port_stop = ahci_port_stop, 285 }; 286 287 static const struct ata_port_operations ahci_vt8251_ops = { 288 .port_disable = ata_port_disable, 289 290 .check_status = ahci_check_status, 291 .check_altstatus = ahci_check_status, 292 .dev_select = ata_noop_dev_select, 293 294 .tf_read = ahci_tf_read, 295 296 .qc_prep = ahci_qc_prep, 297 .qc_issue = ahci_qc_issue, 298 299 .irq_handler = ahci_interrupt, 300 .irq_clear = ahci_irq_clear, 301 .irq_on = ata_dummy_irq_on, 302 .irq_ack = ata_dummy_irq_ack, 303 304 .scr_read = ahci_scr_read, 305 .scr_write = ahci_scr_write, 306 307 .freeze = ahci_freeze, 308 .thaw = ahci_thaw, 309 310 .error_handler = ahci_vt8251_error_handler, 311 .post_internal_cmd = ahci_post_internal_cmd, 312 313 #ifdef CONFIG_PM 314 .port_suspend = ahci_port_suspend, 315 .port_resume = ahci_port_resume, 316 #endif 317 318 .port_start = ahci_port_start, 319 .port_stop = ahci_port_stop, 320 }; 321 322 static const struct ata_port_info ahci_port_info[] = { 323 /* board_ahci */ 324 { 325 .sht = &ahci_sht, 326 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 327 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 328 ATA_FLAG_SKIP_D2H_BSY, 329 .pio_mask = 0x1f, /* pio0-4 */ 330 .udma_mask = 0x7f, /* udma0-6 ; FIXME */ 331 .port_ops = &ahci_ops, 332 }, 333 /* board_ahci_pi */ 334 { 335 .sht = &ahci_sht, 336 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 337 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 338 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI, 339 .pio_mask = 0x1f, /* pio0-4 */ 340 .udma_mask = 0x7f, /* udma0-6 ; FIXME */ 341 .port_ops = &ahci_ops, 342 }, 343 /* board_ahci_vt8251 */ 344 { 345 .sht = &ahci_sht, 346 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 347 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 348 ATA_FLAG_SKIP_D2H_BSY | 349 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ, 350 .pio_mask = 0x1f, /* pio0-4 */ 351 .udma_mask = 0x7f, /* udma0-6 ; FIXME */ 352 .port_ops = &ahci_vt8251_ops, 353 }, 354 /* board_ahci_ign_iferr */ 355 { 356 .sht = &ahci_sht, 357 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 358 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 359 ATA_FLAG_SKIP_D2H_BSY | 360 AHCI_FLAG_IGN_IRQ_IF_ERR, 361 .pio_mask = 0x1f, /* pio0-4 */ 362 .udma_mask = 0x7f, /* udma0-6 ; FIXME */ 363 .port_ops = &ahci_ops, 364 }, 365 }; 366 367 static const struct pci_device_id ahci_pci_tbl[] = { 368 /* Intel */ 369 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 370 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 371 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 372 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 373 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 374 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 375 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 376 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 377 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 378 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 379 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */ 380 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */ 381 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */ 382 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */ 383 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */ 384 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */ 385 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */ 386 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */ 387 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */ 388 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */ 389 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */ 390 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */ 391 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */ 392 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */ 393 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */ 394 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */ 395 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */ 396 397 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 398 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 399 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 400 401 /* ATI */ 402 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */ 403 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */ 404 405 /* VIA */ 406 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 407 408 /* NVIDIA */ 409 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ 410 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ 411 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ 412 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ 413 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ 414 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ 415 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ 416 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ 417 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ 418 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ 419 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ 420 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ 421 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ 422 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ 423 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ 424 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ 425 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ 426 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ 427 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ 428 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ 429 430 /* SiS */ 431 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 432 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ 433 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 434 435 /* Generic, PCI class code for AHCI */ 436 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 437 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 438 439 { } /* terminate list */ 440 }; 441 442 443 static struct pci_driver ahci_pci_driver = { 444 .name = DRV_NAME, 445 .id_table = ahci_pci_tbl, 446 .probe = ahci_init_one, 447 .remove = ata_pci_remove_one, 448 #ifdef CONFIG_PM 449 .suspend = ahci_pci_device_suspend, 450 .resume = ahci_pci_device_resume, 451 #endif 452 }; 453 454 455 static inline int ahci_nr_ports(u32 cap) 456 { 457 return (cap & 0x1f) + 1; 458 } 459 460 static inline void __iomem *ahci_port_base(void __iomem *base, 461 unsigned int port) 462 { 463 return base + 0x100 + (port * 0x80); 464 } 465 466 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) 467 { 468 unsigned int sc_reg; 469 470 switch (sc_reg_in) { 471 case SCR_STATUS: sc_reg = 0; break; 472 case SCR_CONTROL: sc_reg = 1; break; 473 case SCR_ERROR: sc_reg = 2; break; 474 case SCR_ACTIVE: sc_reg = 3; break; 475 default: 476 return 0xffffffffU; 477 } 478 479 return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); 480 } 481 482 483 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, 484 u32 val) 485 { 486 unsigned int sc_reg; 487 488 switch (sc_reg_in) { 489 case SCR_STATUS: sc_reg = 0; break; 490 case SCR_CONTROL: sc_reg = 1; break; 491 case SCR_ERROR: sc_reg = 2; break; 492 case SCR_ACTIVE: sc_reg = 3; break; 493 default: 494 return; 495 } 496 497 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); 498 } 499 500 static void ahci_start_engine(void __iomem *port_mmio) 501 { 502 u32 tmp; 503 504 /* start DMA */ 505 tmp = readl(port_mmio + PORT_CMD); 506 tmp |= PORT_CMD_START; 507 writel(tmp, port_mmio + PORT_CMD); 508 readl(port_mmio + PORT_CMD); /* flush */ 509 } 510 511 static int ahci_stop_engine(void __iomem *port_mmio) 512 { 513 u32 tmp; 514 515 tmp = readl(port_mmio + PORT_CMD); 516 517 /* check if the HBA is idle */ 518 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 519 return 0; 520 521 /* setting HBA to idle */ 522 tmp &= ~PORT_CMD_START; 523 writel(tmp, port_mmio + PORT_CMD); 524 525 /* wait for engine to stop. This could be as long as 500 msec */ 526 tmp = ata_wait_register(port_mmio + PORT_CMD, 527 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 528 if (tmp & PORT_CMD_LIST_ON) 529 return -EIO; 530 531 return 0; 532 } 533 534 static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap, 535 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma) 536 { 537 u32 tmp; 538 539 /* set FIS registers */ 540 if (cap & HOST_CAP_64) 541 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); 542 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 543 544 if (cap & HOST_CAP_64) 545 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI); 546 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 547 548 /* enable FIS reception */ 549 tmp = readl(port_mmio + PORT_CMD); 550 tmp |= PORT_CMD_FIS_RX; 551 writel(tmp, port_mmio + PORT_CMD); 552 553 /* flush */ 554 readl(port_mmio + PORT_CMD); 555 } 556 557 static int ahci_stop_fis_rx(void __iomem *port_mmio) 558 { 559 u32 tmp; 560 561 /* disable FIS reception */ 562 tmp = readl(port_mmio + PORT_CMD); 563 tmp &= ~PORT_CMD_FIS_RX; 564 writel(tmp, port_mmio + PORT_CMD); 565 566 /* wait for completion, spec says 500ms, give it 1000 */ 567 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 568 PORT_CMD_FIS_ON, 10, 1000); 569 if (tmp & PORT_CMD_FIS_ON) 570 return -EBUSY; 571 572 return 0; 573 } 574 575 static void ahci_power_up(void __iomem *port_mmio, u32 cap) 576 { 577 u32 cmd; 578 579 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 580 581 /* spin up device */ 582 if (cap & HOST_CAP_SSS) { 583 cmd |= PORT_CMD_SPIN_UP; 584 writel(cmd, port_mmio + PORT_CMD); 585 } 586 587 /* wake up link */ 588 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 589 } 590 591 #ifdef CONFIG_PM 592 static void ahci_power_down(void __iomem *port_mmio, u32 cap) 593 { 594 u32 cmd, scontrol; 595 596 if (!(cap & HOST_CAP_SSS)) 597 return; 598 599 /* put device into listen mode, first set PxSCTL.DET to 0 */ 600 scontrol = readl(port_mmio + PORT_SCR_CTL); 601 scontrol &= ~0xf; 602 writel(scontrol, port_mmio + PORT_SCR_CTL); 603 604 /* then set PxCMD.SUD to 0 */ 605 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 606 cmd &= ~PORT_CMD_SPIN_UP; 607 writel(cmd, port_mmio + PORT_CMD); 608 } 609 #endif 610 611 static void ahci_init_port(void __iomem *port_mmio, u32 cap, 612 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma) 613 { 614 /* enable FIS reception */ 615 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma); 616 617 /* enable DMA */ 618 ahci_start_engine(port_mmio); 619 } 620 621 static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg) 622 { 623 int rc; 624 625 /* disable DMA */ 626 rc = ahci_stop_engine(port_mmio); 627 if (rc) { 628 *emsg = "failed to stop engine"; 629 return rc; 630 } 631 632 /* disable FIS reception */ 633 rc = ahci_stop_fis_rx(port_mmio); 634 if (rc) { 635 *emsg = "failed stop FIS RX"; 636 return rc; 637 } 638 639 return 0; 640 } 641 642 static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev) 643 { 644 u32 cap_save, impl_save, tmp; 645 646 cap_save = readl(mmio + HOST_CAP); 647 impl_save = readl(mmio + HOST_PORTS_IMPL); 648 649 /* global controller reset */ 650 tmp = readl(mmio + HOST_CTL); 651 if ((tmp & HOST_RESET) == 0) { 652 writel(tmp | HOST_RESET, mmio + HOST_CTL); 653 readl(mmio + HOST_CTL); /* flush */ 654 } 655 656 /* reset must complete within 1 second, or 657 * the hardware should be considered fried. 658 */ 659 ssleep(1); 660 661 tmp = readl(mmio + HOST_CTL); 662 if (tmp & HOST_RESET) { 663 dev_printk(KERN_ERR, &pdev->dev, 664 "controller reset failed (0x%x)\n", tmp); 665 return -EIO; 666 } 667 668 /* turn on AHCI mode */ 669 writel(HOST_AHCI_EN, mmio + HOST_CTL); 670 (void) readl(mmio + HOST_CTL); /* flush */ 671 672 /* These write-once registers are normally cleared on reset. 673 * Restore BIOS values... which we HOPE were present before 674 * reset. 675 */ 676 if (!impl_save) { 677 impl_save = (1 << ahci_nr_ports(cap_save)) - 1; 678 dev_printk(KERN_WARNING, &pdev->dev, 679 "PORTS_IMPL is zero, forcing 0x%x\n", impl_save); 680 } 681 writel(cap_save, mmio + HOST_CAP); 682 writel(impl_save, mmio + HOST_PORTS_IMPL); 683 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 684 685 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 686 u16 tmp16; 687 688 /* configure PCS */ 689 pci_read_config_word(pdev, 0x92, &tmp16); 690 tmp16 |= 0xf; 691 pci_write_config_word(pdev, 0x92, tmp16); 692 } 693 694 return 0; 695 } 696 697 static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev, 698 int n_ports, unsigned int port_flags, 699 struct ahci_host_priv *hpriv) 700 { 701 int i, rc; 702 u32 tmp; 703 704 for (i = 0; i < n_ports; i++) { 705 void __iomem *port_mmio = ahci_port_base(mmio, i); 706 const char *emsg = NULL; 707 708 if ((port_flags & AHCI_FLAG_HONOR_PI) && 709 !(hpriv->port_map & (1 << i))) 710 continue; 711 712 /* make sure port is not active */ 713 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); 714 if (rc) 715 dev_printk(KERN_WARNING, &pdev->dev, 716 "%s (%d)\n", emsg, rc); 717 718 /* clear SError */ 719 tmp = readl(port_mmio + PORT_SCR_ERR); 720 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 721 writel(tmp, port_mmio + PORT_SCR_ERR); 722 723 /* clear port IRQ */ 724 tmp = readl(port_mmio + PORT_IRQ_STAT); 725 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 726 if (tmp) 727 writel(tmp, port_mmio + PORT_IRQ_STAT); 728 729 writel(1 << i, mmio + HOST_IRQ_STAT); 730 } 731 732 tmp = readl(mmio + HOST_CTL); 733 VPRINTK("HOST_CTL 0x%x\n", tmp); 734 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 735 tmp = readl(mmio + HOST_CTL); 736 VPRINTK("HOST_CTL 0x%x\n", tmp); 737 } 738 739 static unsigned int ahci_dev_classify(struct ata_port *ap) 740 { 741 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 742 struct ata_taskfile tf; 743 u32 tmp; 744 745 tmp = readl(port_mmio + PORT_SIG); 746 tf.lbah = (tmp >> 24) & 0xff; 747 tf.lbam = (tmp >> 16) & 0xff; 748 tf.lbal = (tmp >> 8) & 0xff; 749 tf.nsect = (tmp) & 0xff; 750 751 return ata_dev_classify(&tf); 752 } 753 754 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 755 u32 opts) 756 { 757 dma_addr_t cmd_tbl_dma; 758 759 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 760 761 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 762 pp->cmd_slot[tag].status = 0; 763 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 764 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 765 } 766 767 static int ahci_clo(struct ata_port *ap) 768 { 769 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 770 struct ahci_host_priv *hpriv = ap->host->private_data; 771 u32 tmp; 772 773 if (!(hpriv->cap & HOST_CAP_CLO)) 774 return -EOPNOTSUPP; 775 776 tmp = readl(port_mmio + PORT_CMD); 777 tmp |= PORT_CMD_CLO; 778 writel(tmp, port_mmio + PORT_CMD); 779 780 tmp = ata_wait_register(port_mmio + PORT_CMD, 781 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 782 if (tmp & PORT_CMD_CLO) 783 return -EIO; 784 785 return 0; 786 } 787 788 static int ahci_softreset(struct ata_port *ap, unsigned int *class) 789 { 790 struct ahci_port_priv *pp = ap->private_data; 791 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 792 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 793 const u32 cmd_fis_len = 5; /* five dwords */ 794 const char *reason = NULL; 795 struct ata_taskfile tf; 796 u32 tmp; 797 u8 *fis; 798 int rc; 799 800 DPRINTK("ENTER\n"); 801 802 if (ata_port_offline(ap)) { 803 DPRINTK("PHY reports no device\n"); 804 *class = ATA_DEV_NONE; 805 return 0; 806 } 807 808 /* prepare for SRST (AHCI-1.1 10.4.1) */ 809 rc = ahci_stop_engine(port_mmio); 810 if (rc) { 811 reason = "failed to stop engine"; 812 goto fail_restart; 813 } 814 815 /* check BUSY/DRQ, perform Command List Override if necessary */ 816 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) { 817 rc = ahci_clo(ap); 818 819 if (rc == -EOPNOTSUPP) { 820 reason = "port busy but CLO unavailable"; 821 goto fail_restart; 822 } else if (rc) { 823 reason = "port busy but CLO failed"; 824 goto fail_restart; 825 } 826 } 827 828 /* restart engine */ 829 ahci_start_engine(port_mmio); 830 831 ata_tf_init(ap->device, &tf); 832 fis = pp->cmd_tbl; 833 834 /* issue the first D2H Register FIS */ 835 ahci_fill_cmd_slot(pp, 0, 836 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY); 837 838 tf.ctl |= ATA_SRST; 839 ata_tf_to_fis(&tf, fis, 0); 840 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ 841 842 writel(1, port_mmio + PORT_CMD_ISSUE); 843 844 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500); 845 if (tmp & 0x1) { 846 rc = -EIO; 847 reason = "1st FIS failed"; 848 goto fail; 849 } 850 851 /* spec says at least 5us, but be generous and sleep for 1ms */ 852 msleep(1); 853 854 /* issue the second D2H Register FIS */ 855 ahci_fill_cmd_slot(pp, 0, cmd_fis_len); 856 857 tf.ctl &= ~ATA_SRST; 858 ata_tf_to_fis(&tf, fis, 0); 859 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ 860 861 writel(1, port_mmio + PORT_CMD_ISSUE); 862 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 863 864 /* spec mandates ">= 2ms" before checking status. 865 * We wait 150ms, because that was the magic delay used for 866 * ATAPI devices in Hale Landis's ATADRVR, for the period of time 867 * between when the ATA command register is written, and then 868 * status is checked. Because waiting for "a while" before 869 * checking status is fine, post SRST, we perform this magic 870 * delay here as well. 871 */ 872 msleep(150); 873 874 *class = ATA_DEV_NONE; 875 if (ata_port_online(ap)) { 876 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) { 877 rc = -EIO; 878 reason = "device not ready"; 879 goto fail; 880 } 881 *class = ahci_dev_classify(ap); 882 } 883 884 DPRINTK("EXIT, class=%u\n", *class); 885 return 0; 886 887 fail_restart: 888 ahci_start_engine(port_mmio); 889 fail: 890 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); 891 return rc; 892 } 893 894 static int ahci_hardreset(struct ata_port *ap, unsigned int *class) 895 { 896 struct ahci_port_priv *pp = ap->private_data; 897 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 898 struct ata_taskfile tf; 899 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 900 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 901 int rc; 902 903 DPRINTK("ENTER\n"); 904 905 ahci_stop_engine(port_mmio); 906 907 /* clear D2H reception area to properly wait for D2H FIS */ 908 ata_tf_init(ap->device, &tf); 909 tf.command = 0x80; 910 ata_tf_to_fis(&tf, d2h_fis, 0); 911 912 rc = sata_std_hardreset(ap, class); 913 914 ahci_start_engine(port_mmio); 915 916 if (rc == 0 && ata_port_online(ap)) 917 *class = ahci_dev_classify(ap); 918 if (*class == ATA_DEV_UNKNOWN) 919 *class = ATA_DEV_NONE; 920 921 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 922 return rc; 923 } 924 925 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class) 926 { 927 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 928 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 929 int rc; 930 931 DPRINTK("ENTER\n"); 932 933 ahci_stop_engine(port_mmio); 934 935 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context)); 936 937 /* vt8251 needs SError cleared for the port to operate */ 938 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR)); 939 940 ahci_start_engine(port_mmio); 941 942 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 943 944 /* vt8251 doesn't clear BSY on signature FIS reception, 945 * request follow-up softreset. 946 */ 947 return rc ?: -EAGAIN; 948 } 949 950 static void ahci_postreset(struct ata_port *ap, unsigned int *class) 951 { 952 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 953 u32 new_tmp, tmp; 954 955 ata_std_postreset(ap, class); 956 957 /* Make sure port's ATAPI bit is set appropriately */ 958 new_tmp = tmp = readl(port_mmio + PORT_CMD); 959 if (*class == ATA_DEV_ATAPI) 960 new_tmp |= PORT_CMD_ATAPI; 961 else 962 new_tmp &= ~PORT_CMD_ATAPI; 963 if (new_tmp != tmp) { 964 writel(new_tmp, port_mmio + PORT_CMD); 965 readl(port_mmio + PORT_CMD); /* flush */ 966 } 967 } 968 969 static u8 ahci_check_status(struct ata_port *ap) 970 { 971 void __iomem *mmio = ap->ioaddr.cmd_addr; 972 973 return readl(mmio + PORT_TFDATA) & 0xFF; 974 } 975 976 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 977 { 978 struct ahci_port_priv *pp = ap->private_data; 979 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 980 981 ata_tf_from_fis(d2h_fis, tf); 982 } 983 984 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 985 { 986 struct scatterlist *sg; 987 struct ahci_sg *ahci_sg; 988 unsigned int n_sg = 0; 989 990 VPRINTK("ENTER\n"); 991 992 /* 993 * Next, the S/G list. 994 */ 995 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 996 ata_for_each_sg(sg, qc) { 997 dma_addr_t addr = sg_dma_address(sg); 998 u32 sg_len = sg_dma_len(sg); 999 1000 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); 1001 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 1002 ahci_sg->flags_size = cpu_to_le32(sg_len - 1); 1003 1004 ahci_sg++; 1005 n_sg++; 1006 } 1007 1008 return n_sg; 1009 } 1010 1011 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1012 { 1013 struct ata_port *ap = qc->ap; 1014 struct ahci_port_priv *pp = ap->private_data; 1015 int is_atapi = is_atapi_taskfile(&qc->tf); 1016 void *cmd_tbl; 1017 u32 opts; 1018 const u32 cmd_fis_len = 5; /* five dwords */ 1019 unsigned int n_elem; 1020 1021 /* 1022 * Fill in command table information. First, the header, 1023 * a SATA Register - Host to Device command FIS. 1024 */ 1025 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1026 1027 ata_tf_to_fis(&qc->tf, cmd_tbl, 0); 1028 if (is_atapi) { 1029 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1030 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1031 } 1032 1033 n_elem = 0; 1034 if (qc->flags & ATA_QCFLAG_DMAMAP) 1035 n_elem = ahci_fill_sg(qc, cmd_tbl); 1036 1037 /* 1038 * Fill in command slot information. 1039 */ 1040 opts = cmd_fis_len | n_elem << 16; 1041 if (qc->tf.flags & ATA_TFLAG_WRITE) 1042 opts |= AHCI_CMD_WRITE; 1043 if (is_atapi) 1044 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1045 1046 ahci_fill_cmd_slot(pp, qc->tag, opts); 1047 } 1048 1049 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1050 { 1051 struct ahci_port_priv *pp = ap->private_data; 1052 struct ata_eh_info *ehi = &ap->eh_info; 1053 unsigned int err_mask = 0, action = 0; 1054 struct ata_queued_cmd *qc; 1055 u32 serror; 1056 1057 ata_ehi_clear_desc(ehi); 1058 1059 /* AHCI needs SError cleared; otherwise, it might lock up */ 1060 serror = ahci_scr_read(ap, SCR_ERROR); 1061 ahci_scr_write(ap, SCR_ERROR, serror); 1062 1063 /* analyze @irq_stat */ 1064 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); 1065 1066 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1067 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR) 1068 irq_stat &= ~PORT_IRQ_IF_ERR; 1069 1070 if (irq_stat & PORT_IRQ_TF_ERR) 1071 err_mask |= AC_ERR_DEV; 1072 1073 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1074 err_mask |= AC_ERR_HOST_BUS; 1075 action |= ATA_EH_SOFTRESET; 1076 } 1077 1078 if (irq_stat & PORT_IRQ_IF_ERR) { 1079 err_mask |= AC_ERR_ATA_BUS; 1080 action |= ATA_EH_SOFTRESET; 1081 ata_ehi_push_desc(ehi, ", interface fatal error"); 1082 } 1083 1084 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1085 ata_ehi_hotplugged(ehi); 1086 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ? 1087 "connection status changed" : "PHY RDY changed"); 1088 } 1089 1090 if (irq_stat & PORT_IRQ_UNK_FIS) { 1091 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); 1092 1093 err_mask |= AC_ERR_HSM; 1094 action |= ATA_EH_SOFTRESET; 1095 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x", 1096 unk[0], unk[1], unk[2], unk[3]); 1097 } 1098 1099 /* okay, let's hand over to EH */ 1100 ehi->serror |= serror; 1101 ehi->action |= action; 1102 1103 qc = ata_qc_from_tag(ap, ap->active_tag); 1104 if (qc) 1105 qc->err_mask |= err_mask; 1106 else 1107 ehi->err_mask |= err_mask; 1108 1109 if (irq_stat & PORT_IRQ_FREEZE) 1110 ata_port_freeze(ap); 1111 else 1112 ata_port_abort(ap); 1113 } 1114 1115 static void ahci_host_intr(struct ata_port *ap) 1116 { 1117 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1118 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 1119 struct ata_eh_info *ehi = &ap->eh_info; 1120 struct ahci_port_priv *pp = ap->private_data; 1121 u32 status, qc_active; 1122 int rc, known_irq = 0; 1123 1124 status = readl(port_mmio + PORT_IRQ_STAT); 1125 writel(status, port_mmio + PORT_IRQ_STAT); 1126 1127 if (unlikely(status & PORT_IRQ_ERROR)) { 1128 ahci_error_intr(ap, status); 1129 return; 1130 } 1131 1132 if (ap->sactive) 1133 qc_active = readl(port_mmio + PORT_SCR_ACT); 1134 else 1135 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1136 1137 rc = ata_qc_complete_multiple(ap, qc_active, NULL); 1138 if (rc > 0) 1139 return; 1140 if (rc < 0) { 1141 ehi->err_mask |= AC_ERR_HSM; 1142 ehi->action |= ATA_EH_SOFTRESET; 1143 ata_port_freeze(ap); 1144 return; 1145 } 1146 1147 /* hmmm... a spurious interupt */ 1148 1149 /* if !NCQ, ignore. No modern ATA device has broken HSM 1150 * implementation for non-NCQ commands. 1151 */ 1152 if (!ap->sactive) 1153 return; 1154 1155 if (status & PORT_IRQ_D2H_REG_FIS) { 1156 if (!pp->ncq_saw_d2h) 1157 ata_port_printk(ap, KERN_INFO, 1158 "D2H reg with I during NCQ, " 1159 "this message won't be printed again\n"); 1160 pp->ncq_saw_d2h = 1; 1161 known_irq = 1; 1162 } 1163 1164 if (status & PORT_IRQ_DMAS_FIS) { 1165 if (!pp->ncq_saw_dmas) 1166 ata_port_printk(ap, KERN_INFO, 1167 "DMAS FIS during NCQ, " 1168 "this message won't be printed again\n"); 1169 pp->ncq_saw_dmas = 1; 1170 known_irq = 1; 1171 } 1172 1173 if (status & PORT_IRQ_SDB_FIS) { 1174 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1175 1176 if (le32_to_cpu(f[1])) { 1177 /* SDB FIS containing spurious completions 1178 * might be dangerous, whine and fail commands 1179 * with HSM violation. EH will turn off NCQ 1180 * after several such failures. 1181 */ 1182 ata_ehi_push_desc(ehi, 1183 "spurious completions during NCQ " 1184 "issue=0x%x SAct=0x%x FIS=%08x:%08x", 1185 readl(port_mmio + PORT_CMD_ISSUE), 1186 readl(port_mmio + PORT_SCR_ACT), 1187 le32_to_cpu(f[0]), le32_to_cpu(f[1])); 1188 ehi->err_mask |= AC_ERR_HSM; 1189 ehi->action |= ATA_EH_SOFTRESET; 1190 ata_port_freeze(ap); 1191 } else { 1192 if (!pp->ncq_saw_sdb) 1193 ata_port_printk(ap, KERN_INFO, 1194 "spurious SDB FIS %08x:%08x during NCQ, " 1195 "this message won't be printed again\n", 1196 le32_to_cpu(f[0]), le32_to_cpu(f[1])); 1197 pp->ncq_saw_sdb = 1; 1198 } 1199 known_irq = 1; 1200 } 1201 1202 if (!known_irq) 1203 ata_port_printk(ap, KERN_INFO, "spurious interrupt " 1204 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n", 1205 status, ap->active_tag, ap->sactive); 1206 } 1207 1208 static void ahci_irq_clear(struct ata_port *ap) 1209 { 1210 /* TODO */ 1211 } 1212 1213 static irqreturn_t ahci_interrupt(int irq, void *dev_instance) 1214 { 1215 struct ata_host *host = dev_instance; 1216 struct ahci_host_priv *hpriv; 1217 unsigned int i, handled = 0; 1218 void __iomem *mmio; 1219 u32 irq_stat, irq_ack = 0; 1220 1221 VPRINTK("ENTER\n"); 1222 1223 hpriv = host->private_data; 1224 mmio = host->iomap[AHCI_PCI_BAR]; 1225 1226 /* sigh. 0xffffffff is a valid return from h/w */ 1227 irq_stat = readl(mmio + HOST_IRQ_STAT); 1228 irq_stat &= hpriv->port_map; 1229 if (!irq_stat) 1230 return IRQ_NONE; 1231 1232 spin_lock(&host->lock); 1233 1234 for (i = 0; i < host->n_ports; i++) { 1235 struct ata_port *ap; 1236 1237 if (!(irq_stat & (1 << i))) 1238 continue; 1239 1240 ap = host->ports[i]; 1241 if (ap) { 1242 ahci_host_intr(ap); 1243 VPRINTK("port %u\n", i); 1244 } else { 1245 VPRINTK("port %u (no irq)\n", i); 1246 if (ata_ratelimit()) 1247 dev_printk(KERN_WARNING, host->dev, 1248 "interrupt on disabled port %u\n", i); 1249 } 1250 1251 irq_ack |= (1 << i); 1252 } 1253 1254 if (irq_ack) { 1255 writel(irq_ack, mmio + HOST_IRQ_STAT); 1256 handled = 1; 1257 } 1258 1259 spin_unlock(&host->lock); 1260 1261 VPRINTK("EXIT\n"); 1262 1263 return IRQ_RETVAL(handled); 1264 } 1265 1266 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1267 { 1268 struct ata_port *ap = qc->ap; 1269 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 1270 1271 if (qc->tf.protocol == ATA_PROT_NCQ) 1272 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1273 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 1274 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1275 1276 return 0; 1277 } 1278 1279 static void ahci_freeze(struct ata_port *ap) 1280 { 1281 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1282 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 1283 1284 /* turn IRQ off */ 1285 writel(0, port_mmio + PORT_IRQ_MASK); 1286 } 1287 1288 static void ahci_thaw(struct ata_port *ap) 1289 { 1290 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1291 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 1292 u32 tmp; 1293 1294 /* clear IRQ */ 1295 tmp = readl(port_mmio + PORT_IRQ_STAT); 1296 writel(tmp, port_mmio + PORT_IRQ_STAT); 1297 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 1298 1299 /* turn IRQ back on */ 1300 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); 1301 } 1302 1303 static void ahci_error_handler(struct ata_port *ap) 1304 { 1305 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1306 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 1307 1308 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1309 /* restart engine */ 1310 ahci_stop_engine(port_mmio); 1311 ahci_start_engine(port_mmio); 1312 } 1313 1314 /* perform recovery */ 1315 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset, 1316 ahci_postreset); 1317 } 1318 1319 static void ahci_vt8251_error_handler(struct ata_port *ap) 1320 { 1321 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1322 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 1323 1324 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1325 /* restart engine */ 1326 ahci_stop_engine(port_mmio); 1327 ahci_start_engine(port_mmio); 1328 } 1329 1330 /* perform recovery */ 1331 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, 1332 ahci_postreset); 1333 } 1334 1335 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 1336 { 1337 struct ata_port *ap = qc->ap; 1338 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1339 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 1340 1341 if (qc->flags & ATA_QCFLAG_FAILED) 1342 qc->err_mask |= AC_ERR_OTHER; 1343 1344 if (qc->err_mask) { 1345 /* make DMA engine forget about the failed command */ 1346 ahci_stop_engine(port_mmio); 1347 ahci_start_engine(port_mmio); 1348 } 1349 } 1350 1351 #ifdef CONFIG_PM 1352 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 1353 { 1354 struct ahci_host_priv *hpriv = ap->host->private_data; 1355 struct ahci_port_priv *pp = ap->private_data; 1356 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1357 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 1358 const char *emsg = NULL; 1359 int rc; 1360 1361 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); 1362 if (rc == 0) 1363 ahci_power_down(port_mmio, hpriv->cap); 1364 else { 1365 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); 1366 ahci_init_port(port_mmio, hpriv->cap, 1367 pp->cmd_slot_dma, pp->rx_fis_dma); 1368 } 1369 1370 return rc; 1371 } 1372 1373 static int ahci_port_resume(struct ata_port *ap) 1374 { 1375 struct ahci_port_priv *pp = ap->private_data; 1376 struct ahci_host_priv *hpriv = ap->host->private_data; 1377 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1378 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 1379 1380 ahci_power_up(port_mmio, hpriv->cap); 1381 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma); 1382 1383 return 0; 1384 } 1385 1386 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 1387 { 1388 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1389 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 1390 u32 ctl; 1391 1392 if (mesg.event == PM_EVENT_SUSPEND) { 1393 /* AHCI spec rev1.1 section 8.3.3: 1394 * Software must disable interrupts prior to requesting a 1395 * transition of the HBA to D3 state. 1396 */ 1397 ctl = readl(mmio + HOST_CTL); 1398 ctl &= ~HOST_IRQ_EN; 1399 writel(ctl, mmio + HOST_CTL); 1400 readl(mmio + HOST_CTL); /* flush */ 1401 } 1402 1403 return ata_pci_device_suspend(pdev, mesg); 1404 } 1405 1406 static int ahci_pci_device_resume(struct pci_dev *pdev) 1407 { 1408 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1409 struct ahci_host_priv *hpriv = host->private_data; 1410 void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; 1411 int rc; 1412 1413 rc = ata_pci_device_do_resume(pdev); 1414 if (rc) 1415 return rc; 1416 1417 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 1418 rc = ahci_reset_controller(mmio, pdev); 1419 if (rc) 1420 return rc; 1421 1422 ahci_init_controller(mmio, pdev, host->n_ports, 1423 host->ports[0]->flags, hpriv); 1424 } 1425 1426 ata_host_resume(host); 1427 1428 return 0; 1429 } 1430 #endif 1431 1432 static int ahci_port_start(struct ata_port *ap) 1433 { 1434 struct device *dev = ap->host->dev; 1435 struct ahci_host_priv *hpriv = ap->host->private_data; 1436 struct ahci_port_priv *pp; 1437 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1438 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 1439 void *mem; 1440 dma_addr_t mem_dma; 1441 int rc; 1442 1443 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1444 if (!pp) 1445 return -ENOMEM; 1446 1447 rc = ata_pad_alloc(ap, dev); 1448 if (rc) 1449 return rc; 1450 1451 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, 1452 GFP_KERNEL); 1453 if (!mem) 1454 return -ENOMEM; 1455 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); 1456 1457 /* 1458 * First item in chunk of DMA memory: 32-slot command table, 1459 * 32 bytes each in size 1460 */ 1461 pp->cmd_slot = mem; 1462 pp->cmd_slot_dma = mem_dma; 1463 1464 mem += AHCI_CMD_SLOT_SZ; 1465 mem_dma += AHCI_CMD_SLOT_SZ; 1466 1467 /* 1468 * Second item: Received-FIS area 1469 */ 1470 pp->rx_fis = mem; 1471 pp->rx_fis_dma = mem_dma; 1472 1473 mem += AHCI_RX_FIS_SZ; 1474 mem_dma += AHCI_RX_FIS_SZ; 1475 1476 /* 1477 * Third item: data area for storing a single command 1478 * and its scatter-gather table 1479 */ 1480 pp->cmd_tbl = mem; 1481 pp->cmd_tbl_dma = mem_dma; 1482 1483 ap->private_data = pp; 1484 1485 /* power up port */ 1486 ahci_power_up(port_mmio, hpriv->cap); 1487 1488 /* initialize port */ 1489 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma); 1490 1491 return 0; 1492 } 1493 1494 static void ahci_port_stop(struct ata_port *ap) 1495 { 1496 struct ahci_host_priv *hpriv = ap->host->private_data; 1497 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1498 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 1499 const char *emsg = NULL; 1500 int rc; 1501 1502 /* de-initialize port */ 1503 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); 1504 if (rc) 1505 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); 1506 } 1507 1508 static void ahci_setup_port(struct ata_ioports *port, void __iomem *base, 1509 unsigned int port_idx) 1510 { 1511 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx); 1512 base = ahci_port_base(base, port_idx); 1513 VPRINTK("base now==0x%lx\n", base); 1514 1515 port->cmd_addr = base; 1516 port->scr_addr = base + PORT_SCR; 1517 1518 VPRINTK("EXIT\n"); 1519 } 1520 1521 static int ahci_host_init(struct ata_probe_ent *probe_ent) 1522 { 1523 struct ahci_host_priv *hpriv = probe_ent->private_data; 1524 struct pci_dev *pdev = to_pci_dev(probe_ent->dev); 1525 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR]; 1526 unsigned int i, cap_n_ports, using_dac; 1527 int rc; 1528 1529 rc = ahci_reset_controller(mmio, pdev); 1530 if (rc) 1531 return rc; 1532 1533 hpriv->cap = readl(mmio + HOST_CAP); 1534 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL); 1535 cap_n_ports = ahci_nr_ports(hpriv->cap); 1536 1537 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n", 1538 hpriv->cap, hpriv->port_map, cap_n_ports); 1539 1540 if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) { 1541 unsigned int n_ports = cap_n_ports; 1542 u32 port_map = hpriv->port_map; 1543 int max_port = 0; 1544 1545 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { 1546 if (port_map & (1 << i)) { 1547 n_ports--; 1548 port_map &= ~(1 << i); 1549 max_port = i; 1550 } else 1551 probe_ent->dummy_port_mask |= 1 << i; 1552 } 1553 1554 if (n_ports || port_map) 1555 dev_printk(KERN_WARNING, &pdev->dev, 1556 "nr_ports (%u) and implemented port map " 1557 "(0x%x) don't match\n", 1558 cap_n_ports, hpriv->port_map); 1559 1560 probe_ent->n_ports = max_port + 1; 1561 } else 1562 probe_ent->n_ports = cap_n_ports; 1563 1564 using_dac = hpriv->cap & HOST_CAP_64; 1565 if (using_dac && 1566 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 1567 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 1568 if (rc) { 1569 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1570 if (rc) { 1571 dev_printk(KERN_ERR, &pdev->dev, 1572 "64-bit DMA enable failed\n"); 1573 return rc; 1574 } 1575 } 1576 } else { 1577 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1578 if (rc) { 1579 dev_printk(KERN_ERR, &pdev->dev, 1580 "32-bit DMA enable failed\n"); 1581 return rc; 1582 } 1583 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1584 if (rc) { 1585 dev_printk(KERN_ERR, &pdev->dev, 1586 "32-bit consistent DMA enable failed\n"); 1587 return rc; 1588 } 1589 } 1590 1591 for (i = 0; i < probe_ent->n_ports; i++) 1592 ahci_setup_port(&probe_ent->port[i], mmio, i); 1593 1594 ahci_init_controller(mmio, pdev, probe_ent->n_ports, 1595 probe_ent->port_flags, hpriv); 1596 1597 pci_set_master(pdev); 1598 1599 return 0; 1600 } 1601 1602 static void ahci_print_info(struct ata_probe_ent *probe_ent) 1603 { 1604 struct ahci_host_priv *hpriv = probe_ent->private_data; 1605 struct pci_dev *pdev = to_pci_dev(probe_ent->dev); 1606 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR]; 1607 u32 vers, cap, impl, speed; 1608 const char *speed_s; 1609 u16 cc; 1610 const char *scc_s; 1611 1612 vers = readl(mmio + HOST_VERSION); 1613 cap = hpriv->cap; 1614 impl = hpriv->port_map; 1615 1616 speed = (cap >> 20) & 0xf; 1617 if (speed == 1) 1618 speed_s = "1.5"; 1619 else if (speed == 2) 1620 speed_s = "3"; 1621 else 1622 speed_s = "?"; 1623 1624 pci_read_config_word(pdev, 0x0a, &cc); 1625 if (cc == PCI_CLASS_STORAGE_IDE) 1626 scc_s = "IDE"; 1627 else if (cc == PCI_CLASS_STORAGE_SATA) 1628 scc_s = "SATA"; 1629 else if (cc == PCI_CLASS_STORAGE_RAID) 1630 scc_s = "RAID"; 1631 else 1632 scc_s = "unknown"; 1633 1634 dev_printk(KERN_INFO, &pdev->dev, 1635 "AHCI %02x%02x.%02x%02x " 1636 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 1637 , 1638 1639 (vers >> 24) & 0xff, 1640 (vers >> 16) & 0xff, 1641 (vers >> 8) & 0xff, 1642 vers & 0xff, 1643 1644 ((cap >> 8) & 0x1f) + 1, 1645 (cap & 0x1f) + 1, 1646 speed_s, 1647 impl, 1648 scc_s); 1649 1650 dev_printk(KERN_INFO, &pdev->dev, 1651 "flags: " 1652 "%s%s%s%s%s%s" 1653 "%s%s%s%s%s%s%s\n" 1654 , 1655 1656 cap & (1 << 31) ? "64bit " : "", 1657 cap & (1 << 30) ? "ncq " : "", 1658 cap & (1 << 28) ? "ilck " : "", 1659 cap & (1 << 27) ? "stag " : "", 1660 cap & (1 << 26) ? "pm " : "", 1661 cap & (1 << 25) ? "led " : "", 1662 1663 cap & (1 << 24) ? "clo " : "", 1664 cap & (1 << 19) ? "nz " : "", 1665 cap & (1 << 18) ? "only " : "", 1666 cap & (1 << 17) ? "pmp " : "", 1667 cap & (1 << 15) ? "pio " : "", 1668 cap & (1 << 14) ? "slum " : "", 1669 cap & (1 << 13) ? "part " : "" 1670 ); 1671 } 1672 1673 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1674 { 1675 static int printed_version; 1676 unsigned int board_idx = (unsigned int) ent->driver_data; 1677 struct device *dev = &pdev->dev; 1678 struct ata_probe_ent *probe_ent; 1679 struct ahci_host_priv *hpriv; 1680 int rc; 1681 1682 VPRINTK("ENTER\n"); 1683 1684 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1685 1686 if (!printed_version++) 1687 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1688 1689 rc = pcim_enable_device(pdev); 1690 if (rc) 1691 return rc; 1692 1693 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); 1694 if (rc == -EBUSY) 1695 pcim_pin_device(pdev); 1696 if (rc) 1697 return rc; 1698 1699 if (pci_enable_msi(pdev)) 1700 pci_intx(pdev, 1); 1701 1702 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); 1703 if (probe_ent == NULL) 1704 return -ENOMEM; 1705 1706 probe_ent->dev = pci_dev_to_dev(pdev); 1707 INIT_LIST_HEAD(&probe_ent->node); 1708 1709 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1710 if (!hpriv) 1711 return -ENOMEM; 1712 1713 probe_ent->sht = ahci_port_info[board_idx].sht; 1714 probe_ent->port_flags = ahci_port_info[board_idx].flags; 1715 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask; 1716 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask; 1717 probe_ent->port_ops = ahci_port_info[board_idx].port_ops; 1718 1719 probe_ent->irq = pdev->irq; 1720 probe_ent->irq_flags = IRQF_SHARED; 1721 probe_ent->iomap = pcim_iomap_table(pdev); 1722 probe_ent->private_data = hpriv; 1723 1724 /* initialize adapter */ 1725 rc = ahci_host_init(probe_ent); 1726 if (rc) 1727 return rc; 1728 1729 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) && 1730 (hpriv->cap & HOST_CAP_NCQ)) 1731 probe_ent->port_flags |= ATA_FLAG_NCQ; 1732 1733 ahci_print_info(probe_ent); 1734 1735 if (!ata_device_add(probe_ent)) 1736 return -ENODEV; 1737 1738 devm_kfree(dev, probe_ent); 1739 return 0; 1740 } 1741 1742 static int __init ahci_init(void) 1743 { 1744 return pci_register_driver(&ahci_pci_driver); 1745 } 1746 1747 static void __exit ahci_exit(void) 1748 { 1749 pci_unregister_driver(&ahci_pci_driver); 1750 } 1751 1752 1753 MODULE_AUTHOR("Jeff Garzik"); 1754 MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1755 MODULE_LICENSE("GPL"); 1756 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1757 MODULE_VERSION(DRV_VERSION); 1758 1759 module_init(ahci_init); 1760 module_exit(ahci_exit); 1761