1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2025 Intel Corporation 4 */ 5 6 #include <linux/firmware.h> 7 #include <linux/highmem.h> 8 #include <linux/moduleparam.h> 9 #include <linux/pci.h> 10 11 #include "vpu_boot_api.h" 12 #include "ivpu_drv.h" 13 #include "ivpu_fw.h" 14 #include "ivpu_fw_log.h" 15 #include "ivpu_gem.h" 16 #include "ivpu_hw.h" 17 #include "ivpu_ipc.h" 18 #include "ivpu_pm.h" 19 20 #define FW_SHAVE_NN_MAX_SIZE SZ_2M 21 #define FW_FILE_IMAGE_OFFSET (VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE) 22 #define FW_PREEMPT_BUF_MIN_SIZE SZ_4K 23 #define FW_PREEMPT_BUF_MAX_SIZE SZ_32M 24 25 #define WATCHDOG_MSS_REDIRECT 32 26 #define WATCHDOG_NCE_REDIRECT 33 27 28 #define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31) 29 30 /* Check if FW API is compatible with the driver */ 31 #define IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, name, min_major) \ 32 ivpu_fw_check_api(vdev, fw_hdr, #name, \ 33 VPU_##name##_API_VER_INDEX, \ 34 VPU_##name##_API_VER_MAJOR, \ 35 VPU_##name##_API_VER_MINOR, min_major) 36 37 /* Check if API version is lower that the given version */ 38 #define IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, name, major, minor) \ 39 ivpu_fw_check_api_ver_lt(vdev, fw_hdr, #name, VPU_##name##_API_VER_INDEX, major, minor) 40 41 #define IVPU_FOCUS_PRESENT_TIMER_MS 1000 42 43 static char *ivpu_firmware; 44 #if IS_ENABLED(CONFIG_DRM_ACCEL_IVPU_DEBUG) 45 module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644); 46 MODULE_PARM_DESC(firmware, "NPU firmware binary in /lib/firmware/.."); 47 #endif 48 49 static struct { 50 int gen; 51 const char *name; 52 } fw_names[] = { 53 { IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v1.bin" }, 54 { IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v0.0.bin" }, 55 { IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v1.bin" }, 56 { IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v0.0.bin" }, 57 { IVPU_HW_IP_50XX, "intel/vpu/vpu_50xx_v1.bin" }, 58 { IVPU_HW_IP_50XX, "intel/vpu/vpu_50xx_v0.0.bin" }, 59 }; 60 61 /* Production fw_names from the table above */ 62 MODULE_FIRMWARE("intel/vpu/vpu_37xx_v1.bin"); 63 MODULE_FIRMWARE("intel/vpu/vpu_40xx_v1.bin"); 64 MODULE_FIRMWARE("intel/vpu/vpu_50xx_v1.bin"); 65 66 static int ivpu_fw_request(struct ivpu_device *vdev) 67 { 68 int ret = -ENOENT; 69 int i; 70 71 if (ivpu_firmware) { 72 ret = request_firmware(&vdev->fw->file, ivpu_firmware, vdev->drm.dev); 73 if (!ret) 74 vdev->fw->name = ivpu_firmware; 75 return ret; 76 } 77 78 for (i = 0; i < ARRAY_SIZE(fw_names); i++) { 79 if (fw_names[i].gen != ivpu_hw_ip_gen(vdev)) 80 continue; 81 82 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i].name, vdev->drm.dev); 83 if (!ret) { 84 vdev->fw->name = fw_names[i].name; 85 return 0; 86 } 87 } 88 89 ivpu_err(vdev, "Failed to request firmware: %d\n", ret); 90 return ret; 91 } 92 93 static int 94 ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, 95 const char *str, int index, u16 expected_major, u16 expected_minor, 96 u16 min_major) 97 { 98 u16 major = (u16)(fw_hdr->api_version[index] >> 16); 99 u16 minor = (u16)(fw_hdr->api_version[index]); 100 101 if (major < min_major) { 102 ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n", 103 str, major, minor, min_major); 104 return -EINVAL; 105 } 106 if (major != expected_major) { 107 ivpu_warn(vdev, "Major FW %s API version different: %d.%d (expected %d.%d)\n", 108 str, major, minor, expected_major, expected_minor); 109 } 110 ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n", 111 str, major, minor, expected_major, expected_minor); 112 113 return 0; 114 } 115 116 static bool 117 ivpu_fw_check_api_ver_lt(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, 118 const char *str, int index, u16 major, u16 minor) 119 { 120 u16 fw_major = (u16)(fw_hdr->api_version[index] >> 16); 121 u16 fw_minor = (u16)(fw_hdr->api_version[index]); 122 123 if (fw_major < major || (fw_major == major && fw_minor < minor)) 124 return true; 125 126 return false; 127 } 128 129 bool ivpu_is_within_range(u64 addr, size_t size, struct ivpu_addr_range *range) 130 { 131 u64 addr_end; 132 133 if (!range || check_add_overflow(addr, size, &addr_end)) 134 return false; 135 136 if (addr < range->start || addr_end > range->end) 137 return false; 138 139 return true; 140 } 141 142 static u32 143 ivpu_fw_sched_mode_select(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr) 144 { 145 if (ivpu_sched_mode != IVPU_SCHED_MODE_AUTO) 146 return ivpu_sched_mode; 147 148 if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, JSM, 3, 24)) 149 return VPU_SCHEDULING_MODE_OS; 150 151 return VPU_SCHEDULING_MODE_HW; 152 } 153 154 static void 155 ivpu_preemption_config_parse(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr) 156 { 157 struct ivpu_fw_info *fw = vdev->fw; 158 u32 primary_preempt_buf_size, secondary_preempt_buf_size; 159 160 if (fw_hdr->preemption_buffer_1_max_size) 161 primary_preempt_buf_size = fw_hdr->preemption_buffer_1_max_size; 162 else 163 primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size; 164 165 if (fw_hdr->preemption_buffer_2_max_size) 166 secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_max_size; 167 else 168 secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size; 169 170 ivpu_dbg(vdev, FW_BOOT, "Preemption buffer size, primary: %u, secondary: %u\n", 171 primary_preempt_buf_size, secondary_preempt_buf_size); 172 173 if (primary_preempt_buf_size < FW_PREEMPT_BUF_MIN_SIZE || 174 secondary_preempt_buf_size < FW_PREEMPT_BUF_MIN_SIZE) { 175 ivpu_warn(vdev, "Preemption buffers size too small\n"); 176 return; 177 } 178 179 if (primary_preempt_buf_size > FW_PREEMPT_BUF_MAX_SIZE || 180 secondary_preempt_buf_size > FW_PREEMPT_BUF_MAX_SIZE) { 181 ivpu_warn(vdev, "Preemption buffers size too big\n"); 182 return; 183 } 184 185 if (fw->sched_mode != VPU_SCHEDULING_MODE_HW) 186 return; 187 188 if (ivpu_test_mode & IVPU_TEST_MODE_MIP_DISABLE) 189 return; 190 191 vdev->fw->primary_preempt_buf_size = ALIGN(primary_preempt_buf_size, PAGE_SIZE); 192 vdev->fw->secondary_preempt_buf_size = ALIGN(secondary_preempt_buf_size, PAGE_SIZE); 193 } 194 195 static int ivpu_fw_parse(struct ivpu_device *vdev) 196 { 197 struct ivpu_fw_info *fw = vdev->fw; 198 const struct vpu_firmware_header *fw_hdr = (const void *)fw->file->data; 199 struct ivpu_addr_range fw_image_range; 200 u64 boot_params_addr, boot_params_size; 201 u64 fw_version_addr, fw_version_size; 202 u64 runtime_addr, runtime_size; 203 u64 image_load_addr, image_size; 204 205 if (fw->file->size <= FW_FILE_IMAGE_OFFSET) { 206 ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size); 207 return -EINVAL; 208 } 209 210 if (fw_hdr->header_version != VPU_FW_HEADER_VERSION) { 211 ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version); 212 return -EINVAL; 213 } 214 215 boot_params_addr = fw_hdr->boot_params_load_address; 216 boot_params_size = SZ_4K; 217 218 if (!ivpu_is_within_range(boot_params_addr, boot_params_size, &vdev->hw->ranges.runtime)) { 219 ivpu_err(vdev, "Invalid boot params address: 0x%llx\n", boot_params_addr); 220 return -EINVAL; 221 } 222 223 fw_version_addr = fw_hdr->firmware_version_load_address; 224 fw_version_size = ALIGN(fw_hdr->firmware_version_size, SZ_4K); 225 226 if (fw_version_size != SZ_4K) { 227 ivpu_err(vdev, "Invalid firmware version size: %u\n", 228 fw_hdr->firmware_version_size); 229 return -EINVAL; 230 } 231 232 if (!ivpu_is_within_range(fw_version_addr, fw_version_size, &vdev->hw->ranges.runtime)) { 233 ivpu_err(vdev, "Invalid firmware version address: 0x%llx\n", fw_version_addr); 234 return -EINVAL; 235 } 236 237 runtime_addr = fw_hdr->image_load_address; 238 runtime_size = fw_hdr->runtime_size - boot_params_size - fw_version_size; 239 240 image_load_addr = fw_hdr->image_load_address; 241 image_size = fw_hdr->image_size; 242 243 if (!ivpu_is_within_range(runtime_addr, runtime_size, &vdev->hw->ranges.runtime)) { 244 ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx and size %llu\n", 245 runtime_addr, runtime_size); 246 return -EINVAL; 247 } 248 249 if (FW_FILE_IMAGE_OFFSET + image_size > fw->file->size) { 250 ivpu_err(vdev, "Invalid image size: %llu\n", image_size); 251 return -EINVAL; 252 } 253 254 if (!ivpu_is_within_range(image_load_addr, image_size, &vdev->hw->ranges.runtime)) { 255 ivpu_err(vdev, "Invalid firmware load address: 0x%llx and size %llu\n", 256 image_load_addr, image_size); 257 return -EINVAL; 258 } 259 260 if (ivpu_hw_range_init(vdev, &fw_image_range, image_load_addr, image_size)) 261 return -EINVAL; 262 263 if (!ivpu_is_within_range(fw_hdr->entry_point, SZ_4K, &fw_image_range)) { 264 ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point); 265 return -EINVAL; 266 } 267 268 if (fw_hdr->shave_nn_fw_size > FW_SHAVE_NN_MAX_SIZE) { 269 ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size); 270 return -EINVAL; 271 } 272 273 ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n", 274 fw_hdr->header_version, fw_hdr->image_format); 275 276 if (!scnprintf(fw->version, sizeof(fw->version), "%s", fw->file->data + VPU_FW_HEADER_SIZE)) 277 ivpu_warn(vdev, "Missing firmware version\n"); 278 279 ivpu_info(vdev, "Firmware: %s, version: %s\n", fw->name, fw->version); 280 281 if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, BOOT, 3)) 282 return -EINVAL; 283 if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, JSM, 3)) 284 return -EINVAL; 285 286 fw->boot_params_addr = boot_params_addr; 287 fw->boot_params_size = boot_params_size; 288 fw->fw_version_addr = fw_version_addr; 289 fw->fw_version_size = fw_version_size; 290 fw->runtime_addr = runtime_addr; 291 fw->runtime_size = runtime_size; 292 fw->image_load_offset = image_load_addr - runtime_addr; 293 fw->image_size = image_size; 294 fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size); 295 296 fw->cold_boot_entry_point = fw_hdr->entry_point; 297 fw->entry_point = fw->cold_boot_entry_point; 298 299 fw->trace_level = min_t(u32, ivpu_fw_log_level, IVPU_FW_LOG_FATAL); 300 fw->trace_destination_mask = VPU_TRACE_DESTINATION_VERBOSE_TRACING; 301 fw->trace_hw_component_mask = -1; 302 303 fw->dvfs_mode = 0; 304 305 fw->sched_mode = ivpu_fw_sched_mode_select(vdev, fw_hdr); 306 ivpu_info(vdev, "Scheduler mode: %s\n", fw->sched_mode ? "HW" : "OS"); 307 308 ivpu_preemption_config_parse(vdev, fw_hdr); 309 ivpu_dbg(vdev, FW_BOOT, "Mid-inference preemption %s supported\n", 310 ivpu_fw_preempt_buf_size(vdev) ? "is" : "is not"); 311 312 if (fw_hdr->ro_section_start_address && 313 !ivpu_is_within_range(fw_hdr->ro_section_start_address, fw_hdr->ro_section_size, 314 &fw_image_range)) { 315 ivpu_err(vdev, "Invalid read-only section: start address 0x%llx, size %u\n", 316 fw_hdr->ro_section_start_address, fw_hdr->ro_section_size); 317 return -EINVAL; 318 } 319 320 fw->read_only_addr = fw_hdr->ro_section_start_address; 321 fw->read_only_size = fw_hdr->ro_section_size; 322 323 ivpu_dbg(vdev, FW_BOOT, "Boot params: address 0x%llx, size %llu\n", 324 fw->boot_params_addr, fw->boot_params_size); 325 ivpu_dbg(vdev, FW_BOOT, "FW version: address 0x%llx, size %llu\n", 326 fw->fw_version_addr, fw->fw_version_size); 327 ivpu_dbg(vdev, FW_BOOT, "Runtime: address 0x%llx, size %u\n", 328 fw->runtime_addr, fw->runtime_size); 329 ivpu_dbg(vdev, FW_BOOT, "Image load offset: 0x%llx, size %u\n", 330 fw->image_load_offset, fw->image_size); 331 ivpu_dbg(vdev, FW_BOOT, "Read-only section: address 0x%llx, size %u\n", 332 fw->read_only_addr, fw->read_only_size); 333 ivpu_dbg(vdev, FW_BOOT, "FW entry point: 0x%llx\n", fw->entry_point); 334 ivpu_dbg(vdev, FW_BOOT, "SHAVE NN size: %u\n", fw->shave_nn_size); 335 336 return 0; 337 } 338 339 static void ivpu_fw_release(struct ivpu_device *vdev) 340 { 341 release_firmware(vdev->fw->file); 342 } 343 344 /* Initialize workarounds that depend on FW version */ 345 static void 346 ivpu_fw_init_wa(struct ivpu_device *vdev) 347 { 348 const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data; 349 350 if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) || 351 (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE)) 352 vdev->wa.disable_d0i3_msg = true; 353 354 /* Force enable the feature for testing purposes */ 355 if (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_ENABLE) 356 vdev->wa.disable_d0i3_msg = false; 357 358 IVPU_PRINT_WA(disable_d0i3_msg); 359 } 360 361 static int ivpu_fw_mem_init(struct ivpu_device *vdev) 362 { 363 struct ivpu_fw_info *fw = vdev->fw; 364 int log_verb_size; 365 int ret; 366 367 fw->mem_bp = ivpu_bo_create_runtime(vdev, fw->boot_params_addr, fw->boot_params_size, 368 DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE); 369 if (!fw->mem_bp) { 370 ivpu_err(vdev, "Failed to create firmware boot params memory buffer\n"); 371 return -ENOMEM; 372 } 373 374 fw->mem_fw_ver = ivpu_bo_create_runtime(vdev, fw->fw_version_addr, fw->fw_version_size, 375 DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE); 376 if (!fw->mem_fw_ver) { 377 ivpu_err(vdev, "Failed to create firmware version memory buffer\n"); 378 ret = -ENOMEM; 379 goto err_free_bp; 380 } 381 382 fw->mem = ivpu_bo_create_runtime(vdev, fw->runtime_addr, fw->runtime_size, 383 DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE); 384 if (!fw->mem) { 385 ivpu_err(vdev, "Failed to create firmware runtime memory buffer\n"); 386 ret = -ENOMEM; 387 goto err_free_fw_ver; 388 } 389 390 ret = ivpu_mmu_context_set_pages_ro(vdev, &vdev->gctx, fw->read_only_addr, 391 fw->read_only_size); 392 if (ret) { 393 ivpu_err(vdev, "Failed to set firmware image read-only\n"); 394 goto err_free_fw_mem; 395 } 396 397 fw->mem_log_crit = ivpu_bo_create_global(vdev, IVPU_FW_CRITICAL_BUFFER_SIZE, 398 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE); 399 if (!fw->mem_log_crit) { 400 ivpu_err(vdev, "Failed to create critical log buffer\n"); 401 ret = -ENOMEM; 402 goto err_free_fw_mem; 403 } 404 405 if (ivpu_fw_log_level <= IVPU_FW_LOG_INFO) 406 log_verb_size = IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE; 407 else 408 log_verb_size = IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE; 409 410 fw->mem_log_verb = ivpu_bo_create_global(vdev, log_verb_size, 411 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE); 412 if (!fw->mem_log_verb) { 413 ivpu_err(vdev, "Failed to create verbose log buffer\n"); 414 ret = -ENOMEM; 415 goto err_free_log_crit; 416 } 417 418 if (fw->shave_nn_size) { 419 fw->mem_shave_nn = ivpu_bo_create(vdev, &vdev->gctx, &vdev->hw->ranges.shave, 420 fw->shave_nn_size, DRM_IVPU_BO_WC); 421 if (!fw->mem_shave_nn) { 422 ivpu_err(vdev, "Failed to create shavenn buffer\n"); 423 ret = -ENOMEM; 424 goto err_free_log_verb; 425 } 426 } 427 428 return 0; 429 430 err_free_log_verb: 431 ivpu_bo_free(fw->mem_log_verb); 432 err_free_log_crit: 433 ivpu_bo_free(fw->mem_log_crit); 434 err_free_fw_mem: 435 ivpu_bo_free(fw->mem); 436 err_free_fw_ver: 437 ivpu_bo_free(fw->mem_fw_ver); 438 err_free_bp: 439 ivpu_bo_free(fw->mem_bp); 440 return ret; 441 } 442 443 static void ivpu_fw_mem_fini(struct ivpu_device *vdev) 444 { 445 struct ivpu_fw_info *fw = vdev->fw; 446 447 if (fw->mem_shave_nn) { 448 ivpu_bo_free(fw->mem_shave_nn); 449 fw->mem_shave_nn = NULL; 450 } 451 452 ivpu_bo_free(fw->mem_log_verb); 453 ivpu_bo_free(fw->mem_log_crit); 454 ivpu_bo_free(fw->mem); 455 ivpu_bo_free(fw->mem_fw_ver); 456 ivpu_bo_free(fw->mem_bp); 457 458 fw->mem_log_verb = NULL; 459 fw->mem_log_crit = NULL; 460 fw->mem = NULL; 461 fw->mem_fw_ver = NULL; 462 fw->mem_bp = NULL; 463 } 464 465 int ivpu_fw_init(struct ivpu_device *vdev) 466 { 467 int ret; 468 469 ret = ivpu_fw_request(vdev); 470 if (ret) 471 return ret; 472 473 ret = ivpu_fw_parse(vdev); 474 if (ret) 475 goto err_fw_release; 476 477 ivpu_fw_init_wa(vdev); 478 479 ret = ivpu_fw_mem_init(vdev); 480 if (ret) 481 goto err_fw_release; 482 483 ivpu_fw_load(vdev); 484 485 return 0; 486 487 err_fw_release: 488 ivpu_fw_release(vdev); 489 return ret; 490 } 491 492 void ivpu_fw_fini(struct ivpu_device *vdev) 493 { 494 ivpu_fw_mem_fini(vdev); 495 ivpu_fw_release(vdev); 496 } 497 498 void ivpu_fw_load(struct ivpu_device *vdev) 499 { 500 struct ivpu_fw_info *fw = vdev->fw; 501 u64 image_end_offset = fw->image_load_offset + fw->image_size; 502 503 memset(ivpu_bo_vaddr(fw->mem), 0, fw->image_load_offset); 504 memcpy(ivpu_bo_vaddr(fw->mem) + fw->image_load_offset, 505 fw->file->data + FW_FILE_IMAGE_OFFSET, fw->image_size); 506 507 if (IVPU_WA(clear_runtime_mem)) { 508 u8 *start = ivpu_bo_vaddr(fw->mem) + image_end_offset; 509 u64 size = ivpu_bo_size(fw->mem) - image_end_offset; 510 511 memset(start, 0, size); 512 } 513 514 wmb(); /* Flush WC buffers after writing fw->mem */ 515 } 516 517 static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 518 { 519 ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n", 520 boot_params->magic); 521 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n", 522 boot_params->vpu_id); 523 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n", 524 boot_params->vpu_count); 525 ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n", 526 boot_params->frequency); 527 ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n", 528 boot_params->perf_clk_frequency); 529 530 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n", 531 boot_params->ipc_header_area_start); 532 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n", 533 boot_params->ipc_header_area_size); 534 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n", 535 boot_params->shared_region_base); 536 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n", 537 boot_params->shared_region_size); 538 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n", 539 boot_params->ipc_payload_area_start); 540 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n", 541 boot_params->ipc_payload_area_size); 542 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n", 543 boot_params->global_aliased_pio_base); 544 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n", 545 boot_params->global_aliased_pio_size); 546 547 ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n", 548 boot_params->autoconfig); 549 550 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n", 551 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use); 552 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n", 553 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg); 554 555 ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n", 556 boot_params->shave_nn_fw_base); 557 558 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n", 559 boot_params->watchdog_irq_mss); 560 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n", 561 boot_params->watchdog_irq_nce); 562 563 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n", 564 boot_params->host_version_id); 565 ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n", 566 boot_params->si_stepping); 567 ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n", 568 boot_params->device_id); 569 ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n", 570 boot_params->feature_exclusion); 571 ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n", 572 boot_params->sku); 573 ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n", 574 boot_params->min_freq_pll_ratio); 575 ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n", 576 boot_params->pn_freq_pll_ratio); 577 ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n", 578 boot_params->max_freq_pll_ratio); 579 ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n", 580 boot_params->default_trace_level); 581 ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n", 582 boot_params->tracing_buff_message_format_mask); 583 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n", 584 boot_params->trace_destination_mask); 585 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n", 586 boot_params->trace_hw_component_mask); 587 ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", 588 boot_params->boot_type); 589 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n", 590 boot_params->punit_telemetry_sram_base); 591 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n", 592 boot_params->punit_telemetry_sram_size); 593 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n", 594 boot_params->vpu_telemetry_enable); 595 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_scheduling_mode = 0x%x\n", 596 boot_params->vpu_scheduling_mode); 597 ivpu_dbg(vdev, FW_BOOT, "boot_params.dvfs_mode = %u\n", 598 boot_params->dvfs_mode); 599 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_delayed_entry = %d\n", 600 boot_params->d0i3_delayed_entry); 601 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n", 602 boot_params->d0i3_residency_time_us); 603 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n", 604 boot_params->d0i3_entry_vpu_ts); 605 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n", 606 boot_params->system_time_us); 607 ivpu_dbg(vdev, FW_BOOT, "boot_params.power_profile = 0x%x\n", 608 boot_params->power_profile); 609 } 610 611 void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 612 { 613 struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx; 614 615 /* In case of warm boot only update variable params */ 616 if (!ivpu_fw_is_cold_boot(vdev)) { 617 boot_params->d0i3_residency_time_us = 618 ktime_us_delta(ktime_get_boottime(), vdev->hw->d0i3_entry_host_ts); 619 boot_params->d0i3_entry_vpu_ts = vdev->hw->d0i3_entry_vpu_ts; 620 boot_params->system_time_us = ktime_to_us(ktime_get_real()); 621 622 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n", 623 boot_params->d0i3_residency_time_us); 624 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n", 625 boot_params->d0i3_entry_vpu_ts); 626 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n", 627 boot_params->system_time_us); 628 629 boot_params->save_restore_ret_address = 0; 630 vdev->pm->is_warmboot = true; 631 wmb(); /* Flush WC buffers after writing save_restore_ret_address */ 632 return; 633 } 634 635 memset(boot_params, 0, sizeof(*boot_params)); 636 vdev->pm->is_warmboot = false; 637 638 boot_params->magic = VPU_BOOT_PARAMS_MAGIC; 639 boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number; 640 641 /* 642 * This param is a debug firmware feature. It switches default clock 643 * to higher resolution one for fine-grained and more accurate firmware 644 * task profiling. 645 */ 646 boot_params->perf_clk_frequency = ivpu_hw_profiling_freq_get(vdev); 647 648 /* 649 * Uncached region of VPU address space, covers IPC buffers, job queues 650 * and log buffers, programmable to L2$ Uncached by VPU MTRR 651 */ 652 boot_params->shared_region_base = vdev->hw->ranges.global.start; 653 boot_params->shared_region_size = vdev->hw->ranges.global.end - 654 vdev->hw->ranges.global.start; 655 656 boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr; 657 boot_params->ipc_header_area_size = ivpu_bo_size(ipc_mem_rx) / 2; 658 659 boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ivpu_bo_size(ipc_mem_rx) / 2; 660 boot_params->ipc_payload_area_size = ivpu_bo_size(ipc_mem_rx) / 2; 661 662 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { 663 boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start; 664 boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user); 665 } 666 667 /* Allow configuration for L2C_PAGE_TABLE with boot param value */ 668 boot_params->autoconfig = 1; 669 670 /* Enable L2 cache for first 2GB of high memory */ 671 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1; 672 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 673 ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.shave.start); 674 675 if (vdev->fw->mem_shave_nn) 676 boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr; 677 678 boot_params->watchdog_irq_mss = WATCHDOG_MSS_REDIRECT; 679 boot_params->watchdog_irq_nce = WATCHDOG_NCE_REDIRECT; 680 boot_params->si_stepping = ivpu_revision(vdev); 681 boot_params->device_id = ivpu_device_id(vdev); 682 boot_params->feature_exclusion = vdev->hw->tile_fuse; 683 boot_params->sku = vdev->hw->sku; 684 685 boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio; 686 boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio; 687 boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio; 688 689 boot_params->default_trace_level = vdev->fw->trace_level; 690 boot_params->tracing_buff_message_format_mask = BIT(VPU_TRACING_FORMAT_STRING); 691 boot_params->trace_destination_mask = vdev->fw->trace_destination_mask; 692 boot_params->trace_hw_component_mask = vdev->fw->trace_hw_component_mask; 693 boot_params->crit_tracing_buff_addr = vdev->fw->mem_log_crit->vpu_addr; 694 boot_params->crit_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_crit); 695 boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr; 696 boot_params->verbose_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_verb); 697 698 boot_params->punit_telemetry_sram_base = ivpu_hw_telemetry_offset_get(vdev); 699 boot_params->punit_telemetry_sram_size = ivpu_hw_telemetry_size_get(vdev); 700 boot_params->vpu_telemetry_enable = ivpu_hw_telemetry_enable_get(vdev); 701 boot_params->vpu_scheduling_mode = vdev->fw->sched_mode; 702 if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) 703 boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS; 704 boot_params->dvfs_mode = vdev->fw->dvfs_mode; 705 if (!IVPU_WA(disable_d0i3_msg)) 706 boot_params->d0i3_delayed_entry = 1; 707 boot_params->d0i3_residency_time_us = 0; 708 boot_params->d0i3_entry_vpu_ts = 0; 709 if (IVPU_WA(disable_d0i2)) 710 boot_params->power_profile |= BIT(1); 711 712 boot_params->system_time_us = ktime_to_us(ktime_get_real()); 713 wmb(); /* Flush WC buffers after writing bootparams */ 714 715 ivpu_fw_boot_params_print(vdev, boot_params); 716 } 717