1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #ifndef _AIE2_MSG_PRIV_H_ 7 #define _AIE2_MSG_PRIV_H_ 8 9 enum aie2_msg_opcode { 10 MSG_OP_CREATE_CONTEXT = 0x2, 11 MSG_OP_DESTROY_CONTEXT = 0x3, 12 MSG_OP_SYNC_BO = 0x7, 13 MSG_OP_EXECUTE_BUFFER_CF = 0xC, 14 MSG_OP_QUERY_COL_STATUS = 0xD, 15 MSG_OP_QUERY_AIE_TILE_INFO = 0xE, 16 MSG_OP_QUERY_AIE_VERSION = 0xF, 17 MSG_OP_EXEC_DPU = 0x10, 18 MSG_OP_CONFIG_CU = 0x11, 19 MSG_OP_CHAIN_EXEC_BUFFER_CF = 0x12, 20 MSG_OP_CHAIN_EXEC_DPU = 0x13, 21 MSG_OP_CONFIG_DEBUG_BO = 0x14, 22 MSG_OP_CHAIN_EXEC_NPU = 0x18, 23 MSG_OP_MAX_XRT_OPCODE, 24 MSG_OP_SUSPEND = 0x101, 25 MSG_OP_RESUME = 0x102, 26 MSG_OP_ASSIGN_MGMT_PASID = 0x103, 27 MSG_OP_INVOKE_SELF_TEST = 0x104, 28 MSG_OP_MAP_HOST_BUFFER = 0x106, 29 MSG_OP_GET_FIRMWARE_VERSION = 0x108, 30 MSG_OP_SET_RUNTIME_CONFIG = 0x10A, 31 MSG_OP_GET_RUNTIME_CONFIG = 0x10B, 32 MSG_OP_REGISTER_ASYNC_EVENT_MSG = 0x10C, 33 MSG_OP_MAX_DRV_OPCODE, 34 MSG_OP_GET_PROTOCOL_VERSION = 0x301, 35 MSG_OP_MAX_OPCODE 36 }; 37 38 enum aie2_msg_status { 39 AIE2_STATUS_SUCCESS = 0x0, 40 /* AIE Error codes */ 41 AIE2_STATUS_AIE_SATURATION_ERROR = 0x1000001, 42 AIE2_STATUS_AIE_FP_ERROR = 0x1000002, 43 AIE2_STATUS_AIE_STREAM_ERROR = 0x1000003, 44 AIE2_STATUS_AIE_ACCESS_ERROR = 0x1000004, 45 AIE2_STATUS_AIE_BUS_ERROR = 0x1000005, 46 AIE2_STATUS_AIE_INSTRUCTION_ERROR = 0x1000006, 47 AIE2_STATUS_AIE_ECC_ERROR = 0x1000007, 48 AIE2_STATUS_AIE_LOCK_ERROR = 0x1000008, 49 AIE2_STATUS_AIE_DMA_ERROR = 0x1000009, 50 AIE2_STATUS_AIE_MEM_PARITY_ERROR = 0x100000a, 51 AIE2_STATUS_AIE_PWR_CFG_ERROR = 0x100000b, 52 AIE2_STATUS_AIE_BACKTRACK_ERROR = 0x100000c, 53 AIE2_STATUS_MAX_AIE_STATUS_CODE, 54 /* MGMT ERT Error codes */ 55 AIE2_STATUS_MGMT_ERT_SELF_TEST_FAILURE = 0x2000001, 56 AIE2_STATUS_MGMT_ERT_HASH_MISMATCH, 57 AIE2_STATUS_MGMT_ERT_NOAVAIL, 58 AIE2_STATUS_MGMT_ERT_INVALID_PARAM, 59 AIE2_STATUS_MGMT_ERT_ENTER_SUSPEND_FAILURE, 60 AIE2_STATUS_MGMT_ERT_BUSY, 61 AIE2_STATUS_MGMT_ERT_APPLICATION_ACTIVE, 62 MAX_MGMT_ERT_STATUS_CODE, 63 /* APP ERT Error codes */ 64 AIE2_STATUS_APP_ERT_FIRST_ERROR = 0x3000001, 65 AIE2_STATUS_APP_INVALID_INSTR, 66 AIE2_STATUS_APP_LOAD_PDI_FAIL, 67 MAX_APP_ERT_STATUS_CODE, 68 /* NPU RTOS Error Codes */ 69 AIE2_STATUS_INVALID_INPUT_BUFFER = 0x4000001, 70 AIE2_STATUS_INVALID_COMMAND, 71 AIE2_STATUS_INVALID_PARAM, 72 AIE2_STATUS_INVALID_OPERATION = 0x4000006, 73 AIE2_STATUS_ASYNC_EVENT_MSGS_FULL, 74 AIE2_STATUS_MAX_RTOS_STATUS_CODE, 75 MAX_AIE2_STATUS_CODE 76 }; 77 78 struct assign_mgmt_pasid_req { 79 __u16 pasid; 80 __u16 reserved; 81 } __packed; 82 83 struct assign_mgmt_pasid_resp { 84 enum aie2_msg_status status; 85 } __packed; 86 87 struct map_host_buffer_req { 88 __u32 context_id; 89 __u64 buf_addr; 90 __u64 buf_size; 91 } __packed; 92 93 struct map_host_buffer_resp { 94 enum aie2_msg_status status; 95 } __packed; 96 97 #define MAX_CQ_PAIRS 2 98 struct cq_info { 99 __u32 head_addr; 100 __u32 tail_addr; 101 __u32 buf_addr; 102 __u32 buf_size; 103 }; 104 105 struct cq_pair { 106 struct cq_info x2i_q; 107 struct cq_info i2x_q; 108 }; 109 110 struct create_ctx_req { 111 __u32 aie_type; 112 __u8 start_col; 113 __u8 num_col; 114 __u16 reserved; 115 __u8 num_cq_pairs_requested; 116 __u8 reserved1; 117 __u16 pasid; 118 __u32 pad[2]; 119 __u32 sec_comm_target_type; 120 __u32 context_priority; 121 } __packed; 122 123 struct create_ctx_resp { 124 enum aie2_msg_status status; 125 __u32 context_id; 126 __u16 msix_id; 127 __u8 num_cq_pairs_allocated; 128 __u8 reserved; 129 struct cq_pair cq_pair[MAX_CQ_PAIRS]; 130 } __packed; 131 132 struct destroy_ctx_req { 133 __u32 context_id; 134 } __packed; 135 136 struct destroy_ctx_resp { 137 enum aie2_msg_status status; 138 } __packed; 139 140 struct execute_buffer_req { 141 __u32 cu_idx; 142 __u32 payload[19]; 143 } __packed; 144 145 struct exec_dpu_req { 146 __u64 inst_buf_addr; 147 __u32 inst_size; 148 __u32 inst_prop_cnt; 149 __u32 cu_idx; 150 __u32 payload[35]; 151 } __packed; 152 153 enum exec_npu_type { 154 EXEC_NPU_TYPE_NON_ELF = 0x1, 155 EXEC_NPU_TYPE_PARTIAL_ELF = 0x2, 156 }; 157 158 union exec_req { 159 struct execute_buffer_req ebuf; 160 struct exec_dpu_req dpu_req; 161 }; 162 163 struct execute_buffer_resp { 164 enum aie2_msg_status status; 165 } __packed; 166 167 struct aie_tile_info { 168 __u32 size; 169 __u16 major; 170 __u16 minor; 171 __u16 cols; 172 __u16 rows; 173 __u16 core_rows; 174 __u16 mem_rows; 175 __u16 shim_rows; 176 __u16 core_row_start; 177 __u16 mem_row_start; 178 __u16 shim_row_start; 179 __u16 core_dma_channels; 180 __u16 mem_dma_channels; 181 __u16 shim_dma_channels; 182 __u16 core_locks; 183 __u16 mem_locks; 184 __u16 shim_locks; 185 __u16 core_events; 186 __u16 mem_events; 187 __u16 shim_events; 188 __u16 reserved; 189 }; 190 191 struct aie_tile_info_req { 192 __u32 reserved; 193 } __packed; 194 195 struct aie_tile_info_resp { 196 enum aie2_msg_status status; 197 struct aie_tile_info info; 198 } __packed; 199 200 struct aie_version_info_req { 201 __u32 reserved; 202 } __packed; 203 204 struct aie_version_info_resp { 205 enum aie2_msg_status status; 206 __u16 major; 207 __u16 minor; 208 } __packed; 209 210 struct aie_column_info_req { 211 __u64 dump_buff_addr; 212 __u32 dump_buff_size; 213 __u32 num_cols; 214 __u32 aie_bitmap; 215 } __packed; 216 217 struct aie_column_info_resp { 218 enum aie2_msg_status status; 219 __u32 size; 220 } __packed; 221 222 struct suspend_req { 223 __u32 place_holder; 224 } __packed; 225 226 struct suspend_resp { 227 enum aie2_msg_status status; 228 } __packed; 229 230 struct resume_req { 231 __u32 place_holder; 232 } __packed; 233 234 struct resume_resp { 235 enum aie2_msg_status status; 236 } __packed; 237 238 struct check_header_hash_req { 239 __u64 hash_high; 240 __u64 hash_low; 241 } __packed; 242 243 struct check_header_hash_resp { 244 enum aie2_msg_status status; 245 } __packed; 246 247 struct query_error_req { 248 __u64 buf_addr; 249 __u32 buf_size; 250 __u32 next_row; 251 __u32 next_column; 252 __u32 next_module; 253 } __packed; 254 255 struct query_error_resp { 256 enum aie2_msg_status status; 257 __u32 num_err; 258 __u32 has_next_err; 259 __u32 next_row; 260 __u32 next_column; 261 __u32 next_module; 262 } __packed; 263 264 struct protocol_version_req { 265 __u32 reserved; 266 } __packed; 267 268 struct protocol_version_resp { 269 enum aie2_msg_status status; 270 __u32 major; 271 __u32 minor; 272 } __packed; 273 274 struct firmware_version_req { 275 __u32 reserved; 276 } __packed; 277 278 struct firmware_version_resp { 279 enum aie2_msg_status status; 280 __u32 major; 281 __u32 minor; 282 __u32 sub; 283 __u32 build; 284 } __packed; 285 286 #define MAX_NUM_CUS 32 287 #define AIE2_MSG_CFG_CU_PDI_ADDR GENMASK(16, 0) 288 #define AIE2_MSG_CFG_CU_FUNC GENMASK(24, 17) 289 struct config_cu_req { 290 __u32 num_cus; 291 __u32 cfgs[MAX_NUM_CUS]; 292 } __packed; 293 294 struct config_cu_resp { 295 enum aie2_msg_status status; 296 } __packed; 297 298 struct set_runtime_cfg_req { 299 __u32 type; 300 __u64 value; 301 } __packed; 302 303 struct set_runtime_cfg_resp { 304 enum aie2_msg_status status; 305 } __packed; 306 307 struct get_runtime_cfg_req { 308 __u32 type; 309 } __packed; 310 311 struct get_runtime_cfg_resp { 312 enum aie2_msg_status status; 313 __u64 value; 314 } __packed; 315 316 enum async_event_type { 317 ASYNC_EVENT_TYPE_AIE_ERROR, 318 ASYNC_EVENT_TYPE_EXCEPTION, 319 MAX_ASYNC_EVENT_TYPE 320 }; 321 322 #define ASYNC_BUF_SIZE SZ_8K 323 struct async_event_msg_req { 324 __u64 buf_addr; 325 __u32 buf_size; 326 } __packed; 327 328 struct async_event_msg_resp { 329 enum aie2_msg_status status; 330 enum async_event_type type; 331 } __packed; 332 333 #define MAX_CHAIN_CMDBUF_SIZE SZ_4K 334 335 struct cmd_chain_slot_execbuf_cf { 336 __u32 cu_idx; 337 __u32 arg_cnt; 338 __u32 args[] __counted_by(arg_cnt); 339 }; 340 341 struct cmd_chain_slot_dpu { 342 __u64 inst_buf_addr; 343 __u32 inst_size; 344 __u32 inst_prop_cnt; 345 __u32 cu_idx; 346 __u32 arg_cnt; 347 #define MAX_DPU_ARGS_SIZE (34 * sizeof(__u32)) 348 __u32 args[] __counted_by(arg_cnt); 349 }; 350 351 #define MAX_NPU_ARGS_SIZE (26 * sizeof(__u32)) 352 struct cmd_chain_slot_npu { 353 enum exec_npu_type type; 354 u64 inst_buf_addr; 355 u64 save_buf_addr; 356 u64 restore_buf_addr; 357 u32 inst_size; 358 u32 save_size; 359 u32 restore_size; 360 u32 inst_prop_cnt; 361 u32 cu_idx; 362 u32 arg_cnt; 363 u32 args[] __counted_by(arg_cnt); 364 } __packed; 365 366 struct cmd_chain_req { 367 __u64 buf_addr; 368 __u32 buf_size; 369 __u32 count; 370 } __packed; 371 372 struct cmd_chain_npu_req { 373 u32 flags; 374 u32 reserved; 375 u64 buf_addr; 376 u32 buf_size; 377 u32 count; 378 } __packed; 379 380 union exec_chain_req { 381 struct cmd_chain_npu_req npu_req; 382 struct cmd_chain_req req; 383 }; 384 385 struct cmd_chain_resp { 386 enum aie2_msg_status status; 387 __u32 fail_cmd_idx; 388 enum aie2_msg_status fail_cmd_status; 389 } __packed; 390 391 #define AIE2_MSG_SYNC_BO_SRC_TYPE GENMASK(3, 0) 392 #define AIE2_MSG_SYNC_BO_DST_TYPE GENMASK(7, 4) 393 struct sync_bo_req { 394 __u64 src_addr; 395 __u64 dst_addr; 396 __u32 size; 397 #define SYNC_BO_DEV_MEM 0 398 #define SYNC_BO_HOST_MEM 2 399 __u32 type; 400 } __packed; 401 402 struct sync_bo_resp { 403 enum aie2_msg_status status; 404 } __packed; 405 406 #define DEBUG_BO_UNREGISTER 0 407 #define DEBUG_BO_REGISTER 1 408 struct config_debug_bo_req { 409 __u64 offset; 410 __u64 size; 411 /* 412 * config operations. 413 * DEBUG_BO_REGISTER: Register debug buffer 414 * DEBUG_BO_UNREGISTER: Unregister debug buffer 415 */ 416 __u32 config; 417 } __packed; 418 419 struct config_debug_bo_resp { 420 enum aie2_msg_status status; 421 } __packed; 422 #endif /* _AIE2_MSG_PRIV_H_ */ 423