1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #include <drm/amdxdna_accel.h> 7 #include <drm/drm_cache.h> 8 #include <drm/drm_device.h> 9 #include <drm/drm_gem.h> 10 #include <drm/drm_gem_shmem_helper.h> 11 #include <drm/drm_print.h> 12 #include <drm/gpu_scheduler.h> 13 #include <linux/bitfield.h> 14 #include <linux/errno.h> 15 #include <linux/pci.h> 16 #include <linux/types.h> 17 #include <linux/xarray.h> 18 19 #include "aie2_msg_priv.h" 20 #include "aie2_pci.h" 21 #include "amdxdna_ctx.h" 22 #include "amdxdna_gem.h" 23 #include "amdxdna_mailbox.h" 24 #include "amdxdna_mailbox_helper.h" 25 #include "amdxdna_pci_drv.h" 26 27 #define DECLARE_AIE2_MSG(name, op) \ 28 DECLARE_XDNA_MSG_COMMON(name, op, MAX_AIE2_STATUS_CODE) 29 30 #define EXEC_MSG_OPS(xdna) ((xdna)->dev_handle->exec_msg_ops) 31 32 static int aie2_send_mgmt_msg_wait(struct amdxdna_dev_hdl *ndev, 33 struct xdna_mailbox_msg *msg) 34 { 35 struct amdxdna_dev *xdna = ndev->xdna; 36 struct xdna_notify *hdl = msg->handle; 37 int ret; 38 39 if (!ndev->mgmt_chann) 40 return -ENODEV; 41 42 drm_WARN_ON(&xdna->ddev, xdna->rpm_on && !mutex_is_locked(&xdna->dev_lock)); 43 ret = xdna_send_msg_wait(xdna, ndev->mgmt_chann, msg); 44 if (ret == -ETIME) { 45 xdna_mailbox_stop_channel(ndev->mgmt_chann); 46 xdna_mailbox_destroy_channel(ndev->mgmt_chann); 47 ndev->mgmt_chann = NULL; 48 } 49 50 if (!ret && *hdl->data != AIE2_STATUS_SUCCESS) { 51 XDNA_ERR(xdna, "command opcode 0x%x failed, status 0x%x", 52 msg->opcode, *hdl->data); 53 ret = -EINVAL; 54 } 55 56 return ret; 57 } 58 59 int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev) 60 { 61 DECLARE_AIE2_MSG(suspend, MSG_OP_SUSPEND); 62 63 return aie2_send_mgmt_msg_wait(ndev, &msg); 64 } 65 66 int aie2_resume_fw(struct amdxdna_dev_hdl *ndev) 67 { 68 DECLARE_AIE2_MSG(suspend, MSG_OP_RESUME); 69 70 return aie2_send_mgmt_msg_wait(ndev, &msg); 71 } 72 73 int aie2_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 value) 74 { 75 DECLARE_AIE2_MSG(set_runtime_cfg, MSG_OP_SET_RUNTIME_CONFIG); 76 int ret; 77 78 req.type = type; 79 req.value = value; 80 81 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 82 if (ret) { 83 XDNA_ERR(ndev->xdna, "Failed to set runtime config, ret %d", ret); 84 return ret; 85 } 86 87 return 0; 88 } 89 90 int aie2_get_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 *value) 91 { 92 DECLARE_AIE2_MSG(get_runtime_cfg, MSG_OP_GET_RUNTIME_CONFIG); 93 int ret; 94 95 req.type = type; 96 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 97 if (ret) { 98 XDNA_ERR(ndev->xdna, "Failed to get runtime config, ret %d", ret); 99 return ret; 100 } 101 102 *value = resp.value; 103 return 0; 104 } 105 106 int aie2_assign_mgmt_pasid(struct amdxdna_dev_hdl *ndev, u16 pasid) 107 { 108 DECLARE_AIE2_MSG(assign_mgmt_pasid, MSG_OP_ASSIGN_MGMT_PASID); 109 110 req.pasid = pasid; 111 112 return aie2_send_mgmt_msg_wait(ndev, &msg); 113 } 114 115 int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev, struct aie_version *version) 116 { 117 DECLARE_AIE2_MSG(aie_version_info, MSG_OP_QUERY_AIE_VERSION); 118 struct amdxdna_dev *xdna = ndev->xdna; 119 int ret; 120 121 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 122 if (ret) 123 return ret; 124 125 XDNA_DBG(xdna, "Query AIE version - major: %u minor: %u completed", 126 resp.major, resp.minor); 127 128 version->major = resp.major; 129 version->minor = resp.minor; 130 131 return 0; 132 } 133 134 int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev, struct aie_metadata *metadata) 135 { 136 DECLARE_AIE2_MSG(aie_tile_info, MSG_OP_QUERY_AIE_TILE_INFO); 137 int ret; 138 139 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 140 if (ret) 141 return ret; 142 143 metadata->size = resp.info.size; 144 metadata->cols = resp.info.cols; 145 metadata->rows = resp.info.rows; 146 147 metadata->version.major = resp.info.major; 148 metadata->version.minor = resp.info.minor; 149 150 metadata->core.row_count = resp.info.core_rows; 151 metadata->core.row_start = resp.info.core_row_start; 152 metadata->core.dma_channel_count = resp.info.core_dma_channels; 153 metadata->core.lock_count = resp.info.core_locks; 154 metadata->core.event_reg_count = resp.info.core_events; 155 156 metadata->mem.row_count = resp.info.mem_rows; 157 metadata->mem.row_start = resp.info.mem_row_start; 158 metadata->mem.dma_channel_count = resp.info.mem_dma_channels; 159 metadata->mem.lock_count = resp.info.mem_locks; 160 metadata->mem.event_reg_count = resp.info.mem_events; 161 162 metadata->shim.row_count = resp.info.shim_rows; 163 metadata->shim.row_start = resp.info.shim_row_start; 164 metadata->shim.dma_channel_count = resp.info.shim_dma_channels; 165 metadata->shim.lock_count = resp.info.shim_locks; 166 metadata->shim.event_reg_count = resp.info.shim_events; 167 168 return 0; 169 } 170 171 int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev, 172 struct amdxdna_fw_ver *fw_ver) 173 { 174 DECLARE_AIE2_MSG(firmware_version, MSG_OP_GET_FIRMWARE_VERSION); 175 int ret; 176 177 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 178 if (ret) 179 return ret; 180 181 fw_ver->major = resp.major; 182 fw_ver->minor = resp.minor; 183 fw_ver->sub = resp.sub; 184 fw_ver->build = resp.build; 185 186 return 0; 187 } 188 189 int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx) 190 { 191 DECLARE_AIE2_MSG(create_ctx, MSG_OP_CREATE_CONTEXT); 192 struct amdxdna_dev *xdna = ndev->xdna; 193 struct xdna_mailbox_chann_res x2i; 194 struct xdna_mailbox_chann_res i2x; 195 struct cq_pair *cq_pair; 196 u32 intr_reg; 197 int ret; 198 199 req.aie_type = 1; 200 req.start_col = hwctx->start_col; 201 req.num_col = hwctx->num_col; 202 req.num_cq_pairs_requested = 1; 203 req.pasid = hwctx->client->pasid; 204 req.context_priority = 2; 205 206 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 207 if (ret) 208 return ret; 209 210 hwctx->fw_ctx_id = resp.context_id; 211 WARN_ONCE(hwctx->fw_ctx_id == -1, "Unexpected context id"); 212 213 cq_pair = &resp.cq_pair[0]; 214 x2i.mb_head_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->x2i_q.head_addr); 215 x2i.mb_tail_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->x2i_q.tail_addr); 216 x2i.rb_start_addr = AIE2_SRAM_OFF(ndev, cq_pair->x2i_q.buf_addr); 217 x2i.rb_size = cq_pair->x2i_q.buf_size; 218 219 i2x.mb_head_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->i2x_q.head_addr); 220 i2x.mb_tail_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->i2x_q.tail_addr); 221 i2x.rb_start_addr = AIE2_SRAM_OFF(ndev, cq_pair->i2x_q.buf_addr); 222 i2x.rb_size = cq_pair->i2x_q.buf_size; 223 224 ret = pci_irq_vector(to_pci_dev(xdna->ddev.dev), resp.msix_id); 225 if (ret == -EINVAL) { 226 XDNA_ERR(xdna, "not able to create channel"); 227 goto out_destroy_context; 228 } 229 230 intr_reg = i2x.mb_head_ptr_reg + 4; 231 hwctx->priv->mbox_chann = xdna_mailbox_create_channel(ndev->mbox, &x2i, &i2x, 232 intr_reg, ret); 233 if (!hwctx->priv->mbox_chann) { 234 XDNA_ERR(xdna, "not able to create channel"); 235 ret = -EINVAL; 236 goto out_destroy_context; 237 } 238 239 XDNA_DBG(xdna, "%s mailbox channel irq: %d, msix_id: %d", 240 hwctx->name, ret, resp.msix_id); 241 XDNA_DBG(xdna, "%s created fw ctx %d pasid %d", hwctx->name, 242 hwctx->fw_ctx_id, hwctx->client->pasid); 243 244 return 0; 245 246 out_destroy_context: 247 aie2_destroy_context(ndev, hwctx); 248 return ret; 249 } 250 251 int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx) 252 { 253 DECLARE_AIE2_MSG(destroy_ctx, MSG_OP_DESTROY_CONTEXT); 254 struct amdxdna_dev *xdna = ndev->xdna; 255 int ret; 256 257 if (hwctx->fw_ctx_id == -1) 258 return 0; 259 260 xdna_mailbox_stop_channel(hwctx->priv->mbox_chann); 261 262 req.context_id = hwctx->fw_ctx_id; 263 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 264 if (ret) 265 XDNA_WARN(xdna, "%s destroy context failed, ret %d", hwctx->name, ret); 266 267 xdna_mailbox_destroy_channel(hwctx->priv->mbox_chann); 268 XDNA_DBG(xdna, "%s destroyed fw ctx %d", hwctx->name, 269 hwctx->fw_ctx_id); 270 hwctx->priv->mbox_chann = NULL; 271 hwctx->fw_ctx_id = -1; 272 273 return ret; 274 } 275 276 int aie2_map_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u64 size) 277 { 278 DECLARE_AIE2_MSG(map_host_buffer, MSG_OP_MAP_HOST_BUFFER); 279 struct amdxdna_dev *xdna = ndev->xdna; 280 int ret; 281 282 req.context_id = context_id; 283 req.buf_addr = addr; 284 req.buf_size = size; 285 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 286 if (ret) 287 return ret; 288 289 XDNA_DBG(xdna, "fw ctx %d map host buf addr 0x%llx size 0x%llx", 290 context_id, addr, size); 291 292 return 0; 293 } 294 295 static int amdxdna_hwctx_col_map(struct amdxdna_hwctx *hwctx, void *arg) 296 { 297 u32 *bitmap = arg; 298 299 *bitmap |= GENMASK(hwctx->start_col + hwctx->num_col - 1, hwctx->start_col); 300 301 return 0; 302 } 303 304 int aie2_query_status(struct amdxdna_dev_hdl *ndev, char __user *buf, 305 u32 size, u32 *cols_filled) 306 { 307 DECLARE_AIE2_MSG(aie_column_info, MSG_OP_QUERY_COL_STATUS); 308 struct amdxdna_dev *xdna = ndev->xdna; 309 struct amdxdna_client *client; 310 dma_addr_t dma_addr; 311 u32 aie_bitmap = 0; 312 u8 *buff_addr; 313 int ret; 314 315 buff_addr = dma_alloc_noncoherent(xdna->ddev.dev, size, &dma_addr, 316 DMA_FROM_DEVICE, GFP_KERNEL); 317 if (!buff_addr) 318 return -ENOMEM; 319 320 /* Go through each hardware context and mark the AIE columns that are active */ 321 list_for_each_entry(client, &xdna->client_list, node) 322 amdxdna_hwctx_walk(client, &aie_bitmap, amdxdna_hwctx_col_map); 323 324 *cols_filled = 0; 325 req.dump_buff_addr = dma_addr; 326 req.dump_buff_size = size; 327 req.num_cols = hweight32(aie_bitmap); 328 req.aie_bitmap = aie_bitmap; 329 330 drm_clflush_virt_range(buff_addr, size); /* device can access */ 331 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 332 if (ret) { 333 XDNA_ERR(xdna, "Error during NPU query, status %d", ret); 334 goto fail; 335 } 336 337 if (resp.status != AIE2_STATUS_SUCCESS) { 338 XDNA_ERR(xdna, "Query NPU status failed, status 0x%x", resp.status); 339 ret = -EINVAL; 340 goto fail; 341 } 342 XDNA_DBG(xdna, "Query NPU status completed"); 343 344 if (size < resp.size) { 345 ret = -EINVAL; 346 XDNA_ERR(xdna, "Bad buffer size. Available: %u. Needs: %u", size, resp.size); 347 goto fail; 348 } 349 350 if (copy_to_user(buf, buff_addr, resp.size)) { 351 ret = -EFAULT; 352 XDNA_ERR(xdna, "Failed to copy NPU status to user space"); 353 goto fail; 354 } 355 356 *cols_filled = aie_bitmap; 357 358 fail: 359 dma_free_noncoherent(xdna->ddev.dev, size, buff_addr, dma_addr, DMA_FROM_DEVICE); 360 return ret; 361 } 362 363 int aie2_register_asyn_event_msg(struct amdxdna_dev_hdl *ndev, dma_addr_t addr, u32 size, 364 void *handle, int (*cb)(void*, void __iomem *, size_t)) 365 { 366 struct async_event_msg_req req = { 0 }; 367 struct xdna_mailbox_msg msg = { 368 .send_data = (u8 *)&req, 369 .send_size = sizeof(req), 370 .handle = handle, 371 .opcode = MSG_OP_REGISTER_ASYNC_EVENT_MSG, 372 .notify_cb = cb, 373 }; 374 375 req.buf_addr = addr; 376 req.buf_size = size; 377 378 XDNA_DBG(ndev->xdna, "Register addr 0x%llx size 0x%x", addr, size); 379 return xdna_mailbox_send_msg(ndev->mgmt_chann, &msg, TX_TIMEOUT); 380 } 381 382 int aie2_config_cu(struct amdxdna_hwctx *hwctx, 383 int (*notify_cb)(void *, void __iomem *, size_t)) 384 { 385 struct mailbox_channel *chann = hwctx->priv->mbox_chann; 386 struct amdxdna_dev *xdna = hwctx->client->xdna; 387 u32 shift = xdna->dev_info->dev_mem_buf_shift; 388 struct config_cu_req req = { 0 }; 389 struct xdna_mailbox_msg msg; 390 struct drm_gem_object *gobj; 391 struct amdxdna_gem_obj *abo; 392 int i; 393 394 if (!chann) 395 return -ENODEV; 396 397 if (hwctx->cus->num_cus > MAX_NUM_CUS) { 398 XDNA_DBG(xdna, "Exceed maximum CU %d", MAX_NUM_CUS); 399 return -EINVAL; 400 } 401 402 for (i = 0; i < hwctx->cus->num_cus; i++) { 403 struct amdxdna_cu_config *cu = &hwctx->cus->cu_configs[i]; 404 405 if (XDNA_MBZ_DBG(xdna, cu->pad, sizeof(cu->pad))) 406 return -EINVAL; 407 408 gobj = drm_gem_object_lookup(hwctx->client->filp, cu->cu_bo); 409 if (!gobj) { 410 XDNA_ERR(xdna, "Lookup GEM object failed"); 411 return -EINVAL; 412 } 413 abo = to_xdna_obj(gobj); 414 415 if (abo->type != AMDXDNA_BO_DEV) { 416 drm_gem_object_put(gobj); 417 XDNA_ERR(xdna, "Invalid BO type"); 418 return -EINVAL; 419 } 420 421 req.cfgs[i] = FIELD_PREP(AIE2_MSG_CFG_CU_PDI_ADDR, 422 abo->mem.dev_addr >> shift); 423 req.cfgs[i] |= FIELD_PREP(AIE2_MSG_CFG_CU_FUNC, cu->cu_func); 424 XDNA_DBG(xdna, "CU %d full addr 0x%llx, cfg 0x%x", i, 425 abo->mem.dev_addr, req.cfgs[i]); 426 drm_gem_object_put(gobj); 427 } 428 req.num_cus = hwctx->cus->num_cus; 429 430 msg.send_data = (u8 *)&req; 431 msg.send_size = sizeof(req); 432 msg.handle = hwctx; 433 msg.opcode = MSG_OP_CONFIG_CU; 434 msg.notify_cb = notify_cb; 435 return xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT); 436 } 437 438 static int aie2_init_exec_cu_req(struct amdxdna_gem_obj *cmd_bo, void *req, 439 size_t *size, u32 *msg_op) 440 { 441 struct execute_buffer_req *cu_req = req; 442 u32 cmd_len; 443 void *cmd; 444 445 cmd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 446 if (cmd_len > sizeof(cu_req->payload)) 447 return -EINVAL; 448 449 cu_req->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo); 450 if (cu_req->cu_idx == INVALID_CU_IDX) 451 return -EINVAL; 452 453 memcpy(cu_req->payload, cmd, cmd_len); 454 455 *size = sizeof(*cu_req); 456 *msg_op = MSG_OP_EXECUTE_BUFFER_CF; 457 return 0; 458 } 459 460 static int aie2_init_exec_dpu_req(struct amdxdna_gem_obj *cmd_bo, void *req, 461 size_t *size, u32 *msg_op) 462 { 463 struct exec_dpu_req *dpu_req = req; 464 struct amdxdna_cmd_start_npu *sn; 465 u32 cmd_len; 466 467 sn = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 468 if (cmd_len - sizeof(*sn) > sizeof(dpu_req->payload)) 469 return -EINVAL; 470 471 dpu_req->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo); 472 if (dpu_req->cu_idx == INVALID_CU_IDX) 473 return -EINVAL; 474 475 dpu_req->inst_buf_addr = sn->buffer; 476 dpu_req->inst_size = sn->buffer_size; 477 dpu_req->inst_prop_cnt = sn->prop_count; 478 memcpy(dpu_req->payload, sn->prop_args, cmd_len - sizeof(*sn)); 479 480 *size = sizeof(*dpu_req); 481 *msg_op = MSG_OP_EXEC_DPU; 482 return 0; 483 } 484 485 static void aie2_init_exec_chain_req(void *req, u64 slot_addr, size_t size, u32 cmd_cnt) 486 { 487 struct cmd_chain_req *chain_req = req; 488 489 chain_req->buf_addr = slot_addr; 490 chain_req->buf_size = size; 491 chain_req->count = cmd_cnt; 492 } 493 494 static void aie2_init_npu_chain_req(void *req, u64 slot_addr, size_t size, u32 cmd_cnt) 495 { 496 struct cmd_chain_npu_req *npu_chain_req = req; 497 498 npu_chain_req->flags = 0; 499 npu_chain_req->reserved = 0; 500 npu_chain_req->buf_addr = slot_addr; 501 npu_chain_req->buf_size = size; 502 npu_chain_req->count = cmd_cnt; 503 } 504 505 static int 506 aie2_cmdlist_fill_cf(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size) 507 { 508 struct cmd_chain_slot_execbuf_cf *cf_slot = slot; 509 u32 cmd_len; 510 void *cmd; 511 512 cmd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 513 if (*size < sizeof(*cf_slot) + cmd_len) 514 return -EINVAL; 515 516 cf_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo); 517 if (cf_slot->cu_idx == INVALID_CU_IDX) 518 return -EINVAL; 519 520 cf_slot->arg_cnt = cmd_len / sizeof(u32); 521 memcpy(cf_slot->args, cmd, cmd_len); 522 /* Accurate slot size to hint firmware to do necessary copy */ 523 *size = sizeof(*cf_slot) + cmd_len; 524 return 0; 525 } 526 527 static int 528 aie2_cmdlist_fill_dpu(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size) 529 { 530 struct cmd_chain_slot_dpu *dpu_slot = slot; 531 struct amdxdna_cmd_start_npu *sn; 532 u32 cmd_len; 533 u32 arg_sz; 534 535 sn = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 536 arg_sz = cmd_len - sizeof(*sn); 537 if (cmd_len < sizeof(*sn) || arg_sz > MAX_DPU_ARGS_SIZE) 538 return -EINVAL; 539 540 if (*size < sizeof(*dpu_slot) + arg_sz) 541 return -EINVAL; 542 543 dpu_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo); 544 if (dpu_slot->cu_idx == INVALID_CU_IDX) 545 return -EINVAL; 546 547 dpu_slot->inst_buf_addr = sn->buffer; 548 dpu_slot->inst_size = sn->buffer_size; 549 dpu_slot->inst_prop_cnt = sn->prop_count; 550 dpu_slot->arg_cnt = arg_sz / sizeof(u32); 551 memcpy(dpu_slot->args, sn->prop_args, arg_sz); 552 553 /* Accurate slot size to hint firmware to do necessary copy */ 554 *size = sizeof(*dpu_slot) + arg_sz; 555 return 0; 556 } 557 558 static u32 aie2_get_chain_msg_op(u32 cmd_op) 559 { 560 switch (cmd_op) { 561 case ERT_START_CU: 562 return MSG_OP_CHAIN_EXEC_BUFFER_CF; 563 case ERT_START_NPU: 564 return MSG_OP_CHAIN_EXEC_DPU; 565 default: 566 break; 567 } 568 569 return MSG_OP_MAX_OPCODE; 570 } 571 572 static struct aie2_exec_msg_ops legacy_exec_message_ops = { 573 .init_cu_req = aie2_init_exec_cu_req, 574 .init_dpu_req = aie2_init_exec_dpu_req, 575 .init_chain_req = aie2_init_exec_chain_req, 576 .fill_cf_slot = aie2_cmdlist_fill_cf, 577 .fill_dpu_slot = aie2_cmdlist_fill_dpu, 578 .get_chain_msg_op = aie2_get_chain_msg_op, 579 }; 580 581 static int 582 aie2_cmdlist_fill_npu_cf(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size) 583 { 584 struct cmd_chain_slot_npu *npu_slot = slot; 585 u32 cmd_len; 586 void *cmd; 587 588 cmd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 589 if (*size < sizeof(*npu_slot) + cmd_len) 590 return -EINVAL; 591 592 npu_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo); 593 if (npu_slot->cu_idx == INVALID_CU_IDX) 594 return -EINVAL; 595 596 memset(npu_slot, 0, sizeof(*npu_slot)); 597 npu_slot->type = EXEC_NPU_TYPE_NON_ELF; 598 npu_slot->arg_cnt = cmd_len / sizeof(u32); 599 memcpy(npu_slot->args, cmd, cmd_len); 600 601 *size = sizeof(*npu_slot) + cmd_len; 602 return 0; 603 } 604 605 static int 606 aie2_cmdlist_fill_npu_dpu(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size) 607 { 608 struct cmd_chain_slot_npu *npu_slot = slot; 609 struct amdxdna_cmd_start_npu *sn; 610 u32 cmd_len; 611 u32 arg_sz; 612 613 sn = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 614 arg_sz = cmd_len - sizeof(*sn); 615 if (cmd_len < sizeof(*sn) || arg_sz > MAX_NPU_ARGS_SIZE) 616 return -EINVAL; 617 618 if (*size < sizeof(*npu_slot) + arg_sz) 619 return -EINVAL; 620 621 npu_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo); 622 if (npu_slot->cu_idx == INVALID_CU_IDX) 623 return -EINVAL; 624 625 memset(npu_slot, 0, sizeof(*npu_slot)); 626 npu_slot->type = EXEC_NPU_TYPE_PARTIAL_ELF; 627 npu_slot->inst_buf_addr = sn->buffer; 628 npu_slot->inst_size = sn->buffer_size; 629 npu_slot->inst_prop_cnt = sn->prop_count; 630 npu_slot->arg_cnt = arg_sz / sizeof(u32); 631 memcpy(npu_slot->args, sn->prop_args, arg_sz); 632 633 *size = sizeof(*npu_slot) + arg_sz; 634 return 0; 635 } 636 637 static u32 aie2_get_npu_chain_msg_op(u32 cmd_op) 638 { 639 return MSG_OP_CHAIN_EXEC_NPU; 640 } 641 642 static struct aie2_exec_msg_ops npu_exec_message_ops = { 643 .init_cu_req = aie2_init_exec_cu_req, 644 .init_dpu_req = aie2_init_exec_dpu_req, 645 .init_chain_req = aie2_init_npu_chain_req, 646 .fill_cf_slot = aie2_cmdlist_fill_npu_cf, 647 .fill_dpu_slot = aie2_cmdlist_fill_npu_dpu, 648 .get_chain_msg_op = aie2_get_npu_chain_msg_op, 649 }; 650 651 static int aie2_init_exec_req(void *req, struct amdxdna_gem_obj *cmd_abo, 652 size_t *size, u32 *msg_op) 653 { 654 struct amdxdna_dev *xdna = cmd_abo->client->xdna; 655 int ret; 656 u32 op; 657 658 659 op = amdxdna_cmd_get_op(cmd_abo); 660 switch (op) { 661 case ERT_START_CU: 662 ret = EXEC_MSG_OPS(xdna)->init_cu_req(cmd_abo, req, size, msg_op); 663 if (ret) { 664 XDNA_DBG(xdna, "Init CU req failed ret %d", ret); 665 return ret; 666 } 667 break; 668 case ERT_START_NPU: 669 ret = EXEC_MSG_OPS(xdna)->init_dpu_req(cmd_abo, req, size, msg_op); 670 if (ret) { 671 XDNA_DBG(xdna, "Init DPU req failed ret %d", ret); 672 return ret; 673 } 674 675 break; 676 default: 677 XDNA_ERR(xdna, "Unsupported op %d", op); 678 ret = -EOPNOTSUPP; 679 break; 680 } 681 682 return ret; 683 } 684 685 static int 686 aie2_cmdlist_fill_slot(void *slot, struct amdxdna_gem_obj *cmd_abo, 687 size_t *size, u32 *cmd_op) 688 { 689 struct amdxdna_dev *xdna = cmd_abo->client->xdna; 690 int ret; 691 u32 op; 692 693 op = amdxdna_cmd_get_op(cmd_abo); 694 if (*cmd_op == ERT_INVALID_CMD) 695 *cmd_op = op; 696 else if (op != *cmd_op) 697 return -EINVAL; 698 699 switch (op) { 700 case ERT_START_CU: 701 ret = EXEC_MSG_OPS(xdna)->fill_cf_slot(cmd_abo, slot, size); 702 break; 703 case ERT_START_NPU: 704 ret = EXEC_MSG_OPS(xdna)->fill_dpu_slot(cmd_abo, slot, size); 705 break; 706 default: 707 XDNA_INFO(xdna, "Unsupported op %d", op); 708 ret = -EOPNOTSUPP; 709 break; 710 } 711 712 return ret; 713 } 714 715 void aie2_msg_init(struct amdxdna_dev_hdl *ndev) 716 { 717 if (AIE2_FEATURE_ON(ndev, AIE2_NPU_COMMAND)) 718 ndev->exec_msg_ops = &npu_exec_message_ops; 719 else 720 ndev->exec_msg_ops = &legacy_exec_message_ops; 721 } 722 723 static inline struct amdxdna_gem_obj * 724 aie2_cmdlist_get_cmd_buf(struct amdxdna_sched_job *job) 725 { 726 int idx = get_job_idx(job->seq); 727 728 return job->hwctx->priv->cmd_buf[idx]; 729 } 730 731 int aie2_execbuf(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, 732 int (*notify_cb)(void *, void __iomem *, size_t)) 733 { 734 struct mailbox_channel *chann = hwctx->priv->mbox_chann; 735 struct amdxdna_dev *xdna = hwctx->client->xdna; 736 struct amdxdna_gem_obj *cmd_abo = job->cmd_bo; 737 struct xdna_mailbox_msg msg; 738 union exec_req req; 739 int ret; 740 741 if (!chann) 742 return -ENODEV; 743 744 ret = aie2_init_exec_req(&req, cmd_abo, &msg.send_size, &msg.opcode); 745 if (ret) 746 return ret; 747 748 msg.handle = job; 749 msg.notify_cb = notify_cb; 750 msg.send_data = (u8 *)&req; 751 print_hex_dump_debug("cmd: ", DUMP_PREFIX_OFFSET, 16, 4, &req, 752 0x40, false); 753 754 ret = xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT); 755 if (ret) { 756 XDNA_ERR(xdna, "Send message failed"); 757 return ret; 758 } 759 760 return 0; 761 } 762 763 int aie2_cmdlist_multi_execbuf(struct amdxdna_hwctx *hwctx, 764 struct amdxdna_sched_job *job, 765 int (*notify_cb)(void *, void __iomem *, size_t)) 766 { 767 struct amdxdna_gem_obj *cmdbuf_abo = aie2_cmdlist_get_cmd_buf(job); 768 struct mailbox_channel *chann = hwctx->priv->mbox_chann; 769 struct amdxdna_client *client = hwctx->client; 770 struct amdxdna_gem_obj *cmd_abo = job->cmd_bo; 771 struct amdxdna_dev *xdna = client->xdna; 772 struct amdxdna_cmd_chain *payload; 773 struct xdna_mailbox_msg msg; 774 union exec_chain_req req; 775 u32 payload_len; 776 u32 offset = 0; 777 size_t size; 778 int ret; 779 u32 op; 780 u32 i; 781 782 op = amdxdna_cmd_get_op(cmd_abo); 783 payload = amdxdna_cmd_get_payload(cmd_abo, &payload_len); 784 if (op != ERT_CMD_CHAIN || !payload || 785 payload_len < struct_size(payload, data, payload->command_count)) 786 return -EINVAL; 787 788 op = ERT_INVALID_CMD; 789 for (i = 0; i < payload->command_count; i++) { 790 u32 boh = (u32)(payload->data[i]); 791 struct amdxdna_gem_obj *abo; 792 793 abo = amdxdna_gem_get_obj(client, boh, AMDXDNA_BO_CMD); 794 if (!abo) { 795 XDNA_ERR(xdna, "Failed to find cmd BO %d", boh); 796 return -ENOENT; 797 } 798 799 size = cmdbuf_abo->mem.size - offset; 800 ret = aie2_cmdlist_fill_slot(cmdbuf_abo->mem.kva + offset, 801 abo, &size, &op); 802 amdxdna_gem_put_obj(abo); 803 if (ret) 804 return ret; 805 806 offset += size; 807 } 808 msg.opcode = EXEC_MSG_OPS(xdna)->get_chain_msg_op(op); 809 if (msg.opcode == MSG_OP_MAX_OPCODE) 810 return -EOPNOTSUPP; 811 812 /* The offset is the accumulated total size of the cmd buffer */ 813 EXEC_MSG_OPS(xdna)->init_chain_req(&req, cmdbuf_abo->mem.dev_addr, 814 offset, payload->command_count); 815 drm_clflush_virt_range(cmdbuf_abo->mem.kva, offset); 816 817 msg.handle = job; 818 msg.notify_cb = notify_cb; 819 msg.send_data = (u8 *)&req; 820 msg.send_size = sizeof(req); 821 ret = xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT); 822 if (ret) { 823 XDNA_ERR(xdna, "Send message failed"); 824 return ret; 825 } 826 827 return 0; 828 } 829 830 int aie2_cmdlist_single_execbuf(struct amdxdna_hwctx *hwctx, 831 struct amdxdna_sched_job *job, 832 int (*notify_cb)(void *, void __iomem *, size_t)) 833 { 834 struct amdxdna_gem_obj *cmdbuf_abo = aie2_cmdlist_get_cmd_buf(job); 835 struct mailbox_channel *chann = hwctx->priv->mbox_chann; 836 struct amdxdna_dev *xdna = hwctx->client->xdna; 837 struct amdxdna_gem_obj *cmd_abo = job->cmd_bo; 838 struct xdna_mailbox_msg msg; 839 union exec_chain_req req; 840 u32 op = ERT_INVALID_CMD; 841 size_t size; 842 int ret; 843 844 size = cmdbuf_abo->mem.size; 845 ret = aie2_cmdlist_fill_slot(cmdbuf_abo->mem.kva, cmd_abo, &size, &op); 846 if (ret) 847 return ret; 848 849 msg.opcode = EXEC_MSG_OPS(xdna)->get_chain_msg_op(op); 850 if (msg.opcode == MSG_OP_MAX_OPCODE) 851 return -EOPNOTSUPP; 852 853 EXEC_MSG_OPS(xdna)->init_chain_req(&req, cmdbuf_abo->mem.dev_addr, 854 size, 1); 855 drm_clflush_virt_range(cmdbuf_abo->mem.kva, size); 856 857 msg.handle = job; 858 msg.notify_cb = notify_cb; 859 msg.send_data = (u8 *)&req; 860 msg.send_size = sizeof(req); 861 ret = xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT); 862 if (ret) { 863 XDNA_ERR(hwctx->client->xdna, "Send message failed"); 864 return ret; 865 } 866 867 return 0; 868 } 869 870 int aie2_sync_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, 871 int (*notify_cb)(void *, void __iomem *, size_t)) 872 { 873 struct mailbox_channel *chann = hwctx->priv->mbox_chann; 874 struct amdxdna_gem_obj *abo = to_xdna_obj(job->bos[0]); 875 struct amdxdna_dev *xdna = hwctx->client->xdna; 876 struct xdna_mailbox_msg msg; 877 struct sync_bo_req req; 878 int ret = 0; 879 880 req.src_addr = 0; 881 req.dst_addr = amdxdna_dev_bo_offset(abo); 882 req.size = abo->mem.size; 883 884 /* Device to Host */ 885 req.type = FIELD_PREP(AIE2_MSG_SYNC_BO_SRC_TYPE, SYNC_BO_DEV_MEM) | 886 FIELD_PREP(AIE2_MSG_SYNC_BO_DST_TYPE, SYNC_BO_HOST_MEM); 887 888 XDNA_DBG(xdna, "sync %d bytes src(0x%llx) to dst(0x%llx) completed", 889 req.size, req.src_addr, req.dst_addr); 890 891 msg.handle = job; 892 msg.notify_cb = notify_cb; 893 msg.send_data = (u8 *)&req; 894 msg.send_size = sizeof(req); 895 msg.opcode = MSG_OP_SYNC_BO; 896 897 ret = xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT); 898 if (ret) { 899 XDNA_ERR(xdna, "Send message failed"); 900 return ret; 901 } 902 903 return 0; 904 } 905 906 int aie2_config_debug_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, 907 int (*notify_cb)(void *, void __iomem *, size_t)) 908 { 909 struct mailbox_channel *chann = hwctx->priv->mbox_chann; 910 struct amdxdna_gem_obj *abo = to_xdna_obj(job->bos[0]); 911 struct amdxdna_dev *xdna = hwctx->client->xdna; 912 struct config_debug_bo_req req; 913 struct xdna_mailbox_msg msg; 914 915 if (job->drv_cmd->opcode == ATTACH_DEBUG_BO) 916 req.config = DEBUG_BO_REGISTER; 917 else 918 req.config = DEBUG_BO_UNREGISTER; 919 920 req.offset = amdxdna_dev_bo_offset(abo); 921 req.size = abo->mem.size; 922 923 XDNA_DBG(xdna, "offset 0x%llx size 0x%llx config %d", 924 req.offset, req.size, req.config); 925 926 msg.handle = job; 927 msg.notify_cb = notify_cb; 928 msg.send_data = (u8 *)&req; 929 msg.send_size = sizeof(req); 930 msg.opcode = MSG_OP_CONFIG_DEBUG_BO; 931 932 return xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT); 933 } 934