xref: /linux/arch/xtensa/kernel/setup.c (revision c537b994505099b7197e7d3125b942ecbcc51eb6)
1 /*
2  * arch/xtensa/kernel/setup.c
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1995  Linus Torvalds
9  * Copyright (C) 2001 - 2005  Tensilica Inc.
10  *
11  * Chris Zankel	<chris@zankel.net>
12  * Joe Taylor	<joe@tensilica.com, joetylr@yahoo.com>
13  * Kevin Chea
14  * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
15  */
16 
17 #include <linux/errno.h>
18 #include <linux/init.h>
19 #include <linux/proc_fs.h>
20 #include <linux/screen_info.h>
21 #include <linux/bootmem.h>
22 #include <linux/kernel.h>
23 
24 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
25 # include <linux/console.h>
26 #endif
27 
28 #ifdef CONFIG_RTC
29 # include <linux/timex.h>
30 #endif
31 
32 #ifdef CONFIG_PROC_FS
33 # include <linux/seq_file.h>
34 #endif
35 
36 #include <asm/system.h>
37 #include <asm/bootparam.h>
38 #include <asm/pgtable.h>
39 #include <asm/processor.h>
40 #include <asm/timex.h>
41 #include <asm/platform.h>
42 #include <asm/page.h>
43 #include <asm/setup.h>
44 
45 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
46 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
47 #endif
48 
49 #ifdef CONFIG_BLK_DEV_FD
50 extern struct fd_ops no_fd_ops;
51 struct fd_ops *fd_ops;
52 #endif
53 
54 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
55 extern struct ide_ops no_ide_ops;
56 struct ide_ops *ide_ops;
57 #endif
58 
59 extern struct rtc_ops no_rtc_ops;
60 struct rtc_ops *rtc_ops;
61 
62 #ifdef CONFIG_PC_KEYB
63 extern struct kbd_ops no_kbd_ops;
64 struct kbd_ops *kbd_ops;
65 #endif
66 
67 #ifdef CONFIG_BLK_DEV_INITRD
68 extern void *initrd_start;
69 extern void *initrd_end;
70 extern void *__initrd_start;
71 extern void *__initrd_end;
72 int initrd_is_mapped = 0;
73 extern int initrd_below_start_ok;
74 #endif
75 
76 unsigned char aux_device_present;
77 extern unsigned long loops_per_jiffy;
78 
79 /* Command line specified as configuration option. */
80 
81 static char __initdata command_line[COMMAND_LINE_SIZE];
82 
83 #ifdef CONFIG_CMDLINE_BOOL
84 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
85 #endif
86 
87 sysmem_info_t __initdata sysmem;
88 
89 #ifdef CONFIG_BLK_DEV_INITRD
90 int initrd_is_mapped;
91 #endif
92 
93 extern void init_mmu(void);
94 
95 /*
96  * Boot parameter parsing.
97  *
98  * The Xtensa port uses a list of variable-sized tags to pass data to
99  * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
100  * to be recognised. The list is terminated with a zero-sized
101  * BP_TAG_LAST tag.
102  */
103 
104 typedef struct tagtable {
105 	u32 tag;
106 	int (*parse)(const bp_tag_t*);
107 } tagtable_t;
108 
109 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn 		\
110 	__attribute__((unused, __section__(".taglist"))) = { tag, fn }
111 
112 /* parse current tag */
113 
114 static int __init parse_tag_mem(const bp_tag_t *tag)
115 {
116 	meminfo_t *mi = (meminfo_t*)(tag->data);
117 
118 	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
119 		return -1;
120 
121 	if (sysmem.nr_banks >= SYSMEM_BANKS_MAX) {
122 		printk(KERN_WARNING
123 		       "Ignoring memory bank 0x%08lx size %ldKB\n",
124 		       (unsigned long)mi->start,
125 		       (unsigned long)mi->end - (unsigned long)mi->start);
126 		return -EINVAL;
127 	}
128 	sysmem.bank[sysmem.nr_banks].type  = mi->type;
129 	sysmem.bank[sysmem.nr_banks].start = PAGE_ALIGN(mi->start);
130 	sysmem.bank[sysmem.nr_banks].end   = mi->end & PAGE_SIZE;
131 	sysmem.nr_banks++;
132 
133 	return 0;
134 }
135 
136 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
137 
138 #ifdef CONFIG_BLK_DEV_INITRD
139 
140 static int __init parse_tag_initrd(const bp_tag_t* tag)
141 {
142 	meminfo_t* mi;
143 	mi = (meminfo_t*)(tag->data);
144 	initrd_start = (void*)(mi->start);
145 	initrd_end = (void*)(mi->end);
146 
147 	return 0;
148 }
149 
150 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
151 
152 #endif /* CONFIG_BLK_DEV_INITRD */
153 
154 static int __init parse_tag_cmdline(const bp_tag_t* tag)
155 {
156 	strncpy(command_line, (char*)(tag->data), COMMAND_LINE_SIZE);
157 	command_line[COMMAND_LINE_SIZE - 1] = '\0';
158 	return 0;
159 }
160 
161 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
162 
163 static int __init parse_bootparam(const bp_tag_t* tag)
164 {
165 	extern tagtable_t __tagtable_begin, __tagtable_end;
166 	tagtable_t *t;
167 
168 	/* Boot parameters must start with a BP_TAG_FIRST tag. */
169 
170 	if (tag->id != BP_TAG_FIRST) {
171 		printk(KERN_WARNING "Invalid boot parameters!\n");
172 		return 0;
173 	}
174 
175 	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
176 
177 	/* Parse all tags. */
178 
179 	while (tag != NULL && tag->id != BP_TAG_LAST) {
180 	 	for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
181 			if (tag->id == t->tag) {
182 				t->parse(tag);
183 				break;
184 			}
185 		}
186 		if (t == &__tagtable_end)
187 			printk(KERN_WARNING "Ignoring tag "
188 			       "0x%08x\n", tag->id);
189 		tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
190 	}
191 
192 	return 0;
193 }
194 
195 /*
196  * Initialize architecture. (Early stage)
197  */
198 
199 void __init init_arch(bp_tag_t *bp_start)
200 {
201 
202 #ifdef CONFIG_BLK_DEV_INITRD
203 	initrd_start = &__initrd_start;
204 	initrd_end = &__initrd_end;
205 #endif
206 
207 	sysmem.nr_banks = 0;
208 
209 #ifdef CONFIG_CMDLINE_BOOL
210 	strcpy(command_line, default_command_line);
211 #endif
212 
213 	/* Parse boot parameters */
214 
215         if (bp_start)
216 	  parse_bootparam(bp_start);
217 
218 	if (sysmem.nr_banks == 0) {
219 		sysmem.nr_banks = 1;
220 		sysmem.bank[0].start = PLATFORM_DEFAULT_MEM_START;
221 		sysmem.bank[0].end = PLATFORM_DEFAULT_MEM_START
222 				     + PLATFORM_DEFAULT_MEM_SIZE;
223 	}
224 
225 	/* Early hook for platforms */
226 
227 	platform_init(bp_start);
228 
229 	/* Initialize MMU. */
230 
231 	init_mmu();
232 }
233 
234 /*
235  * Initialize system. Setup memory and reserve regions.
236  */
237 
238 extern char _end;
239 extern char _stext;
240 extern char _WindowVectors_text_start;
241 extern char _WindowVectors_text_end;
242 extern char _DebugInterruptVector_literal_start;
243 extern char _DebugInterruptVector_text_end;
244 extern char _KernelExceptionVector_literal_start;
245 extern char _KernelExceptionVector_text_end;
246 extern char _UserExceptionVector_literal_start;
247 extern char _UserExceptionVector_text_end;
248 extern char _DoubleExceptionVector_literal_start;
249 extern char _DoubleExceptionVector_text_end;
250 
251 void __init setup_arch(char **cmdline_p)
252 {
253 	extern int mem_reserve(unsigned long, unsigned long, int);
254 	extern void bootmem_init(void);
255 
256 	memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
257 	boot_command_line[COMMAND_LINE_SIZE-1] = '\0';
258 	*cmdline_p = command_line;
259 
260 	/* Reserve some memory regions */
261 
262 #ifdef CONFIG_BLK_DEV_INITRD
263 	if (initrd_start < initrd_end) {
264 		initrd_is_mapped = mem_reserve(__pa(initrd_start),
265 					       __pa(initrd_end), 0);
266 		initrd_below_start_ok = 1;
267  	} else {
268 		initrd_start = 0;
269 	}
270 #endif
271 
272 	mem_reserve(__pa(&_stext),__pa(&_end), 1);
273 
274 	mem_reserve(__pa(&_WindowVectors_text_start),
275 		    __pa(&_WindowVectors_text_end), 0);
276 
277 	mem_reserve(__pa(&_DebugInterruptVector_literal_start),
278 		    __pa(&_DebugInterruptVector_text_end), 0);
279 
280 	mem_reserve(__pa(&_KernelExceptionVector_literal_start),
281 		    __pa(&_KernelExceptionVector_text_end), 0);
282 
283 	mem_reserve(__pa(&_UserExceptionVector_literal_start),
284 		    __pa(&_UserExceptionVector_text_end), 0);
285 
286 	mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
287 		    __pa(&_DoubleExceptionVector_text_end), 0);
288 
289 	bootmem_init();
290 
291 	platform_setup(cmdline_p);
292 
293 
294 	paging_init();
295 
296 #ifdef CONFIG_VT
297 # if defined(CONFIG_VGA_CONSOLE)
298 	conswitchp = &vga_con;
299 # elif defined(CONFIG_DUMMY_CONSOLE)
300 	conswitchp = &dummy_con;
301 # endif
302 #endif
303 
304 #ifdef CONFIG_PCI
305 	platform_pcibios_init();
306 #endif
307 }
308 
309 void machine_restart(char * cmd)
310 {
311 	platform_restart();
312 }
313 
314 void machine_halt(void)
315 {
316 	platform_halt();
317 	while (1);
318 }
319 
320 void machine_power_off(void)
321 {
322 	platform_power_off();
323 	while (1);
324 }
325 #ifdef CONFIG_PROC_FS
326 
327 /*
328  * Display some core information through /proc/cpuinfo.
329  */
330 
331 static int
332 c_show(struct seq_file *f, void *slot)
333 {
334 	/* high-level stuff */
335 	seq_printf(f,"processor\t: 0\n"
336 		     "vendor_id\t: Tensilica\n"
337 		     "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
338 		     "core ID\t\t: " XCHAL_CORE_ID "\n"
339 		     "build ID\t: 0x%x\n"
340 		     "byte order\t: %s\n"
341  		     "cpu MHz\t\t: %lu.%02lu\n"
342 		     "bogomips\t: %lu.%02lu\n",
343 		     XCHAL_BUILD_UNIQUE_ID,
344 		     XCHAL_HAVE_BE ?  "big" : "little",
345 		     CCOUNT_PER_JIFFY/(1000000/HZ),
346 		     (CCOUNT_PER_JIFFY/(10000/HZ)) % 100,
347 		     loops_per_jiffy/(500000/HZ),
348 		     (loops_per_jiffy/(5000/HZ)) % 100);
349 
350 	seq_printf(f,"flags\t\t: "
351 #if XCHAL_HAVE_NMI
352 		     "nmi "
353 #endif
354 #if XCHAL_HAVE_DEBUG
355 		     "debug "
356 # if XCHAL_HAVE_OCD
357 		     "ocd "
358 # endif
359 #endif
360 #if XCHAL_HAVE_DENSITY
361 	    	     "density "
362 #endif
363 #if XCHAL_HAVE_BOOLEANS
364 		     "boolean "
365 #endif
366 #if XCHAL_HAVE_LOOPS
367 		     "loop "
368 #endif
369 #if XCHAL_HAVE_NSA
370 		     "nsa "
371 #endif
372 #if XCHAL_HAVE_MINMAX
373 		     "minmax "
374 #endif
375 #if XCHAL_HAVE_SEXT
376 		     "sext "
377 #endif
378 #if XCHAL_HAVE_CLAMPS
379 		     "clamps "
380 #endif
381 #if XCHAL_HAVE_MAC16
382 		     "mac16 "
383 #endif
384 #if XCHAL_HAVE_MUL16
385 		     "mul16 "
386 #endif
387 #if XCHAL_HAVE_MUL32
388 		     "mul32 "
389 #endif
390 #if XCHAL_HAVE_MUL32_HIGH
391 		     "mul32h "
392 #endif
393 #if XCHAL_HAVE_FP
394 		     "fpu "
395 #endif
396 		     "\n");
397 
398 	/* Registers. */
399 	seq_printf(f,"physical aregs\t: %d\n"
400 		     "misc regs\t: %d\n"
401 		     "ibreak\t\t: %d\n"
402 		     "dbreak\t\t: %d\n",
403 		     XCHAL_NUM_AREGS,
404 		     XCHAL_NUM_MISC_REGS,
405 		     XCHAL_NUM_IBREAK,
406 		     XCHAL_NUM_DBREAK);
407 
408 
409 	/* Interrupt. */
410 	seq_printf(f,"num ints\t: %d\n"
411 		     "ext ints\t: %d\n"
412 		     "int levels\t: %d\n"
413 		     "timers\t\t: %d\n"
414 		     "debug level\t: %d\n",
415 		     XCHAL_NUM_INTERRUPTS,
416 		     XCHAL_NUM_EXTINTERRUPTS,
417 		     XCHAL_NUM_INTLEVELS,
418 		     XCHAL_NUM_TIMERS,
419 		     XCHAL_DEBUGLEVEL);
420 
421 	/* Cache */
422 	seq_printf(f,"icache line size: %d\n"
423 		     "icache ways\t: %d\n"
424 		     "icache size\t: %d\n"
425 		     "icache flags\t: "
426 #if XCHAL_ICACHE_LINE_LOCKABLE
427 		     "lock"
428 #endif
429 		     "\n"
430 		     "dcache line size: %d\n"
431 		     "dcache ways\t: %d\n"
432 		     "dcache size\t: %d\n"
433 		     "dcache flags\t: "
434 #if XCHAL_DCACHE_IS_WRITEBACK
435 		     "writeback"
436 #endif
437 #if XCHAL_DCACHE_LINE_LOCKABLE
438 		     "lock"
439 #endif
440 		     "\n",
441 		     XCHAL_ICACHE_LINESIZE,
442 		     XCHAL_ICACHE_WAYS,
443 		     XCHAL_ICACHE_SIZE,
444 		     XCHAL_DCACHE_LINESIZE,
445 		     XCHAL_DCACHE_WAYS,
446 		     XCHAL_DCACHE_SIZE);
447 
448 	return 0;
449 }
450 
451 /*
452  * We show only CPU #0 info.
453  */
454 static void *
455 c_start(struct seq_file *f, loff_t *pos)
456 {
457 	return (void *) ((*pos == 0) ? (void *)1 : NULL);
458 }
459 
460 static void *
461 c_next(struct seq_file *f, void *v, loff_t *pos)
462 {
463 	return NULL;
464 }
465 
466 static void
467 c_stop(struct seq_file *f, void *v)
468 {
469 }
470 
471 struct seq_operations cpuinfo_op =
472 {
473 	start:  c_start,
474 	next:   c_next,
475 	stop:   c_stop,
476 	show:   c_show
477 };
478 
479 #endif /* CONFIG_PROC_FS */
480 
481