1c622b29dSMax Filippov /* 2c622b29dSMax Filippov * arch/xtensa/include/asm/initialize_mmu.h 3c622b29dSMax Filippov * 4c622b29dSMax Filippov * Initializes MMU: 5c622b29dSMax Filippov * 6c622b29dSMax Filippov * For the new V3 MMU we remap the TLB from virtual == physical 7c622b29dSMax Filippov * to the standard Linux mapping used in earlier MMU's. 8c622b29dSMax Filippov * 910b60595SRandy Dunlap * For the MMU we also support a new configuration register that 10c622b29dSMax Filippov * specifies how the S32C1I instruction operates with the cache 11c622b29dSMax Filippov * controller. 12c622b29dSMax Filippov * 13c622b29dSMax Filippov * This file is subject to the terms and conditions of the GNU General 14c622b29dSMax Filippov * Public License. See the file "COPYING" in the main directory of 15c622b29dSMax Filippov * this archive for more details. 16c622b29dSMax Filippov * 17c622b29dSMax Filippov * Copyright (C) 2008 - 2012 Tensilica, Inc. 18c622b29dSMax Filippov * 19c622b29dSMax Filippov * Marc Gauthier <marc@tensilica.com> 20c622b29dSMax Filippov * Pete Delaney <piet@tensilica.com> 21c622b29dSMax Filippov */ 22c622b29dSMax Filippov 23c622b29dSMax Filippov #ifndef _XTENSA_INITIALIZE_MMU_H 24c622b29dSMax Filippov #define _XTENSA_INITIALIZE_MMU_H 25c622b29dSMax Filippov 266af4ab57SMax Filippov #include <linux/init.h> 27ca5999fdSMike Rapoport #include <linux/pgtable.h> 28e85e335fSMax Filippov #include <asm/vectors.h> 29e85e335fSMax Filippov 302eabc180SMax Filippov #if XCHAL_HAVE_PTP_MMU 316cb97111SBaruch Siach #define CA_BYPASS (_PAGE_CA_BYPASS | _PAGE_HW_WRITE | _PAGE_HW_EXEC) 326cb97111SBaruch Siach #define CA_WRITEBACK (_PAGE_CA_WB | _PAGE_HW_WRITE | _PAGE_HW_EXEC) 332eabc180SMax Filippov #else 342eabc180SMax Filippov #define CA_WRITEBACK (0x4) 352eabc180SMax Filippov #endif 362eabc180SMax Filippov 37c622b29dSMax Filippov #ifdef __ASSEMBLY__ 38c622b29dSMax Filippov 39c622b29dSMax Filippov #define XTENSA_HWVERSION_RC_2009_0 230000 40c622b29dSMax Filippov 41c622b29dSMax Filippov .macro initialize_mmu 42c622b29dSMax Filippov 43c622b29dSMax Filippov #if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) 44c622b29dSMax Filippov /* 45c622b29dSMax Filippov * We Have Atomic Operation Control (ATOMCTL) Register; Initialize it. 46*87670c57SJonathan Corbet * For details see Documentation/arch/xtensa/atomctl.rst 47c622b29dSMax Filippov */ 48c622b29dSMax Filippov #if XCHAL_DCACHE_IS_COHERENT 49c622b29dSMax Filippov movi a3, 0x25 /* For SMP/MX -- internal for writeback, 50c622b29dSMax Filippov * RCW otherwise 51c622b29dSMax Filippov */ 52c622b29dSMax Filippov #else 53c622b29dSMax Filippov movi a3, 0x29 /* non-MX -- Most cores use Std Memory 54c622b29dSMax Filippov * Controlers which usually can't use RCW 55c622b29dSMax Filippov */ 56c622b29dSMax Filippov #endif 57c622b29dSMax Filippov wsr a3, atomctl 58c622b29dSMax Filippov #endif /* XCHAL_HAVE_S32C1I && 59c622b29dSMax Filippov * (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) 60c622b29dSMax Filippov */ 61c622b29dSMax Filippov 62e85e335fSMax Filippov #if defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY 63e85e335fSMax Filippov /* 64e85e335fSMax Filippov * Have MMU v3 65e85e335fSMax Filippov */ 66e85e335fSMax Filippov 67e85e335fSMax Filippov #if !XCHAL_HAVE_VECBASE 68e85e335fSMax Filippov # error "MMU v3 requires reloc vectors" 69e85e335fSMax Filippov #endif 70e85e335fSMax Filippov 71e85e335fSMax Filippov movi a1, 0 72e85e335fSMax Filippov _call0 1f 73e85e335fSMax Filippov _j 2f 74e85e335fSMax Filippov 75e85e335fSMax Filippov .align 4 76f96c4ad6SMax Filippov 1: 77a9f2fc62SMax Filippov 78a9f2fc62SMax Filippov #if CONFIG_KERNEL_LOAD_ADDRESS < 0x40000000ul 79a9f2fc62SMax Filippov #define TEMP_MAPPING_VADDR 0x40000000 80a9f2fc62SMax Filippov #else 81a9f2fc62SMax Filippov #define TEMP_MAPPING_VADDR 0x00000000 82a9f2fc62SMax Filippov #endif 83e85e335fSMax Filippov 84e85e335fSMax Filippov /* Step 1: invalidate mapping at 0x40000000..0x5FFFFFFF. */ 85e85e335fSMax Filippov 86a9f2fc62SMax Filippov movi a2, TEMP_MAPPING_VADDR | XCHAL_SPANNING_WAY 87e85e335fSMax Filippov idtlb a2 88e85e335fSMax Filippov iitlb a2 89e85e335fSMax Filippov isync 90e85e335fSMax Filippov 91e85e335fSMax Filippov /* Step 2: map 0x40000000..0x47FFFFFF to paddr containing this code 92e85e335fSMax Filippov * and jump to the new mapping. 93e85e335fSMax Filippov */ 94e85e335fSMax Filippov 95e85e335fSMax Filippov srli a3, a0, 27 96e85e335fSMax Filippov slli a3, a3, 27 97e85e335fSMax Filippov addi a3, a3, CA_BYPASS 98a9f2fc62SMax Filippov addi a7, a2, 5 - XCHAL_SPANNING_WAY 99e85e335fSMax Filippov wdtlb a3, a7 100e85e335fSMax Filippov witlb a3, a7 101e85e335fSMax Filippov isync 102e85e335fSMax Filippov 103e85e335fSMax Filippov slli a4, a0, 5 104e85e335fSMax Filippov srli a4, a4, 5 105a9f2fc62SMax Filippov addi a5, a2, -XCHAL_SPANNING_WAY 106e85e335fSMax Filippov add a4, a4, a5 107e85e335fSMax Filippov jx a4 108e85e335fSMax Filippov 109e85e335fSMax Filippov /* Step 3: unmap everything other than current area. 110e85e335fSMax Filippov * Start at 0x60000000, wrap around, and end with 0x20000000 111e85e335fSMax Filippov */ 112e85e335fSMax Filippov 2: movi a4, 0x20000000 113e85e335fSMax Filippov add a5, a2, a4 114e85e335fSMax Filippov 3: idtlb a5 115e85e335fSMax Filippov iitlb a5 116e85e335fSMax Filippov add a5, a5, a4 117e85e335fSMax Filippov bne a5, a2, 3b 118e85e335fSMax Filippov 119d39af902SMax Filippov /* Step 4: Setup MMU with the requested static mappings. */ 120d39af902SMax Filippov 121e85e335fSMax Filippov movi a6, 0x01000000 122e85e335fSMax Filippov wsr a6, ITLBCFG 123e85e335fSMax Filippov wsr a6, DTLBCFG 124e85e335fSMax Filippov isync 125e85e335fSMax Filippov 126d39af902SMax Filippov movi a5, XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_TLB_WAY 127d39af902SMax Filippov movi a4, XCHAL_KSEG_PADDR + CA_WRITEBACK 128e85e335fSMax Filippov wdtlb a4, a5 129e85e335fSMax Filippov witlb a4, a5 130e85e335fSMax Filippov 131d39af902SMax Filippov movi a5, XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_TLB_WAY 132d39af902SMax Filippov movi a4, XCHAL_KSEG_PADDR + CA_BYPASS 133e85e335fSMax Filippov wdtlb a4, a5 134e85e335fSMax Filippov witlb a4, a5 135e85e335fSMax Filippov 136d39af902SMax Filippov #ifdef CONFIG_XTENSA_KSEG_512M 137d39af902SMax Filippov movi a5, XCHAL_KSEG_CACHED_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY 138d39af902SMax Filippov movi a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_WRITEBACK 139d39af902SMax Filippov wdtlb a4, a5 140d39af902SMax Filippov witlb a4, a5 141d39af902SMax Filippov 142d39af902SMax Filippov movi a5, XCHAL_KSEG_BYPASS_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY 143d39af902SMax Filippov movi a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_BYPASS 144d39af902SMax Filippov wdtlb a4, a5 145d39af902SMax Filippov witlb a4, a5 146d39af902SMax Filippov #endif 147d39af902SMax Filippov 148a9f2fc62SMax Filippov movi a5, XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_TLB_WAY 1496cb97111SBaruch Siach movi a4, XCHAL_KIO_DEFAULT_PADDR + CA_WRITEBACK 150e85e335fSMax Filippov wdtlb a4, a5 151e85e335fSMax Filippov witlb a4, a5 152e85e335fSMax Filippov 153a9f2fc62SMax Filippov movi a5, XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_TLB_WAY 1546cb97111SBaruch Siach movi a4, XCHAL_KIO_DEFAULT_PADDR + CA_BYPASS 155e85e335fSMax Filippov wdtlb a4, a5 156e85e335fSMax Filippov witlb a4, a5 157e85e335fSMax Filippov 158e85e335fSMax Filippov isync 159e85e335fSMax Filippov 160a9f2fc62SMax Filippov /* Jump to self, using final mappings. */ 161e85e335fSMax Filippov movi a4, 1f 162e85e335fSMax Filippov jx a4 163e85e335fSMax Filippov 164e85e335fSMax Filippov 1: 165e85e335fSMax Filippov /* Step 5: remove temporary mapping. */ 166e85e335fSMax Filippov idtlb a7 167e85e335fSMax Filippov iitlb a7 168e85e335fSMax Filippov isync 169e85e335fSMax Filippov 170e85e335fSMax Filippov movi a0, 0 171e85e335fSMax Filippov wsr a0, ptevaddr 172e85e335fSMax Filippov rsync 173e85e335fSMax Filippov 174e85e335fSMax Filippov #endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && 175e85e335fSMax Filippov XCHAL_HAVE_SPANNING_WAY */ 176e85e335fSMax Filippov 1777bb516caSMax Filippov .endm 1782eabc180SMax Filippov 1797bb516caSMax Filippov .macro initialize_cacheattr 1807bb516caSMax Filippov 181a5944195SMax Filippov #if !defined(CONFIG_MMU) && (XCHAL_HAVE_TLBS || XCHAL_HAVE_MPU) 1827bb516caSMax Filippov #if CONFIG_MEMMAP_CACHEATTR == 0x22222222 && XCHAL_HAVE_PTP_MMU 1837bb516caSMax Filippov #error Default MEMMAP_CACHEATTR of 0x22222222 does not work with full MMU. 1847bb516caSMax Filippov #endif 1857bb516caSMax Filippov 186a5944195SMax Filippov #if XCHAL_HAVE_MPU 1876af4ab57SMax Filippov __REFCONST 188a5944195SMax Filippov .align 4 189a5944195SMax Filippov .Lattribute_table: 190a5944195SMax Filippov .long 0x000000, 0x1fff00, 0x1ddf00, 0x1eef00 191a5944195SMax Filippov .long 0x006600, 0x000000, 0x000000, 0x000000 192a5944195SMax Filippov .long 0x000000, 0x000000, 0x000000, 0x000000 193a5944195SMax Filippov .long 0x000000, 0x000000, 0x000000, 0x000000 194a5944195SMax Filippov .previous 195a5944195SMax Filippov 196a5944195SMax Filippov movi a3, .Lattribute_table 197a5944195SMax Filippov movi a4, CONFIG_MEMMAP_CACHEATTR 198a5944195SMax Filippov movi a5, 1 199a5944195SMax Filippov movi a6, XCHAL_MPU_ENTRIES 200a5944195SMax Filippov movi a10, 0x20000000 201a5944195SMax Filippov movi a11, -1 202a5944195SMax Filippov 1: 203a5944195SMax Filippov sub a5, a5, a10 204a5944195SMax Filippov extui a8, a4, 28, 4 205a5944195SMax Filippov beq a8, a11, 2f 206a5944195SMax Filippov addi a6, a6, -1 207a5944195SMax Filippov mov a11, a8 208a5944195SMax Filippov 2: 209a5944195SMax Filippov addx4 a9, a8, a3 210a5944195SMax Filippov l32i a9, a9, 0 211a5944195SMax Filippov or a9, a9, a6 212a5944195SMax Filippov wptlb a9, a5 213a5944195SMax Filippov slli a4, a4, 4 214a5944195SMax Filippov bgeu a5, a10, 1b 215a5944195SMax Filippov 216a5944195SMax Filippov #else 2177bb516caSMax Filippov movi a5, XCHAL_SPANNING_WAY 2182eabc180SMax Filippov movi a6, ~_PAGE_ATTRIB_MASK 2197bb516caSMax Filippov movi a4, CONFIG_MEMMAP_CACHEATTR 2202eabc180SMax Filippov movi a8, 0x20000000 2212eabc180SMax Filippov 1: 2222eabc180SMax Filippov rdtlb1 a3, a5 2237bb516caSMax Filippov xor a3, a3, a4 2242eabc180SMax Filippov and a3, a3, a6 2257bb516caSMax Filippov xor a3, a3, a4 2262eabc180SMax Filippov wdtlb a3, a5 2277bb516caSMax Filippov ritlb1 a3, a5 2287bb516caSMax Filippov xor a3, a3, a4 2297bb516caSMax Filippov and a3, a3, a6 2307bb516caSMax Filippov xor a3, a3, a4 2317bb516caSMax Filippov witlb a3, a5 2322eabc180SMax Filippov 2337bb516caSMax Filippov add a5, a5, a8 2347bb516caSMax Filippov srli a4, a4, 4 2357bb516caSMax Filippov bgeu a5, a8, 1b 2367bb516caSMax Filippov 2377bb516caSMax Filippov isync 2382eabc180SMax Filippov #endif 239a5944195SMax Filippov #endif 2402eabc180SMax Filippov 241c622b29dSMax Filippov .endm 242c622b29dSMax Filippov 243c622b29dSMax Filippov #endif /*__ASSEMBLY__*/ 244c622b29dSMax Filippov 245c622b29dSMax Filippov #endif /* _XTENSA_INITIALIZE_MMU_H */ 246