1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
2fb9aa6f1SThomas Gleixner /*
3fb9aa6f1SThomas Gleixner * Low-Level PCI Access for i386 machines
4fb9aa6f1SThomas Gleixner *
5fb9aa6f1SThomas Gleixner * Copyright 1993, 1994 Drew Eckhardt
6fb9aa6f1SThomas Gleixner * Visionary Computing
7fb9aa6f1SThomas Gleixner * (Unix and Linux consulting and custom programming)
8fb9aa6f1SThomas Gleixner * Drew@Colorado.EDU
9fb9aa6f1SThomas Gleixner * +1 (303) 786-7975
10fb9aa6f1SThomas Gleixner *
11fb9aa6f1SThomas Gleixner * Drew's work was sponsored by:
12fb9aa6f1SThomas Gleixner * iX Multiuser Multitasking Magazine
13fb9aa6f1SThomas Gleixner * Hannover, Germany
14fb9aa6f1SThomas Gleixner * hm@ix.de
15fb9aa6f1SThomas Gleixner *
16fb9aa6f1SThomas Gleixner * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
17fb9aa6f1SThomas Gleixner *
18fb9aa6f1SThomas Gleixner * For more information, please consult the following manuals (look at
19fb9aa6f1SThomas Gleixner * http://www.pcisig.com/ for how to get them):
20fb9aa6f1SThomas Gleixner *
21fb9aa6f1SThomas Gleixner * PCI BIOS Specification
22fb9aa6f1SThomas Gleixner * PCI Local Bus Specification
23fb9aa6f1SThomas Gleixner * PCI to PCI Bridge Specification
24fb9aa6f1SThomas Gleixner * PCI System Design Guide
25fb9aa6f1SThomas Gleixner *
26fb9aa6f1SThomas Gleixner */
27fb9aa6f1SThomas Gleixner
28fb9aa6f1SThomas Gleixner #include <linux/types.h>
29fb9aa6f1SThomas Gleixner #include <linux/kernel.h>
3069c60c88SPaul Gortmaker #include <linux/export.h>
31fb9aa6f1SThomas Gleixner #include <linux/pci.h>
32fb9aa6f1SThomas Gleixner #include <linux/init.h>
33fb9aa6f1SThomas Gleixner #include <linux/ioport.h>
34fb9aa6f1SThomas Gleixner #include <linux/errno.h>
3557c8a661SMike Rapoport #include <linux/memblock.h>
3603d72aa1Svenkatesh.pallipadi@intel.com
37eb243d1dSIngo Molnar #include <asm/memtype.h>
3866441bd3SIngo Molnar #include <asm/e820/api.h>
3982487711SJaswinder Singh Rajput #include <asm/pci_x86.h>
40857fdc53SYinghai Lu #include <asm/io_apic.h>
41fb9aa6f1SThomas Gleixner
42fb9aa6f1SThomas Gleixner
43925845bdSMyron Stowe /*
44925845bdSMyron Stowe * This list of dynamic mappings is for temporarily maintaining
45925845bdSMyron Stowe * original BIOS BAR addresses for possible reinstatement.
46925845bdSMyron Stowe */
47925845bdSMyron Stowe struct pcibios_fwaddrmap {
48925845bdSMyron Stowe struct list_head list;
49925845bdSMyron Stowe struct pci_dev *dev;
50925845bdSMyron Stowe resource_size_t fw_addr[DEVICE_COUNT_RESOURCE];
51925845bdSMyron Stowe };
52925845bdSMyron Stowe
53925845bdSMyron Stowe static LIST_HEAD(pcibios_fwaddrmappings);
54925845bdSMyron Stowe static DEFINE_SPINLOCK(pcibios_fwaddrmap_lock);
5574521602SYinghai Lu static bool pcibios_fw_addr_done;
56925845bdSMyron Stowe
57925845bdSMyron Stowe /* Must be called with 'pcibios_fwaddrmap_lock' lock held. */
pcibios_fwaddrmap_lookup(struct pci_dev * dev)58925845bdSMyron Stowe static struct pcibios_fwaddrmap *pcibios_fwaddrmap_lookup(struct pci_dev *dev)
59925845bdSMyron Stowe {
60925845bdSMyron Stowe struct pcibios_fwaddrmap *map;
61925845bdSMyron Stowe
62868f7a09SLance Roy lockdep_assert_held(&pcibios_fwaddrmap_lock);
6363ab387cSMyron Stowe
64925845bdSMyron Stowe list_for_each_entry(map, &pcibios_fwaddrmappings, list)
65925845bdSMyron Stowe if (map->dev == dev)
66925845bdSMyron Stowe return map;
67925845bdSMyron Stowe
68925845bdSMyron Stowe return NULL;
69925845bdSMyron Stowe }
70925845bdSMyron Stowe
71925845bdSMyron Stowe static void
pcibios_save_fw_addr(struct pci_dev * dev,int idx,resource_size_t fw_addr)72925845bdSMyron Stowe pcibios_save_fw_addr(struct pci_dev *dev, int idx, resource_size_t fw_addr)
73925845bdSMyron Stowe {
74925845bdSMyron Stowe unsigned long flags;
75925845bdSMyron Stowe struct pcibios_fwaddrmap *map;
76925845bdSMyron Stowe
7774521602SYinghai Lu if (pcibios_fw_addr_done)
7874521602SYinghai Lu return;
7974521602SYinghai Lu
80925845bdSMyron Stowe spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
81925845bdSMyron Stowe map = pcibios_fwaddrmap_lookup(dev);
82925845bdSMyron Stowe if (!map) {
83925845bdSMyron Stowe spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
84925845bdSMyron Stowe map = kzalloc(sizeof(*map), GFP_KERNEL);
85925845bdSMyron Stowe if (!map)
86925845bdSMyron Stowe return;
87925845bdSMyron Stowe
88925845bdSMyron Stowe map->dev = pci_dev_get(dev);
89925845bdSMyron Stowe map->fw_addr[idx] = fw_addr;
90925845bdSMyron Stowe INIT_LIST_HEAD(&map->list);
91925845bdSMyron Stowe
92925845bdSMyron Stowe spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
93925845bdSMyron Stowe list_add_tail(&map->list, &pcibios_fwaddrmappings);
94925845bdSMyron Stowe } else
95925845bdSMyron Stowe map->fw_addr[idx] = fw_addr;
96925845bdSMyron Stowe spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
97925845bdSMyron Stowe }
98925845bdSMyron Stowe
pcibios_retrieve_fw_addr(struct pci_dev * dev,int idx)99925845bdSMyron Stowe resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
100925845bdSMyron Stowe {
101925845bdSMyron Stowe unsigned long flags;
102925845bdSMyron Stowe struct pcibios_fwaddrmap *map;
103925845bdSMyron Stowe resource_size_t fw_addr = 0;
104925845bdSMyron Stowe
10574521602SYinghai Lu if (pcibios_fw_addr_done)
10674521602SYinghai Lu return 0;
10774521602SYinghai Lu
108925845bdSMyron Stowe spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
109925845bdSMyron Stowe map = pcibios_fwaddrmap_lookup(dev);
110925845bdSMyron Stowe if (map)
111925845bdSMyron Stowe fw_addr = map->fw_addr[idx];
112925845bdSMyron Stowe spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
113925845bdSMyron Stowe
114925845bdSMyron Stowe return fw_addr;
115925845bdSMyron Stowe }
116925845bdSMyron Stowe
pcibios_fw_addr_list_del(void)11774521602SYinghai Lu static void __init pcibios_fw_addr_list_del(void)
118925845bdSMyron Stowe {
119925845bdSMyron Stowe unsigned long flags;
120925845bdSMyron Stowe struct pcibios_fwaddrmap *entry, *next;
121925845bdSMyron Stowe
122925845bdSMyron Stowe spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
123925845bdSMyron Stowe list_for_each_entry_safe(entry, next, &pcibios_fwaddrmappings, list) {
124925845bdSMyron Stowe list_del(&entry->list);
125925845bdSMyron Stowe pci_dev_put(entry->dev);
126925845bdSMyron Stowe kfree(entry);
127925845bdSMyron Stowe }
128925845bdSMyron Stowe spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
12974521602SYinghai Lu pcibios_fw_addr_done = true;
130925845bdSMyron Stowe }
131925845bdSMyron Stowe
132036fff4cSGary Hade static int
skip_isa_ioresource_align(struct pci_dev * dev)133036fff4cSGary Hade skip_isa_ioresource_align(struct pci_dev *dev) {
134036fff4cSGary Hade
135036fff4cSGary Hade if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
13611949255SGary Hade !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
137036fff4cSGary Hade return 1;
138036fff4cSGary Hade return 0;
139036fff4cSGary Hade }
140036fff4cSGary Hade
141fb9aa6f1SThomas Gleixner /*
142fb9aa6f1SThomas Gleixner * We need to avoid collisions with `mirrored' VGA ports
143fb9aa6f1SThomas Gleixner * and other strange ISA hardware, so we always want the
144fb9aa6f1SThomas Gleixner * addresses to be allocated in the 0x000-0x0ff region
145fb9aa6f1SThomas Gleixner * modulo 0x400.
146fb9aa6f1SThomas Gleixner *
147fb9aa6f1SThomas Gleixner * Why? Because some silly external IO cards only decode
148fb9aa6f1SThomas Gleixner * the low 10 bits of the IO address. The 0x00-0xff region
149fb9aa6f1SThomas Gleixner * is reserved for motherboard devices that decode all 16
150fb9aa6f1SThomas Gleixner * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
151fb9aa6f1SThomas Gleixner * but we want to try to avoid allocating at 0x2900-0x2bff
152fb9aa6f1SThomas Gleixner * which might have be mirrored at 0x0100-0x03ff..
153fb9aa6f1SThomas Gleixner */
154b26b2d49SDominik Brodowski resource_size_t
pcibios_align_resource(void * data,const struct resource * res,resource_size_t size,resource_size_t align)1553b7a17fcSDominik Brodowski pcibios_align_resource(void *data, const struct resource *res,
156fb9aa6f1SThomas Gleixner resource_size_t size, resource_size_t align)
157fb9aa6f1SThomas Gleixner {
158036fff4cSGary Hade struct pci_dev *dev = data;
159d14125ecSBjorn Helgaas resource_size_t start = res->start;
160fb9aa6f1SThomas Gleixner
161b26b2d49SDominik Brodowski if (res->flags & IORESOURCE_IO) {
162d14125ecSBjorn Helgaas if (skip_isa_ioresource_align(dev))
163d14125ecSBjorn Helgaas return start;
164d14125ecSBjorn Helgaas if (start & 0x300)
165d14125ecSBjorn Helgaas start = (start + 0x3ff) & ~0x3ff;
166cbace46aSChristoph Schulz } else if (res->flags & IORESOURCE_MEM) {
167cbace46aSChristoph Schulz /* The low 1MB range is reserved for ISA cards */
168cbace46aSChristoph Schulz if (start < BIOS_END)
169cbace46aSChristoph Schulz start = BIOS_END;
170fb9aa6f1SThomas Gleixner }
171b26b2d49SDominik Brodowski return start;
172fb9aa6f1SThomas Gleixner }
1736c00a61eSDave Airlie EXPORT_SYMBOL(pcibios_align_resource);
174fb9aa6f1SThomas Gleixner
175fb9aa6f1SThomas Gleixner /*
176fb9aa6f1SThomas Gleixner * Handle resources of PCI devices. If the world were perfect, we could
177fb9aa6f1SThomas Gleixner * just allocate all the resource regions and do nothing more. It isn't.
178fb9aa6f1SThomas Gleixner * On the other hand, we cannot just re-allocate all devices, as it would
179fb9aa6f1SThomas Gleixner * require us to know lots of host bridge internals. So we attempt to
180fb9aa6f1SThomas Gleixner * keep as much of the original configuration as possible, but tweak it
181fb9aa6f1SThomas Gleixner * when it's found to be wrong.
182fb9aa6f1SThomas Gleixner *
183fb9aa6f1SThomas Gleixner * Known BIOS problems we have to work around:
184fb9aa6f1SThomas Gleixner * - I/O or memory regions not configured
185fb9aa6f1SThomas Gleixner * - regions configured, but not enabled in the command register
186fb9aa6f1SThomas Gleixner * - bogus I/O addresses above 64K used
187fb9aa6f1SThomas Gleixner * - expansion ROMs left enabled (this may sound harmless, but given
188fb9aa6f1SThomas Gleixner * the fact the PCI specs explicitly allow address decoders to be
189fb9aa6f1SThomas Gleixner * shared between expansion ROMs and other resource regions, it's
190fb9aa6f1SThomas Gleixner * at least dangerous)
191837c4ef1SYinghai Lu * - bad resource sizes or overlaps with other regions
192fb9aa6f1SThomas Gleixner *
193fb9aa6f1SThomas Gleixner * Our solution:
194fb9aa6f1SThomas Gleixner * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
195fb9aa6f1SThomas Gleixner * This gives us fixed barriers on where we can allocate.
196fb9aa6f1SThomas Gleixner * (2) Allocate resources for all enabled devices. If there is
197fb9aa6f1SThomas Gleixner * a collision, just mark the resource as unallocated. Also
198fb9aa6f1SThomas Gleixner * disable expansion ROMs during this step.
199fb9aa6f1SThomas Gleixner * (3) Try to allocate resources for disabled devices. If the
200fb9aa6f1SThomas Gleixner * resources were assigned correctly, everything goes well,
201fb9aa6f1SThomas Gleixner * if they weren't, they won't disturb allocation of other
202fb9aa6f1SThomas Gleixner * resources.
203fb9aa6f1SThomas Gleixner * (4) Assign new addresses to resources which were either
204fb9aa6f1SThomas Gleixner * not configured at all or misconfigured. If explicitly
205fb9aa6f1SThomas Gleixner * requested by the user, configure expansion ROM address
206fb9aa6f1SThomas Gleixner * as well.
207fb9aa6f1SThomas Gleixner */
208fb9aa6f1SThomas Gleixner
pcibios_allocate_bridge_resources(struct pci_dev * dev)209b95168e0SYinghai Lu static void pcibios_allocate_bridge_resources(struct pci_dev *dev)
210fb9aa6f1SThomas Gleixner {
211fb9aa6f1SThomas Gleixner int idx;
212a76117dfSMatthew Wilcox struct resource *r;
213fb9aa6f1SThomas Gleixner
214f7ac356dSYinghai Lu for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
215fb9aa6f1SThomas Gleixner r = &dev->resource[idx];
216fb9aa6f1SThomas Gleixner if (!r->flags)
217fb9aa6f1SThomas Gleixner continue;
218c70d6505SMika Westerberg if (r->parent) /* Already allocated */
219c70d6505SMika Westerberg continue;
220851b0936SYinghai Lu if (!r->start || pci_claim_bridge_resource(dev, idx) < 0) {
221fb9aa6f1SThomas Gleixner /*
222fb9aa6f1SThomas Gleixner * Something is wrong with the region.
223fb9aa6f1SThomas Gleixner * Invalidate the resource to prevent
224fb9aa6f1SThomas Gleixner * child resource allocations in this
225fb9aa6f1SThomas Gleixner * range.
226fb9aa6f1SThomas Gleixner */
227837c4ef1SYinghai Lu r->start = r->end = 0;
228fb9aa6f1SThomas Gleixner r->flags = 0;
229fb9aa6f1SThomas Gleixner }
230fb9aa6f1SThomas Gleixner }
231fb9aa6f1SThomas Gleixner }
232f7ac356dSYinghai Lu
pcibios_allocate_bus_resources(struct pci_bus * bus)233b95168e0SYinghai Lu static void pcibios_allocate_bus_resources(struct pci_bus *bus)
234f7ac356dSYinghai Lu {
23583edc87cSYinghai Lu struct pci_bus *child;
236f7ac356dSYinghai Lu
237f7ac356dSYinghai Lu /* Depth-First Search on bus tree */
238f7ac356dSYinghai Lu if (bus->self)
239f7ac356dSYinghai Lu pcibios_allocate_bridge_resources(bus->self);
24083edc87cSYinghai Lu list_for_each_entry(child, &bus->children, node)
24183edc87cSYinghai Lu pcibios_allocate_bus_resources(child);
242fb9aa6f1SThomas Gleixner }
243fb9aa6f1SThomas Gleixner
244575939cfSYinghai Lu struct pci_check_idx_range {
245575939cfSYinghai Lu int start;
246575939cfSYinghai Lu int end;
247575939cfSYinghai Lu };
248575939cfSYinghai Lu
pcibios_allocate_dev_resources(struct pci_dev * dev,int pass)249b95168e0SYinghai Lu static void pcibios_allocate_dev_resources(struct pci_dev *dev, int pass)
250fb9aa6f1SThomas Gleixner {
251575939cfSYinghai Lu int idx, disabled, i;
252fb9aa6f1SThomas Gleixner u16 command;
253a76117dfSMatthew Wilcox struct resource *r;
254fb9aa6f1SThomas Gleixner
255575939cfSYinghai Lu struct pci_check_idx_range idx_range[] = {
256575939cfSYinghai Lu { PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
257575939cfSYinghai Lu #ifdef CONFIG_PCI_IOV
258575939cfSYinghai Lu { PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
259575939cfSYinghai Lu #endif
260575939cfSYinghai Lu };
261575939cfSYinghai Lu
262fb9aa6f1SThomas Gleixner pci_read_config_word(dev, PCI_COMMAND, &command);
263575939cfSYinghai Lu for (i = 0; i < ARRAY_SIZE(idx_range); i++)
264575939cfSYinghai Lu for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
265fb9aa6f1SThomas Gleixner r = &dev->resource[idx];
266fb9aa6f1SThomas Gleixner if (r->parent) /* Already allocated */
267fb9aa6f1SThomas Gleixner continue;
268fb9aa6f1SThomas Gleixner if (!r->start) /* Address not assigned at all */
269fb9aa6f1SThomas Gleixner continue;
270fb9aa6f1SThomas Gleixner if (r->flags & IORESOURCE_IO)
271fb9aa6f1SThomas Gleixner disabled = !(command & PCI_COMMAND_IO);
272fb9aa6f1SThomas Gleixner else
273fb9aa6f1SThomas Gleixner disabled = !(command & PCI_COMMAND_MEMORY);
274fb9aa6f1SThomas Gleixner if (pass == disabled) {
275c7dabef8SBjorn Helgaas dev_dbg(&dev->dev,
276865df576SBjorn Helgaas "BAR %d: reserving %pr (d=%d, p=%d)\n",
277c7dabef8SBjorn Helgaas idx, r, disabled, pass);
278a76117dfSMatthew Wilcox if (pci_claim_resource(dev, idx) < 0) {
2794e4ba944SBjorn Helgaas if (r->flags & IORESOURCE_PCI_FIXED) {
2804e4ba944SBjorn Helgaas dev_info(&dev->dev, "BAR %d %pR is immovable\n",
2814e4ba944SBjorn Helgaas idx, r);
2824e4ba944SBjorn Helgaas } else {
283fb9aa6f1SThomas Gleixner /* We'll assign a new address later */
2846535943fSMyron Stowe pcibios_save_fw_addr(dev,
2856535943fSMyron Stowe idx, r->start);
286fb9aa6f1SThomas Gleixner r->end -= r->start;
287fb9aa6f1SThomas Gleixner r->start = 0;
288fb9aa6f1SThomas Gleixner }
289fb9aa6f1SThomas Gleixner }
290fb9aa6f1SThomas Gleixner }
2914e4ba944SBjorn Helgaas }
292fb9aa6f1SThomas Gleixner if (!pass) {
293fb9aa6f1SThomas Gleixner r = &dev->resource[PCI_ROM_RESOURCE];
294fb9aa6f1SThomas Gleixner if (r->flags & IORESOURCE_ROM_ENABLE) {
295fb9aa6f1SThomas Gleixner /* Turn the ROM off, leave the resource region,
296fb9aa6f1SThomas Gleixner * but keep it unregistered. */
297fb9aa6f1SThomas Gleixner u32 reg;
298c7dabef8SBjorn Helgaas dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
299fb9aa6f1SThomas Gleixner r->flags &= ~IORESOURCE_ROM_ENABLE;
300c7f4bbc9SYinghai Lu pci_read_config_dword(dev, dev->rom_base_reg, ®);
301fb9aa6f1SThomas Gleixner pci_write_config_dword(dev, dev->rom_base_reg,
302fb9aa6f1SThomas Gleixner reg & ~PCI_ROM_ADDRESS_ENABLE);
303fb9aa6f1SThomas Gleixner }
304fb9aa6f1SThomas Gleixner }
305fb9aa6f1SThomas Gleixner }
306c7f4bbc9SYinghai Lu
pcibios_allocate_resources(struct pci_bus * bus,int pass)307b95168e0SYinghai Lu static void pcibios_allocate_resources(struct pci_bus *bus, int pass)
308c7f4bbc9SYinghai Lu {
30983edc87cSYinghai Lu struct pci_dev *dev;
31083edc87cSYinghai Lu struct pci_bus *child;
311c7f4bbc9SYinghai Lu
31283edc87cSYinghai Lu list_for_each_entry(dev, &bus->devices, bus_list) {
313c7f4bbc9SYinghai Lu pcibios_allocate_dev_resources(dev, pass);
31483edc87cSYinghai Lu
31583edc87cSYinghai Lu child = dev->subordinate;
31683edc87cSYinghai Lu if (child)
31783edc87cSYinghai Lu pcibios_allocate_resources(child, pass);
31883edc87cSYinghai Lu }
319fb9aa6f1SThomas Gleixner }
320fb9aa6f1SThomas Gleixner
pcibios_allocate_dev_rom_resource(struct pci_dev * dev)321b95168e0SYinghai Lu static void pcibios_allocate_dev_rom_resource(struct pci_dev *dev)
322fb9aa6f1SThomas Gleixner {
323a76117dfSMatthew Wilcox struct resource *r;
324fb9aa6f1SThomas Gleixner
325fb9aa6f1SThomas Gleixner /*
326fb9aa6f1SThomas Gleixner * Try to use BIOS settings for ROMs, otherwise let
327fb9aa6f1SThomas Gleixner * pci_assign_unassigned_resources() allocate the new
328fb9aa6f1SThomas Gleixner * addresses.
329fb9aa6f1SThomas Gleixner */
330fb9aa6f1SThomas Gleixner r = &dev->resource[PCI_ROM_RESOURCE];
331fb9aa6f1SThomas Gleixner if (!r->flags || !r->start)
332dc2f56faSYinghai Lu return;
333c70d6505SMika Westerberg if (r->parent) /* Already allocated */
334c70d6505SMika Westerberg return;
335dc2f56faSYinghai Lu
336a76117dfSMatthew Wilcox if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
337fb9aa6f1SThomas Gleixner r->end -= r->start;
338fb9aa6f1SThomas Gleixner r->start = 0;
339fb9aa6f1SThomas Gleixner }
340fb9aa6f1SThomas Gleixner }
pcibios_allocate_rom_resources(struct pci_bus * bus)341b95168e0SYinghai Lu static void pcibios_allocate_rom_resources(struct pci_bus *bus)
342dc2f56faSYinghai Lu {
343dc2f56faSYinghai Lu struct pci_dev *dev;
344dc2f56faSYinghai Lu struct pci_bus *child;
345dc2f56faSYinghai Lu
346dc2f56faSYinghai Lu list_for_each_entry(dev, &bus->devices, bus_list) {
347dc2f56faSYinghai Lu pcibios_allocate_dev_rom_resource(dev);
348dc2f56faSYinghai Lu
349dc2f56faSYinghai Lu child = dev->subordinate;
350dc2f56faSYinghai Lu if (child)
351dc2f56faSYinghai Lu pcibios_allocate_rom_resources(child);
352fb9aa6f1SThomas Gleixner }
353dc2f56faSYinghai Lu }
354dc2f56faSYinghai Lu
pcibios_assign_resources(void)355dc2f56faSYinghai Lu static int __init pcibios_assign_resources(void)
356dc2f56faSYinghai Lu {
357dc2f56faSYinghai Lu struct pci_bus *bus;
358dc2f56faSYinghai Lu
359dc2f56faSYinghai Lu if (!(pci_probe & PCI_ASSIGN_ROMS))
360dc2f56faSYinghai Lu list_for_each_entry(bus, &pci_root_buses, node)
361dc2f56faSYinghai Lu pcibios_allocate_rom_resources(bus);
362fb9aa6f1SThomas Gleixner
363fb9aa6f1SThomas Gleixner pci_assign_unassigned_resources();
3646535943fSMyron Stowe pcibios_fw_addr_list_del();
365fb9aa6f1SThomas Gleixner
366fb9aa6f1SThomas Gleixner return 0;
367fb9aa6f1SThomas Gleixner }
368fb9aa6f1SThomas Gleixner
369*638920a6SAlex Shi /*
370*638920a6SAlex Shi * This is an fs_initcall (one below subsys_initcall) in order to reserve
371*638920a6SAlex Shi * resources properly.
372adc429d6SBjorn Helgaas */
373adc429d6SBjorn Helgaas fs_initcall(pcibios_assign_resources);
374adc429d6SBjorn Helgaas
pcibios_resource_survey_bus(struct pci_bus * bus)375b3e65e1fSYinghai Lu void pcibios_resource_survey_bus(struct pci_bus *bus)
376b3e65e1fSYinghai Lu {
377b3e65e1fSYinghai Lu dev_printk(KERN_DEBUG, &bus->dev, "Allocating resources\n");
378b3e65e1fSYinghai Lu
379b3e65e1fSYinghai Lu pcibios_allocate_bus_resources(bus);
380b3e65e1fSYinghai Lu
381b3e65e1fSYinghai Lu pcibios_allocate_resources(bus, 0);
382b3e65e1fSYinghai Lu pcibios_allocate_resources(bus, 1);
383b3e65e1fSYinghai Lu
384b3e65e1fSYinghai Lu if (!(pci_probe & PCI_ASSIGN_ROMS))
385b3e65e1fSYinghai Lu pcibios_allocate_rom_resources(bus);
386b3e65e1fSYinghai Lu }
387b3e65e1fSYinghai Lu
pcibios_resource_survey(void)388fb9aa6f1SThomas Gleixner void __init pcibios_resource_survey(void)
389fb9aa6f1SThomas Gleixner {
39083edc87cSYinghai Lu struct pci_bus *bus;
39183edc87cSYinghai Lu
392fb9aa6f1SThomas Gleixner DBG("PCI: Allocating resources\n");
39383edc87cSYinghai Lu
39483edc87cSYinghai Lu list_for_each_entry(bus, &pci_root_buses, node)
39583edc87cSYinghai Lu pcibios_allocate_bus_resources(bus);
39683edc87cSYinghai Lu
39783edc87cSYinghai Lu list_for_each_entry(bus, &pci_root_buses, node)
39883edc87cSYinghai Lu pcibios_allocate_resources(bus, 0);
39983edc87cSYinghai Lu list_for_each_entry(bus, &pci_root_buses, node)
40083edc87cSYinghai Lu pcibios_allocate_resources(bus, 1);
401a5444d15SIngo Molnar
4021506c8dcSIngo Molnar e820__reserve_resources_late();
403857fdc53SYinghai Lu /*
404857fdc53SYinghai Lu * Insert the IO APIC resources after PCI initialization has
4050d2eb44fSLucas De Marchi * occurred to handle IO APICS that are mapped in on a BAR in
406857fdc53SYinghai Lu * PCI space, but before trying to assign unassigned pci res.
407857fdc53SYinghai Lu */
408857fdc53SYinghai Lu ioapic_insert_resources();
409fb9aa6f1SThomas Gleixner }
410