1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This module enables machines with Intel VT-x extensions to run virtual 6 * machines without emulation or binary translation. 7 * 8 * Copyright (C) 2006 Qumranet, Inc. 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 */ 15 16 #include <linux/frame.h> 17 #include <linux/highmem.h> 18 #include <linux/hrtimer.h> 19 #include <linux/kernel.h> 20 #include <linux/kvm_host.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/mm.h> 25 #include <linux/sched.h> 26 #include <linux/sched/smt.h> 27 #include <linux/slab.h> 28 #include <linux/tboot.h> 29 #include <linux/trace_events.h> 30 31 #include <asm/apic.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/cpu_device_id.h> 35 #include <asm/debugreg.h> 36 #include <asm/desc.h> 37 #include <asm/fpu/internal.h> 38 #include <asm/io.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/kexec.h> 41 #include <asm/perf_event.h> 42 #include <asm/mce.h> 43 #include <asm/mmu_context.h> 44 #include <asm/mshyperv.h> 45 #include <asm/mwait.h> 46 #include <asm/spec-ctrl.h> 47 #include <asm/virtext.h> 48 #include <asm/vmx.h> 49 50 #include "capabilities.h" 51 #include "cpuid.h" 52 #include "evmcs.h" 53 #include "irq.h" 54 #include "kvm_cache_regs.h" 55 #include "lapic.h" 56 #include "mmu.h" 57 #include "nested.h" 58 #include "ops.h" 59 #include "pmu.h" 60 #include "trace.h" 61 #include "vmcs.h" 62 #include "vmcs12.h" 63 #include "vmx.h" 64 #include "x86.h" 65 66 MODULE_AUTHOR("Qumranet"); 67 MODULE_LICENSE("GPL"); 68 69 #ifdef MODULE 70 static const struct x86_cpu_id vmx_cpu_id[] = { 71 X86_MATCH_FEATURE(X86_FEATURE_VMX, NULL), 72 {} 73 }; 74 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 75 #endif 76 77 bool __read_mostly enable_vpid = 1; 78 module_param_named(vpid, enable_vpid, bool, 0444); 79 80 static bool __read_mostly enable_vnmi = 1; 81 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 82 83 bool __read_mostly flexpriority_enabled = 1; 84 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 85 86 bool __read_mostly enable_ept = 1; 87 module_param_named(ept, enable_ept, bool, S_IRUGO); 88 89 bool __read_mostly enable_unrestricted_guest = 1; 90 module_param_named(unrestricted_guest, 91 enable_unrestricted_guest, bool, S_IRUGO); 92 93 bool __read_mostly enable_ept_ad_bits = 1; 94 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 95 96 static bool __read_mostly emulate_invalid_guest_state = true; 97 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 98 99 static bool __read_mostly fasteoi = 1; 100 module_param(fasteoi, bool, S_IRUGO); 101 102 bool __read_mostly enable_apicv = 1; 103 module_param(enable_apicv, bool, S_IRUGO); 104 105 /* 106 * If nested=1, nested virtualization is supported, i.e., guests may use 107 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 108 * use VMX instructions. 109 */ 110 static bool __read_mostly nested = 1; 111 module_param(nested, bool, S_IRUGO); 112 113 bool __read_mostly enable_pml = 1; 114 module_param_named(pml, enable_pml, bool, S_IRUGO); 115 116 static bool __read_mostly dump_invalid_vmcs = 0; 117 module_param(dump_invalid_vmcs, bool, 0644); 118 119 #define MSR_BITMAP_MODE_X2APIC 1 120 #define MSR_BITMAP_MODE_X2APIC_APICV 2 121 122 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 123 124 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 125 static int __read_mostly cpu_preemption_timer_multi; 126 static bool __read_mostly enable_preemption_timer = 1; 127 #ifdef CONFIG_X86_64 128 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 129 #endif 130 131 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 132 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 133 #define KVM_VM_CR0_ALWAYS_ON \ 134 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 135 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 136 #define KVM_CR4_GUEST_OWNED_BITS \ 137 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 138 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) 139 140 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 141 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 142 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 143 144 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 145 146 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 147 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 148 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 149 RTIT_STATUS_BYTECNT)) 150 151 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \ 152 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f) 153 154 /* 155 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 156 * ple_gap: upper bound on the amount of time between two successive 157 * executions of PAUSE in a loop. Also indicate if ple enabled. 158 * According to test, this time is usually smaller than 128 cycles. 159 * ple_window: upper bound on the amount of time a guest is allowed to execute 160 * in a PAUSE loop. Tests indicate that most spinlocks are held for 161 * less than 2^12 cycles 162 * Time is measured based on a counter that runs at the same rate as the TSC, 163 * refer SDM volume 3b section 21.6.13 & 22.1.3. 164 */ 165 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 166 module_param(ple_gap, uint, 0444); 167 168 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 169 module_param(ple_window, uint, 0444); 170 171 /* Default doubles per-vcpu window every exit. */ 172 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 173 module_param(ple_window_grow, uint, 0444); 174 175 /* Default resets per-vcpu window every exit to ple_window. */ 176 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 177 module_param(ple_window_shrink, uint, 0444); 178 179 /* Default is to compute the maximum so we can never overflow. */ 180 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 181 module_param(ple_window_max, uint, 0444); 182 183 /* Default is SYSTEM mode, 1 for host-guest mode */ 184 int __read_mostly pt_mode = PT_MODE_SYSTEM; 185 module_param(pt_mode, int, S_IRUGO); 186 187 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 188 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 189 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 190 191 /* Storage for pre module init parameter parsing */ 192 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 193 194 static const struct { 195 const char *option; 196 bool for_parse; 197 } vmentry_l1d_param[] = { 198 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 199 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 200 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 201 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 202 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 203 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 204 }; 205 206 #define L1D_CACHE_ORDER 4 207 static void *vmx_l1d_flush_pages; 208 209 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 210 { 211 struct page *page; 212 unsigned int i; 213 214 if (!boot_cpu_has_bug(X86_BUG_L1TF)) { 215 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 216 return 0; 217 } 218 219 if (!enable_ept) { 220 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 221 return 0; 222 } 223 224 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 225 u64 msr; 226 227 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 228 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 229 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 230 return 0; 231 } 232 } 233 234 /* If set to auto use the default l1tf mitigation method */ 235 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 236 switch (l1tf_mitigation) { 237 case L1TF_MITIGATION_OFF: 238 l1tf = VMENTER_L1D_FLUSH_NEVER; 239 break; 240 case L1TF_MITIGATION_FLUSH_NOWARN: 241 case L1TF_MITIGATION_FLUSH: 242 case L1TF_MITIGATION_FLUSH_NOSMT: 243 l1tf = VMENTER_L1D_FLUSH_COND; 244 break; 245 case L1TF_MITIGATION_FULL: 246 case L1TF_MITIGATION_FULL_FORCE: 247 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 248 break; 249 } 250 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 251 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 252 } 253 254 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 255 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 256 /* 257 * This allocation for vmx_l1d_flush_pages is not tied to a VM 258 * lifetime and so should not be charged to a memcg. 259 */ 260 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 261 if (!page) 262 return -ENOMEM; 263 vmx_l1d_flush_pages = page_address(page); 264 265 /* 266 * Initialize each page with a different pattern in 267 * order to protect against KSM in the nested 268 * virtualization case. 269 */ 270 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 271 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 272 PAGE_SIZE); 273 } 274 } 275 276 l1tf_vmx_mitigation = l1tf; 277 278 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 279 static_branch_enable(&vmx_l1d_should_flush); 280 else 281 static_branch_disable(&vmx_l1d_should_flush); 282 283 if (l1tf == VMENTER_L1D_FLUSH_COND) 284 static_branch_enable(&vmx_l1d_flush_cond); 285 else 286 static_branch_disable(&vmx_l1d_flush_cond); 287 return 0; 288 } 289 290 static int vmentry_l1d_flush_parse(const char *s) 291 { 292 unsigned int i; 293 294 if (s) { 295 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 296 if (vmentry_l1d_param[i].for_parse && 297 sysfs_streq(s, vmentry_l1d_param[i].option)) 298 return i; 299 } 300 } 301 return -EINVAL; 302 } 303 304 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 305 { 306 int l1tf, ret; 307 308 l1tf = vmentry_l1d_flush_parse(s); 309 if (l1tf < 0) 310 return l1tf; 311 312 if (!boot_cpu_has(X86_BUG_L1TF)) 313 return 0; 314 315 /* 316 * Has vmx_init() run already? If not then this is the pre init 317 * parameter parsing. In that case just store the value and let 318 * vmx_init() do the proper setup after enable_ept has been 319 * established. 320 */ 321 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 322 vmentry_l1d_flush_param = l1tf; 323 return 0; 324 } 325 326 mutex_lock(&vmx_l1d_flush_mutex); 327 ret = vmx_setup_l1d_flush(l1tf); 328 mutex_unlock(&vmx_l1d_flush_mutex); 329 return ret; 330 } 331 332 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 333 { 334 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 335 return sprintf(s, "???\n"); 336 337 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 338 } 339 340 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 341 .set = vmentry_l1d_flush_set, 342 .get = vmentry_l1d_flush_get, 343 }; 344 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 345 346 static bool guest_state_valid(struct kvm_vcpu *vcpu); 347 static u32 vmx_segment_access_rights(struct kvm_segment *var); 348 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 349 u32 msr, int type); 350 351 void vmx_vmexit(void); 352 353 #define vmx_insn_failed(fmt...) \ 354 do { \ 355 WARN_ONCE(1, fmt); \ 356 pr_warn_ratelimited(fmt); \ 357 } while (0) 358 359 asmlinkage void vmread_error(unsigned long field, bool fault) 360 { 361 if (fault) 362 kvm_spurious_fault(); 363 else 364 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); 365 } 366 367 noinline void vmwrite_error(unsigned long field, unsigned long value) 368 { 369 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", 370 field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); 371 } 372 373 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) 374 { 375 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); 376 } 377 378 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) 379 { 380 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); 381 } 382 383 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) 384 { 385 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", 386 ext, vpid, gva); 387 } 388 389 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) 390 { 391 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", 392 ext, eptp, gpa); 393 } 394 395 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 396 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 397 /* 398 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 399 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 400 */ 401 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 402 403 /* 404 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we 405 * can find which vCPU should be waken up. 406 */ 407 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); 408 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); 409 410 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 411 static DEFINE_SPINLOCK(vmx_vpid_lock); 412 413 struct vmcs_config vmcs_config; 414 struct vmx_capability vmx_capability; 415 416 #define VMX_SEGMENT_FIELD(seg) \ 417 [VCPU_SREG_##seg] = { \ 418 .selector = GUEST_##seg##_SELECTOR, \ 419 .base = GUEST_##seg##_BASE, \ 420 .limit = GUEST_##seg##_LIMIT, \ 421 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 422 } 423 424 static const struct kvm_vmx_segment_field { 425 unsigned selector; 426 unsigned base; 427 unsigned limit; 428 unsigned ar_bytes; 429 } kvm_vmx_segment_fields[] = { 430 VMX_SEGMENT_FIELD(CS), 431 VMX_SEGMENT_FIELD(DS), 432 VMX_SEGMENT_FIELD(ES), 433 VMX_SEGMENT_FIELD(FS), 434 VMX_SEGMENT_FIELD(GS), 435 VMX_SEGMENT_FIELD(SS), 436 VMX_SEGMENT_FIELD(TR), 437 VMX_SEGMENT_FIELD(LDTR), 438 }; 439 440 static unsigned long host_idt_base; 441 442 /* 443 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 444 * will emulate SYSCALL in legacy mode if the vendor string in guest 445 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 446 * support this emulation, IA32_STAR must always be included in 447 * vmx_msr_index[], even in i386 builds. 448 */ 449 const u32 vmx_msr_index[] = { 450 #ifdef CONFIG_X86_64 451 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 452 #endif 453 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 454 MSR_IA32_TSX_CTRL, 455 }; 456 457 #if IS_ENABLED(CONFIG_HYPERV) 458 static bool __read_mostly enlightened_vmcs = true; 459 module_param(enlightened_vmcs, bool, 0444); 460 461 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 462 static void check_ept_pointer_match(struct kvm *kvm) 463 { 464 struct kvm_vcpu *vcpu; 465 u64 tmp_eptp = INVALID_PAGE; 466 int i; 467 468 kvm_for_each_vcpu(i, vcpu, kvm) { 469 if (!VALID_PAGE(tmp_eptp)) { 470 tmp_eptp = to_vmx(vcpu)->ept_pointer; 471 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 472 to_kvm_vmx(kvm)->ept_pointers_match 473 = EPT_POINTERS_MISMATCH; 474 return; 475 } 476 } 477 478 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 479 } 480 481 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 482 void *data) 483 { 484 struct kvm_tlb_range *range = data; 485 486 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 487 range->pages); 488 } 489 490 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 491 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 492 { 493 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 494 495 /* 496 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 497 * of the base of EPT PML4 table, strip off EPT configuration 498 * information. 499 */ 500 if (range) 501 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 502 kvm_fill_hv_flush_list_func, (void *)range); 503 else 504 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 505 } 506 507 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 508 struct kvm_tlb_range *range) 509 { 510 struct kvm_vcpu *vcpu; 511 int ret = 0, i; 512 513 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 514 515 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 516 check_ept_pointer_match(kvm); 517 518 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 519 kvm_for_each_vcpu(i, vcpu, kvm) { 520 /* If ept_pointer is invalid pointer, bypass flush request. */ 521 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 522 ret |= __hv_remote_flush_tlb_with_range( 523 kvm, vcpu, range); 524 } 525 } else { 526 ret = __hv_remote_flush_tlb_with_range(kvm, 527 kvm_get_vcpu(kvm, 0), range); 528 } 529 530 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 531 return ret; 532 } 533 static int hv_remote_flush_tlb(struct kvm *kvm) 534 { 535 return hv_remote_flush_tlb_with_range(kvm, NULL); 536 } 537 538 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) 539 { 540 struct hv_enlightened_vmcs *evmcs; 541 struct hv_partition_assist_pg **p_hv_pa_pg = 542 &vcpu->kvm->arch.hyperv.hv_pa_pg; 543 /* 544 * Synthetic VM-Exit is not enabled in current code and so All 545 * evmcs in singe VM shares same assist page. 546 */ 547 if (!*p_hv_pa_pg) 548 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); 549 550 if (!*p_hv_pa_pg) 551 return -ENOMEM; 552 553 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; 554 555 evmcs->partition_assist_page = 556 __pa(*p_hv_pa_pg); 557 evmcs->hv_vm_id = (unsigned long)vcpu->kvm; 558 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; 559 560 return 0; 561 } 562 563 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 564 565 /* 566 * Comment's format: document - errata name - stepping - processor name. 567 * Refer from 568 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 569 */ 570 static u32 vmx_preemption_cpu_tfms[] = { 571 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 572 0x000206E6, 573 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 574 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 575 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 576 0x00020652, 577 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 578 0x00020655, 579 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 580 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 581 /* 582 * 320767.pdf - AAP86 - B1 - 583 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 584 */ 585 0x000106E5, 586 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 587 0x000106A0, 588 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 589 0x000106A1, 590 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 591 0x000106A4, 592 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 593 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 594 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 595 0x000106A5, 596 /* Xeon E3-1220 V2 */ 597 0x000306A8, 598 }; 599 600 static inline bool cpu_has_broken_vmx_preemption_timer(void) 601 { 602 u32 eax = cpuid_eax(0x00000001), i; 603 604 /* Clear the reserved bits */ 605 eax &= ~(0x3U << 14 | 0xfU << 28); 606 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 607 if (eax == vmx_preemption_cpu_tfms[i]) 608 return true; 609 610 return false; 611 } 612 613 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 614 { 615 return flexpriority_enabled && lapic_in_kernel(vcpu); 616 } 617 618 static inline bool report_flexpriority(void) 619 { 620 return flexpriority_enabled; 621 } 622 623 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) 624 { 625 int i; 626 627 for (i = 0; i < vmx->nmsrs; ++i) 628 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) 629 return i; 630 return -1; 631 } 632 633 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) 634 { 635 int i; 636 637 i = __find_msr_index(vmx, msr); 638 if (i >= 0) 639 return &vmx->guest_msrs[i]; 640 return NULL; 641 } 642 643 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data) 644 { 645 int ret = 0; 646 647 u64 old_msr_data = msr->data; 648 msr->data = data; 649 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 650 preempt_disable(); 651 ret = kvm_set_shared_msr(msr->index, msr->data, 652 msr->mask); 653 preempt_enable(); 654 if (ret) 655 msr->data = old_msr_data; 656 } 657 return ret; 658 } 659 660 #ifdef CONFIG_KEXEC_CORE 661 static void crash_vmclear_local_loaded_vmcss(void) 662 { 663 int cpu = raw_smp_processor_id(); 664 struct loaded_vmcs *v; 665 666 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 667 loaded_vmcss_on_cpu_link) 668 vmcs_clear(v->vmcs); 669 } 670 #endif /* CONFIG_KEXEC_CORE */ 671 672 static void __loaded_vmcs_clear(void *arg) 673 { 674 struct loaded_vmcs *loaded_vmcs = arg; 675 int cpu = raw_smp_processor_id(); 676 677 if (loaded_vmcs->cpu != cpu) 678 return; /* vcpu migration can race with cpu offline */ 679 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 680 per_cpu(current_vmcs, cpu) = NULL; 681 682 vmcs_clear(loaded_vmcs->vmcs); 683 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 684 vmcs_clear(loaded_vmcs->shadow_vmcs); 685 686 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 687 688 /* 689 * Ensure all writes to loaded_vmcs, including deleting it from its 690 * current percpu list, complete before setting loaded_vmcs->vcpu to 691 * -1, otherwise a different cpu can see vcpu == -1 first and add 692 * loaded_vmcs to its percpu list before it's deleted from this cpu's 693 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs(). 694 */ 695 smp_wmb(); 696 697 loaded_vmcs->cpu = -1; 698 loaded_vmcs->launched = 0; 699 } 700 701 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 702 { 703 int cpu = loaded_vmcs->cpu; 704 705 if (cpu != -1) 706 smp_call_function_single(cpu, 707 __loaded_vmcs_clear, loaded_vmcs, 1); 708 } 709 710 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 711 unsigned field) 712 { 713 bool ret; 714 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 715 716 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) { 717 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS); 718 vmx->segment_cache.bitmask = 0; 719 } 720 ret = vmx->segment_cache.bitmask & mask; 721 vmx->segment_cache.bitmask |= mask; 722 return ret; 723 } 724 725 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 726 { 727 u16 *p = &vmx->segment_cache.seg[seg].selector; 728 729 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 730 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 731 return *p; 732 } 733 734 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 735 { 736 ulong *p = &vmx->segment_cache.seg[seg].base; 737 738 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 739 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 740 return *p; 741 } 742 743 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 744 { 745 u32 *p = &vmx->segment_cache.seg[seg].limit; 746 747 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 748 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 749 return *p; 750 } 751 752 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 753 { 754 u32 *p = &vmx->segment_cache.seg[seg].ar; 755 756 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 757 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 758 return *p; 759 } 760 761 void update_exception_bitmap(struct kvm_vcpu *vcpu) 762 { 763 u32 eb; 764 765 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 766 (1u << DB_VECTOR) | (1u << AC_VECTOR); 767 /* 768 * Guest access to VMware backdoor ports could legitimately 769 * trigger #GP because of TSS I/O permission bitmap. 770 * We intercept those #GP and allow access to them anyway 771 * as VMware does. 772 */ 773 if (enable_vmware_backdoor) 774 eb |= (1u << GP_VECTOR); 775 if ((vcpu->guest_debug & 776 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 777 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 778 eb |= 1u << BP_VECTOR; 779 if (to_vmx(vcpu)->rmode.vm86_active) 780 eb = ~0; 781 if (enable_ept) 782 eb &= ~(1u << PF_VECTOR); 783 784 /* When we are running a nested L2 guest and L1 specified for it a 785 * certain exception bitmap, we must trap the same exceptions and pass 786 * them to L1. When running L2, we will only handle the exceptions 787 * specified above if L1 did not want them. 788 */ 789 if (is_guest_mode(vcpu)) 790 eb |= get_vmcs12(vcpu)->exception_bitmap; 791 792 vmcs_write32(EXCEPTION_BITMAP, eb); 793 } 794 795 /* 796 * Check if MSR is intercepted for currently loaded MSR bitmap. 797 */ 798 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 799 { 800 unsigned long *msr_bitmap; 801 int f = sizeof(unsigned long); 802 803 if (!cpu_has_vmx_msr_bitmap()) 804 return true; 805 806 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 807 808 if (msr <= 0x1fff) { 809 return !!test_bit(msr, msr_bitmap + 0x800 / f); 810 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 811 msr &= 0x1fff; 812 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 813 } 814 815 return true; 816 } 817 818 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 819 unsigned long entry, unsigned long exit) 820 { 821 vm_entry_controls_clearbit(vmx, entry); 822 vm_exit_controls_clearbit(vmx, exit); 823 } 824 825 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr) 826 { 827 unsigned int i; 828 829 for (i = 0; i < m->nr; ++i) { 830 if (m->val[i].index == msr) 831 return i; 832 } 833 return -ENOENT; 834 } 835 836 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 837 { 838 int i; 839 struct msr_autoload *m = &vmx->msr_autoload; 840 841 switch (msr) { 842 case MSR_EFER: 843 if (cpu_has_load_ia32_efer()) { 844 clear_atomic_switch_msr_special(vmx, 845 VM_ENTRY_LOAD_IA32_EFER, 846 VM_EXIT_LOAD_IA32_EFER); 847 return; 848 } 849 break; 850 case MSR_CORE_PERF_GLOBAL_CTRL: 851 if (cpu_has_load_perf_global_ctrl()) { 852 clear_atomic_switch_msr_special(vmx, 853 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 854 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 855 return; 856 } 857 break; 858 } 859 i = vmx_find_msr_index(&m->guest, msr); 860 if (i < 0) 861 goto skip_guest; 862 --m->guest.nr; 863 m->guest.val[i] = m->guest.val[m->guest.nr]; 864 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 865 866 skip_guest: 867 i = vmx_find_msr_index(&m->host, msr); 868 if (i < 0) 869 return; 870 871 --m->host.nr; 872 m->host.val[i] = m->host.val[m->host.nr]; 873 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 874 } 875 876 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 877 unsigned long entry, unsigned long exit, 878 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 879 u64 guest_val, u64 host_val) 880 { 881 vmcs_write64(guest_val_vmcs, guest_val); 882 if (host_val_vmcs != HOST_IA32_EFER) 883 vmcs_write64(host_val_vmcs, host_val); 884 vm_entry_controls_setbit(vmx, entry); 885 vm_exit_controls_setbit(vmx, exit); 886 } 887 888 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 889 u64 guest_val, u64 host_val, bool entry_only) 890 { 891 int i, j = 0; 892 struct msr_autoload *m = &vmx->msr_autoload; 893 894 switch (msr) { 895 case MSR_EFER: 896 if (cpu_has_load_ia32_efer()) { 897 add_atomic_switch_msr_special(vmx, 898 VM_ENTRY_LOAD_IA32_EFER, 899 VM_EXIT_LOAD_IA32_EFER, 900 GUEST_IA32_EFER, 901 HOST_IA32_EFER, 902 guest_val, host_val); 903 return; 904 } 905 break; 906 case MSR_CORE_PERF_GLOBAL_CTRL: 907 if (cpu_has_load_perf_global_ctrl()) { 908 add_atomic_switch_msr_special(vmx, 909 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 910 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 911 GUEST_IA32_PERF_GLOBAL_CTRL, 912 HOST_IA32_PERF_GLOBAL_CTRL, 913 guest_val, host_val); 914 return; 915 } 916 break; 917 case MSR_IA32_PEBS_ENABLE: 918 /* PEBS needs a quiescent period after being disabled (to write 919 * a record). Disabling PEBS through VMX MSR swapping doesn't 920 * provide that period, so a CPU could write host's record into 921 * guest's memory. 922 */ 923 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 924 } 925 926 i = vmx_find_msr_index(&m->guest, msr); 927 if (!entry_only) 928 j = vmx_find_msr_index(&m->host, msr); 929 930 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) || 931 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) { 932 printk_once(KERN_WARNING "Not enough msr switch entries. " 933 "Can't add msr %x\n", msr); 934 return; 935 } 936 if (i < 0) { 937 i = m->guest.nr++; 938 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 939 } 940 m->guest.val[i].index = msr; 941 m->guest.val[i].value = guest_val; 942 943 if (entry_only) 944 return; 945 946 if (j < 0) { 947 j = m->host.nr++; 948 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 949 } 950 m->host.val[j].index = msr; 951 m->host.val[j].value = host_val; 952 } 953 954 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) 955 { 956 u64 guest_efer = vmx->vcpu.arch.efer; 957 u64 ignore_bits = 0; 958 959 /* Shadow paging assumes NX to be available. */ 960 if (!enable_ept) 961 guest_efer |= EFER_NX; 962 963 /* 964 * LMA and LME handled by hardware; SCE meaningless outside long mode. 965 */ 966 ignore_bits |= EFER_SCE; 967 #ifdef CONFIG_X86_64 968 ignore_bits |= EFER_LMA | EFER_LME; 969 /* SCE is meaningful only in long mode on Intel */ 970 if (guest_efer & EFER_LMA) 971 ignore_bits &= ~(u64)EFER_SCE; 972 #endif 973 974 /* 975 * On EPT, we can't emulate NX, so we must switch EFER atomically. 976 * On CPUs that support "load IA32_EFER", always switch EFER 977 * atomically, since it's faster than switching it manually. 978 */ 979 if (cpu_has_load_ia32_efer() || 980 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 981 if (!(guest_efer & EFER_LMA)) 982 guest_efer &= ~EFER_LME; 983 if (guest_efer != host_efer) 984 add_atomic_switch_msr(vmx, MSR_EFER, 985 guest_efer, host_efer, false); 986 else 987 clear_atomic_switch_msr(vmx, MSR_EFER); 988 return false; 989 } else { 990 clear_atomic_switch_msr(vmx, MSR_EFER); 991 992 guest_efer &= ~ignore_bits; 993 guest_efer |= host_efer & ignore_bits; 994 995 vmx->guest_msrs[efer_offset].data = guest_efer; 996 vmx->guest_msrs[efer_offset].mask = ~ignore_bits; 997 998 return true; 999 } 1000 } 1001 1002 #ifdef CONFIG_X86_32 1003 /* 1004 * On 32-bit kernels, VM exits still load the FS and GS bases from the 1005 * VMCS rather than the segment table. KVM uses this helper to figure 1006 * out the current bases to poke them into the VMCS before entry. 1007 */ 1008 static unsigned long segment_base(u16 selector) 1009 { 1010 struct desc_struct *table; 1011 unsigned long v; 1012 1013 if (!(selector & ~SEGMENT_RPL_MASK)) 1014 return 0; 1015 1016 table = get_current_gdt_ro(); 1017 1018 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 1019 u16 ldt_selector = kvm_read_ldt(); 1020 1021 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 1022 return 0; 1023 1024 table = (struct desc_struct *)segment_base(ldt_selector); 1025 } 1026 v = get_desc_base(&table[selector >> 3]); 1027 return v; 1028 } 1029 #endif 1030 1031 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx) 1032 { 1033 return vmx_pt_mode_is_host_guest() && 1034 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 1035 } 1036 1037 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 1038 { 1039 u32 i; 1040 1041 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1042 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1043 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1044 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1045 for (i = 0; i < addr_range; i++) { 1046 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1047 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1048 } 1049 } 1050 1051 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 1052 { 1053 u32 i; 1054 1055 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1056 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1057 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1058 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1059 for (i = 0; i < addr_range; i++) { 1060 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1061 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1062 } 1063 } 1064 1065 static void pt_guest_enter(struct vcpu_vmx *vmx) 1066 { 1067 if (vmx_pt_mode_is_system()) 1068 return; 1069 1070 /* 1071 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1072 * Save host state before VM entry. 1073 */ 1074 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1075 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1076 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1077 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1078 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1079 } 1080 } 1081 1082 static void pt_guest_exit(struct vcpu_vmx *vmx) 1083 { 1084 if (vmx_pt_mode_is_system()) 1085 return; 1086 1087 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1088 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1089 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1090 } 1091 1092 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1093 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1094 } 1095 1096 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 1097 unsigned long fs_base, unsigned long gs_base) 1098 { 1099 if (unlikely(fs_sel != host->fs_sel)) { 1100 if (!(fs_sel & 7)) 1101 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1102 else 1103 vmcs_write16(HOST_FS_SELECTOR, 0); 1104 host->fs_sel = fs_sel; 1105 } 1106 if (unlikely(gs_sel != host->gs_sel)) { 1107 if (!(gs_sel & 7)) 1108 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1109 else 1110 vmcs_write16(HOST_GS_SELECTOR, 0); 1111 host->gs_sel = gs_sel; 1112 } 1113 if (unlikely(fs_base != host->fs_base)) { 1114 vmcs_writel(HOST_FS_BASE, fs_base); 1115 host->fs_base = fs_base; 1116 } 1117 if (unlikely(gs_base != host->gs_base)) { 1118 vmcs_writel(HOST_GS_BASE, gs_base); 1119 host->gs_base = gs_base; 1120 } 1121 } 1122 1123 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1124 { 1125 struct vcpu_vmx *vmx = to_vmx(vcpu); 1126 struct vmcs_host_state *host_state; 1127 #ifdef CONFIG_X86_64 1128 int cpu = raw_smp_processor_id(); 1129 #endif 1130 unsigned long fs_base, gs_base; 1131 u16 fs_sel, gs_sel; 1132 int i; 1133 1134 vmx->req_immediate_exit = false; 1135 1136 /* 1137 * Note that guest MSRs to be saved/restored can also be changed 1138 * when guest state is loaded. This happens when guest transitions 1139 * to/from long-mode by setting MSR_EFER.LMA. 1140 */ 1141 if (!vmx->guest_msrs_ready) { 1142 vmx->guest_msrs_ready = true; 1143 for (i = 0; i < vmx->save_nmsrs; ++i) 1144 kvm_set_shared_msr(vmx->guest_msrs[i].index, 1145 vmx->guest_msrs[i].data, 1146 vmx->guest_msrs[i].mask); 1147 1148 } 1149 1150 if (vmx->nested.need_vmcs12_to_shadow_sync) 1151 nested_sync_vmcs12_to_shadow(vcpu); 1152 1153 if (vmx->guest_state_loaded) 1154 return; 1155 1156 host_state = &vmx->loaded_vmcs->host_state; 1157 1158 /* 1159 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1160 * allow segment selectors with cpl > 0 or ti == 1. 1161 */ 1162 host_state->ldt_sel = kvm_read_ldt(); 1163 1164 #ifdef CONFIG_X86_64 1165 savesegment(ds, host_state->ds_sel); 1166 savesegment(es, host_state->es_sel); 1167 1168 gs_base = cpu_kernelmode_gs_base(cpu); 1169 if (likely(is_64bit_mm(current->mm))) { 1170 save_fsgs_for_kvm(); 1171 fs_sel = current->thread.fsindex; 1172 gs_sel = current->thread.gsindex; 1173 fs_base = current->thread.fsbase; 1174 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1175 } else { 1176 savesegment(fs, fs_sel); 1177 savesegment(gs, gs_sel); 1178 fs_base = read_msr(MSR_FS_BASE); 1179 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1180 } 1181 1182 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1183 #else 1184 savesegment(fs, fs_sel); 1185 savesegment(gs, gs_sel); 1186 fs_base = segment_base(fs_sel); 1187 gs_base = segment_base(gs_sel); 1188 #endif 1189 1190 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); 1191 vmx->guest_state_loaded = true; 1192 } 1193 1194 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1195 { 1196 struct vmcs_host_state *host_state; 1197 1198 if (!vmx->guest_state_loaded) 1199 return; 1200 1201 host_state = &vmx->loaded_vmcs->host_state; 1202 1203 ++vmx->vcpu.stat.host_state_reload; 1204 1205 #ifdef CONFIG_X86_64 1206 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1207 #endif 1208 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1209 kvm_load_ldt(host_state->ldt_sel); 1210 #ifdef CONFIG_X86_64 1211 load_gs_index(host_state->gs_sel); 1212 #else 1213 loadsegment(gs, host_state->gs_sel); 1214 #endif 1215 } 1216 if (host_state->fs_sel & 7) 1217 loadsegment(fs, host_state->fs_sel); 1218 #ifdef CONFIG_X86_64 1219 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1220 loadsegment(ds, host_state->ds_sel); 1221 loadsegment(es, host_state->es_sel); 1222 } 1223 #endif 1224 invalidate_tss_limit(); 1225 #ifdef CONFIG_X86_64 1226 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1227 #endif 1228 load_fixmap_gdt(raw_smp_processor_id()); 1229 vmx->guest_state_loaded = false; 1230 vmx->guest_msrs_ready = false; 1231 } 1232 1233 #ifdef CONFIG_X86_64 1234 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1235 { 1236 preempt_disable(); 1237 if (vmx->guest_state_loaded) 1238 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1239 preempt_enable(); 1240 return vmx->msr_guest_kernel_gs_base; 1241 } 1242 1243 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1244 { 1245 preempt_disable(); 1246 if (vmx->guest_state_loaded) 1247 wrmsrl(MSR_KERNEL_GS_BASE, data); 1248 preempt_enable(); 1249 vmx->msr_guest_kernel_gs_base = data; 1250 } 1251 #endif 1252 1253 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) 1254 { 1255 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1256 struct pi_desc old, new; 1257 unsigned int dest; 1258 1259 /* 1260 * In case of hot-plug or hot-unplug, we may have to undo 1261 * vmx_vcpu_pi_put even if there is no assigned device. And we 1262 * always keep PI.NDST up to date for simplicity: it makes the 1263 * code easier, and CPU migration is not a fast path. 1264 */ 1265 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) 1266 return; 1267 1268 /* 1269 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change 1270 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the 1271 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that 1272 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up 1273 * correctly. 1274 */ 1275 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) { 1276 pi_clear_sn(pi_desc); 1277 goto after_clear_sn; 1278 } 1279 1280 /* The full case. */ 1281 do { 1282 old.control = new.control = pi_desc->control; 1283 1284 dest = cpu_physical_id(cpu); 1285 1286 if (x2apic_enabled()) 1287 new.ndst = dest; 1288 else 1289 new.ndst = (dest << 8) & 0xFF00; 1290 1291 new.sn = 0; 1292 } while (cmpxchg64(&pi_desc->control, old.control, 1293 new.control) != old.control); 1294 1295 after_clear_sn: 1296 1297 /* 1298 * Clear SN before reading the bitmap. The VT-d firmware 1299 * writes the bitmap and reads SN atomically (5.2.3 in the 1300 * spec), so it doesn't really have a memory barrier that 1301 * pairs with this, but we cannot do that and we need one. 1302 */ 1303 smp_mb__after_atomic(); 1304 1305 if (!pi_is_pir_empty(pi_desc)) 1306 pi_set_on(pi_desc); 1307 } 1308 1309 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu) 1310 { 1311 struct vcpu_vmx *vmx = to_vmx(vcpu); 1312 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1313 1314 if (!already_loaded) { 1315 loaded_vmcs_clear(vmx->loaded_vmcs); 1316 local_irq_disable(); 1317 1318 /* 1319 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to 1320 * this cpu's percpu list, otherwise it may not yet be deleted 1321 * from its previous cpu's percpu list. Pairs with the 1322 * smb_wmb() in __loaded_vmcs_clear(). 1323 */ 1324 smp_rmb(); 1325 1326 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1327 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1328 local_irq_enable(); 1329 } 1330 1331 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { 1332 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1333 vmcs_load(vmx->loaded_vmcs->vmcs); 1334 indirect_branch_prediction_barrier(); 1335 } 1336 1337 if (!already_loaded) { 1338 void *gdt = get_current_gdt_ro(); 1339 unsigned long sysenter_esp; 1340 1341 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1342 1343 /* 1344 * Linux uses per-cpu TSS and GDT, so set these when switching 1345 * processors. See 22.2.4. 1346 */ 1347 vmcs_writel(HOST_TR_BASE, 1348 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1349 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1350 1351 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1352 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1353 1354 vmx->loaded_vmcs->cpu = cpu; 1355 } 1356 1357 /* Setup TSC multiplier */ 1358 if (kvm_has_tsc_control && 1359 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1360 decache_tsc_multiplier(vmx); 1361 } 1362 1363 /* 1364 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1365 * vcpu mutex is already taken. 1366 */ 1367 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1368 { 1369 struct vcpu_vmx *vmx = to_vmx(vcpu); 1370 1371 vmx_vcpu_load_vmcs(vcpu, cpu); 1372 1373 vmx_vcpu_pi_load(vcpu, cpu); 1374 1375 vmx->host_pkru = read_pkru(); 1376 vmx->host_debugctlmsr = get_debugctlmsr(); 1377 } 1378 1379 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) 1380 { 1381 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1382 1383 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 1384 !irq_remapping_cap(IRQ_POSTING_CAP) || 1385 !kvm_vcpu_apicv_active(vcpu)) 1386 return; 1387 1388 /* Set SN when the vCPU is preempted */ 1389 if (vcpu->preempted) 1390 pi_set_sn(pi_desc); 1391 } 1392 1393 static void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1394 { 1395 vmx_vcpu_pi_put(vcpu); 1396 1397 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1398 } 1399 1400 static bool emulation_required(struct kvm_vcpu *vcpu) 1401 { 1402 return emulate_invalid_guest_state && !guest_state_valid(vcpu); 1403 } 1404 1405 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1406 { 1407 struct vcpu_vmx *vmx = to_vmx(vcpu); 1408 unsigned long rflags, save_rflags; 1409 1410 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) { 1411 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1412 rflags = vmcs_readl(GUEST_RFLAGS); 1413 if (vmx->rmode.vm86_active) { 1414 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1415 save_rflags = vmx->rmode.save_rflags; 1416 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1417 } 1418 vmx->rflags = rflags; 1419 } 1420 return vmx->rflags; 1421 } 1422 1423 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1424 { 1425 struct vcpu_vmx *vmx = to_vmx(vcpu); 1426 unsigned long old_rflags; 1427 1428 if (enable_unrestricted_guest) { 1429 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1430 vmx->rflags = rflags; 1431 vmcs_writel(GUEST_RFLAGS, rflags); 1432 return; 1433 } 1434 1435 old_rflags = vmx_get_rflags(vcpu); 1436 vmx->rflags = rflags; 1437 if (vmx->rmode.vm86_active) { 1438 vmx->rmode.save_rflags = rflags; 1439 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1440 } 1441 vmcs_writel(GUEST_RFLAGS, rflags); 1442 1443 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM) 1444 vmx->emulation_required = emulation_required(vcpu); 1445 } 1446 1447 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1448 { 1449 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1450 int ret = 0; 1451 1452 if (interruptibility & GUEST_INTR_STATE_STI) 1453 ret |= KVM_X86_SHADOW_INT_STI; 1454 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1455 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1456 1457 return ret; 1458 } 1459 1460 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1461 { 1462 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1463 u32 interruptibility = interruptibility_old; 1464 1465 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1466 1467 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1468 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1469 else if (mask & KVM_X86_SHADOW_INT_STI) 1470 interruptibility |= GUEST_INTR_STATE_STI; 1471 1472 if ((interruptibility != interruptibility_old)) 1473 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1474 } 1475 1476 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1477 { 1478 struct vcpu_vmx *vmx = to_vmx(vcpu); 1479 unsigned long value; 1480 1481 /* 1482 * Any MSR write that attempts to change bits marked reserved will 1483 * case a #GP fault. 1484 */ 1485 if (data & vmx->pt_desc.ctl_bitmask) 1486 return 1; 1487 1488 /* 1489 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1490 * result in a #GP unless the same write also clears TraceEn. 1491 */ 1492 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1493 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1494 return 1; 1495 1496 /* 1497 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1498 * and FabricEn would cause #GP, if 1499 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1500 */ 1501 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1502 !(data & RTIT_CTL_FABRIC_EN) && 1503 !intel_pt_validate_cap(vmx->pt_desc.caps, 1504 PT_CAP_single_range_output)) 1505 return 1; 1506 1507 /* 1508 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1509 * utilize encodings marked reserved will casue a #GP fault. 1510 */ 1511 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1512 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1513 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1514 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1515 return 1; 1516 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1517 PT_CAP_cycle_thresholds); 1518 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1519 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1520 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1521 return 1; 1522 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1523 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1524 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1525 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1526 return 1; 1527 1528 /* 1529 * If ADDRx_CFG is reserved or the encodings is >2 will 1530 * cause a #GP fault. 1531 */ 1532 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1533 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1534 return 1; 1535 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1536 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1537 return 1; 1538 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1539 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1540 return 1; 1541 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1542 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1543 return 1; 1544 1545 return 0; 1546 } 1547 1548 static int skip_emulated_instruction(struct kvm_vcpu *vcpu) 1549 { 1550 unsigned long rip; 1551 1552 /* 1553 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on 1554 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be 1555 * set when EPT misconfig occurs. In practice, real hardware updates 1556 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors 1557 * (namely Hyper-V) don't set it due to it being undefined behavior, 1558 * i.e. we end up advancing IP with some random value. 1559 */ 1560 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || 1561 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) { 1562 rip = kvm_rip_read(vcpu); 1563 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1564 kvm_rip_write(vcpu, rip); 1565 } else { 1566 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 1567 return 0; 1568 } 1569 1570 /* skipping an emulated instruction also counts */ 1571 vmx_set_interrupt_shadow(vcpu, 0); 1572 1573 return 1; 1574 } 1575 1576 1577 /* 1578 * Recognizes a pending MTF VM-exit and records the nested state for later 1579 * delivery. 1580 */ 1581 static void vmx_update_emulated_instruction(struct kvm_vcpu *vcpu) 1582 { 1583 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1584 struct vcpu_vmx *vmx = to_vmx(vcpu); 1585 1586 if (!is_guest_mode(vcpu)) 1587 return; 1588 1589 /* 1590 * Per the SDM, MTF takes priority over debug-trap exceptions besides 1591 * T-bit traps. As instruction emulation is completed (i.e. at the 1592 * instruction boundary), any #DB exception pending delivery must be a 1593 * debug-trap. Record the pending MTF state to be delivered in 1594 * vmx_check_nested_events(). 1595 */ 1596 if (nested_cpu_has_mtf(vmcs12) && 1597 (!vcpu->arch.exception.pending || 1598 vcpu->arch.exception.nr == DB_VECTOR)) 1599 vmx->nested.mtf_pending = true; 1600 else 1601 vmx->nested.mtf_pending = false; 1602 } 1603 1604 static int vmx_skip_emulated_instruction(struct kvm_vcpu *vcpu) 1605 { 1606 vmx_update_emulated_instruction(vcpu); 1607 return skip_emulated_instruction(vcpu); 1608 } 1609 1610 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1611 { 1612 /* 1613 * Ensure that we clear the HLT state in the VMCS. We don't need to 1614 * explicitly skip the instruction because if the HLT state is set, 1615 * then the instruction is already executing and RIP has already been 1616 * advanced. 1617 */ 1618 if (kvm_hlt_in_guest(vcpu->kvm) && 1619 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1620 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1621 } 1622 1623 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1624 { 1625 struct vcpu_vmx *vmx = to_vmx(vcpu); 1626 unsigned nr = vcpu->arch.exception.nr; 1627 bool has_error_code = vcpu->arch.exception.has_error_code; 1628 u32 error_code = vcpu->arch.exception.error_code; 1629 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1630 1631 kvm_deliver_exception_payload(vcpu); 1632 1633 if (has_error_code) { 1634 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1635 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1636 } 1637 1638 if (vmx->rmode.vm86_active) { 1639 int inc_eip = 0; 1640 if (kvm_exception_is_soft(nr)) 1641 inc_eip = vcpu->arch.event_exit_inst_len; 1642 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); 1643 return; 1644 } 1645 1646 WARN_ON_ONCE(vmx->emulation_required); 1647 1648 if (kvm_exception_is_soft(nr)) { 1649 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1650 vmx->vcpu.arch.event_exit_inst_len); 1651 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1652 } else 1653 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1654 1655 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1656 1657 vmx_clear_hlt(vcpu); 1658 } 1659 1660 /* 1661 * Swap MSR entry in host/guest MSR entry array. 1662 */ 1663 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) 1664 { 1665 struct shared_msr_entry tmp; 1666 1667 tmp = vmx->guest_msrs[to]; 1668 vmx->guest_msrs[to] = vmx->guest_msrs[from]; 1669 vmx->guest_msrs[from] = tmp; 1670 } 1671 1672 /* 1673 * Set up the vmcs to automatically save and restore system 1674 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1675 * mode, as fiddling with msrs is very expensive. 1676 */ 1677 static void setup_msrs(struct vcpu_vmx *vmx) 1678 { 1679 int save_nmsrs, index; 1680 1681 save_nmsrs = 0; 1682 #ifdef CONFIG_X86_64 1683 /* 1684 * The SYSCALL MSRs are only needed on long mode guests, and only 1685 * when EFER.SCE is set. 1686 */ 1687 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1688 index = __find_msr_index(vmx, MSR_STAR); 1689 if (index >= 0) 1690 move_msr_up(vmx, index, save_nmsrs++); 1691 index = __find_msr_index(vmx, MSR_LSTAR); 1692 if (index >= 0) 1693 move_msr_up(vmx, index, save_nmsrs++); 1694 index = __find_msr_index(vmx, MSR_SYSCALL_MASK); 1695 if (index >= 0) 1696 move_msr_up(vmx, index, save_nmsrs++); 1697 } 1698 #endif 1699 index = __find_msr_index(vmx, MSR_EFER); 1700 if (index >= 0 && update_transition_efer(vmx, index)) 1701 move_msr_up(vmx, index, save_nmsrs++); 1702 index = __find_msr_index(vmx, MSR_TSC_AUX); 1703 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1704 move_msr_up(vmx, index, save_nmsrs++); 1705 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL); 1706 if (index >= 0) 1707 move_msr_up(vmx, index, save_nmsrs++); 1708 1709 vmx->save_nmsrs = save_nmsrs; 1710 vmx->guest_msrs_ready = false; 1711 1712 if (cpu_has_vmx_msr_bitmap()) 1713 vmx_update_msr_bitmap(&vmx->vcpu); 1714 } 1715 1716 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) 1717 { 1718 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1719 1720 if (is_guest_mode(vcpu) && 1721 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1722 return vcpu->arch.tsc_offset - vmcs12->tsc_offset; 1723 1724 return vcpu->arch.tsc_offset; 1725 } 1726 1727 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1728 { 1729 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1730 u64 g_tsc_offset = 0; 1731 1732 /* 1733 * We're here if L1 chose not to trap WRMSR to TSC. According 1734 * to the spec, this should set L1's TSC; The offset that L1 1735 * set for L2 remains unchanged, and still needs to be added 1736 * to the newly set TSC to get L2's TSC. 1737 */ 1738 if (is_guest_mode(vcpu) && 1739 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1740 g_tsc_offset = vmcs12->tsc_offset; 1741 1742 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1743 vcpu->arch.tsc_offset - g_tsc_offset, 1744 offset); 1745 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1746 return offset + g_tsc_offset; 1747 } 1748 1749 /* 1750 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1751 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1752 * all guests if the "nested" module option is off, and can also be disabled 1753 * for a single guest by disabling its VMX cpuid bit. 1754 */ 1755 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1756 { 1757 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1758 } 1759 1760 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1761 uint64_t val) 1762 { 1763 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1764 1765 return !(val & ~valid_bits); 1766 } 1767 1768 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1769 { 1770 switch (msr->index) { 1771 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1772 if (!nested) 1773 return 1; 1774 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1775 default: 1776 return 1; 1777 } 1778 } 1779 1780 /* 1781 * Reads an msr value (of 'msr_index') into 'pdata'. 1782 * Returns 0 on success, non-0 otherwise. 1783 * Assumes vcpu_load() was already called. 1784 */ 1785 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1786 { 1787 struct vcpu_vmx *vmx = to_vmx(vcpu); 1788 struct shared_msr_entry *msr; 1789 u32 index; 1790 1791 switch (msr_info->index) { 1792 #ifdef CONFIG_X86_64 1793 case MSR_FS_BASE: 1794 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1795 break; 1796 case MSR_GS_BASE: 1797 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1798 break; 1799 case MSR_KERNEL_GS_BASE: 1800 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1801 break; 1802 #endif 1803 case MSR_EFER: 1804 return kvm_get_msr_common(vcpu, msr_info); 1805 case MSR_IA32_TSX_CTRL: 1806 if (!msr_info->host_initiated && 1807 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 1808 return 1; 1809 goto find_shared_msr; 1810 case MSR_IA32_UMWAIT_CONTROL: 1811 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1812 return 1; 1813 1814 msr_info->data = vmx->msr_ia32_umwait_control; 1815 break; 1816 case MSR_IA32_SPEC_CTRL: 1817 if (!msr_info->host_initiated && 1818 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1819 return 1; 1820 1821 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1822 break; 1823 case MSR_IA32_SYSENTER_CS: 1824 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1825 break; 1826 case MSR_IA32_SYSENTER_EIP: 1827 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1828 break; 1829 case MSR_IA32_SYSENTER_ESP: 1830 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1831 break; 1832 case MSR_IA32_BNDCFGS: 1833 if (!kvm_mpx_supported() || 1834 (!msr_info->host_initiated && 1835 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1836 return 1; 1837 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1838 break; 1839 case MSR_IA32_MCG_EXT_CTL: 1840 if (!msr_info->host_initiated && 1841 !(vmx->msr_ia32_feature_control & 1842 FEAT_CTL_LMCE_ENABLED)) 1843 return 1; 1844 msr_info->data = vcpu->arch.mcg_ext_ctl; 1845 break; 1846 case MSR_IA32_FEAT_CTL: 1847 msr_info->data = vmx->msr_ia32_feature_control; 1848 break; 1849 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1850 if (!nested_vmx_allowed(vcpu)) 1851 return 1; 1852 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1853 &msr_info->data)) 1854 return 1; 1855 /* 1856 * Enlightened VMCS v1 doesn't have certain fields, but buggy 1857 * Hyper-V versions are still trying to use corresponding 1858 * features when they are exposed. Filter out the essential 1859 * minimum. 1860 */ 1861 if (!msr_info->host_initiated && 1862 vmx->nested.enlightened_vmcs_enabled) 1863 nested_evmcs_filter_control_msr(msr_info->index, 1864 &msr_info->data); 1865 break; 1866 case MSR_IA32_RTIT_CTL: 1867 if (!vmx_pt_mode_is_host_guest()) 1868 return 1; 1869 msr_info->data = vmx->pt_desc.guest.ctl; 1870 break; 1871 case MSR_IA32_RTIT_STATUS: 1872 if (!vmx_pt_mode_is_host_guest()) 1873 return 1; 1874 msr_info->data = vmx->pt_desc.guest.status; 1875 break; 1876 case MSR_IA32_RTIT_CR3_MATCH: 1877 if (!vmx_pt_mode_is_host_guest() || 1878 !intel_pt_validate_cap(vmx->pt_desc.caps, 1879 PT_CAP_cr3_filtering)) 1880 return 1; 1881 msr_info->data = vmx->pt_desc.guest.cr3_match; 1882 break; 1883 case MSR_IA32_RTIT_OUTPUT_BASE: 1884 if (!vmx_pt_mode_is_host_guest() || 1885 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1886 PT_CAP_topa_output) && 1887 !intel_pt_validate_cap(vmx->pt_desc.caps, 1888 PT_CAP_single_range_output))) 1889 return 1; 1890 msr_info->data = vmx->pt_desc.guest.output_base; 1891 break; 1892 case MSR_IA32_RTIT_OUTPUT_MASK: 1893 if (!vmx_pt_mode_is_host_guest() || 1894 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1895 PT_CAP_topa_output) && 1896 !intel_pt_validate_cap(vmx->pt_desc.caps, 1897 PT_CAP_single_range_output))) 1898 return 1; 1899 msr_info->data = vmx->pt_desc.guest.output_mask; 1900 break; 1901 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1902 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1903 if (!vmx_pt_mode_is_host_guest() || 1904 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1905 PT_CAP_num_address_ranges))) 1906 return 1; 1907 if (index % 2) 1908 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1909 else 1910 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1911 break; 1912 case MSR_TSC_AUX: 1913 if (!msr_info->host_initiated && 1914 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1915 return 1; 1916 goto find_shared_msr; 1917 default: 1918 find_shared_msr: 1919 msr = find_msr_entry(vmx, msr_info->index); 1920 if (msr) { 1921 msr_info->data = msr->data; 1922 break; 1923 } 1924 return kvm_get_msr_common(vcpu, msr_info); 1925 } 1926 1927 return 0; 1928 } 1929 1930 /* 1931 * Writes msr value into the appropriate "register". 1932 * Returns 0 on success, non-0 otherwise. 1933 * Assumes vcpu_load() was already called. 1934 */ 1935 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1936 { 1937 struct vcpu_vmx *vmx = to_vmx(vcpu); 1938 struct shared_msr_entry *msr; 1939 int ret = 0; 1940 u32 msr_index = msr_info->index; 1941 u64 data = msr_info->data; 1942 u32 index; 1943 1944 switch (msr_index) { 1945 case MSR_EFER: 1946 ret = kvm_set_msr_common(vcpu, msr_info); 1947 break; 1948 #ifdef CONFIG_X86_64 1949 case MSR_FS_BASE: 1950 vmx_segment_cache_clear(vmx); 1951 vmcs_writel(GUEST_FS_BASE, data); 1952 break; 1953 case MSR_GS_BASE: 1954 vmx_segment_cache_clear(vmx); 1955 vmcs_writel(GUEST_GS_BASE, data); 1956 break; 1957 case MSR_KERNEL_GS_BASE: 1958 vmx_write_guest_kernel_gs_base(vmx, data); 1959 break; 1960 #endif 1961 case MSR_IA32_SYSENTER_CS: 1962 if (is_guest_mode(vcpu)) 1963 get_vmcs12(vcpu)->guest_sysenter_cs = data; 1964 vmcs_write32(GUEST_SYSENTER_CS, data); 1965 break; 1966 case MSR_IA32_SYSENTER_EIP: 1967 if (is_guest_mode(vcpu)) 1968 get_vmcs12(vcpu)->guest_sysenter_eip = data; 1969 vmcs_writel(GUEST_SYSENTER_EIP, data); 1970 break; 1971 case MSR_IA32_SYSENTER_ESP: 1972 if (is_guest_mode(vcpu)) 1973 get_vmcs12(vcpu)->guest_sysenter_esp = data; 1974 vmcs_writel(GUEST_SYSENTER_ESP, data); 1975 break; 1976 case MSR_IA32_DEBUGCTLMSR: 1977 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & 1978 VM_EXIT_SAVE_DEBUG_CONTROLS) 1979 get_vmcs12(vcpu)->guest_ia32_debugctl = data; 1980 1981 ret = kvm_set_msr_common(vcpu, msr_info); 1982 break; 1983 1984 case MSR_IA32_BNDCFGS: 1985 if (!kvm_mpx_supported() || 1986 (!msr_info->host_initiated && 1987 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1988 return 1; 1989 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 1990 (data & MSR_IA32_BNDCFGS_RSVD)) 1991 return 1; 1992 vmcs_write64(GUEST_BNDCFGS, data); 1993 break; 1994 case MSR_IA32_UMWAIT_CONTROL: 1995 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1996 return 1; 1997 1998 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ 1999 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) 2000 return 1; 2001 2002 vmx->msr_ia32_umwait_control = data; 2003 break; 2004 case MSR_IA32_SPEC_CTRL: 2005 if (!msr_info->host_initiated && 2006 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2007 return 1; 2008 2009 if (data & ~kvm_spec_ctrl_valid_bits(vcpu)) 2010 return 1; 2011 2012 vmx->spec_ctrl = data; 2013 if (!data) 2014 break; 2015 2016 /* 2017 * For non-nested: 2018 * When it's written (to non-zero) for the first time, pass 2019 * it through. 2020 * 2021 * For nested: 2022 * The handling of the MSR bitmap for L2 guests is done in 2023 * nested_vmx_prepare_msr_bitmap. We should not touch the 2024 * vmcs02.msr_bitmap here since it gets completely overwritten 2025 * in the merging. We update the vmcs01 here for L1 as well 2026 * since it will end up touching the MSR anyway now. 2027 */ 2028 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, 2029 MSR_IA32_SPEC_CTRL, 2030 MSR_TYPE_RW); 2031 break; 2032 case MSR_IA32_TSX_CTRL: 2033 if (!msr_info->host_initiated && 2034 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 2035 return 1; 2036 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) 2037 return 1; 2038 goto find_shared_msr; 2039 case MSR_IA32_PRED_CMD: 2040 if (!msr_info->host_initiated && 2041 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2042 return 1; 2043 2044 if (data & ~PRED_CMD_IBPB) 2045 return 1; 2046 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL)) 2047 return 1; 2048 if (!data) 2049 break; 2050 2051 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 2052 2053 /* 2054 * For non-nested: 2055 * When it's written (to non-zero) for the first time, pass 2056 * it through. 2057 * 2058 * For nested: 2059 * The handling of the MSR bitmap for L2 guests is done in 2060 * nested_vmx_prepare_msr_bitmap. We should not touch the 2061 * vmcs02.msr_bitmap here since it gets completely overwritten 2062 * in the merging. 2063 */ 2064 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, 2065 MSR_TYPE_W); 2066 break; 2067 case MSR_IA32_CR_PAT: 2068 if (!kvm_pat_valid(data)) 2069 return 1; 2070 2071 if (is_guest_mode(vcpu) && 2072 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) 2073 get_vmcs12(vcpu)->guest_ia32_pat = data; 2074 2075 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2076 vmcs_write64(GUEST_IA32_PAT, data); 2077 vcpu->arch.pat = data; 2078 break; 2079 } 2080 ret = kvm_set_msr_common(vcpu, msr_info); 2081 break; 2082 case MSR_IA32_TSC_ADJUST: 2083 ret = kvm_set_msr_common(vcpu, msr_info); 2084 break; 2085 case MSR_IA32_MCG_EXT_CTL: 2086 if ((!msr_info->host_initiated && 2087 !(to_vmx(vcpu)->msr_ia32_feature_control & 2088 FEAT_CTL_LMCE_ENABLED)) || 2089 (data & ~MCG_EXT_CTL_LMCE_EN)) 2090 return 1; 2091 vcpu->arch.mcg_ext_ctl = data; 2092 break; 2093 case MSR_IA32_FEAT_CTL: 2094 if (!vmx_feature_control_msr_valid(vcpu, data) || 2095 (to_vmx(vcpu)->msr_ia32_feature_control & 2096 FEAT_CTL_LOCKED && !msr_info->host_initiated)) 2097 return 1; 2098 vmx->msr_ia32_feature_control = data; 2099 if (msr_info->host_initiated && data == 0) 2100 vmx_leave_nested(vcpu); 2101 break; 2102 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 2103 if (!msr_info->host_initiated) 2104 return 1; /* they are read-only */ 2105 if (!nested_vmx_allowed(vcpu)) 2106 return 1; 2107 return vmx_set_vmx_msr(vcpu, msr_index, data); 2108 case MSR_IA32_RTIT_CTL: 2109 if (!vmx_pt_mode_is_host_guest() || 2110 vmx_rtit_ctl_check(vcpu, data) || 2111 vmx->nested.vmxon) 2112 return 1; 2113 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 2114 vmx->pt_desc.guest.ctl = data; 2115 pt_update_intercept_for_msr(vmx); 2116 break; 2117 case MSR_IA32_RTIT_STATUS: 2118 if (!pt_can_write_msr(vmx)) 2119 return 1; 2120 if (data & MSR_IA32_RTIT_STATUS_MASK) 2121 return 1; 2122 vmx->pt_desc.guest.status = data; 2123 break; 2124 case MSR_IA32_RTIT_CR3_MATCH: 2125 if (!pt_can_write_msr(vmx)) 2126 return 1; 2127 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2128 PT_CAP_cr3_filtering)) 2129 return 1; 2130 vmx->pt_desc.guest.cr3_match = data; 2131 break; 2132 case MSR_IA32_RTIT_OUTPUT_BASE: 2133 if (!pt_can_write_msr(vmx)) 2134 return 1; 2135 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2136 PT_CAP_topa_output) && 2137 !intel_pt_validate_cap(vmx->pt_desc.caps, 2138 PT_CAP_single_range_output)) 2139 return 1; 2140 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK) 2141 return 1; 2142 vmx->pt_desc.guest.output_base = data; 2143 break; 2144 case MSR_IA32_RTIT_OUTPUT_MASK: 2145 if (!pt_can_write_msr(vmx)) 2146 return 1; 2147 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2148 PT_CAP_topa_output) && 2149 !intel_pt_validate_cap(vmx->pt_desc.caps, 2150 PT_CAP_single_range_output)) 2151 return 1; 2152 vmx->pt_desc.guest.output_mask = data; 2153 break; 2154 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2155 if (!pt_can_write_msr(vmx)) 2156 return 1; 2157 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2158 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2159 PT_CAP_num_address_ranges)) 2160 return 1; 2161 if (is_noncanonical_address(data, vcpu)) 2162 return 1; 2163 if (index % 2) 2164 vmx->pt_desc.guest.addr_b[index / 2] = data; 2165 else 2166 vmx->pt_desc.guest.addr_a[index / 2] = data; 2167 break; 2168 case MSR_TSC_AUX: 2169 if (!msr_info->host_initiated && 2170 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2171 return 1; 2172 /* Check reserved bit, higher 32 bits should be zero */ 2173 if ((data >> 32) != 0) 2174 return 1; 2175 goto find_shared_msr; 2176 2177 default: 2178 find_shared_msr: 2179 msr = find_msr_entry(vmx, msr_index); 2180 if (msr) 2181 ret = vmx_set_guest_msr(vmx, msr, data); 2182 else 2183 ret = kvm_set_msr_common(vcpu, msr_info); 2184 } 2185 2186 return ret; 2187 } 2188 2189 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2190 { 2191 kvm_register_mark_available(vcpu, reg); 2192 2193 switch (reg) { 2194 case VCPU_REGS_RSP: 2195 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2196 break; 2197 case VCPU_REGS_RIP: 2198 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2199 break; 2200 case VCPU_EXREG_PDPTR: 2201 if (enable_ept) 2202 ept_save_pdptrs(vcpu); 2203 break; 2204 case VCPU_EXREG_CR3: 2205 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) 2206 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2207 break; 2208 default: 2209 WARN_ON_ONCE(1); 2210 break; 2211 } 2212 } 2213 2214 static __init int cpu_has_kvm_support(void) 2215 { 2216 return cpu_has_vmx(); 2217 } 2218 2219 static __init int vmx_disabled_by_bios(void) 2220 { 2221 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2222 !boot_cpu_has(X86_FEATURE_VMX); 2223 } 2224 2225 static int kvm_cpu_vmxon(u64 vmxon_pointer) 2226 { 2227 u64 msr; 2228 2229 cr4_set_bits(X86_CR4_VMXE); 2230 intel_pt_handle_vmx(1); 2231 2232 asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t" 2233 _ASM_EXTABLE(1b, %l[fault]) 2234 : : [vmxon_pointer] "m"(vmxon_pointer) 2235 : : fault); 2236 return 0; 2237 2238 fault: 2239 WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n", 2240 rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr); 2241 intel_pt_handle_vmx(0); 2242 cr4_clear_bits(X86_CR4_VMXE); 2243 2244 return -EFAULT; 2245 } 2246 2247 static int hardware_enable(void) 2248 { 2249 int cpu = raw_smp_processor_id(); 2250 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2251 int r; 2252 2253 if (cr4_read_shadow() & X86_CR4_VMXE) 2254 return -EBUSY; 2255 2256 /* 2257 * This can happen if we hot-added a CPU but failed to allocate 2258 * VP assist page for it. 2259 */ 2260 if (static_branch_unlikely(&enable_evmcs) && 2261 !hv_get_vp_assist_page(cpu)) 2262 return -EFAULT; 2263 2264 r = kvm_cpu_vmxon(phys_addr); 2265 if (r) 2266 return r; 2267 2268 if (enable_ept) 2269 ept_sync_global(); 2270 2271 return 0; 2272 } 2273 2274 static void vmclear_local_loaded_vmcss(void) 2275 { 2276 int cpu = raw_smp_processor_id(); 2277 struct loaded_vmcs *v, *n; 2278 2279 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2280 loaded_vmcss_on_cpu_link) 2281 __loaded_vmcs_clear(v); 2282 } 2283 2284 2285 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2286 * tricks. 2287 */ 2288 static void kvm_cpu_vmxoff(void) 2289 { 2290 asm volatile (__ex("vmxoff")); 2291 2292 intel_pt_handle_vmx(0); 2293 cr4_clear_bits(X86_CR4_VMXE); 2294 } 2295 2296 static void hardware_disable(void) 2297 { 2298 vmclear_local_loaded_vmcss(); 2299 kvm_cpu_vmxoff(); 2300 } 2301 2302 /* 2303 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID 2304 * directly instead of going through cpu_has(), to ensure KVM is trapping 2305 * ENCLS whenever it's supported in hardware. It does not matter whether 2306 * the host OS supports or has enabled SGX. 2307 */ 2308 static bool cpu_has_sgx(void) 2309 { 2310 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0)); 2311 } 2312 2313 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2314 u32 msr, u32 *result) 2315 { 2316 u32 vmx_msr_low, vmx_msr_high; 2317 u32 ctl = ctl_min | ctl_opt; 2318 2319 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2320 2321 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2322 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2323 2324 /* Ensure minimum (required) set of control bits are supported. */ 2325 if (ctl_min & ~ctl) 2326 return -EIO; 2327 2328 *result = ctl; 2329 return 0; 2330 } 2331 2332 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2333 struct vmx_capability *vmx_cap) 2334 { 2335 u32 vmx_msr_low, vmx_msr_high; 2336 u32 min, opt, min2, opt2; 2337 u32 _pin_based_exec_control = 0; 2338 u32 _cpu_based_exec_control = 0; 2339 u32 _cpu_based_2nd_exec_control = 0; 2340 u32 _vmexit_control = 0; 2341 u32 _vmentry_control = 0; 2342 2343 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2344 min = CPU_BASED_HLT_EXITING | 2345 #ifdef CONFIG_X86_64 2346 CPU_BASED_CR8_LOAD_EXITING | 2347 CPU_BASED_CR8_STORE_EXITING | 2348 #endif 2349 CPU_BASED_CR3_LOAD_EXITING | 2350 CPU_BASED_CR3_STORE_EXITING | 2351 CPU_BASED_UNCOND_IO_EXITING | 2352 CPU_BASED_MOV_DR_EXITING | 2353 CPU_BASED_USE_TSC_OFFSETTING | 2354 CPU_BASED_MWAIT_EXITING | 2355 CPU_BASED_MONITOR_EXITING | 2356 CPU_BASED_INVLPG_EXITING | 2357 CPU_BASED_RDPMC_EXITING; 2358 2359 opt = CPU_BASED_TPR_SHADOW | 2360 CPU_BASED_USE_MSR_BITMAPS | 2361 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2362 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2363 &_cpu_based_exec_control) < 0) 2364 return -EIO; 2365 #ifdef CONFIG_X86_64 2366 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2367 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2368 ~CPU_BASED_CR8_STORE_EXITING; 2369 #endif 2370 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2371 min2 = 0; 2372 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2373 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2374 SECONDARY_EXEC_WBINVD_EXITING | 2375 SECONDARY_EXEC_ENABLE_VPID | 2376 SECONDARY_EXEC_ENABLE_EPT | 2377 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2378 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2379 SECONDARY_EXEC_DESC | 2380 SECONDARY_EXEC_RDTSCP | 2381 SECONDARY_EXEC_ENABLE_INVPCID | 2382 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2383 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2384 SECONDARY_EXEC_SHADOW_VMCS | 2385 SECONDARY_EXEC_XSAVES | 2386 SECONDARY_EXEC_RDSEED_EXITING | 2387 SECONDARY_EXEC_RDRAND_EXITING | 2388 SECONDARY_EXEC_ENABLE_PML | 2389 SECONDARY_EXEC_TSC_SCALING | 2390 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2391 SECONDARY_EXEC_PT_USE_GPA | 2392 SECONDARY_EXEC_PT_CONCEAL_VMX | 2393 SECONDARY_EXEC_ENABLE_VMFUNC; 2394 if (cpu_has_sgx()) 2395 opt2 |= SECONDARY_EXEC_ENCLS_EXITING; 2396 if (adjust_vmx_controls(min2, opt2, 2397 MSR_IA32_VMX_PROCBASED_CTLS2, 2398 &_cpu_based_2nd_exec_control) < 0) 2399 return -EIO; 2400 } 2401 #ifndef CONFIG_X86_64 2402 if (!(_cpu_based_2nd_exec_control & 2403 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2404 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2405 #endif 2406 2407 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2408 _cpu_based_2nd_exec_control &= ~( 2409 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2410 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2411 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2412 2413 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2414 &vmx_cap->ept, &vmx_cap->vpid); 2415 2416 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2417 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2418 enabled */ 2419 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2420 CPU_BASED_CR3_STORE_EXITING | 2421 CPU_BASED_INVLPG_EXITING); 2422 } else if (vmx_cap->ept) { 2423 vmx_cap->ept = 0; 2424 pr_warn_once("EPT CAP should not exist if not support " 2425 "1-setting enable EPT VM-execution control\n"); 2426 } 2427 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2428 vmx_cap->vpid) { 2429 vmx_cap->vpid = 0; 2430 pr_warn_once("VPID CAP should not exist if not support " 2431 "1-setting enable VPID VM-execution control\n"); 2432 } 2433 2434 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2435 #ifdef CONFIG_X86_64 2436 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2437 #endif 2438 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2439 VM_EXIT_LOAD_IA32_PAT | 2440 VM_EXIT_LOAD_IA32_EFER | 2441 VM_EXIT_CLEAR_BNDCFGS | 2442 VM_EXIT_PT_CONCEAL_PIP | 2443 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2444 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2445 &_vmexit_control) < 0) 2446 return -EIO; 2447 2448 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2449 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2450 PIN_BASED_VMX_PREEMPTION_TIMER; 2451 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2452 &_pin_based_exec_control) < 0) 2453 return -EIO; 2454 2455 if (cpu_has_broken_vmx_preemption_timer()) 2456 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2457 if (!(_cpu_based_2nd_exec_control & 2458 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2459 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2460 2461 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2462 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2463 VM_ENTRY_LOAD_IA32_PAT | 2464 VM_ENTRY_LOAD_IA32_EFER | 2465 VM_ENTRY_LOAD_BNDCFGS | 2466 VM_ENTRY_PT_CONCEAL_PIP | 2467 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2468 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2469 &_vmentry_control) < 0) 2470 return -EIO; 2471 2472 /* 2473 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2474 * can't be used due to an errata where VM Exit may incorrectly clear 2475 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2476 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2477 */ 2478 if (boot_cpu_data.x86 == 0x6) { 2479 switch (boot_cpu_data.x86_model) { 2480 case 26: /* AAK155 */ 2481 case 30: /* AAP115 */ 2482 case 37: /* AAT100 */ 2483 case 44: /* BC86,AAY89,BD102 */ 2484 case 46: /* BA97 */ 2485 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2486 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2487 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2488 "does not work properly. Using workaround\n"); 2489 break; 2490 default: 2491 break; 2492 } 2493 } 2494 2495 2496 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2497 2498 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2499 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2500 return -EIO; 2501 2502 #ifdef CONFIG_X86_64 2503 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2504 if (vmx_msr_high & (1u<<16)) 2505 return -EIO; 2506 #endif 2507 2508 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2509 if (((vmx_msr_high >> 18) & 15) != 6) 2510 return -EIO; 2511 2512 vmcs_conf->size = vmx_msr_high & 0x1fff; 2513 vmcs_conf->order = get_order(vmcs_conf->size); 2514 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2515 2516 vmcs_conf->revision_id = vmx_msr_low; 2517 2518 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2519 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2520 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2521 vmcs_conf->vmexit_ctrl = _vmexit_control; 2522 vmcs_conf->vmentry_ctrl = _vmentry_control; 2523 2524 if (static_branch_unlikely(&enable_evmcs)) 2525 evmcs_sanitize_exec_ctrls(vmcs_conf); 2526 2527 return 0; 2528 } 2529 2530 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2531 { 2532 int node = cpu_to_node(cpu); 2533 struct page *pages; 2534 struct vmcs *vmcs; 2535 2536 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2537 if (!pages) 2538 return NULL; 2539 vmcs = page_address(pages); 2540 memset(vmcs, 0, vmcs_config.size); 2541 2542 /* KVM supports Enlightened VMCS v1 only */ 2543 if (static_branch_unlikely(&enable_evmcs)) 2544 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2545 else 2546 vmcs->hdr.revision_id = vmcs_config.revision_id; 2547 2548 if (shadow) 2549 vmcs->hdr.shadow_vmcs = 1; 2550 return vmcs; 2551 } 2552 2553 void free_vmcs(struct vmcs *vmcs) 2554 { 2555 free_pages((unsigned long)vmcs, vmcs_config.order); 2556 } 2557 2558 /* 2559 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2560 */ 2561 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2562 { 2563 if (!loaded_vmcs->vmcs) 2564 return; 2565 loaded_vmcs_clear(loaded_vmcs); 2566 free_vmcs(loaded_vmcs->vmcs); 2567 loaded_vmcs->vmcs = NULL; 2568 if (loaded_vmcs->msr_bitmap) 2569 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2570 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2571 } 2572 2573 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2574 { 2575 loaded_vmcs->vmcs = alloc_vmcs(false); 2576 if (!loaded_vmcs->vmcs) 2577 return -ENOMEM; 2578 2579 vmcs_clear(loaded_vmcs->vmcs); 2580 2581 loaded_vmcs->shadow_vmcs = NULL; 2582 loaded_vmcs->hv_timer_soft_disabled = false; 2583 loaded_vmcs->cpu = -1; 2584 loaded_vmcs->launched = 0; 2585 2586 if (cpu_has_vmx_msr_bitmap()) { 2587 loaded_vmcs->msr_bitmap = (unsigned long *) 2588 __get_free_page(GFP_KERNEL_ACCOUNT); 2589 if (!loaded_vmcs->msr_bitmap) 2590 goto out_vmcs; 2591 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2592 2593 if (IS_ENABLED(CONFIG_HYPERV) && 2594 static_branch_unlikely(&enable_evmcs) && 2595 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2596 struct hv_enlightened_vmcs *evmcs = 2597 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2598 2599 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2600 } 2601 } 2602 2603 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2604 memset(&loaded_vmcs->controls_shadow, 0, 2605 sizeof(struct vmcs_controls_shadow)); 2606 2607 return 0; 2608 2609 out_vmcs: 2610 free_loaded_vmcs(loaded_vmcs); 2611 return -ENOMEM; 2612 } 2613 2614 static void free_kvm_area(void) 2615 { 2616 int cpu; 2617 2618 for_each_possible_cpu(cpu) { 2619 free_vmcs(per_cpu(vmxarea, cpu)); 2620 per_cpu(vmxarea, cpu) = NULL; 2621 } 2622 } 2623 2624 static __init int alloc_kvm_area(void) 2625 { 2626 int cpu; 2627 2628 for_each_possible_cpu(cpu) { 2629 struct vmcs *vmcs; 2630 2631 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2632 if (!vmcs) { 2633 free_kvm_area(); 2634 return -ENOMEM; 2635 } 2636 2637 /* 2638 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2639 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2640 * revision_id reported by MSR_IA32_VMX_BASIC. 2641 * 2642 * However, even though not explicitly documented by 2643 * TLFS, VMXArea passed as VMXON argument should 2644 * still be marked with revision_id reported by 2645 * physical CPU. 2646 */ 2647 if (static_branch_unlikely(&enable_evmcs)) 2648 vmcs->hdr.revision_id = vmcs_config.revision_id; 2649 2650 per_cpu(vmxarea, cpu) = vmcs; 2651 } 2652 return 0; 2653 } 2654 2655 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2656 struct kvm_segment *save) 2657 { 2658 if (!emulate_invalid_guest_state) { 2659 /* 2660 * CS and SS RPL should be equal during guest entry according 2661 * to VMX spec, but in reality it is not always so. Since vcpu 2662 * is in the middle of the transition from real mode to 2663 * protected mode it is safe to assume that RPL 0 is a good 2664 * default value. 2665 */ 2666 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2667 save->selector &= ~SEGMENT_RPL_MASK; 2668 save->dpl = save->selector & SEGMENT_RPL_MASK; 2669 save->s = 1; 2670 } 2671 vmx_set_segment(vcpu, save, seg); 2672 } 2673 2674 static void enter_pmode(struct kvm_vcpu *vcpu) 2675 { 2676 unsigned long flags; 2677 struct vcpu_vmx *vmx = to_vmx(vcpu); 2678 2679 /* 2680 * Update real mode segment cache. It may be not up-to-date if sement 2681 * register was written while vcpu was in a guest mode. 2682 */ 2683 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2684 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2685 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2686 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2687 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2688 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2689 2690 vmx->rmode.vm86_active = 0; 2691 2692 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2693 2694 flags = vmcs_readl(GUEST_RFLAGS); 2695 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2696 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2697 vmcs_writel(GUEST_RFLAGS, flags); 2698 2699 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2700 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2701 2702 update_exception_bitmap(vcpu); 2703 2704 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2705 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2706 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2707 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2708 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2709 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2710 } 2711 2712 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2713 { 2714 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2715 struct kvm_segment var = *save; 2716 2717 var.dpl = 0x3; 2718 if (seg == VCPU_SREG_CS) 2719 var.type = 0x3; 2720 2721 if (!emulate_invalid_guest_state) { 2722 var.selector = var.base >> 4; 2723 var.base = var.base & 0xffff0; 2724 var.limit = 0xffff; 2725 var.g = 0; 2726 var.db = 0; 2727 var.present = 1; 2728 var.s = 1; 2729 var.l = 0; 2730 var.unusable = 0; 2731 var.type = 0x3; 2732 var.avl = 0; 2733 if (save->base & 0xf) 2734 printk_once(KERN_WARNING "kvm: segment base is not " 2735 "paragraph aligned when entering " 2736 "protected mode (seg=%d)", seg); 2737 } 2738 2739 vmcs_write16(sf->selector, var.selector); 2740 vmcs_writel(sf->base, var.base); 2741 vmcs_write32(sf->limit, var.limit); 2742 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2743 } 2744 2745 static void enter_rmode(struct kvm_vcpu *vcpu) 2746 { 2747 unsigned long flags; 2748 struct vcpu_vmx *vmx = to_vmx(vcpu); 2749 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2750 2751 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2752 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2753 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2754 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2755 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2756 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2757 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2758 2759 vmx->rmode.vm86_active = 1; 2760 2761 /* 2762 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2763 * vcpu. Warn the user that an update is overdue. 2764 */ 2765 if (!kvm_vmx->tss_addr) 2766 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2767 "called before entering vcpu\n"); 2768 2769 vmx_segment_cache_clear(vmx); 2770 2771 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2772 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2773 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2774 2775 flags = vmcs_readl(GUEST_RFLAGS); 2776 vmx->rmode.save_rflags = flags; 2777 2778 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2779 2780 vmcs_writel(GUEST_RFLAGS, flags); 2781 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2782 update_exception_bitmap(vcpu); 2783 2784 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2785 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2786 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2787 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2788 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2789 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2790 2791 kvm_mmu_reset_context(vcpu); 2792 } 2793 2794 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2795 { 2796 struct vcpu_vmx *vmx = to_vmx(vcpu); 2797 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); 2798 2799 if (!msr) 2800 return; 2801 2802 vcpu->arch.efer = efer; 2803 if (efer & EFER_LMA) { 2804 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2805 msr->data = efer; 2806 } else { 2807 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2808 2809 msr->data = efer & ~EFER_LME; 2810 } 2811 setup_msrs(vmx); 2812 } 2813 2814 #ifdef CONFIG_X86_64 2815 2816 static void enter_lmode(struct kvm_vcpu *vcpu) 2817 { 2818 u32 guest_tr_ar; 2819 2820 vmx_segment_cache_clear(to_vmx(vcpu)); 2821 2822 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2823 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2824 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2825 __func__); 2826 vmcs_write32(GUEST_TR_AR_BYTES, 2827 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2828 | VMX_AR_TYPE_BUSY_64_TSS); 2829 } 2830 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2831 } 2832 2833 static void exit_lmode(struct kvm_vcpu *vcpu) 2834 { 2835 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2836 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2837 } 2838 2839 #endif 2840 2841 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2842 { 2843 int vpid = to_vmx(vcpu)->vpid; 2844 2845 if (!vpid_sync_vcpu_addr(vpid, addr)) 2846 vpid_sync_context(vpid); 2847 2848 /* 2849 * If VPIDs are not supported or enabled, then the above is a no-op. 2850 * But we don't really need a TLB flush in that case anyway, because 2851 * each VM entry/exit includes an implicit flush when VPID is 0. 2852 */ 2853 } 2854 2855 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) 2856 { 2857 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2858 2859 vcpu->arch.cr0 &= ~cr0_guest_owned_bits; 2860 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; 2861 } 2862 2863 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) 2864 { 2865 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2866 2867 vcpu->arch.cr4 &= ~cr4_guest_owned_bits; 2868 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; 2869 } 2870 2871 static void ept_load_pdptrs(struct kvm_vcpu *vcpu) 2872 { 2873 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2874 2875 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR)) 2876 return; 2877 2878 if (is_pae_paging(vcpu)) { 2879 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2880 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2881 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2882 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2883 } 2884 } 2885 2886 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2887 { 2888 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2889 2890 if (is_pae_paging(vcpu)) { 2891 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2892 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2893 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2894 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2895 } 2896 2897 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 2898 } 2899 2900 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2901 unsigned long cr0, 2902 struct kvm_vcpu *vcpu) 2903 { 2904 struct vcpu_vmx *vmx = to_vmx(vcpu); 2905 2906 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) 2907 vmx_cache_reg(vcpu, VCPU_EXREG_CR3); 2908 if (!(cr0 & X86_CR0_PG)) { 2909 /* From paging/starting to nonpaging */ 2910 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2911 CPU_BASED_CR3_STORE_EXITING); 2912 vcpu->arch.cr0 = cr0; 2913 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2914 } else if (!is_paging(vcpu)) { 2915 /* From nonpaging to paging */ 2916 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2917 CPU_BASED_CR3_STORE_EXITING); 2918 vcpu->arch.cr0 = cr0; 2919 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2920 } 2921 2922 if (!(cr0 & X86_CR0_WP)) 2923 *hw_cr0 &= ~X86_CR0_WP; 2924 } 2925 2926 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 2927 { 2928 struct vcpu_vmx *vmx = to_vmx(vcpu); 2929 unsigned long hw_cr0; 2930 2931 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 2932 if (enable_unrestricted_guest) 2933 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 2934 else { 2935 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 2936 2937 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 2938 enter_pmode(vcpu); 2939 2940 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 2941 enter_rmode(vcpu); 2942 } 2943 2944 #ifdef CONFIG_X86_64 2945 if (vcpu->arch.efer & EFER_LME) { 2946 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 2947 enter_lmode(vcpu); 2948 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 2949 exit_lmode(vcpu); 2950 } 2951 #endif 2952 2953 if (enable_ept && !enable_unrestricted_guest) 2954 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 2955 2956 vmcs_writel(CR0_READ_SHADOW, cr0); 2957 vmcs_writel(GUEST_CR0, hw_cr0); 2958 vcpu->arch.cr0 = cr0; 2959 2960 /* depends on vcpu->arch.cr0 to be set to a new value */ 2961 vmx->emulation_required = emulation_required(vcpu); 2962 } 2963 2964 static int get_ept_level(struct kvm_vcpu *vcpu) 2965 { 2966 if (is_guest_mode(vcpu) && nested_cpu_has_ept(get_vmcs12(vcpu))) 2967 return vmx_eptp_page_walk_level(nested_ept_get_eptp(vcpu)); 2968 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) 2969 return 5; 2970 return 4; 2971 } 2972 2973 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) 2974 { 2975 u64 eptp = VMX_EPTP_MT_WB; 2976 2977 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 2978 2979 if (enable_ept_ad_bits && 2980 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 2981 eptp |= VMX_EPTP_AD_ENABLE_BIT; 2982 eptp |= (root_hpa & PAGE_MASK); 2983 2984 return eptp; 2985 } 2986 2987 void vmx_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long cr3) 2988 { 2989 struct kvm *kvm = vcpu->kvm; 2990 bool update_guest_cr3 = true; 2991 unsigned long guest_cr3; 2992 u64 eptp; 2993 2994 guest_cr3 = cr3; 2995 if (enable_ept) { 2996 eptp = construct_eptp(vcpu, cr3); 2997 vmcs_write64(EPT_POINTER, eptp); 2998 2999 if (kvm_x86_ops.tlb_remote_flush) { 3000 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3001 to_vmx(vcpu)->ept_pointer = eptp; 3002 to_kvm_vmx(kvm)->ept_pointers_match 3003 = EPT_POINTERS_CHECK; 3004 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 3005 } 3006 3007 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */ 3008 if (is_guest_mode(vcpu)) 3009 update_guest_cr3 = false; 3010 else if (!enable_unrestricted_guest && !is_paging(vcpu)) 3011 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 3012 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 3013 guest_cr3 = vcpu->arch.cr3; 3014 else /* vmcs01.GUEST_CR3 is already up-to-date. */ 3015 update_guest_cr3 = false; 3016 ept_load_pdptrs(vcpu); 3017 } 3018 3019 if (update_guest_cr3) 3020 vmcs_writel(GUEST_CR3, guest_cr3); 3021 } 3022 3023 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 3024 { 3025 struct vcpu_vmx *vmx = to_vmx(vcpu); 3026 /* 3027 * Pass through host's Machine Check Enable value to hw_cr4, which 3028 * is in force while we are in guest mode. Do not let guests control 3029 * this bit, even if host CR4.MCE == 0. 3030 */ 3031 unsigned long hw_cr4; 3032 3033 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 3034 if (enable_unrestricted_guest) 3035 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 3036 else if (vmx->rmode.vm86_active) 3037 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 3038 else 3039 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 3040 3041 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 3042 if (cr4 & X86_CR4_UMIP) { 3043 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); 3044 hw_cr4 &= ~X86_CR4_UMIP; 3045 } else if (!is_guest_mode(vcpu) || 3046 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { 3047 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); 3048 } 3049 } 3050 3051 if (cr4 & X86_CR4_VMXE) { 3052 /* 3053 * To use VMXON (and later other VMX instructions), a guest 3054 * must first be able to turn on cr4.VMXE (see handle_vmon()). 3055 * So basically the check on whether to allow nested VMX 3056 * is here. We operate under the default treatment of SMM, 3057 * so VMX cannot be enabled under SMM. 3058 */ 3059 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 3060 return 1; 3061 } 3062 3063 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 3064 return 1; 3065 3066 vcpu->arch.cr4 = cr4; 3067 3068 if (!enable_unrestricted_guest) { 3069 if (enable_ept) { 3070 if (!is_paging(vcpu)) { 3071 hw_cr4 &= ~X86_CR4_PAE; 3072 hw_cr4 |= X86_CR4_PSE; 3073 } else if (!(cr4 & X86_CR4_PAE)) { 3074 hw_cr4 &= ~X86_CR4_PAE; 3075 } 3076 } 3077 3078 /* 3079 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 3080 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 3081 * to be manually disabled when guest switches to non-paging 3082 * mode. 3083 * 3084 * If !enable_unrestricted_guest, the CPU is always running 3085 * with CR0.PG=1 and CR4 needs to be modified. 3086 * If enable_unrestricted_guest, the CPU automatically 3087 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 3088 */ 3089 if (!is_paging(vcpu)) 3090 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 3091 } 3092 3093 vmcs_writel(CR4_READ_SHADOW, cr4); 3094 vmcs_writel(GUEST_CR4, hw_cr4); 3095 return 0; 3096 } 3097 3098 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3099 { 3100 struct vcpu_vmx *vmx = to_vmx(vcpu); 3101 u32 ar; 3102 3103 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3104 *var = vmx->rmode.segs[seg]; 3105 if (seg == VCPU_SREG_TR 3106 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 3107 return; 3108 var->base = vmx_read_guest_seg_base(vmx, seg); 3109 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3110 return; 3111 } 3112 var->base = vmx_read_guest_seg_base(vmx, seg); 3113 var->limit = vmx_read_guest_seg_limit(vmx, seg); 3114 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3115 ar = vmx_read_guest_seg_ar(vmx, seg); 3116 var->unusable = (ar >> 16) & 1; 3117 var->type = ar & 15; 3118 var->s = (ar >> 4) & 1; 3119 var->dpl = (ar >> 5) & 3; 3120 /* 3121 * Some userspaces do not preserve unusable property. Since usable 3122 * segment has to be present according to VMX spec we can use present 3123 * property to amend userspace bug by making unusable segment always 3124 * nonpresent. vmx_segment_access_rights() already marks nonpresent 3125 * segment as unusable. 3126 */ 3127 var->present = !var->unusable; 3128 var->avl = (ar >> 12) & 1; 3129 var->l = (ar >> 13) & 1; 3130 var->db = (ar >> 14) & 1; 3131 var->g = (ar >> 15) & 1; 3132 } 3133 3134 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3135 { 3136 struct kvm_segment s; 3137 3138 if (to_vmx(vcpu)->rmode.vm86_active) { 3139 vmx_get_segment(vcpu, &s, seg); 3140 return s.base; 3141 } 3142 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3143 } 3144 3145 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3146 { 3147 struct vcpu_vmx *vmx = to_vmx(vcpu); 3148 3149 if (unlikely(vmx->rmode.vm86_active)) 3150 return 0; 3151 else { 3152 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3153 return VMX_AR_DPL(ar); 3154 } 3155 } 3156 3157 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3158 { 3159 u32 ar; 3160 3161 if (var->unusable || !var->present) 3162 ar = 1 << 16; 3163 else { 3164 ar = var->type & 15; 3165 ar |= (var->s & 1) << 4; 3166 ar |= (var->dpl & 3) << 5; 3167 ar |= (var->present & 1) << 7; 3168 ar |= (var->avl & 1) << 12; 3169 ar |= (var->l & 1) << 13; 3170 ar |= (var->db & 1) << 14; 3171 ar |= (var->g & 1) << 15; 3172 } 3173 3174 return ar; 3175 } 3176 3177 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3178 { 3179 struct vcpu_vmx *vmx = to_vmx(vcpu); 3180 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3181 3182 vmx_segment_cache_clear(vmx); 3183 3184 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3185 vmx->rmode.segs[seg] = *var; 3186 if (seg == VCPU_SREG_TR) 3187 vmcs_write16(sf->selector, var->selector); 3188 else if (var->s) 3189 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3190 goto out; 3191 } 3192 3193 vmcs_writel(sf->base, var->base); 3194 vmcs_write32(sf->limit, var->limit); 3195 vmcs_write16(sf->selector, var->selector); 3196 3197 /* 3198 * Fix the "Accessed" bit in AR field of segment registers for older 3199 * qemu binaries. 3200 * IA32 arch specifies that at the time of processor reset the 3201 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3202 * is setting it to 0 in the userland code. This causes invalid guest 3203 * state vmexit when "unrestricted guest" mode is turned on. 3204 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3205 * tree. Newer qemu binaries with that qemu fix would not need this 3206 * kvm hack. 3207 */ 3208 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) 3209 var->type |= 0x1; /* Accessed */ 3210 3211 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3212 3213 out: 3214 vmx->emulation_required = emulation_required(vcpu); 3215 } 3216 3217 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3218 { 3219 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3220 3221 *db = (ar >> 14) & 1; 3222 *l = (ar >> 13) & 1; 3223 } 3224 3225 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3226 { 3227 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3228 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3229 } 3230 3231 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3232 { 3233 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3234 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3235 } 3236 3237 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3238 { 3239 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3240 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3241 } 3242 3243 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3244 { 3245 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3246 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3247 } 3248 3249 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3250 { 3251 struct kvm_segment var; 3252 u32 ar; 3253 3254 vmx_get_segment(vcpu, &var, seg); 3255 var.dpl = 0x3; 3256 if (seg == VCPU_SREG_CS) 3257 var.type = 0x3; 3258 ar = vmx_segment_access_rights(&var); 3259 3260 if (var.base != (var.selector << 4)) 3261 return false; 3262 if (var.limit != 0xffff) 3263 return false; 3264 if (ar != 0xf3) 3265 return false; 3266 3267 return true; 3268 } 3269 3270 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3271 { 3272 struct kvm_segment cs; 3273 unsigned int cs_rpl; 3274 3275 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3276 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3277 3278 if (cs.unusable) 3279 return false; 3280 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3281 return false; 3282 if (!cs.s) 3283 return false; 3284 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3285 if (cs.dpl > cs_rpl) 3286 return false; 3287 } else { 3288 if (cs.dpl != cs_rpl) 3289 return false; 3290 } 3291 if (!cs.present) 3292 return false; 3293 3294 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3295 return true; 3296 } 3297 3298 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3299 { 3300 struct kvm_segment ss; 3301 unsigned int ss_rpl; 3302 3303 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3304 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3305 3306 if (ss.unusable) 3307 return true; 3308 if (ss.type != 3 && ss.type != 7) 3309 return false; 3310 if (!ss.s) 3311 return false; 3312 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3313 return false; 3314 if (!ss.present) 3315 return false; 3316 3317 return true; 3318 } 3319 3320 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3321 { 3322 struct kvm_segment var; 3323 unsigned int rpl; 3324 3325 vmx_get_segment(vcpu, &var, seg); 3326 rpl = var.selector & SEGMENT_RPL_MASK; 3327 3328 if (var.unusable) 3329 return true; 3330 if (!var.s) 3331 return false; 3332 if (!var.present) 3333 return false; 3334 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3335 if (var.dpl < rpl) /* DPL < RPL */ 3336 return false; 3337 } 3338 3339 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3340 * rights flags 3341 */ 3342 return true; 3343 } 3344 3345 static bool tr_valid(struct kvm_vcpu *vcpu) 3346 { 3347 struct kvm_segment tr; 3348 3349 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3350 3351 if (tr.unusable) 3352 return false; 3353 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3354 return false; 3355 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3356 return false; 3357 if (!tr.present) 3358 return false; 3359 3360 return true; 3361 } 3362 3363 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3364 { 3365 struct kvm_segment ldtr; 3366 3367 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3368 3369 if (ldtr.unusable) 3370 return true; 3371 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3372 return false; 3373 if (ldtr.type != 2) 3374 return false; 3375 if (!ldtr.present) 3376 return false; 3377 3378 return true; 3379 } 3380 3381 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3382 { 3383 struct kvm_segment cs, ss; 3384 3385 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3386 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3387 3388 return ((cs.selector & SEGMENT_RPL_MASK) == 3389 (ss.selector & SEGMENT_RPL_MASK)); 3390 } 3391 3392 /* 3393 * Check if guest state is valid. Returns true if valid, false if 3394 * not. 3395 * We assume that registers are always usable 3396 */ 3397 static bool guest_state_valid(struct kvm_vcpu *vcpu) 3398 { 3399 if (enable_unrestricted_guest) 3400 return true; 3401 3402 /* real mode guest state checks */ 3403 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3404 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3405 return false; 3406 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3407 return false; 3408 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3409 return false; 3410 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3411 return false; 3412 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3413 return false; 3414 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3415 return false; 3416 } else { 3417 /* protected mode guest state checks */ 3418 if (!cs_ss_rpl_check(vcpu)) 3419 return false; 3420 if (!code_segment_valid(vcpu)) 3421 return false; 3422 if (!stack_segment_valid(vcpu)) 3423 return false; 3424 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3425 return false; 3426 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3427 return false; 3428 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3429 return false; 3430 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3431 return false; 3432 if (!tr_valid(vcpu)) 3433 return false; 3434 if (!ldtr_valid(vcpu)) 3435 return false; 3436 } 3437 /* TODO: 3438 * - Add checks on RIP 3439 * - Add checks on RFLAGS 3440 */ 3441 3442 return true; 3443 } 3444 3445 static int init_rmode_tss(struct kvm *kvm) 3446 { 3447 gfn_t fn; 3448 u16 data = 0; 3449 int idx, r; 3450 3451 idx = srcu_read_lock(&kvm->srcu); 3452 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3453 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3454 if (r < 0) 3455 goto out; 3456 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3457 r = kvm_write_guest_page(kvm, fn++, &data, 3458 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3459 if (r < 0) 3460 goto out; 3461 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3462 if (r < 0) 3463 goto out; 3464 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3465 if (r < 0) 3466 goto out; 3467 data = ~0; 3468 r = kvm_write_guest_page(kvm, fn, &data, 3469 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3470 sizeof(u8)); 3471 out: 3472 srcu_read_unlock(&kvm->srcu, idx); 3473 return r; 3474 } 3475 3476 static int init_rmode_identity_map(struct kvm *kvm) 3477 { 3478 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3479 int i, r = 0; 3480 kvm_pfn_t identity_map_pfn; 3481 u32 tmp; 3482 3483 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3484 mutex_lock(&kvm->slots_lock); 3485 3486 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3487 goto out; 3488 3489 if (!kvm_vmx->ept_identity_map_addr) 3490 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3491 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3492 3493 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3494 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3495 if (r < 0) 3496 goto out; 3497 3498 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3499 if (r < 0) 3500 goto out; 3501 /* Set up identity-mapping pagetable for EPT in real mode */ 3502 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3503 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3504 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3505 r = kvm_write_guest_page(kvm, identity_map_pfn, 3506 &tmp, i * sizeof(tmp), sizeof(tmp)); 3507 if (r < 0) 3508 goto out; 3509 } 3510 kvm_vmx->ept_identity_pagetable_done = true; 3511 3512 out: 3513 mutex_unlock(&kvm->slots_lock); 3514 return r; 3515 } 3516 3517 static void seg_setup(int seg) 3518 { 3519 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3520 unsigned int ar; 3521 3522 vmcs_write16(sf->selector, 0); 3523 vmcs_writel(sf->base, 0); 3524 vmcs_write32(sf->limit, 0xffff); 3525 ar = 0x93; 3526 if (seg == VCPU_SREG_CS) 3527 ar |= 0x08; /* code segment */ 3528 3529 vmcs_write32(sf->ar_bytes, ar); 3530 } 3531 3532 static int alloc_apic_access_page(struct kvm *kvm) 3533 { 3534 struct page *page; 3535 int r = 0; 3536 3537 mutex_lock(&kvm->slots_lock); 3538 if (kvm->arch.apic_access_page_done) 3539 goto out; 3540 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3541 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3542 if (r) 3543 goto out; 3544 3545 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3546 if (is_error_page(page)) { 3547 r = -EFAULT; 3548 goto out; 3549 } 3550 3551 /* 3552 * Do not pin the page in memory, so that memory hot-unplug 3553 * is able to migrate it. 3554 */ 3555 put_page(page); 3556 kvm->arch.apic_access_page_done = true; 3557 out: 3558 mutex_unlock(&kvm->slots_lock); 3559 return r; 3560 } 3561 3562 int allocate_vpid(void) 3563 { 3564 int vpid; 3565 3566 if (!enable_vpid) 3567 return 0; 3568 spin_lock(&vmx_vpid_lock); 3569 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3570 if (vpid < VMX_NR_VPIDS) 3571 __set_bit(vpid, vmx_vpid_bitmap); 3572 else 3573 vpid = 0; 3574 spin_unlock(&vmx_vpid_lock); 3575 return vpid; 3576 } 3577 3578 void free_vpid(int vpid) 3579 { 3580 if (!enable_vpid || vpid == 0) 3581 return; 3582 spin_lock(&vmx_vpid_lock); 3583 __clear_bit(vpid, vmx_vpid_bitmap); 3584 spin_unlock(&vmx_vpid_lock); 3585 } 3586 3587 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 3588 u32 msr, int type) 3589 { 3590 int f = sizeof(unsigned long); 3591 3592 if (!cpu_has_vmx_msr_bitmap()) 3593 return; 3594 3595 if (static_branch_unlikely(&enable_evmcs)) 3596 evmcs_touch_msr_bitmap(); 3597 3598 /* 3599 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3600 * have the write-low and read-high bitmap offsets the wrong way round. 3601 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3602 */ 3603 if (msr <= 0x1fff) { 3604 if (type & MSR_TYPE_R) 3605 /* read-low */ 3606 __clear_bit(msr, msr_bitmap + 0x000 / f); 3607 3608 if (type & MSR_TYPE_W) 3609 /* write-low */ 3610 __clear_bit(msr, msr_bitmap + 0x800 / f); 3611 3612 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3613 msr &= 0x1fff; 3614 if (type & MSR_TYPE_R) 3615 /* read-high */ 3616 __clear_bit(msr, msr_bitmap + 0x400 / f); 3617 3618 if (type & MSR_TYPE_W) 3619 /* write-high */ 3620 __clear_bit(msr, msr_bitmap + 0xc00 / f); 3621 3622 } 3623 } 3624 3625 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, 3626 u32 msr, int type) 3627 { 3628 int f = sizeof(unsigned long); 3629 3630 if (!cpu_has_vmx_msr_bitmap()) 3631 return; 3632 3633 if (static_branch_unlikely(&enable_evmcs)) 3634 evmcs_touch_msr_bitmap(); 3635 3636 /* 3637 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3638 * have the write-low and read-high bitmap offsets the wrong way round. 3639 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3640 */ 3641 if (msr <= 0x1fff) { 3642 if (type & MSR_TYPE_R) 3643 /* read-low */ 3644 __set_bit(msr, msr_bitmap + 0x000 / f); 3645 3646 if (type & MSR_TYPE_W) 3647 /* write-low */ 3648 __set_bit(msr, msr_bitmap + 0x800 / f); 3649 3650 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3651 msr &= 0x1fff; 3652 if (type & MSR_TYPE_R) 3653 /* read-high */ 3654 __set_bit(msr, msr_bitmap + 0x400 / f); 3655 3656 if (type & MSR_TYPE_W) 3657 /* write-high */ 3658 __set_bit(msr, msr_bitmap + 0xc00 / f); 3659 3660 } 3661 } 3662 3663 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, 3664 u32 msr, int type, bool value) 3665 { 3666 if (value) 3667 vmx_enable_intercept_for_msr(msr_bitmap, msr, type); 3668 else 3669 vmx_disable_intercept_for_msr(msr_bitmap, msr, type); 3670 } 3671 3672 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3673 { 3674 u8 mode = 0; 3675 3676 if (cpu_has_secondary_exec_ctrls() && 3677 (secondary_exec_controls_get(to_vmx(vcpu)) & 3678 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3679 mode |= MSR_BITMAP_MODE_X2APIC; 3680 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3681 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3682 } 3683 3684 return mode; 3685 } 3686 3687 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, 3688 u8 mode) 3689 { 3690 int msr; 3691 3692 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3693 unsigned word = msr / BITS_PER_LONG; 3694 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3695 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 3696 } 3697 3698 if (mode & MSR_BITMAP_MODE_X2APIC) { 3699 /* 3700 * TPR reads and writes can be virtualized even if virtual interrupt 3701 * delivery is not in use. 3702 */ 3703 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); 3704 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3705 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); 3706 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3707 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3708 } 3709 } 3710 } 3711 3712 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3713 { 3714 struct vcpu_vmx *vmx = to_vmx(vcpu); 3715 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3716 u8 mode = vmx_msr_bitmap_mode(vcpu); 3717 u8 changed = mode ^ vmx->msr_bitmap_mode; 3718 3719 if (!changed) 3720 return; 3721 3722 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3723 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); 3724 3725 vmx->msr_bitmap_mode = mode; 3726 } 3727 3728 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx) 3729 { 3730 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3731 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3732 u32 i; 3733 3734 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, 3735 MSR_TYPE_RW, flag); 3736 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, 3737 MSR_TYPE_RW, flag); 3738 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, 3739 MSR_TYPE_RW, flag); 3740 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, 3741 MSR_TYPE_RW, flag); 3742 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3743 vmx_set_intercept_for_msr(msr_bitmap, 3744 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3745 vmx_set_intercept_for_msr(msr_bitmap, 3746 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3747 } 3748 } 3749 3750 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3751 { 3752 struct vcpu_vmx *vmx = to_vmx(vcpu); 3753 void *vapic_page; 3754 u32 vppr; 3755 int rvi; 3756 3757 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3758 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3759 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) 3760 return false; 3761 3762 rvi = vmx_get_rvi(); 3763 3764 vapic_page = vmx->nested.virtual_apic_map.hva; 3765 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3766 3767 return ((rvi & 0xf0) > (vppr & 0xf0)); 3768 } 3769 3770 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3771 bool nested) 3772 { 3773 #ifdef CONFIG_SMP 3774 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3775 3776 if (vcpu->mode == IN_GUEST_MODE) { 3777 /* 3778 * The vector of interrupt to be delivered to vcpu had 3779 * been set in PIR before this function. 3780 * 3781 * Following cases will be reached in this block, and 3782 * we always send a notification event in all cases as 3783 * explained below. 3784 * 3785 * Case 1: vcpu keeps in non-root mode. Sending a 3786 * notification event posts the interrupt to vcpu. 3787 * 3788 * Case 2: vcpu exits to root mode and is still 3789 * runnable. PIR will be synced to vIRR before the 3790 * next vcpu entry. Sending a notification event in 3791 * this case has no effect, as vcpu is not in root 3792 * mode. 3793 * 3794 * Case 3: vcpu exits to root mode and is blocked. 3795 * vcpu_block() has already synced PIR to vIRR and 3796 * never blocks vcpu if vIRR is not cleared. Therefore, 3797 * a blocked vcpu here does not wait for any requested 3798 * interrupts in PIR, and sending a notification event 3799 * which has no effect is safe here. 3800 */ 3801 3802 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3803 return true; 3804 } 3805 #endif 3806 return false; 3807 } 3808 3809 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3810 int vector) 3811 { 3812 struct vcpu_vmx *vmx = to_vmx(vcpu); 3813 3814 if (is_guest_mode(vcpu) && 3815 vector == vmx->nested.posted_intr_nv) { 3816 /* 3817 * If a posted intr is not recognized by hardware, 3818 * we will accomplish it in the next vmentry. 3819 */ 3820 vmx->nested.pi_pending = true; 3821 kvm_make_request(KVM_REQ_EVENT, vcpu); 3822 /* the PIR and ON have been set by L1. */ 3823 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3824 kvm_vcpu_kick(vcpu); 3825 return 0; 3826 } 3827 return -1; 3828 } 3829 /* 3830 * Send interrupt to vcpu via posted interrupt way. 3831 * 1. If target vcpu is running(non-root mode), send posted interrupt 3832 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3833 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3834 * interrupt from PIR in next vmentry. 3835 */ 3836 static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3837 { 3838 struct vcpu_vmx *vmx = to_vmx(vcpu); 3839 int r; 3840 3841 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3842 if (!r) 3843 return 0; 3844 3845 if (!vcpu->arch.apicv_active) 3846 return -1; 3847 3848 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3849 return 0; 3850 3851 /* If a previous notification has sent the IPI, nothing to do. */ 3852 if (pi_test_and_set_on(&vmx->pi_desc)) 3853 return 0; 3854 3855 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 3856 kvm_vcpu_kick(vcpu); 3857 3858 return 0; 3859 } 3860 3861 /* 3862 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 3863 * will not change in the lifetime of the guest. 3864 * Note that host-state that does change is set elsewhere. E.g., host-state 3865 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 3866 */ 3867 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 3868 { 3869 u32 low32, high32; 3870 unsigned long tmpl; 3871 unsigned long cr0, cr3, cr4; 3872 3873 cr0 = read_cr0(); 3874 WARN_ON(cr0 & X86_CR0_TS); 3875 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 3876 3877 /* 3878 * Save the most likely value for this task's CR3 in the VMCS. 3879 * We can't use __get_current_cr3_fast() because we're not atomic. 3880 */ 3881 cr3 = __read_cr3(); 3882 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 3883 vmx->loaded_vmcs->host_state.cr3 = cr3; 3884 3885 /* Save the most likely value for this task's CR4 in the VMCS. */ 3886 cr4 = cr4_read_shadow(); 3887 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 3888 vmx->loaded_vmcs->host_state.cr4 = cr4; 3889 3890 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 3891 #ifdef CONFIG_X86_64 3892 /* 3893 * Load null selectors, so we can avoid reloading them in 3894 * vmx_prepare_switch_to_host(), in case userspace uses 3895 * the null selectors too (the expected case). 3896 */ 3897 vmcs_write16(HOST_DS_SELECTOR, 0); 3898 vmcs_write16(HOST_ES_SELECTOR, 0); 3899 #else 3900 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3901 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3902 #endif 3903 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3904 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 3905 3906 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ 3907 3908 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 3909 3910 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 3911 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 3912 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 3913 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 3914 3915 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 3916 rdmsr(MSR_IA32_CR_PAT, low32, high32); 3917 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 3918 } 3919 3920 if (cpu_has_load_ia32_efer()) 3921 vmcs_write64(HOST_IA32_EFER, host_efer); 3922 } 3923 3924 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 3925 { 3926 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; 3927 if (enable_ept) 3928 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; 3929 if (is_guest_mode(&vmx->vcpu)) 3930 vmx->vcpu.arch.cr4_guest_owned_bits &= 3931 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; 3932 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); 3933 } 3934 3935 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 3936 { 3937 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 3938 3939 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 3940 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 3941 3942 if (!enable_vnmi) 3943 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 3944 3945 if (!enable_preemption_timer) 3946 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 3947 3948 return pin_based_exec_ctrl; 3949 } 3950 3951 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 3952 { 3953 struct vcpu_vmx *vmx = to_vmx(vcpu); 3954 3955 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 3956 if (cpu_has_secondary_exec_ctrls()) { 3957 if (kvm_vcpu_apicv_active(vcpu)) 3958 secondary_exec_controls_setbit(vmx, 3959 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3960 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3961 else 3962 secondary_exec_controls_clearbit(vmx, 3963 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3964 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3965 } 3966 3967 if (cpu_has_vmx_msr_bitmap()) 3968 vmx_update_msr_bitmap(vcpu); 3969 } 3970 3971 u32 vmx_exec_control(struct vcpu_vmx *vmx) 3972 { 3973 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 3974 3975 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 3976 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 3977 3978 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 3979 exec_control &= ~CPU_BASED_TPR_SHADOW; 3980 #ifdef CONFIG_X86_64 3981 exec_control |= CPU_BASED_CR8_STORE_EXITING | 3982 CPU_BASED_CR8_LOAD_EXITING; 3983 #endif 3984 } 3985 if (!enable_ept) 3986 exec_control |= CPU_BASED_CR3_STORE_EXITING | 3987 CPU_BASED_CR3_LOAD_EXITING | 3988 CPU_BASED_INVLPG_EXITING; 3989 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 3990 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 3991 CPU_BASED_MONITOR_EXITING); 3992 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 3993 exec_control &= ~CPU_BASED_HLT_EXITING; 3994 return exec_control; 3995 } 3996 3997 3998 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 3999 { 4000 struct kvm_vcpu *vcpu = &vmx->vcpu; 4001 4002 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 4003 4004 if (vmx_pt_mode_is_system()) 4005 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 4006 if (!cpu_need_virtualize_apic_accesses(vcpu)) 4007 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 4008 if (vmx->vpid == 0) 4009 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 4010 if (!enable_ept) { 4011 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 4012 enable_unrestricted_guest = 0; 4013 } 4014 if (!enable_unrestricted_guest) 4015 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 4016 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 4017 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 4018 if (!kvm_vcpu_apicv_active(vcpu)) 4019 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 4020 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 4021 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 4022 4023 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 4024 * in vmx_set_cr4. */ 4025 exec_control &= ~SECONDARY_EXEC_DESC; 4026 4027 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 4028 (handle_vmptrld). 4029 We can NOT enable shadow_vmcs here because we don't have yet 4030 a current VMCS12 4031 */ 4032 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 4033 4034 if (!enable_pml) 4035 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 4036 4037 if (vmx_xsaves_supported()) { 4038 /* Exposing XSAVES only when XSAVE is exposed */ 4039 bool xsaves_enabled = 4040 boot_cpu_has(X86_FEATURE_XSAVE) && 4041 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 4042 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 4043 4044 vcpu->arch.xsaves_enabled = xsaves_enabled; 4045 4046 if (!xsaves_enabled) 4047 exec_control &= ~SECONDARY_EXEC_XSAVES; 4048 4049 if (nested) { 4050 if (xsaves_enabled) 4051 vmx->nested.msrs.secondary_ctls_high |= 4052 SECONDARY_EXEC_XSAVES; 4053 else 4054 vmx->nested.msrs.secondary_ctls_high &= 4055 ~SECONDARY_EXEC_XSAVES; 4056 } 4057 } 4058 4059 if (cpu_has_vmx_rdtscp()) { 4060 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); 4061 if (!rdtscp_enabled) 4062 exec_control &= ~SECONDARY_EXEC_RDTSCP; 4063 4064 if (nested) { 4065 if (rdtscp_enabled) 4066 vmx->nested.msrs.secondary_ctls_high |= 4067 SECONDARY_EXEC_RDTSCP; 4068 else 4069 vmx->nested.msrs.secondary_ctls_high &= 4070 ~SECONDARY_EXEC_RDTSCP; 4071 } 4072 } 4073 4074 if (cpu_has_vmx_invpcid()) { 4075 /* Exposing INVPCID only when PCID is exposed */ 4076 bool invpcid_enabled = 4077 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && 4078 guest_cpuid_has(vcpu, X86_FEATURE_PCID); 4079 4080 if (!invpcid_enabled) { 4081 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 4082 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 4083 } 4084 4085 if (nested) { 4086 if (invpcid_enabled) 4087 vmx->nested.msrs.secondary_ctls_high |= 4088 SECONDARY_EXEC_ENABLE_INVPCID; 4089 else 4090 vmx->nested.msrs.secondary_ctls_high &= 4091 ~SECONDARY_EXEC_ENABLE_INVPCID; 4092 } 4093 } 4094 4095 if (vmx_rdrand_supported()) { 4096 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); 4097 if (rdrand_enabled) 4098 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; 4099 4100 if (nested) { 4101 if (rdrand_enabled) 4102 vmx->nested.msrs.secondary_ctls_high |= 4103 SECONDARY_EXEC_RDRAND_EXITING; 4104 else 4105 vmx->nested.msrs.secondary_ctls_high &= 4106 ~SECONDARY_EXEC_RDRAND_EXITING; 4107 } 4108 } 4109 4110 if (vmx_rdseed_supported()) { 4111 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); 4112 if (rdseed_enabled) 4113 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; 4114 4115 if (nested) { 4116 if (rdseed_enabled) 4117 vmx->nested.msrs.secondary_ctls_high |= 4118 SECONDARY_EXEC_RDSEED_EXITING; 4119 else 4120 vmx->nested.msrs.secondary_ctls_high &= 4121 ~SECONDARY_EXEC_RDSEED_EXITING; 4122 } 4123 } 4124 4125 if (vmx_waitpkg_supported()) { 4126 bool waitpkg_enabled = 4127 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG); 4128 4129 if (!waitpkg_enabled) 4130 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4131 4132 if (nested) { 4133 if (waitpkg_enabled) 4134 vmx->nested.msrs.secondary_ctls_high |= 4135 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4136 else 4137 vmx->nested.msrs.secondary_ctls_high &= 4138 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4139 } 4140 } 4141 4142 vmx->secondary_exec_control = exec_control; 4143 } 4144 4145 static void ept_set_mmio_spte_mask(void) 4146 { 4147 /* 4148 * EPT Misconfigurations can be generated if the value of bits 2:0 4149 * of an EPT paging-structure entry is 110b (write/execute). 4150 */ 4151 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, 4152 VMX_EPT_MISCONFIG_WX_VALUE, 0); 4153 } 4154 4155 #define VMX_XSS_EXIT_BITMAP 0 4156 4157 /* 4158 * Noting that the initialization of Guest-state Area of VMCS is in 4159 * vmx_vcpu_reset(). 4160 */ 4161 static void init_vmcs(struct vcpu_vmx *vmx) 4162 { 4163 if (nested) 4164 nested_vmx_set_vmcs_shadowing_bitmap(); 4165 4166 if (cpu_has_vmx_msr_bitmap()) 4167 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4168 4169 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4170 4171 /* Control */ 4172 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4173 4174 exec_controls_set(vmx, vmx_exec_control(vmx)); 4175 4176 if (cpu_has_secondary_exec_ctrls()) { 4177 vmx_compute_secondary_exec_control(vmx); 4178 secondary_exec_controls_set(vmx, vmx->secondary_exec_control); 4179 } 4180 4181 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4182 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4183 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4184 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4185 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4186 4187 vmcs_write16(GUEST_INTR_STATUS, 0); 4188 4189 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4190 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4191 } 4192 4193 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4194 vmcs_write32(PLE_GAP, ple_gap); 4195 vmx->ple_window = ple_window; 4196 vmx->ple_window_dirty = true; 4197 } 4198 4199 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4200 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4201 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4202 4203 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4204 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4205 vmx_set_constant_host_state(vmx); 4206 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4207 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4208 4209 if (cpu_has_vmx_vmfunc()) 4210 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4211 4212 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4213 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4214 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4215 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4216 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4217 4218 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4219 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4220 4221 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); 4222 4223 /* 22.2.1, 20.8.1 */ 4224 vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); 4225 4226 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; 4227 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); 4228 4229 set_cr4_guest_host_mask(vmx); 4230 4231 if (vmx->vpid != 0) 4232 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4233 4234 if (vmx_xsaves_supported()) 4235 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4236 4237 if (enable_pml) { 4238 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4239 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4240 } 4241 4242 if (cpu_has_vmx_encls_vmexit()) 4243 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4244 4245 if (vmx_pt_mode_is_host_guest()) { 4246 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4247 /* Bit[6~0] are forced to 1, writes are ignored. */ 4248 vmx->pt_desc.guest.output_mask = 0x7F; 4249 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4250 } 4251 } 4252 4253 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4254 { 4255 struct vcpu_vmx *vmx = to_vmx(vcpu); 4256 struct msr_data apic_base_msr; 4257 u64 cr0; 4258 4259 vmx->rmode.vm86_active = 0; 4260 vmx->spec_ctrl = 0; 4261 4262 vmx->msr_ia32_umwait_control = 0; 4263 4264 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4265 vmx->hv_deadline_tsc = -1; 4266 kvm_set_cr8(vcpu, 0); 4267 4268 if (!init_event) { 4269 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4270 MSR_IA32_APICBASE_ENABLE; 4271 if (kvm_vcpu_is_reset_bsp(vcpu)) 4272 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4273 apic_base_msr.host_initiated = true; 4274 kvm_set_apic_base(vcpu, &apic_base_msr); 4275 } 4276 4277 vmx_segment_cache_clear(vmx); 4278 4279 seg_setup(VCPU_SREG_CS); 4280 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4281 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4282 4283 seg_setup(VCPU_SREG_DS); 4284 seg_setup(VCPU_SREG_ES); 4285 seg_setup(VCPU_SREG_FS); 4286 seg_setup(VCPU_SREG_GS); 4287 seg_setup(VCPU_SREG_SS); 4288 4289 vmcs_write16(GUEST_TR_SELECTOR, 0); 4290 vmcs_writel(GUEST_TR_BASE, 0); 4291 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4292 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4293 4294 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4295 vmcs_writel(GUEST_LDTR_BASE, 0); 4296 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4297 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4298 4299 if (!init_event) { 4300 vmcs_write32(GUEST_SYSENTER_CS, 0); 4301 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4302 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4303 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4304 } 4305 4306 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4307 kvm_rip_write(vcpu, 0xfff0); 4308 4309 vmcs_writel(GUEST_GDTR_BASE, 0); 4310 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4311 4312 vmcs_writel(GUEST_IDTR_BASE, 0); 4313 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4314 4315 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4316 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4317 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4318 if (kvm_mpx_supported()) 4319 vmcs_write64(GUEST_BNDCFGS, 0); 4320 4321 setup_msrs(vmx); 4322 4323 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4324 4325 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4326 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4327 if (cpu_need_tpr_shadow(vcpu)) 4328 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4329 __pa(vcpu->arch.apic->regs)); 4330 vmcs_write32(TPR_THRESHOLD, 0); 4331 } 4332 4333 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4334 4335 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4336 vmx->vcpu.arch.cr0 = cr0; 4337 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4338 vmx_set_cr4(vcpu, 0); 4339 vmx_set_efer(vcpu, 0); 4340 4341 update_exception_bitmap(vcpu); 4342 4343 vpid_sync_context(vmx->vpid); 4344 if (init_event) 4345 vmx_clear_hlt(vcpu); 4346 } 4347 4348 static void enable_irq_window(struct kvm_vcpu *vcpu) 4349 { 4350 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4351 } 4352 4353 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4354 { 4355 if (!enable_vnmi || 4356 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4357 enable_irq_window(vcpu); 4358 return; 4359 } 4360 4361 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 4362 } 4363 4364 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4365 { 4366 struct vcpu_vmx *vmx = to_vmx(vcpu); 4367 uint32_t intr; 4368 int irq = vcpu->arch.interrupt.nr; 4369 4370 trace_kvm_inj_virq(irq); 4371 4372 ++vcpu->stat.irq_injections; 4373 if (vmx->rmode.vm86_active) { 4374 int inc_eip = 0; 4375 if (vcpu->arch.interrupt.soft) 4376 inc_eip = vcpu->arch.event_exit_inst_len; 4377 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); 4378 return; 4379 } 4380 intr = irq | INTR_INFO_VALID_MASK; 4381 if (vcpu->arch.interrupt.soft) { 4382 intr |= INTR_TYPE_SOFT_INTR; 4383 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4384 vmx->vcpu.arch.event_exit_inst_len); 4385 } else 4386 intr |= INTR_TYPE_EXT_INTR; 4387 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4388 4389 vmx_clear_hlt(vcpu); 4390 } 4391 4392 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4393 { 4394 struct vcpu_vmx *vmx = to_vmx(vcpu); 4395 4396 if (!enable_vnmi) { 4397 /* 4398 * Tracking the NMI-blocked state in software is built upon 4399 * finding the next open IRQ window. This, in turn, depends on 4400 * well-behaving guests: They have to keep IRQs disabled at 4401 * least as long as the NMI handler runs. Otherwise we may 4402 * cause NMI nesting, maybe breaking the guest. But as this is 4403 * highly unlikely, we can live with the residual risk. 4404 */ 4405 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4406 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4407 } 4408 4409 ++vcpu->stat.nmi_injections; 4410 vmx->loaded_vmcs->nmi_known_unmasked = false; 4411 4412 if (vmx->rmode.vm86_active) { 4413 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); 4414 return; 4415 } 4416 4417 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4418 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4419 4420 vmx_clear_hlt(vcpu); 4421 } 4422 4423 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4424 { 4425 struct vcpu_vmx *vmx = to_vmx(vcpu); 4426 bool masked; 4427 4428 if (!enable_vnmi) 4429 return vmx->loaded_vmcs->soft_vnmi_blocked; 4430 if (vmx->loaded_vmcs->nmi_known_unmasked) 4431 return false; 4432 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4433 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4434 return masked; 4435 } 4436 4437 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4438 { 4439 struct vcpu_vmx *vmx = to_vmx(vcpu); 4440 4441 if (!enable_vnmi) { 4442 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4443 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4444 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4445 } 4446 } else { 4447 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4448 if (masked) 4449 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4450 GUEST_INTR_STATE_NMI); 4451 else 4452 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4453 GUEST_INTR_STATE_NMI); 4454 } 4455 } 4456 4457 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) 4458 { 4459 if (to_vmx(vcpu)->nested.nested_run_pending) 4460 return 0; 4461 4462 if (!enable_vnmi && 4463 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4464 return 0; 4465 4466 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4467 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI 4468 | GUEST_INTR_STATE_NMI)); 4469 } 4470 4471 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) 4472 { 4473 if (to_vmx(vcpu)->nested.nested_run_pending) 4474 return false; 4475 4476 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) 4477 return true; 4478 4479 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && 4480 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4481 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4482 } 4483 4484 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4485 { 4486 int ret; 4487 4488 if (enable_unrestricted_guest) 4489 return 0; 4490 4491 mutex_lock(&kvm->slots_lock); 4492 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4493 PAGE_SIZE * 3); 4494 mutex_unlock(&kvm->slots_lock); 4495 4496 if (ret) 4497 return ret; 4498 to_kvm_vmx(kvm)->tss_addr = addr; 4499 return init_rmode_tss(kvm); 4500 } 4501 4502 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4503 { 4504 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4505 return 0; 4506 } 4507 4508 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4509 { 4510 switch (vec) { 4511 case BP_VECTOR: 4512 /* 4513 * Update instruction length as we may reinject the exception 4514 * from user space while in guest debugging mode. 4515 */ 4516 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4517 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4518 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4519 return false; 4520 /* fall through */ 4521 case DB_VECTOR: 4522 if (vcpu->guest_debug & 4523 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 4524 return false; 4525 /* fall through */ 4526 case DE_VECTOR: 4527 case OF_VECTOR: 4528 case BR_VECTOR: 4529 case UD_VECTOR: 4530 case DF_VECTOR: 4531 case SS_VECTOR: 4532 case GP_VECTOR: 4533 case MF_VECTOR: 4534 return true; 4535 } 4536 return false; 4537 } 4538 4539 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4540 int vec, u32 err_code) 4541 { 4542 /* 4543 * Instruction with address size override prefix opcode 0x67 4544 * Cause the #SS fault with 0 error code in VM86 mode. 4545 */ 4546 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4547 if (kvm_emulate_instruction(vcpu, 0)) { 4548 if (vcpu->arch.halt_request) { 4549 vcpu->arch.halt_request = 0; 4550 return kvm_vcpu_halt(vcpu); 4551 } 4552 return 1; 4553 } 4554 return 0; 4555 } 4556 4557 /* 4558 * Forward all other exceptions that are valid in real mode. 4559 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4560 * the required debugging infrastructure rework. 4561 */ 4562 kvm_queue_exception(vcpu, vec); 4563 return 1; 4564 } 4565 4566 /* 4567 * Trigger machine check on the host. We assume all the MSRs are already set up 4568 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4569 * We pass a fake environment to the machine check handler because we want 4570 * the guest to be always treated like user space, no matter what context 4571 * it used internally. 4572 */ 4573 static void kvm_machine_check(void) 4574 { 4575 #if defined(CONFIG_X86_MCE) 4576 struct pt_regs regs = { 4577 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4578 .flags = X86_EFLAGS_IF, 4579 }; 4580 4581 do_machine_check(®s, 0); 4582 #endif 4583 } 4584 4585 static int handle_machine_check(struct kvm_vcpu *vcpu) 4586 { 4587 /* handled by vmx_vcpu_run() */ 4588 return 1; 4589 } 4590 4591 /* 4592 * If the host has split lock detection disabled, then #AC is 4593 * unconditionally injected into the guest, which is the pre split lock 4594 * detection behaviour. 4595 * 4596 * If the host has split lock detection enabled then #AC is 4597 * only injected into the guest when: 4598 * - Guest CPL == 3 (user mode) 4599 * - Guest has #AC detection enabled in CR0 4600 * - Guest EFLAGS has AC bit set 4601 */ 4602 static inline bool guest_inject_ac(struct kvm_vcpu *vcpu) 4603 { 4604 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) 4605 return true; 4606 4607 return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) && 4608 (kvm_get_rflags(vcpu) & X86_EFLAGS_AC); 4609 } 4610 4611 static int handle_exception_nmi(struct kvm_vcpu *vcpu) 4612 { 4613 struct vcpu_vmx *vmx = to_vmx(vcpu); 4614 struct kvm_run *kvm_run = vcpu->run; 4615 u32 intr_info, ex_no, error_code; 4616 unsigned long cr2, rip, dr6; 4617 u32 vect_info; 4618 4619 vect_info = vmx->idt_vectoring_info; 4620 intr_info = vmx->exit_intr_info; 4621 4622 if (is_machine_check(intr_info) || is_nmi(intr_info)) 4623 return 1; /* handled by handle_exception_nmi_irqoff() */ 4624 4625 if (is_invalid_opcode(intr_info)) 4626 return handle_ud(vcpu); 4627 4628 error_code = 0; 4629 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4630 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4631 4632 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4633 WARN_ON_ONCE(!enable_vmware_backdoor); 4634 4635 /* 4636 * VMware backdoor emulation on #GP interception only handles 4637 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero 4638 * error code on #GP. 4639 */ 4640 if (error_code) { 4641 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4642 return 1; 4643 } 4644 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); 4645 } 4646 4647 /* 4648 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4649 * MMIO, it is better to report an internal error. 4650 * See the comments in vmx_handle_exit. 4651 */ 4652 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4653 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4654 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4655 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4656 vcpu->run->internal.ndata = 3; 4657 vcpu->run->internal.data[0] = vect_info; 4658 vcpu->run->internal.data[1] = intr_info; 4659 vcpu->run->internal.data[2] = error_code; 4660 return 0; 4661 } 4662 4663 if (is_page_fault(intr_info)) { 4664 cr2 = vmcs_readl(EXIT_QUALIFICATION); 4665 /* EPT won't cause page fault directly */ 4666 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); 4667 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4668 } 4669 4670 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4671 4672 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4673 return handle_rmode_exception(vcpu, ex_no, error_code); 4674 4675 switch (ex_no) { 4676 case DB_VECTOR: 4677 dr6 = vmcs_readl(EXIT_QUALIFICATION); 4678 if (!(vcpu->guest_debug & 4679 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4680 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4681 vcpu->arch.dr6 |= dr6 | DR6_RTM; 4682 if (is_icebp(intr_info)) 4683 WARN_ON(!skip_emulated_instruction(vcpu)); 4684 4685 kvm_queue_exception(vcpu, DB_VECTOR); 4686 return 1; 4687 } 4688 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; 4689 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4690 /* fall through */ 4691 case BP_VECTOR: 4692 /* 4693 * Update instruction length as we may reinject #BP from 4694 * user space while in guest debugging mode. Reading it for 4695 * #DB as well causes no harm, it is not used in that case. 4696 */ 4697 vmx->vcpu.arch.event_exit_inst_len = 4698 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4699 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4700 rip = kvm_rip_read(vcpu); 4701 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4702 kvm_run->debug.arch.exception = ex_no; 4703 break; 4704 case AC_VECTOR: 4705 if (guest_inject_ac(vcpu)) { 4706 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4707 return 1; 4708 } 4709 4710 /* 4711 * Handle split lock. Depending on detection mode this will 4712 * either warn and disable split lock detection for this 4713 * task or force SIGBUS on it. 4714 */ 4715 if (handle_guest_split_lock(kvm_rip_read(vcpu))) 4716 return 1; 4717 fallthrough; 4718 default: 4719 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4720 kvm_run->ex.exception = ex_no; 4721 kvm_run->ex.error_code = error_code; 4722 break; 4723 } 4724 return 0; 4725 } 4726 4727 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu) 4728 { 4729 ++vcpu->stat.irq_exits; 4730 return 1; 4731 } 4732 4733 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4734 { 4735 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4736 vcpu->mmio_needed = 0; 4737 return 0; 4738 } 4739 4740 static int handle_io(struct kvm_vcpu *vcpu) 4741 { 4742 unsigned long exit_qualification; 4743 int size, in, string; 4744 unsigned port; 4745 4746 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4747 string = (exit_qualification & 16) != 0; 4748 4749 ++vcpu->stat.io_exits; 4750 4751 if (string) 4752 return kvm_emulate_instruction(vcpu, 0); 4753 4754 port = exit_qualification >> 16; 4755 size = (exit_qualification & 7) + 1; 4756 in = (exit_qualification & 8) != 0; 4757 4758 return kvm_fast_pio(vcpu, size, port, in); 4759 } 4760 4761 static void 4762 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4763 { 4764 /* 4765 * Patch in the VMCALL instruction: 4766 */ 4767 hypercall[0] = 0x0f; 4768 hypercall[1] = 0x01; 4769 hypercall[2] = 0xc1; 4770 } 4771 4772 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4773 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4774 { 4775 if (is_guest_mode(vcpu)) { 4776 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4777 unsigned long orig_val = val; 4778 4779 /* 4780 * We get here when L2 changed cr0 in a way that did not change 4781 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4782 * but did change L0 shadowed bits. So we first calculate the 4783 * effective cr0 value that L1 would like to write into the 4784 * hardware. It consists of the L2-owned bits from the new 4785 * value combined with the L1-owned bits from L1's guest_cr0. 4786 */ 4787 val = (val & ~vmcs12->cr0_guest_host_mask) | 4788 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4789 4790 if (!nested_guest_cr0_valid(vcpu, val)) 4791 return 1; 4792 4793 if (kvm_set_cr0(vcpu, val)) 4794 return 1; 4795 vmcs_writel(CR0_READ_SHADOW, orig_val); 4796 return 0; 4797 } else { 4798 if (to_vmx(vcpu)->nested.vmxon && 4799 !nested_host_cr0_valid(vcpu, val)) 4800 return 1; 4801 4802 return kvm_set_cr0(vcpu, val); 4803 } 4804 } 4805 4806 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4807 { 4808 if (is_guest_mode(vcpu)) { 4809 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4810 unsigned long orig_val = val; 4811 4812 /* analogously to handle_set_cr0 */ 4813 val = (val & ~vmcs12->cr4_guest_host_mask) | 4814 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4815 if (kvm_set_cr4(vcpu, val)) 4816 return 1; 4817 vmcs_writel(CR4_READ_SHADOW, orig_val); 4818 return 0; 4819 } else 4820 return kvm_set_cr4(vcpu, val); 4821 } 4822 4823 static int handle_desc(struct kvm_vcpu *vcpu) 4824 { 4825 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4826 return kvm_emulate_instruction(vcpu, 0); 4827 } 4828 4829 static int handle_cr(struct kvm_vcpu *vcpu) 4830 { 4831 unsigned long exit_qualification, val; 4832 int cr; 4833 int reg; 4834 int err; 4835 int ret; 4836 4837 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4838 cr = exit_qualification & 15; 4839 reg = (exit_qualification >> 8) & 15; 4840 switch ((exit_qualification >> 4) & 3) { 4841 case 0: /* mov to cr */ 4842 val = kvm_register_readl(vcpu, reg); 4843 trace_kvm_cr_write(cr, val); 4844 switch (cr) { 4845 case 0: 4846 err = handle_set_cr0(vcpu, val); 4847 return kvm_complete_insn_gp(vcpu, err); 4848 case 3: 4849 WARN_ON_ONCE(enable_unrestricted_guest); 4850 err = kvm_set_cr3(vcpu, val); 4851 return kvm_complete_insn_gp(vcpu, err); 4852 case 4: 4853 err = handle_set_cr4(vcpu, val); 4854 return kvm_complete_insn_gp(vcpu, err); 4855 case 8: { 4856 u8 cr8_prev = kvm_get_cr8(vcpu); 4857 u8 cr8 = (u8)val; 4858 err = kvm_set_cr8(vcpu, cr8); 4859 ret = kvm_complete_insn_gp(vcpu, err); 4860 if (lapic_in_kernel(vcpu)) 4861 return ret; 4862 if (cr8_prev <= cr8) 4863 return ret; 4864 /* 4865 * TODO: we might be squashing a 4866 * KVM_GUESTDBG_SINGLESTEP-triggered 4867 * KVM_EXIT_DEBUG here. 4868 */ 4869 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 4870 return 0; 4871 } 4872 } 4873 break; 4874 case 2: /* clts */ 4875 WARN_ONCE(1, "Guest should always own CR0.TS"); 4876 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 4877 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 4878 return kvm_skip_emulated_instruction(vcpu); 4879 case 1: /*mov from cr*/ 4880 switch (cr) { 4881 case 3: 4882 WARN_ON_ONCE(enable_unrestricted_guest); 4883 val = kvm_read_cr3(vcpu); 4884 kvm_register_write(vcpu, reg, val); 4885 trace_kvm_cr_read(cr, val); 4886 return kvm_skip_emulated_instruction(vcpu); 4887 case 8: 4888 val = kvm_get_cr8(vcpu); 4889 kvm_register_write(vcpu, reg, val); 4890 trace_kvm_cr_read(cr, val); 4891 return kvm_skip_emulated_instruction(vcpu); 4892 } 4893 break; 4894 case 3: /* lmsw */ 4895 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 4896 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 4897 kvm_lmsw(vcpu, val); 4898 4899 return kvm_skip_emulated_instruction(vcpu); 4900 default: 4901 break; 4902 } 4903 vcpu->run->exit_reason = 0; 4904 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 4905 (int)(exit_qualification >> 4) & 3, cr); 4906 return 0; 4907 } 4908 4909 static int handle_dr(struct kvm_vcpu *vcpu) 4910 { 4911 unsigned long exit_qualification; 4912 int dr, dr7, reg; 4913 4914 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4915 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 4916 4917 /* First, if DR does not exist, trigger UD */ 4918 if (!kvm_require_dr(vcpu, dr)) 4919 return 1; 4920 4921 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 4922 if (!kvm_require_cpl(vcpu, 0)) 4923 return 1; 4924 dr7 = vmcs_readl(GUEST_DR7); 4925 if (dr7 & DR7_GD) { 4926 /* 4927 * As the vm-exit takes precedence over the debug trap, we 4928 * need to emulate the latter, either for the host or the 4929 * guest debugging itself. 4930 */ 4931 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 4932 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; 4933 vcpu->run->debug.arch.dr7 = dr7; 4934 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 4935 vcpu->run->debug.arch.exception = DB_VECTOR; 4936 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 4937 return 0; 4938 } else { 4939 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4940 vcpu->arch.dr6 |= DR6_BD | DR6_RTM; 4941 kvm_queue_exception(vcpu, DB_VECTOR); 4942 return 1; 4943 } 4944 } 4945 4946 if (vcpu->guest_debug == 0) { 4947 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4948 4949 /* 4950 * No more DR vmexits; force a reload of the debug registers 4951 * and reenter on this instruction. The next vmexit will 4952 * retrieve the full state of the debug registers. 4953 */ 4954 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 4955 return 1; 4956 } 4957 4958 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 4959 if (exit_qualification & TYPE_MOV_FROM_DR) { 4960 unsigned long val; 4961 4962 if (kvm_get_dr(vcpu, dr, &val)) 4963 return 1; 4964 kvm_register_write(vcpu, reg, val); 4965 } else 4966 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 4967 return 1; 4968 4969 return kvm_skip_emulated_instruction(vcpu); 4970 } 4971 4972 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) 4973 { 4974 return vcpu->arch.dr6; 4975 } 4976 4977 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) 4978 { 4979 } 4980 4981 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 4982 { 4983 get_debugreg(vcpu->arch.db[0], 0); 4984 get_debugreg(vcpu->arch.db[1], 1); 4985 get_debugreg(vcpu->arch.db[2], 2); 4986 get_debugreg(vcpu->arch.db[3], 3); 4987 get_debugreg(vcpu->arch.dr6, 6); 4988 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 4989 4990 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 4991 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4992 } 4993 4994 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 4995 { 4996 vmcs_writel(GUEST_DR7, val); 4997 } 4998 4999 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 5000 { 5001 kvm_apic_update_ppr(vcpu); 5002 return 1; 5003 } 5004 5005 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 5006 { 5007 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 5008 5009 kvm_make_request(KVM_REQ_EVENT, vcpu); 5010 5011 ++vcpu->stat.irq_window_exits; 5012 return 1; 5013 } 5014 5015 static int handle_vmcall(struct kvm_vcpu *vcpu) 5016 { 5017 return kvm_emulate_hypercall(vcpu); 5018 } 5019 5020 static int handle_invd(struct kvm_vcpu *vcpu) 5021 { 5022 return kvm_emulate_instruction(vcpu, 0); 5023 } 5024 5025 static int handle_invlpg(struct kvm_vcpu *vcpu) 5026 { 5027 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5028 5029 kvm_mmu_invlpg(vcpu, exit_qualification); 5030 return kvm_skip_emulated_instruction(vcpu); 5031 } 5032 5033 static int handle_rdpmc(struct kvm_vcpu *vcpu) 5034 { 5035 int err; 5036 5037 err = kvm_rdpmc(vcpu); 5038 return kvm_complete_insn_gp(vcpu, err); 5039 } 5040 5041 static int handle_wbinvd(struct kvm_vcpu *vcpu) 5042 { 5043 return kvm_emulate_wbinvd(vcpu); 5044 } 5045 5046 static int handle_xsetbv(struct kvm_vcpu *vcpu) 5047 { 5048 u64 new_bv = kvm_read_edx_eax(vcpu); 5049 u32 index = kvm_rcx_read(vcpu); 5050 5051 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 5052 return kvm_skip_emulated_instruction(vcpu); 5053 return 1; 5054 } 5055 5056 static int handle_apic_access(struct kvm_vcpu *vcpu) 5057 { 5058 if (likely(fasteoi)) { 5059 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5060 int access_type, offset; 5061 5062 access_type = exit_qualification & APIC_ACCESS_TYPE; 5063 offset = exit_qualification & APIC_ACCESS_OFFSET; 5064 /* 5065 * Sane guest uses MOV to write EOI, with written value 5066 * not cared. So make a short-circuit here by avoiding 5067 * heavy instruction emulation. 5068 */ 5069 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 5070 (offset == APIC_EOI)) { 5071 kvm_lapic_set_eoi(vcpu); 5072 return kvm_skip_emulated_instruction(vcpu); 5073 } 5074 } 5075 return kvm_emulate_instruction(vcpu, 0); 5076 } 5077 5078 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 5079 { 5080 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5081 int vector = exit_qualification & 0xff; 5082 5083 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 5084 kvm_apic_set_eoi_accelerated(vcpu, vector); 5085 return 1; 5086 } 5087 5088 static int handle_apic_write(struct kvm_vcpu *vcpu) 5089 { 5090 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5091 u32 offset = exit_qualification & 0xfff; 5092 5093 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 5094 kvm_apic_write_nodecode(vcpu, offset); 5095 return 1; 5096 } 5097 5098 static int handle_task_switch(struct kvm_vcpu *vcpu) 5099 { 5100 struct vcpu_vmx *vmx = to_vmx(vcpu); 5101 unsigned long exit_qualification; 5102 bool has_error_code = false; 5103 u32 error_code = 0; 5104 u16 tss_selector; 5105 int reason, type, idt_v, idt_index; 5106 5107 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5108 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5109 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5110 5111 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5112 5113 reason = (u32)exit_qualification >> 30; 5114 if (reason == TASK_SWITCH_GATE && idt_v) { 5115 switch (type) { 5116 case INTR_TYPE_NMI_INTR: 5117 vcpu->arch.nmi_injected = false; 5118 vmx_set_nmi_mask(vcpu, true); 5119 break; 5120 case INTR_TYPE_EXT_INTR: 5121 case INTR_TYPE_SOFT_INTR: 5122 kvm_clear_interrupt_queue(vcpu); 5123 break; 5124 case INTR_TYPE_HARD_EXCEPTION: 5125 if (vmx->idt_vectoring_info & 5126 VECTORING_INFO_DELIVER_CODE_MASK) { 5127 has_error_code = true; 5128 error_code = 5129 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5130 } 5131 /* fall through */ 5132 case INTR_TYPE_SOFT_EXCEPTION: 5133 kvm_clear_exception_queue(vcpu); 5134 break; 5135 default: 5136 break; 5137 } 5138 } 5139 tss_selector = exit_qualification; 5140 5141 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5142 type != INTR_TYPE_EXT_INTR && 5143 type != INTR_TYPE_NMI_INTR)) 5144 WARN_ON(!skip_emulated_instruction(vcpu)); 5145 5146 /* 5147 * TODO: What about debug traps on tss switch? 5148 * Are we supposed to inject them and update dr6? 5149 */ 5150 return kvm_task_switch(vcpu, tss_selector, 5151 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, 5152 reason, has_error_code, error_code); 5153 } 5154 5155 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5156 { 5157 unsigned long exit_qualification; 5158 gpa_t gpa; 5159 u64 error_code; 5160 5161 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5162 5163 /* 5164 * EPT violation happened while executing iret from NMI, 5165 * "blocked by NMI" bit has to be set before next VM entry. 5166 * There are errata that may cause this bit to not be set: 5167 * AAK134, BY25. 5168 */ 5169 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5170 enable_vnmi && 5171 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5172 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5173 5174 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5175 trace_kvm_page_fault(gpa, exit_qualification); 5176 5177 /* Is it a read fault? */ 5178 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5179 ? PFERR_USER_MASK : 0; 5180 /* Is it a write fault? */ 5181 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5182 ? PFERR_WRITE_MASK : 0; 5183 /* Is it a fetch fault? */ 5184 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5185 ? PFERR_FETCH_MASK : 0; 5186 /* ept page table entry is present? */ 5187 error_code |= (exit_qualification & 5188 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5189 EPT_VIOLATION_EXECUTABLE)) 5190 ? PFERR_PRESENT_MASK : 0; 5191 5192 error_code |= (exit_qualification & 0x100) != 0 ? 5193 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5194 5195 vcpu->arch.exit_qualification = exit_qualification; 5196 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5197 } 5198 5199 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5200 { 5201 gpa_t gpa; 5202 5203 /* 5204 * A nested guest cannot optimize MMIO vmexits, because we have an 5205 * nGPA here instead of the required GPA. 5206 */ 5207 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5208 if (!is_guest_mode(vcpu) && 5209 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5210 trace_kvm_fast_mmio(gpa); 5211 return kvm_skip_emulated_instruction(vcpu); 5212 } 5213 5214 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5215 } 5216 5217 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5218 { 5219 WARN_ON_ONCE(!enable_vnmi); 5220 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 5221 ++vcpu->stat.nmi_window_exits; 5222 kvm_make_request(KVM_REQ_EVENT, vcpu); 5223 5224 return 1; 5225 } 5226 5227 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5228 { 5229 struct vcpu_vmx *vmx = to_vmx(vcpu); 5230 bool intr_window_requested; 5231 unsigned count = 130; 5232 5233 /* 5234 * We should never reach the point where we are emulating L2 5235 * due to invalid guest state as that means we incorrectly 5236 * allowed a nested VMEntry with an invalid vmcs12. 5237 */ 5238 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending); 5239 5240 intr_window_requested = exec_controls_get(vmx) & 5241 CPU_BASED_INTR_WINDOW_EXITING; 5242 5243 while (vmx->emulation_required && count-- != 0) { 5244 if (intr_window_requested && vmx_interrupt_allowed(vcpu)) 5245 return handle_interrupt_window(&vmx->vcpu); 5246 5247 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5248 return 1; 5249 5250 if (!kvm_emulate_instruction(vcpu, 0)) 5251 return 0; 5252 5253 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5254 vcpu->arch.exception.pending) { 5255 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5256 vcpu->run->internal.suberror = 5257 KVM_INTERNAL_ERROR_EMULATION; 5258 vcpu->run->internal.ndata = 0; 5259 return 0; 5260 } 5261 5262 if (vcpu->arch.halt_request) { 5263 vcpu->arch.halt_request = 0; 5264 return kvm_vcpu_halt(vcpu); 5265 } 5266 5267 /* 5268 * Note, return 1 and not 0, vcpu_run() is responsible for 5269 * morphing the pending signal into the proper return code. 5270 */ 5271 if (signal_pending(current)) 5272 return 1; 5273 5274 if (need_resched()) 5275 schedule(); 5276 } 5277 5278 return 1; 5279 } 5280 5281 static void grow_ple_window(struct kvm_vcpu *vcpu) 5282 { 5283 struct vcpu_vmx *vmx = to_vmx(vcpu); 5284 unsigned int old = vmx->ple_window; 5285 5286 vmx->ple_window = __grow_ple_window(old, ple_window, 5287 ple_window_grow, 5288 ple_window_max); 5289 5290 if (vmx->ple_window != old) { 5291 vmx->ple_window_dirty = true; 5292 trace_kvm_ple_window_update(vcpu->vcpu_id, 5293 vmx->ple_window, old); 5294 } 5295 } 5296 5297 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5298 { 5299 struct vcpu_vmx *vmx = to_vmx(vcpu); 5300 unsigned int old = vmx->ple_window; 5301 5302 vmx->ple_window = __shrink_ple_window(old, ple_window, 5303 ple_window_shrink, 5304 ple_window); 5305 5306 if (vmx->ple_window != old) { 5307 vmx->ple_window_dirty = true; 5308 trace_kvm_ple_window_update(vcpu->vcpu_id, 5309 vmx->ple_window, old); 5310 } 5311 } 5312 5313 /* 5314 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. 5315 */ 5316 static void wakeup_handler(void) 5317 { 5318 struct kvm_vcpu *vcpu; 5319 int cpu = smp_processor_id(); 5320 5321 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5322 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), 5323 blocked_vcpu_list) { 5324 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 5325 5326 if (pi_test_on(pi_desc) == 1) 5327 kvm_vcpu_kick(vcpu); 5328 } 5329 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5330 } 5331 5332 static void vmx_enable_tdp(void) 5333 { 5334 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5335 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5336 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5337 0ull, VMX_EPT_EXECUTABLE_MASK, 5338 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5339 VMX_EPT_RWX_MASK, 0ull); 5340 5341 ept_set_mmio_spte_mask(); 5342 } 5343 5344 /* 5345 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5346 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5347 */ 5348 static int handle_pause(struct kvm_vcpu *vcpu) 5349 { 5350 if (!kvm_pause_in_guest(vcpu->kvm)) 5351 grow_ple_window(vcpu); 5352 5353 /* 5354 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5355 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5356 * never set PAUSE_EXITING and just set PLE if supported, 5357 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5358 */ 5359 kvm_vcpu_on_spin(vcpu, true); 5360 return kvm_skip_emulated_instruction(vcpu); 5361 } 5362 5363 static int handle_nop(struct kvm_vcpu *vcpu) 5364 { 5365 return kvm_skip_emulated_instruction(vcpu); 5366 } 5367 5368 static int handle_mwait(struct kvm_vcpu *vcpu) 5369 { 5370 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5371 return handle_nop(vcpu); 5372 } 5373 5374 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5375 { 5376 kvm_queue_exception(vcpu, UD_VECTOR); 5377 return 1; 5378 } 5379 5380 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5381 { 5382 return 1; 5383 } 5384 5385 static int handle_monitor(struct kvm_vcpu *vcpu) 5386 { 5387 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5388 return handle_nop(vcpu); 5389 } 5390 5391 static int handle_invpcid(struct kvm_vcpu *vcpu) 5392 { 5393 u32 vmx_instruction_info; 5394 unsigned long type; 5395 bool pcid_enabled; 5396 gva_t gva; 5397 struct x86_exception e; 5398 unsigned i; 5399 unsigned long roots_to_free = 0; 5400 struct { 5401 u64 pcid; 5402 u64 gla; 5403 } operand; 5404 5405 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5406 kvm_queue_exception(vcpu, UD_VECTOR); 5407 return 1; 5408 } 5409 5410 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5411 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5412 5413 if (type > 3) { 5414 kvm_inject_gp(vcpu, 0); 5415 return 1; 5416 } 5417 5418 /* According to the Intel instruction reference, the memory operand 5419 * is read even if it isn't needed (e.g., for type==all) 5420 */ 5421 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5422 vmx_instruction_info, false, 5423 sizeof(operand), &gva)) 5424 return 1; 5425 5426 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5427 kvm_inject_page_fault(vcpu, &e); 5428 return 1; 5429 } 5430 5431 if (operand.pcid >> 12 != 0) { 5432 kvm_inject_gp(vcpu, 0); 5433 return 1; 5434 } 5435 5436 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 5437 5438 switch (type) { 5439 case INVPCID_TYPE_INDIV_ADDR: 5440 if ((!pcid_enabled && (operand.pcid != 0)) || 5441 is_noncanonical_address(operand.gla, vcpu)) { 5442 kvm_inject_gp(vcpu, 0); 5443 return 1; 5444 } 5445 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 5446 return kvm_skip_emulated_instruction(vcpu); 5447 5448 case INVPCID_TYPE_SINGLE_CTXT: 5449 if (!pcid_enabled && (operand.pcid != 0)) { 5450 kvm_inject_gp(vcpu, 0); 5451 return 1; 5452 } 5453 5454 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 5455 kvm_mmu_sync_roots(vcpu); 5456 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 5457 } 5458 5459 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 5460 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3) 5461 == operand.pcid) 5462 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5463 5464 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 5465 /* 5466 * If neither the current cr3 nor any of the prev_roots use the 5467 * given PCID, then nothing needs to be done here because a 5468 * resync will happen anyway before switching to any other CR3. 5469 */ 5470 5471 return kvm_skip_emulated_instruction(vcpu); 5472 5473 case INVPCID_TYPE_ALL_NON_GLOBAL: 5474 /* 5475 * Currently, KVM doesn't mark global entries in the shadow 5476 * page tables, so a non-global flush just degenerates to a 5477 * global flush. If needed, we could optimize this later by 5478 * keeping track of global entries in shadow page tables. 5479 */ 5480 5481 /* fall-through */ 5482 case INVPCID_TYPE_ALL_INCL_GLOBAL: 5483 kvm_mmu_unload(vcpu); 5484 return kvm_skip_emulated_instruction(vcpu); 5485 5486 default: 5487 BUG(); /* We have already checked above that type <= 3 */ 5488 } 5489 } 5490 5491 static int handle_pml_full(struct kvm_vcpu *vcpu) 5492 { 5493 unsigned long exit_qualification; 5494 5495 trace_kvm_pml_full(vcpu->vcpu_id); 5496 5497 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5498 5499 /* 5500 * PML buffer FULL happened while executing iret from NMI, 5501 * "blocked by NMI" bit has to be set before next VM entry. 5502 */ 5503 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5504 enable_vnmi && 5505 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5506 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5507 GUEST_INTR_STATE_NMI); 5508 5509 /* 5510 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5511 * here.., and there's no userspace involvement needed for PML. 5512 */ 5513 return 1; 5514 } 5515 5516 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5517 { 5518 struct vcpu_vmx *vmx = to_vmx(vcpu); 5519 5520 if (!vmx->req_immediate_exit && 5521 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) 5522 kvm_lapic_expired_hv_timer(vcpu); 5523 5524 return 1; 5525 } 5526 5527 /* 5528 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5529 * are overwritten by nested_vmx_setup() when nested=1. 5530 */ 5531 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5532 { 5533 kvm_queue_exception(vcpu, UD_VECTOR); 5534 return 1; 5535 } 5536 5537 static int handle_encls(struct kvm_vcpu *vcpu) 5538 { 5539 /* 5540 * SGX virtualization is not yet supported. There is no software 5541 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5542 * to prevent the guest from executing ENCLS. 5543 */ 5544 kvm_queue_exception(vcpu, UD_VECTOR); 5545 return 1; 5546 } 5547 5548 /* 5549 * The exit handlers return 1 if the exit was handled fully and guest execution 5550 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5551 * to be done to userspace and return 0. 5552 */ 5553 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5554 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, 5555 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5556 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5557 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5558 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5559 [EXIT_REASON_CR_ACCESS] = handle_cr, 5560 [EXIT_REASON_DR_ACCESS] = handle_dr, 5561 [EXIT_REASON_CPUID] = kvm_emulate_cpuid, 5562 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr, 5563 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr, 5564 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window, 5565 [EXIT_REASON_HLT] = kvm_emulate_halt, 5566 [EXIT_REASON_INVD] = handle_invd, 5567 [EXIT_REASON_INVLPG] = handle_invlpg, 5568 [EXIT_REASON_RDPMC] = handle_rdpmc, 5569 [EXIT_REASON_VMCALL] = handle_vmcall, 5570 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5571 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5572 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5573 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5574 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5575 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5576 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5577 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5578 [EXIT_REASON_VMON] = handle_vmx_instruction, 5579 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5580 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5581 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5582 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5583 [EXIT_REASON_WBINVD] = handle_wbinvd, 5584 [EXIT_REASON_XSETBV] = handle_xsetbv, 5585 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5586 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5587 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5588 [EXIT_REASON_LDTR_TR] = handle_desc, 5589 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5590 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5591 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5592 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5593 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5594 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5595 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5596 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5597 [EXIT_REASON_RDRAND] = handle_invalid_op, 5598 [EXIT_REASON_RDSEED] = handle_invalid_op, 5599 [EXIT_REASON_PML_FULL] = handle_pml_full, 5600 [EXIT_REASON_INVPCID] = handle_invpcid, 5601 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5602 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5603 [EXIT_REASON_ENCLS] = handle_encls, 5604 }; 5605 5606 static const int kvm_vmx_max_exit_handlers = 5607 ARRAY_SIZE(kvm_vmx_exit_handlers); 5608 5609 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) 5610 { 5611 *info1 = vmcs_readl(EXIT_QUALIFICATION); 5612 *info2 = vmcs_read32(VM_EXIT_INTR_INFO); 5613 } 5614 5615 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5616 { 5617 if (vmx->pml_pg) { 5618 __free_page(vmx->pml_pg); 5619 vmx->pml_pg = NULL; 5620 } 5621 } 5622 5623 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5624 { 5625 struct vcpu_vmx *vmx = to_vmx(vcpu); 5626 u64 *pml_buf; 5627 u16 pml_idx; 5628 5629 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5630 5631 /* Do nothing if PML buffer is empty */ 5632 if (pml_idx == (PML_ENTITY_NUM - 1)) 5633 return; 5634 5635 /* PML index always points to next available PML buffer entity */ 5636 if (pml_idx >= PML_ENTITY_NUM) 5637 pml_idx = 0; 5638 else 5639 pml_idx++; 5640 5641 pml_buf = page_address(vmx->pml_pg); 5642 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5643 u64 gpa; 5644 5645 gpa = pml_buf[pml_idx]; 5646 WARN_ON(gpa & (PAGE_SIZE - 1)); 5647 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5648 } 5649 5650 /* reset PML index */ 5651 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5652 } 5653 5654 /* 5655 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5656 * Called before reporting dirty_bitmap to userspace. 5657 */ 5658 static void kvm_flush_pml_buffers(struct kvm *kvm) 5659 { 5660 int i; 5661 struct kvm_vcpu *vcpu; 5662 /* 5663 * We only need to kick vcpu out of guest mode here, as PML buffer 5664 * is flushed at beginning of all VMEXITs, and it's obvious that only 5665 * vcpus running in guest are possible to have unflushed GPAs in PML 5666 * buffer. 5667 */ 5668 kvm_for_each_vcpu(i, vcpu, kvm) 5669 kvm_vcpu_kick(vcpu); 5670 } 5671 5672 static void vmx_dump_sel(char *name, uint32_t sel) 5673 { 5674 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5675 name, vmcs_read16(sel), 5676 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5677 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5678 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5679 } 5680 5681 static void vmx_dump_dtsel(char *name, uint32_t limit) 5682 { 5683 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5684 name, vmcs_read32(limit), 5685 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5686 } 5687 5688 void dump_vmcs(void) 5689 { 5690 u32 vmentry_ctl, vmexit_ctl; 5691 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; 5692 unsigned long cr4; 5693 u64 efer; 5694 int i, n; 5695 5696 if (!dump_invalid_vmcs) { 5697 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); 5698 return; 5699 } 5700 5701 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5702 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5703 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5704 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5705 cr4 = vmcs_readl(GUEST_CR4); 5706 efer = vmcs_read64(GUEST_IA32_EFER); 5707 secondary_exec_control = 0; 5708 if (cpu_has_secondary_exec_ctrls()) 5709 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5710 5711 pr_err("*** Guest State ***\n"); 5712 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5713 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5714 vmcs_readl(CR0_GUEST_HOST_MASK)); 5715 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5716 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5717 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5718 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5719 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5720 { 5721 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5722 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5723 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5724 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5725 } 5726 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5727 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5728 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5729 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5730 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5731 vmcs_readl(GUEST_SYSENTER_ESP), 5732 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5733 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5734 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5735 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5736 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5737 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5738 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5739 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5740 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5741 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5742 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5743 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5744 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5745 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5746 efer, vmcs_read64(GUEST_IA32_PAT)); 5747 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5748 vmcs_read64(GUEST_IA32_DEBUGCTL), 5749 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5750 if (cpu_has_load_perf_global_ctrl() && 5751 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5752 pr_err("PerfGlobCtl = 0x%016llx\n", 5753 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5754 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5755 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5756 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5757 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5758 vmcs_read32(GUEST_ACTIVITY_STATE)); 5759 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5760 pr_err("InterruptStatus = %04x\n", 5761 vmcs_read16(GUEST_INTR_STATUS)); 5762 5763 pr_err("*** Host State ***\n"); 5764 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5765 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5766 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5767 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5768 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5769 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5770 vmcs_read16(HOST_TR_SELECTOR)); 5771 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5772 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5773 vmcs_readl(HOST_TR_BASE)); 5774 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5775 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5776 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5777 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5778 vmcs_readl(HOST_CR4)); 5779 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5780 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5781 vmcs_read32(HOST_IA32_SYSENTER_CS), 5782 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5783 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5784 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5785 vmcs_read64(HOST_IA32_EFER), 5786 vmcs_read64(HOST_IA32_PAT)); 5787 if (cpu_has_load_perf_global_ctrl() && 5788 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5789 pr_err("PerfGlobCtl = 0x%016llx\n", 5790 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5791 5792 pr_err("*** Control State ***\n"); 5793 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5794 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5795 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5796 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5797 vmcs_read32(EXCEPTION_BITMAP), 5798 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5799 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5800 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5801 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5802 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5803 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5804 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5805 vmcs_read32(VM_EXIT_INTR_INFO), 5806 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5807 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5808 pr_err(" reason=%08x qualification=%016lx\n", 5809 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5810 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5811 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5812 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5813 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5814 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5815 pr_err("TSC Multiplier = 0x%016llx\n", 5816 vmcs_read64(TSC_MULTIPLIER)); 5817 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { 5818 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { 5819 u16 status = vmcs_read16(GUEST_INTR_STATUS); 5820 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); 5821 } 5822 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5823 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) 5824 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); 5825 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); 5826 } 5827 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5828 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5829 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5830 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5831 n = vmcs_read32(CR3_TARGET_COUNT); 5832 for (i = 0; i + 1 < n; i += 4) 5833 pr_err("CR3 target%u=%016lx target%u=%016lx\n", 5834 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), 5835 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); 5836 if (i < n) 5837 pr_err("CR3 target%u=%016lx\n", 5838 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); 5839 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5840 pr_err("PLE Gap=%08x Window=%08x\n", 5841 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5842 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5843 pr_err("Virtual processor ID = 0x%04x\n", 5844 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5845 } 5846 5847 /* 5848 * The guest has exited. See if we can fix it or if we need userspace 5849 * assistance. 5850 */ 5851 static int vmx_handle_exit(struct kvm_vcpu *vcpu, 5852 enum exit_fastpath_completion exit_fastpath) 5853 { 5854 struct vcpu_vmx *vmx = to_vmx(vcpu); 5855 u32 exit_reason = vmx->exit_reason; 5856 u32 vectoring_info = vmx->idt_vectoring_info; 5857 5858 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); 5859 5860 /* 5861 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5862 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5863 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5864 * mode as if vcpus is in root mode, the PML buffer must has been 5865 * flushed already. 5866 */ 5867 if (enable_pml) 5868 vmx_flush_pml_buffer(vcpu); 5869 5870 /* If guest state is invalid, start emulating */ 5871 if (vmx->emulation_required) 5872 return handle_invalid_guest_state(vcpu); 5873 5874 if (is_guest_mode(vcpu)) { 5875 /* 5876 * The host physical addresses of some pages of guest memory 5877 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC 5878 * Page). The CPU may write to these pages via their host 5879 * physical address while L2 is running, bypassing any 5880 * address-translation-based dirty tracking (e.g. EPT write 5881 * protection). 5882 * 5883 * Mark them dirty on every exit from L2 to prevent them from 5884 * getting out of sync with dirty tracking. 5885 */ 5886 nested_mark_vmcs12_pages_dirty(vcpu); 5887 5888 if (nested_vmx_exit_reflected(vcpu, exit_reason)) 5889 return nested_vmx_reflect_vmexit(vcpu, exit_reason); 5890 } 5891 5892 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5893 dump_vmcs(); 5894 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5895 vcpu->run->fail_entry.hardware_entry_failure_reason 5896 = exit_reason; 5897 return 0; 5898 } 5899 5900 if (unlikely(vmx->fail)) { 5901 dump_vmcs(); 5902 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5903 vcpu->run->fail_entry.hardware_entry_failure_reason 5904 = vmcs_read32(VM_INSTRUCTION_ERROR); 5905 return 0; 5906 } 5907 5908 /* 5909 * Note: 5910 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 5911 * delivery event since it indicates guest is accessing MMIO. 5912 * The vm-exit can be triggered again after return to guest that 5913 * will cause infinite loop. 5914 */ 5915 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 5916 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 5917 exit_reason != EXIT_REASON_EPT_VIOLATION && 5918 exit_reason != EXIT_REASON_PML_FULL && 5919 exit_reason != EXIT_REASON_TASK_SWITCH)) { 5920 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5921 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 5922 vcpu->run->internal.ndata = 3; 5923 vcpu->run->internal.data[0] = vectoring_info; 5924 vcpu->run->internal.data[1] = exit_reason; 5925 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 5926 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 5927 vcpu->run->internal.ndata++; 5928 vcpu->run->internal.data[3] = 5929 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5930 } 5931 return 0; 5932 } 5933 5934 if (unlikely(!enable_vnmi && 5935 vmx->loaded_vmcs->soft_vnmi_blocked)) { 5936 if (vmx_interrupt_allowed(vcpu)) { 5937 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5938 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 5939 vcpu->arch.nmi_pending) { 5940 /* 5941 * This CPU don't support us in finding the end of an 5942 * NMI-blocked window if the guest runs with IRQs 5943 * disabled. So we pull the trigger after 1 s of 5944 * futile waiting, but inform the user about this. 5945 */ 5946 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 5947 "state on VCPU %d after 1 s timeout\n", 5948 __func__, vcpu->vcpu_id); 5949 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5950 } 5951 } 5952 5953 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) { 5954 kvm_skip_emulated_instruction(vcpu); 5955 return 1; 5956 } 5957 5958 if (exit_reason >= kvm_vmx_max_exit_handlers) 5959 goto unexpected_vmexit; 5960 #ifdef CONFIG_RETPOLINE 5961 if (exit_reason == EXIT_REASON_MSR_WRITE) 5962 return kvm_emulate_wrmsr(vcpu); 5963 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER) 5964 return handle_preemption_timer(vcpu); 5965 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW) 5966 return handle_interrupt_window(vcpu); 5967 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 5968 return handle_external_interrupt(vcpu); 5969 else if (exit_reason == EXIT_REASON_HLT) 5970 return kvm_emulate_halt(vcpu); 5971 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG) 5972 return handle_ept_misconfig(vcpu); 5973 #endif 5974 5975 exit_reason = array_index_nospec(exit_reason, 5976 kvm_vmx_max_exit_handlers); 5977 if (!kvm_vmx_exit_handlers[exit_reason]) 5978 goto unexpected_vmexit; 5979 5980 return kvm_vmx_exit_handlers[exit_reason](vcpu); 5981 5982 unexpected_vmexit: 5983 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason); 5984 dump_vmcs(); 5985 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5986 vcpu->run->internal.suberror = 5987 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 5988 vcpu->run->internal.ndata = 1; 5989 vcpu->run->internal.data[0] = exit_reason; 5990 return 0; 5991 } 5992 5993 /* 5994 * Software based L1D cache flush which is used when microcode providing 5995 * the cache control MSR is not loaded. 5996 * 5997 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 5998 * flush it is required to read in 64 KiB because the replacement algorithm 5999 * is not exactly LRU. This could be sized at runtime via topology 6000 * information but as all relevant affected CPUs have 32KiB L1D cache size 6001 * there is no point in doing so. 6002 */ 6003 static void vmx_l1d_flush(struct kvm_vcpu *vcpu) 6004 { 6005 int size = PAGE_SIZE << L1D_CACHE_ORDER; 6006 6007 /* 6008 * This code is only executed when the the flush mode is 'cond' or 6009 * 'always' 6010 */ 6011 if (static_branch_likely(&vmx_l1d_flush_cond)) { 6012 bool flush_l1d; 6013 6014 /* 6015 * Clear the per-vcpu flush bit, it gets set again 6016 * either from vcpu_run() or from one of the unsafe 6017 * VMEXIT handlers. 6018 */ 6019 flush_l1d = vcpu->arch.l1tf_flush_l1d; 6020 vcpu->arch.l1tf_flush_l1d = false; 6021 6022 /* 6023 * Clear the per-cpu flush bit, it gets set again from 6024 * the interrupt handlers. 6025 */ 6026 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 6027 kvm_clear_cpu_l1tf_flush_l1d(); 6028 6029 if (!flush_l1d) 6030 return; 6031 } 6032 6033 vcpu->stat.l1d_flush++; 6034 6035 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 6036 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 6037 return; 6038 } 6039 6040 asm volatile( 6041 /* First ensure the pages are in the TLB */ 6042 "xorl %%eax, %%eax\n" 6043 ".Lpopulate_tlb:\n\t" 6044 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6045 "addl $4096, %%eax\n\t" 6046 "cmpl %%eax, %[size]\n\t" 6047 "jne .Lpopulate_tlb\n\t" 6048 "xorl %%eax, %%eax\n\t" 6049 "cpuid\n\t" 6050 /* Now fill the cache */ 6051 "xorl %%eax, %%eax\n" 6052 ".Lfill_cache:\n" 6053 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 6054 "addl $64, %%eax\n\t" 6055 "cmpl %%eax, %[size]\n\t" 6056 "jne .Lfill_cache\n\t" 6057 "lfence\n" 6058 :: [flush_pages] "r" (vmx_l1d_flush_pages), 6059 [size] "r" (size) 6060 : "eax", "ebx", "ecx", "edx"); 6061 } 6062 6063 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 6064 { 6065 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 6066 int tpr_threshold; 6067 6068 if (is_guest_mode(vcpu) && 6069 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 6070 return; 6071 6072 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr; 6073 if (is_guest_mode(vcpu)) 6074 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold; 6075 else 6076 vmcs_write32(TPR_THRESHOLD, tpr_threshold); 6077 } 6078 6079 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 6080 { 6081 struct vcpu_vmx *vmx = to_vmx(vcpu); 6082 u32 sec_exec_control; 6083 6084 if (!lapic_in_kernel(vcpu)) 6085 return; 6086 6087 if (!flexpriority_enabled && 6088 !cpu_has_vmx_virtualize_x2apic_mode()) 6089 return; 6090 6091 /* Postpone execution until vmcs01 is the current VMCS. */ 6092 if (is_guest_mode(vcpu)) { 6093 vmx->nested.change_vmcs01_virtual_apic_mode = true; 6094 return; 6095 } 6096 6097 sec_exec_control = secondary_exec_controls_get(vmx); 6098 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6099 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 6100 6101 switch (kvm_get_apic_mode(vcpu)) { 6102 case LAPIC_MODE_INVALID: 6103 WARN_ONCE(true, "Invalid local APIC state"); 6104 case LAPIC_MODE_DISABLED: 6105 break; 6106 case LAPIC_MODE_XAPIC: 6107 if (flexpriority_enabled) { 6108 sec_exec_control |= 6109 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6110 vmx_flush_tlb(vcpu, true); 6111 } 6112 break; 6113 case LAPIC_MODE_X2APIC: 6114 if (cpu_has_vmx_virtualize_x2apic_mode()) 6115 sec_exec_control |= 6116 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 6117 break; 6118 } 6119 secondary_exec_controls_set(vmx, sec_exec_control); 6120 6121 vmx_update_msr_bitmap(vcpu); 6122 } 6123 6124 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) 6125 { 6126 if (!is_guest_mode(vcpu)) { 6127 vmcs_write64(APIC_ACCESS_ADDR, hpa); 6128 vmx_flush_tlb(vcpu, true); 6129 } 6130 } 6131 6132 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6133 { 6134 u16 status; 6135 u8 old; 6136 6137 if (max_isr == -1) 6138 max_isr = 0; 6139 6140 status = vmcs_read16(GUEST_INTR_STATUS); 6141 old = status >> 8; 6142 if (max_isr != old) { 6143 status &= 0xff; 6144 status |= max_isr << 8; 6145 vmcs_write16(GUEST_INTR_STATUS, status); 6146 } 6147 } 6148 6149 static void vmx_set_rvi(int vector) 6150 { 6151 u16 status; 6152 u8 old; 6153 6154 if (vector == -1) 6155 vector = 0; 6156 6157 status = vmcs_read16(GUEST_INTR_STATUS); 6158 old = (u8)status & 0xff; 6159 if ((u8)vector != old) { 6160 status &= ~0xff; 6161 status |= (u8)vector; 6162 vmcs_write16(GUEST_INTR_STATUS, status); 6163 } 6164 } 6165 6166 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6167 { 6168 /* 6169 * When running L2, updating RVI is only relevant when 6170 * vmcs12 virtual-interrupt-delivery enabled. 6171 * However, it can be enabled only when L1 also 6172 * intercepts external-interrupts and in that case 6173 * we should not update vmcs02 RVI but instead intercept 6174 * interrupt. Therefore, do nothing when running L2. 6175 */ 6176 if (!is_guest_mode(vcpu)) 6177 vmx_set_rvi(max_irr); 6178 } 6179 6180 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6181 { 6182 struct vcpu_vmx *vmx = to_vmx(vcpu); 6183 int max_irr; 6184 bool max_irr_updated; 6185 6186 WARN_ON(!vcpu->arch.apicv_active); 6187 if (pi_test_on(&vmx->pi_desc)) { 6188 pi_clear_on(&vmx->pi_desc); 6189 /* 6190 * IOMMU can write to PID.ON, so the barrier matters even on UP. 6191 * But on x86 this is just a compiler barrier anyway. 6192 */ 6193 smp_mb__after_atomic(); 6194 max_irr_updated = 6195 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6196 6197 /* 6198 * If we are running L2 and L1 has a new pending interrupt 6199 * which can be injected, we should re-evaluate 6200 * what should be done with this new L1 interrupt. 6201 * If L1 intercepts external-interrupts, we should 6202 * exit from L2 to L1. Otherwise, interrupt should be 6203 * delivered directly to L2. 6204 */ 6205 if (is_guest_mode(vcpu) && max_irr_updated) { 6206 if (nested_exit_on_intr(vcpu)) 6207 kvm_vcpu_exiting_guest_mode(vcpu); 6208 else 6209 kvm_make_request(KVM_REQ_EVENT, vcpu); 6210 } 6211 } else { 6212 max_irr = kvm_lapic_find_highest_irr(vcpu); 6213 } 6214 vmx_hwapic_irr_update(vcpu, max_irr); 6215 return max_irr; 6216 } 6217 6218 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) 6219 { 6220 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 6221 6222 return pi_test_on(pi_desc) || 6223 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc)); 6224 } 6225 6226 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6227 { 6228 if (!kvm_vcpu_apicv_active(vcpu)) 6229 return; 6230 6231 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6232 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6233 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6234 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6235 } 6236 6237 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6238 { 6239 struct vcpu_vmx *vmx = to_vmx(vcpu); 6240 6241 pi_clear_on(&vmx->pi_desc); 6242 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6243 } 6244 6245 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) 6246 { 6247 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6248 6249 /* if exit due to PF check for async PF */ 6250 if (is_page_fault(vmx->exit_intr_info)) { 6251 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); 6252 /* Handle machine checks before interrupts are enabled */ 6253 } else if (is_machine_check(vmx->exit_intr_info)) { 6254 kvm_machine_check(); 6255 /* We need to handle NMIs before interrupts are enabled */ 6256 } else if (is_nmi(vmx->exit_intr_info)) { 6257 kvm_before_interrupt(&vmx->vcpu); 6258 asm("int $2"); 6259 kvm_after_interrupt(&vmx->vcpu); 6260 } 6261 } 6262 6263 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) 6264 { 6265 unsigned int vector; 6266 unsigned long entry; 6267 #ifdef CONFIG_X86_64 6268 unsigned long tmp; 6269 #endif 6270 gate_desc *desc; 6271 u32 intr_info; 6272 6273 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6274 if (WARN_ONCE(!is_external_intr(intr_info), 6275 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) 6276 return; 6277 6278 vector = intr_info & INTR_INFO_VECTOR_MASK; 6279 desc = (gate_desc *)host_idt_base + vector; 6280 entry = gate_offset(desc); 6281 6282 kvm_before_interrupt(vcpu); 6283 6284 asm volatile( 6285 #ifdef CONFIG_X86_64 6286 "mov %%" _ASM_SP ", %[sp]\n\t" 6287 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" 6288 "push $%c[ss]\n\t" 6289 "push %[sp]\n\t" 6290 #endif 6291 "pushf\n\t" 6292 __ASM_SIZE(push) " $%c[cs]\n\t" 6293 CALL_NOSPEC 6294 : 6295 #ifdef CONFIG_X86_64 6296 [sp]"=&r"(tmp), 6297 #endif 6298 ASM_CALL_CONSTRAINT 6299 : 6300 [thunk_target]"r"(entry), 6301 [ss]"i"(__KERNEL_DS), 6302 [cs]"i"(__KERNEL_CS) 6303 ); 6304 6305 kvm_after_interrupt(vcpu); 6306 } 6307 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff); 6308 6309 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu, 6310 enum exit_fastpath_completion *exit_fastpath) 6311 { 6312 struct vcpu_vmx *vmx = to_vmx(vcpu); 6313 6314 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6315 handle_external_interrupt_irqoff(vcpu); 6316 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI) 6317 handle_exception_nmi_irqoff(vmx); 6318 else if (!is_guest_mode(vcpu) && 6319 vmx->exit_reason == EXIT_REASON_MSR_WRITE) 6320 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu); 6321 } 6322 6323 static bool vmx_has_emulated_msr(int index) 6324 { 6325 switch (index) { 6326 case MSR_IA32_SMBASE: 6327 /* 6328 * We cannot do SMM unless we can run the guest in big 6329 * real mode. 6330 */ 6331 return enable_unrestricted_guest || emulate_invalid_guest_state; 6332 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 6333 return nested; 6334 case MSR_AMD64_VIRT_SPEC_CTRL: 6335 /* This is AMD only. */ 6336 return false; 6337 default: 6338 return true; 6339 } 6340 } 6341 6342 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6343 { 6344 u32 exit_intr_info; 6345 bool unblock_nmi; 6346 u8 vector; 6347 bool idtv_info_valid; 6348 6349 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6350 6351 if (enable_vnmi) { 6352 if (vmx->loaded_vmcs->nmi_known_unmasked) 6353 return; 6354 /* 6355 * Can't use vmx->exit_intr_info since we're not sure what 6356 * the exit reason is. 6357 */ 6358 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6359 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6360 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6361 /* 6362 * SDM 3: 27.7.1.2 (September 2008) 6363 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6364 * a guest IRET fault. 6365 * SDM 3: 23.2.2 (September 2008) 6366 * Bit 12 is undefined in any of the following cases: 6367 * If the VM exit sets the valid bit in the IDT-vectoring 6368 * information field. 6369 * If the VM exit is due to a double fault. 6370 */ 6371 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6372 vector != DF_VECTOR && !idtv_info_valid) 6373 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6374 GUEST_INTR_STATE_NMI); 6375 else 6376 vmx->loaded_vmcs->nmi_known_unmasked = 6377 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6378 & GUEST_INTR_STATE_NMI); 6379 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6380 vmx->loaded_vmcs->vnmi_blocked_time += 6381 ktime_to_ns(ktime_sub(ktime_get(), 6382 vmx->loaded_vmcs->entry_time)); 6383 } 6384 6385 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6386 u32 idt_vectoring_info, 6387 int instr_len_field, 6388 int error_code_field) 6389 { 6390 u8 vector; 6391 int type; 6392 bool idtv_info_valid; 6393 6394 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6395 6396 vcpu->arch.nmi_injected = false; 6397 kvm_clear_exception_queue(vcpu); 6398 kvm_clear_interrupt_queue(vcpu); 6399 6400 if (!idtv_info_valid) 6401 return; 6402 6403 kvm_make_request(KVM_REQ_EVENT, vcpu); 6404 6405 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6406 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6407 6408 switch (type) { 6409 case INTR_TYPE_NMI_INTR: 6410 vcpu->arch.nmi_injected = true; 6411 /* 6412 * SDM 3: 27.7.1.2 (September 2008) 6413 * Clear bit "block by NMI" before VM entry if a NMI 6414 * delivery faulted. 6415 */ 6416 vmx_set_nmi_mask(vcpu, false); 6417 break; 6418 case INTR_TYPE_SOFT_EXCEPTION: 6419 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6420 /* fall through */ 6421 case INTR_TYPE_HARD_EXCEPTION: 6422 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6423 u32 err = vmcs_read32(error_code_field); 6424 kvm_requeue_exception_e(vcpu, vector, err); 6425 } else 6426 kvm_requeue_exception(vcpu, vector); 6427 break; 6428 case INTR_TYPE_SOFT_INTR: 6429 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6430 /* fall through */ 6431 case INTR_TYPE_EXT_INTR: 6432 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6433 break; 6434 default: 6435 break; 6436 } 6437 } 6438 6439 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6440 { 6441 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6442 VM_EXIT_INSTRUCTION_LEN, 6443 IDT_VECTORING_ERROR_CODE); 6444 } 6445 6446 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6447 { 6448 __vmx_complete_interrupts(vcpu, 6449 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6450 VM_ENTRY_INSTRUCTION_LEN, 6451 VM_ENTRY_EXCEPTION_ERROR_CODE); 6452 6453 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6454 } 6455 6456 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6457 { 6458 int i, nr_msrs; 6459 struct perf_guest_switch_msr *msrs; 6460 6461 msrs = perf_guest_get_msrs(&nr_msrs); 6462 6463 if (!msrs) 6464 return; 6465 6466 for (i = 0; i < nr_msrs; i++) 6467 if (msrs[i].host == msrs[i].guest) 6468 clear_atomic_switch_msr(vmx, msrs[i].msr); 6469 else 6470 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6471 msrs[i].host, false); 6472 } 6473 6474 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx) 6475 { 6476 u32 host_umwait_control; 6477 6478 if (!vmx_has_waitpkg(vmx)) 6479 return; 6480 6481 host_umwait_control = get_umwait_control_msr(); 6482 6483 if (vmx->msr_ia32_umwait_control != host_umwait_control) 6484 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL, 6485 vmx->msr_ia32_umwait_control, 6486 host_umwait_control, false); 6487 else 6488 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL); 6489 } 6490 6491 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6492 { 6493 struct vcpu_vmx *vmx = to_vmx(vcpu); 6494 u64 tscl; 6495 u32 delta_tsc; 6496 6497 if (vmx->req_immediate_exit) { 6498 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); 6499 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6500 } else if (vmx->hv_deadline_tsc != -1) { 6501 tscl = rdtsc(); 6502 if (vmx->hv_deadline_tsc > tscl) 6503 /* set_hv_timer ensures the delta fits in 32-bits */ 6504 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6505 cpu_preemption_timer_multi); 6506 else 6507 delta_tsc = 0; 6508 6509 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); 6510 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6511 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { 6512 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); 6513 vmx->loaded_vmcs->hv_timer_soft_disabled = true; 6514 } 6515 } 6516 6517 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6518 { 6519 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6520 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6521 vmcs_writel(HOST_RSP, host_rsp); 6522 } 6523 } 6524 6525 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6526 6527 static void vmx_vcpu_run(struct kvm_vcpu *vcpu) 6528 { 6529 struct vcpu_vmx *vmx = to_vmx(vcpu); 6530 unsigned long cr3, cr4; 6531 6532 /* Record the guest's net vcpu time for enforced NMI injections. */ 6533 if (unlikely(!enable_vnmi && 6534 vmx->loaded_vmcs->soft_vnmi_blocked)) 6535 vmx->loaded_vmcs->entry_time = ktime_get(); 6536 6537 /* Don't enter VMX if guest state is invalid, let the exit handler 6538 start emulation until we arrive back to a valid state */ 6539 if (vmx->emulation_required) 6540 return; 6541 6542 if (vmx->ple_window_dirty) { 6543 vmx->ple_window_dirty = false; 6544 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6545 } 6546 6547 /* 6548 * We did this in prepare_switch_to_guest, because it needs to 6549 * be within srcu_read_lock. 6550 */ 6551 WARN_ON_ONCE(vmx->nested.need_vmcs12_to_shadow_sync); 6552 6553 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP)) 6554 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6555 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP)) 6556 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6557 6558 cr3 = __get_current_cr3_fast(); 6559 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6560 vmcs_writel(HOST_CR3, cr3); 6561 vmx->loaded_vmcs->host_state.cr3 = cr3; 6562 } 6563 6564 cr4 = cr4_read_shadow(); 6565 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6566 vmcs_writel(HOST_CR4, cr4); 6567 vmx->loaded_vmcs->host_state.cr4 = cr4; 6568 } 6569 6570 /* When single-stepping over STI and MOV SS, we must clear the 6571 * corresponding interruptibility bits in the guest state. Otherwise 6572 * vmentry fails as it then expects bit 14 (BS) in pending debug 6573 * exceptions being set, but that's not correct for the guest debugging 6574 * case. */ 6575 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6576 vmx_set_interrupt_shadow(vcpu, 0); 6577 6578 kvm_load_guest_xsave_state(vcpu); 6579 6580 if (static_cpu_has(X86_FEATURE_PKU) && 6581 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && 6582 vcpu->arch.pkru != vmx->host_pkru) 6583 __write_pkru(vcpu->arch.pkru); 6584 6585 pt_guest_enter(vmx); 6586 6587 if (vcpu_to_pmu(vcpu)->version) 6588 atomic_switch_perf_msrs(vmx); 6589 atomic_switch_umwait_control_msr(vmx); 6590 6591 if (enable_preemption_timer) 6592 vmx_update_hv_timer(vcpu); 6593 6594 if (lapic_in_kernel(vcpu) && 6595 vcpu->arch.apic->lapic_timer.timer_advance_ns) 6596 kvm_wait_lapic_expire(vcpu); 6597 6598 /* 6599 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6600 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6601 * is no need to worry about the conditional branch over the wrmsr 6602 * being speculatively taken. 6603 */ 6604 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6605 6606 /* L1D Flush includes CPU buffer clear to mitigate MDS */ 6607 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6608 vmx_l1d_flush(vcpu); 6609 else if (static_branch_unlikely(&mds_user_clear)) 6610 mds_clear_cpu_buffers(); 6611 6612 if (vcpu->arch.cr2 != read_cr2()) 6613 write_cr2(vcpu->arch.cr2); 6614 6615 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6616 vmx->loaded_vmcs->launched); 6617 6618 vcpu->arch.cr2 = read_cr2(); 6619 6620 /* 6621 * We do not use IBRS in the kernel. If this vCPU has used the 6622 * SPEC_CTRL MSR it may have left it on; save the value and 6623 * turn it off. This is much more efficient than blindly adding 6624 * it to the atomic save/restore list. Especially as the former 6625 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6626 * 6627 * For non-nested case: 6628 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6629 * save it. 6630 * 6631 * For nested case: 6632 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6633 * save it. 6634 */ 6635 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6636 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6637 6638 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6639 6640 /* All fields are clean at this point */ 6641 if (static_branch_unlikely(&enable_evmcs)) 6642 current_evmcs->hv_clean_fields |= 6643 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6644 6645 if (static_branch_unlikely(&enable_evmcs)) 6646 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; 6647 6648 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6649 if (vmx->host_debugctlmsr) 6650 update_debugctlmsr(vmx->host_debugctlmsr); 6651 6652 #ifndef CONFIG_X86_64 6653 /* 6654 * The sysexit path does not restore ds/es, so we must set them to 6655 * a reasonable value ourselves. 6656 * 6657 * We can't defer this to vmx_prepare_switch_to_host() since that 6658 * function may be executed in interrupt context, which saves and 6659 * restore segments around it, nullifying its effect. 6660 */ 6661 loadsegment(ds, __USER_DS); 6662 loadsegment(es, __USER_DS); 6663 #endif 6664 6665 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 6666 | (1 << VCPU_EXREG_RFLAGS) 6667 | (1 << VCPU_EXREG_PDPTR) 6668 | (1 << VCPU_EXREG_SEGMENTS) 6669 | (1 << VCPU_EXREG_CR3)); 6670 vcpu->arch.regs_dirty = 0; 6671 6672 pt_guest_exit(vmx); 6673 6674 /* 6675 * eager fpu is enabled if PKEY is supported and CR4 is switched 6676 * back on host, so it is safe to read guest PKRU from current 6677 * XSAVE. 6678 */ 6679 if (static_cpu_has(X86_FEATURE_PKU) && 6680 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { 6681 vcpu->arch.pkru = rdpkru(); 6682 if (vcpu->arch.pkru != vmx->host_pkru) 6683 __write_pkru(vmx->host_pkru); 6684 } 6685 6686 kvm_load_host_xsave_state(vcpu); 6687 6688 vmx->nested.nested_run_pending = 0; 6689 vmx->idt_vectoring_info = 0; 6690 6691 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); 6692 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) 6693 kvm_machine_check(); 6694 6695 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6696 return; 6697 6698 vmx->loaded_vmcs->launched = 1; 6699 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6700 6701 vmx_recover_nmi_blocking(vmx); 6702 vmx_complete_interrupts(vmx); 6703 } 6704 6705 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6706 { 6707 struct vcpu_vmx *vmx = to_vmx(vcpu); 6708 6709 if (enable_pml) 6710 vmx_destroy_pml_buffer(vmx); 6711 free_vpid(vmx->vpid); 6712 nested_vmx_free_vcpu(vcpu); 6713 free_loaded_vmcs(vmx->loaded_vmcs); 6714 } 6715 6716 static int vmx_create_vcpu(struct kvm_vcpu *vcpu) 6717 { 6718 struct vcpu_vmx *vmx; 6719 unsigned long *msr_bitmap; 6720 int i, cpu, err; 6721 6722 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0); 6723 vmx = to_vmx(vcpu); 6724 6725 err = -ENOMEM; 6726 6727 vmx->vpid = allocate_vpid(); 6728 6729 /* 6730 * If PML is turned on, failure on enabling PML just results in failure 6731 * of creating the vcpu, therefore we can simplify PML logic (by 6732 * avoiding dealing with cases, such as enabling PML partially on vcpus 6733 * for the guest), etc. 6734 */ 6735 if (enable_pml) { 6736 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6737 if (!vmx->pml_pg) 6738 goto free_vpid; 6739 } 6740 6741 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS); 6742 6743 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { 6744 u32 index = vmx_msr_index[i]; 6745 u32 data_low, data_high; 6746 int j = vmx->nmsrs; 6747 6748 if (rdmsr_safe(index, &data_low, &data_high) < 0) 6749 continue; 6750 if (wrmsr_safe(index, data_low, data_high) < 0) 6751 continue; 6752 6753 vmx->guest_msrs[j].index = i; 6754 vmx->guest_msrs[j].data = 0; 6755 switch (index) { 6756 case MSR_IA32_TSX_CTRL: 6757 /* 6758 * No need to pass TSX_CTRL_CPUID_CLEAR through, so 6759 * let's avoid changing CPUID bits under the host 6760 * kernel's feet. 6761 */ 6762 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR; 6763 break; 6764 default: 6765 vmx->guest_msrs[j].mask = -1ull; 6766 break; 6767 } 6768 ++vmx->nmsrs; 6769 } 6770 6771 err = alloc_loaded_vmcs(&vmx->vmcs01); 6772 if (err < 0) 6773 goto free_pml; 6774 6775 msr_bitmap = vmx->vmcs01.msr_bitmap; 6776 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R); 6777 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); 6778 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); 6779 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6780 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6781 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6782 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6783 if (kvm_cstate_in_guest(vcpu->kvm)) { 6784 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R); 6785 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); 6786 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); 6787 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); 6788 } 6789 vmx->msr_bitmap_mode = 0; 6790 6791 vmx->loaded_vmcs = &vmx->vmcs01; 6792 cpu = get_cpu(); 6793 vmx_vcpu_load(vcpu, cpu); 6794 vcpu->cpu = cpu; 6795 init_vmcs(vmx); 6796 vmx_vcpu_put(vcpu); 6797 put_cpu(); 6798 if (cpu_need_virtualize_apic_accesses(vcpu)) { 6799 err = alloc_apic_access_page(vcpu->kvm); 6800 if (err) 6801 goto free_vmcs; 6802 } 6803 6804 if (enable_ept && !enable_unrestricted_guest) { 6805 err = init_rmode_identity_map(vcpu->kvm); 6806 if (err) 6807 goto free_vmcs; 6808 } 6809 6810 if (nested) 6811 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, 6812 vmx_capability.ept); 6813 else 6814 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6815 6816 vmx->nested.posted_intr_nv = -1; 6817 vmx->nested.current_vmptr = -1ull; 6818 6819 vcpu->arch.microcode_version = 0x100000000ULL; 6820 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED; 6821 6822 /* 6823 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6824 * or POSTED_INTR_WAKEUP_VECTOR. 6825 */ 6826 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6827 vmx->pi_desc.sn = 1; 6828 6829 vmx->ept_pointer = INVALID_PAGE; 6830 6831 return 0; 6832 6833 free_vmcs: 6834 free_loaded_vmcs(vmx->loaded_vmcs); 6835 free_pml: 6836 vmx_destroy_pml_buffer(vmx); 6837 free_vpid: 6838 free_vpid(vmx->vpid); 6839 return err; 6840 } 6841 6842 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6843 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6844 6845 static int vmx_vm_init(struct kvm *kvm) 6846 { 6847 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6848 6849 if (!ple_gap) 6850 kvm->arch.pause_in_guest = true; 6851 6852 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6853 switch (l1tf_mitigation) { 6854 case L1TF_MITIGATION_OFF: 6855 case L1TF_MITIGATION_FLUSH_NOWARN: 6856 /* 'I explicitly don't care' is set */ 6857 break; 6858 case L1TF_MITIGATION_FLUSH: 6859 case L1TF_MITIGATION_FLUSH_NOSMT: 6860 case L1TF_MITIGATION_FULL: 6861 /* 6862 * Warn upon starting the first VM in a potentially 6863 * insecure environment. 6864 */ 6865 if (sched_smt_active()) 6866 pr_warn_once(L1TF_MSG_SMT); 6867 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6868 pr_warn_once(L1TF_MSG_L1D); 6869 break; 6870 case L1TF_MITIGATION_FULL_FORCE: 6871 /* Flush is enforced */ 6872 break; 6873 } 6874 } 6875 kvm_apicv_init(kvm, enable_apicv); 6876 return 0; 6877 } 6878 6879 static int __init vmx_check_processor_compat(void) 6880 { 6881 struct vmcs_config vmcs_conf; 6882 struct vmx_capability vmx_cap; 6883 6884 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 6885 !this_cpu_has(X86_FEATURE_VMX)) { 6886 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id()); 6887 return -EIO; 6888 } 6889 6890 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 6891 return -EIO; 6892 if (nested) 6893 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept); 6894 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 6895 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 6896 smp_processor_id()); 6897 return -EIO; 6898 } 6899 return 0; 6900 } 6901 6902 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 6903 { 6904 u8 cache; 6905 u64 ipat = 0; 6906 6907 /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in 6908 * memory aliases with conflicting memory types and sometimes MCEs. 6909 * We have to be careful as to what are honored and when. 6910 * 6911 * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to 6912 * UC. The effective memory type is UC or WC depending on guest PAT. 6913 * This was historically the source of MCEs and we want to be 6914 * conservative. 6915 * 6916 * When there is no need to deal with noncoherent DMA (e.g., no VT-d 6917 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The 6918 * EPT memory type is set to WB. The effective memory type is forced 6919 * WB. 6920 * 6921 * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The 6922 * EPT memory type is used to emulate guest CD/MTRR. 6923 */ 6924 6925 if (is_mmio) { 6926 cache = MTRR_TYPE_UNCACHABLE; 6927 goto exit; 6928 } 6929 6930 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 6931 ipat = VMX_EPT_IPAT_BIT; 6932 cache = MTRR_TYPE_WRBACK; 6933 goto exit; 6934 } 6935 6936 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 6937 ipat = VMX_EPT_IPAT_BIT; 6938 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 6939 cache = MTRR_TYPE_WRBACK; 6940 else 6941 cache = MTRR_TYPE_UNCACHABLE; 6942 goto exit; 6943 } 6944 6945 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 6946 6947 exit: 6948 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 6949 } 6950 6951 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) 6952 { 6953 /* 6954 * These bits in the secondary execution controls field 6955 * are dynamic, the others are mostly based on the hypervisor 6956 * architecture and the guest's CPUID. Do not touch the 6957 * dynamic bits. 6958 */ 6959 u32 mask = 6960 SECONDARY_EXEC_SHADOW_VMCS | 6961 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6962 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6963 SECONDARY_EXEC_DESC; 6964 6965 u32 new_ctl = vmx->secondary_exec_control; 6966 u32 cur_ctl = secondary_exec_controls_get(vmx); 6967 6968 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); 6969 } 6970 6971 /* 6972 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 6973 * (indicating "allowed-1") if they are supported in the guest's CPUID. 6974 */ 6975 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 6976 { 6977 struct vcpu_vmx *vmx = to_vmx(vcpu); 6978 struct kvm_cpuid_entry2 *entry; 6979 6980 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 6981 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 6982 6983 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 6984 if (entry && (entry->_reg & (_cpuid_mask))) \ 6985 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 6986 } while (0) 6987 6988 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 6989 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME)); 6990 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME)); 6991 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC)); 6992 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE)); 6993 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE)); 6994 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE)); 6995 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE)); 6996 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE)); 6997 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR)); 6998 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM)); 6999 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX)); 7000 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX)); 7001 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID)); 7002 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE)); 7003 7004 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 7005 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE)); 7006 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP)); 7007 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP)); 7008 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU)); 7009 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP)); 7010 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57)); 7011 7012 #undef cr4_fixed1_update 7013 } 7014 7015 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 7016 { 7017 struct vcpu_vmx *vmx = to_vmx(vcpu); 7018 7019 if (kvm_mpx_supported()) { 7020 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 7021 7022 if (mpx_enabled) { 7023 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 7024 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 7025 } else { 7026 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 7027 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 7028 } 7029 } 7030 } 7031 7032 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 7033 { 7034 struct vcpu_vmx *vmx = to_vmx(vcpu); 7035 struct kvm_cpuid_entry2 *best = NULL; 7036 int i; 7037 7038 for (i = 0; i < PT_CPUID_LEAVES; i++) { 7039 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 7040 if (!best) 7041 return; 7042 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 7043 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 7044 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 7045 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 7046 } 7047 7048 /* Get the number of configurable Address Ranges for filtering */ 7049 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 7050 PT_CAP_num_address_ranges); 7051 7052 /* Initialize and clear the no dependency bits */ 7053 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 7054 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 7055 7056 /* 7057 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 7058 * will inject an #GP 7059 */ 7060 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 7061 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 7062 7063 /* 7064 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 7065 * PSBFreq can be set 7066 */ 7067 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 7068 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 7069 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 7070 7071 /* 7072 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 7073 * MTCFreq can be set 7074 */ 7075 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 7076 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 7077 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 7078 7079 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 7080 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 7081 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 7082 RTIT_CTL_PTW_EN); 7083 7084 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 7085 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 7086 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 7087 7088 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 7089 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 7090 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 7091 7092 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 7093 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 7094 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 7095 7096 /* unmask address range configure area */ 7097 for (i = 0; i < vmx->pt_desc.addr_range; i++) 7098 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 7099 } 7100 7101 static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 7102 { 7103 struct vcpu_vmx *vmx = to_vmx(vcpu); 7104 7105 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */ 7106 vcpu->arch.xsaves_enabled = false; 7107 7108 if (cpu_has_secondary_exec_ctrls()) { 7109 vmx_compute_secondary_exec_control(vmx); 7110 vmcs_set_secondary_exec_control(vmx); 7111 } 7112 7113 if (nested_vmx_allowed(vcpu)) 7114 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7115 FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7116 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 7117 else 7118 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7119 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7120 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX); 7121 7122 if (nested_vmx_allowed(vcpu)) { 7123 nested_vmx_cr_fixed1_bits_update(vcpu); 7124 nested_vmx_entry_exit_ctls_update(vcpu); 7125 } 7126 7127 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 7128 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 7129 update_intel_pt_cfg(vcpu); 7130 7131 if (boot_cpu_has(X86_FEATURE_RTM)) { 7132 struct shared_msr_entry *msr; 7133 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL); 7134 if (msr) { 7135 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM); 7136 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE); 7137 } 7138 } 7139 } 7140 7141 static __init void vmx_set_cpu_caps(void) 7142 { 7143 kvm_set_cpu_caps(); 7144 7145 /* CPUID 0x1 */ 7146 if (nested) 7147 kvm_cpu_cap_set(X86_FEATURE_VMX); 7148 7149 /* CPUID 0x7 */ 7150 if (kvm_mpx_supported()) 7151 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX); 7152 if (cpu_has_vmx_invpcid()) 7153 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID); 7154 if (vmx_pt_mode_is_host_guest()) 7155 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT); 7156 7157 /* PKU is not yet implemented for shadow paging. */ 7158 if (enable_ept && boot_cpu_has(X86_FEATURE_OSPKE)) 7159 kvm_cpu_cap_check_and_set(X86_FEATURE_PKU); 7160 7161 if (vmx_umip_emulated()) 7162 kvm_cpu_cap_set(X86_FEATURE_UMIP); 7163 7164 /* CPUID 0xD.1 */ 7165 supported_xss = 0; 7166 if (!vmx_xsaves_supported()) 7167 kvm_cpu_cap_clear(X86_FEATURE_XSAVES); 7168 7169 /* CPUID 0x80000001 */ 7170 if (!cpu_has_vmx_rdtscp()) 7171 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 7172 } 7173 7174 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 7175 { 7176 to_vmx(vcpu)->req_immediate_exit = true; 7177 } 7178 7179 static int vmx_check_intercept_io(struct kvm_vcpu *vcpu, 7180 struct x86_instruction_info *info) 7181 { 7182 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7183 unsigned short port; 7184 bool intercept; 7185 int size; 7186 7187 if (info->intercept == x86_intercept_in || 7188 info->intercept == x86_intercept_ins) { 7189 port = info->src_val; 7190 size = info->dst_bytes; 7191 } else { 7192 port = info->dst_val; 7193 size = info->src_bytes; 7194 } 7195 7196 /* 7197 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction 7198 * VM-exits depend on the 'unconditional IO exiting' VM-execution 7199 * control. 7200 * 7201 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps. 7202 */ 7203 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) 7204 intercept = nested_cpu_has(vmcs12, 7205 CPU_BASED_UNCOND_IO_EXITING); 7206 else 7207 intercept = nested_vmx_check_io_bitmaps(vcpu, port, size); 7208 7209 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7210 return intercept ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; 7211 } 7212 7213 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 7214 struct x86_instruction_info *info, 7215 enum x86_intercept_stage stage, 7216 struct x86_exception *exception) 7217 { 7218 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7219 7220 switch (info->intercept) { 7221 /* 7222 * RDPID causes #UD if disabled through secondary execution controls. 7223 * Because it is marked as EmulateOnUD, we need to intercept it here. 7224 */ 7225 case x86_intercept_rdtscp: 7226 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { 7227 exception->vector = UD_VECTOR; 7228 exception->error_code_valid = false; 7229 return X86EMUL_PROPAGATE_FAULT; 7230 } 7231 break; 7232 7233 case x86_intercept_in: 7234 case x86_intercept_ins: 7235 case x86_intercept_out: 7236 case x86_intercept_outs: 7237 return vmx_check_intercept_io(vcpu, info); 7238 7239 case x86_intercept_lgdt: 7240 case x86_intercept_lidt: 7241 case x86_intercept_lldt: 7242 case x86_intercept_ltr: 7243 case x86_intercept_sgdt: 7244 case x86_intercept_sidt: 7245 case x86_intercept_sldt: 7246 case x86_intercept_str: 7247 if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC)) 7248 return X86EMUL_CONTINUE; 7249 7250 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ 7251 break; 7252 7253 /* TODO: check more intercepts... */ 7254 default: 7255 break; 7256 } 7257 7258 return X86EMUL_UNHANDLEABLE; 7259 } 7260 7261 #ifdef CONFIG_X86_64 7262 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 7263 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 7264 u64 divisor, u64 *result) 7265 { 7266 u64 low = a << shift, high = a >> (64 - shift); 7267 7268 /* To avoid the overflow on divq */ 7269 if (high >= divisor) 7270 return 1; 7271 7272 /* Low hold the result, high hold rem which is discarded */ 7273 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7274 "rm" (divisor), "0" (low), "1" (high)); 7275 *result = low; 7276 7277 return 0; 7278 } 7279 7280 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 7281 bool *expired) 7282 { 7283 struct vcpu_vmx *vmx; 7284 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7285 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; 7286 7287 if (kvm_mwait_in_guest(vcpu->kvm) || 7288 kvm_can_post_timer_interrupt(vcpu)) 7289 return -EOPNOTSUPP; 7290 7291 vmx = to_vmx(vcpu); 7292 tscl = rdtsc(); 7293 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7294 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7295 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, 7296 ktimer->timer_advance_ns); 7297 7298 if (delta_tsc > lapic_timer_advance_cycles) 7299 delta_tsc -= lapic_timer_advance_cycles; 7300 else 7301 delta_tsc = 0; 7302 7303 /* Convert to host delta tsc if tsc scaling is enabled */ 7304 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7305 delta_tsc && u64_shl_div_u64(delta_tsc, 7306 kvm_tsc_scaling_ratio_frac_bits, 7307 vcpu->arch.tsc_scaling_ratio, &delta_tsc)) 7308 return -ERANGE; 7309 7310 /* 7311 * If the delta tsc can't fit in the 32 bit after the multi shift, 7312 * we can't use the preemption timer. 7313 * It's possible that it fits on later vmentries, but checking 7314 * on every vmentry is costly so we just use an hrtimer. 7315 */ 7316 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7317 return -ERANGE; 7318 7319 vmx->hv_deadline_tsc = tscl + delta_tsc; 7320 *expired = !delta_tsc; 7321 return 0; 7322 } 7323 7324 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7325 { 7326 to_vmx(vcpu)->hv_deadline_tsc = -1; 7327 } 7328 #endif 7329 7330 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7331 { 7332 if (!kvm_pause_in_guest(vcpu->kvm)) 7333 shrink_ple_window(vcpu); 7334 } 7335 7336 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7337 struct kvm_memory_slot *slot) 7338 { 7339 if (!kvm_dirty_log_manual_protect_and_init_set(kvm)) 7340 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7341 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7342 } 7343 7344 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7345 struct kvm_memory_slot *slot) 7346 { 7347 kvm_mmu_slot_set_dirty(kvm, slot); 7348 } 7349 7350 static void vmx_flush_log_dirty(struct kvm *kvm) 7351 { 7352 kvm_flush_pml_buffers(kvm); 7353 } 7354 7355 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) 7356 { 7357 struct vmcs12 *vmcs12; 7358 struct vcpu_vmx *vmx = to_vmx(vcpu); 7359 gpa_t gpa, dst; 7360 7361 if (is_guest_mode(vcpu)) { 7362 WARN_ON_ONCE(vmx->nested.pml_full); 7363 7364 /* 7365 * Check if PML is enabled for the nested guest. 7366 * Whether eptp bit 6 is set is already checked 7367 * as part of A/D emulation. 7368 */ 7369 vmcs12 = get_vmcs12(vcpu); 7370 if (!nested_cpu_has_pml(vmcs12)) 7371 return 0; 7372 7373 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 7374 vmx->nested.pml_full = true; 7375 return 1; 7376 } 7377 7378 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; 7379 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 7380 7381 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 7382 offset_in_page(dst), sizeof(gpa))) 7383 return 0; 7384 7385 vmcs12->guest_pml_index--; 7386 } 7387 7388 return 0; 7389 } 7390 7391 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7392 struct kvm_memory_slot *memslot, 7393 gfn_t offset, unsigned long mask) 7394 { 7395 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7396 } 7397 7398 static void __pi_post_block(struct kvm_vcpu *vcpu) 7399 { 7400 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7401 struct pi_desc old, new; 7402 unsigned int dest; 7403 7404 do { 7405 old.control = new.control = pi_desc->control; 7406 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, 7407 "Wakeup handler not enabled while the VCPU is blocked\n"); 7408 7409 dest = cpu_physical_id(vcpu->cpu); 7410 7411 if (x2apic_enabled()) 7412 new.ndst = dest; 7413 else 7414 new.ndst = (dest << 8) & 0xFF00; 7415 7416 /* set 'NV' to 'notification vector' */ 7417 new.nv = POSTED_INTR_VECTOR; 7418 } while (cmpxchg64(&pi_desc->control, old.control, 7419 new.control) != old.control); 7420 7421 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { 7422 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7423 list_del(&vcpu->blocked_vcpu_list); 7424 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7425 vcpu->pre_pcpu = -1; 7426 } 7427 } 7428 7429 /* 7430 * This routine does the following things for vCPU which is going 7431 * to be blocked if VT-d PI is enabled. 7432 * - Store the vCPU to the wakeup list, so when interrupts happen 7433 * we can find the right vCPU to wake up. 7434 * - Change the Posted-interrupt descriptor as below: 7435 * 'NDST' <-- vcpu->pre_pcpu 7436 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR 7437 * - If 'ON' is set during this process, which means at least one 7438 * interrupt is posted for this vCPU, we cannot block it, in 7439 * this case, return 1, otherwise, return 0. 7440 * 7441 */ 7442 static int pi_pre_block(struct kvm_vcpu *vcpu) 7443 { 7444 unsigned int dest; 7445 struct pi_desc old, new; 7446 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7447 7448 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 7449 !irq_remapping_cap(IRQ_POSTING_CAP) || 7450 !kvm_vcpu_apicv_active(vcpu)) 7451 return 0; 7452 7453 WARN_ON(irqs_disabled()); 7454 local_irq_disable(); 7455 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { 7456 vcpu->pre_pcpu = vcpu->cpu; 7457 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7458 list_add_tail(&vcpu->blocked_vcpu_list, 7459 &per_cpu(blocked_vcpu_on_cpu, 7460 vcpu->pre_pcpu)); 7461 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7462 } 7463 7464 do { 7465 old.control = new.control = pi_desc->control; 7466 7467 WARN((pi_desc->sn == 1), 7468 "Warning: SN field of posted-interrupts " 7469 "is set before blocking\n"); 7470 7471 /* 7472 * Since vCPU can be preempted during this process, 7473 * vcpu->cpu could be different with pre_pcpu, we 7474 * need to set pre_pcpu as the destination of wakeup 7475 * notification event, then we can find the right vCPU 7476 * to wakeup in wakeup handler if interrupts happen 7477 * when the vCPU is in blocked state. 7478 */ 7479 dest = cpu_physical_id(vcpu->pre_pcpu); 7480 7481 if (x2apic_enabled()) 7482 new.ndst = dest; 7483 else 7484 new.ndst = (dest << 8) & 0xFF00; 7485 7486 /* set 'NV' to 'wakeup vector' */ 7487 new.nv = POSTED_INTR_WAKEUP_VECTOR; 7488 } while (cmpxchg64(&pi_desc->control, old.control, 7489 new.control) != old.control); 7490 7491 /* We should not block the vCPU if an interrupt is posted for it. */ 7492 if (pi_test_on(pi_desc) == 1) 7493 __pi_post_block(vcpu); 7494 7495 local_irq_enable(); 7496 return (vcpu->pre_pcpu == -1); 7497 } 7498 7499 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7500 { 7501 if (pi_pre_block(vcpu)) 7502 return 1; 7503 7504 if (kvm_lapic_hv_timer_in_use(vcpu)) 7505 kvm_lapic_switch_to_sw_timer(vcpu); 7506 7507 return 0; 7508 } 7509 7510 static void pi_post_block(struct kvm_vcpu *vcpu) 7511 { 7512 if (vcpu->pre_pcpu == -1) 7513 return; 7514 7515 WARN_ON(irqs_disabled()); 7516 local_irq_disable(); 7517 __pi_post_block(vcpu); 7518 local_irq_enable(); 7519 } 7520 7521 static void vmx_post_block(struct kvm_vcpu *vcpu) 7522 { 7523 if (kvm_x86_ops.set_hv_timer) 7524 kvm_lapic_switch_to_hv_timer(vcpu); 7525 7526 pi_post_block(vcpu); 7527 } 7528 7529 /* 7530 * vmx_update_pi_irte - set IRTE for Posted-Interrupts 7531 * 7532 * @kvm: kvm 7533 * @host_irq: host irq of the interrupt 7534 * @guest_irq: gsi of the interrupt 7535 * @set: set or unset PI 7536 * returns 0 on success, < 0 on failure 7537 */ 7538 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 7539 uint32_t guest_irq, bool set) 7540 { 7541 struct kvm_kernel_irq_routing_entry *e; 7542 struct kvm_irq_routing_table *irq_rt; 7543 struct kvm_lapic_irq irq; 7544 struct kvm_vcpu *vcpu; 7545 struct vcpu_data vcpu_info; 7546 int idx, ret = 0; 7547 7548 if (!kvm_arch_has_assigned_device(kvm) || 7549 !irq_remapping_cap(IRQ_POSTING_CAP) || 7550 !kvm_vcpu_apicv_active(kvm->vcpus[0])) 7551 return 0; 7552 7553 idx = srcu_read_lock(&kvm->irq_srcu); 7554 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 7555 if (guest_irq >= irq_rt->nr_rt_entries || 7556 hlist_empty(&irq_rt->map[guest_irq])) { 7557 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", 7558 guest_irq, irq_rt->nr_rt_entries); 7559 goto out; 7560 } 7561 7562 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 7563 if (e->type != KVM_IRQ_ROUTING_MSI) 7564 continue; 7565 /* 7566 * VT-d PI cannot support posting multicast/broadcast 7567 * interrupts to a vCPU, we still use interrupt remapping 7568 * for these kind of interrupts. 7569 * 7570 * For lowest-priority interrupts, we only support 7571 * those with single CPU as the destination, e.g. user 7572 * configures the interrupts via /proc/irq or uses 7573 * irqbalance to make the interrupts single-CPU. 7574 * 7575 * We will support full lowest-priority interrupt later. 7576 * 7577 * In addition, we can only inject generic interrupts using 7578 * the PI mechanism, refuse to route others through it. 7579 */ 7580 7581 kvm_set_msi_irq(kvm, e, &irq); 7582 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || 7583 !kvm_irq_is_postable(&irq)) { 7584 /* 7585 * Make sure the IRTE is in remapped mode if 7586 * we don't handle it in posted mode. 7587 */ 7588 ret = irq_set_vcpu_affinity(host_irq, NULL); 7589 if (ret < 0) { 7590 printk(KERN_INFO 7591 "failed to back to remapped mode, irq: %u\n", 7592 host_irq); 7593 goto out; 7594 } 7595 7596 continue; 7597 } 7598 7599 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); 7600 vcpu_info.vector = irq.vector; 7601 7602 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, 7603 vcpu_info.vector, vcpu_info.pi_desc_addr, set); 7604 7605 if (set) 7606 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); 7607 else 7608 ret = irq_set_vcpu_affinity(host_irq, NULL); 7609 7610 if (ret < 0) { 7611 printk(KERN_INFO "%s: failed to update PI IRTE\n", 7612 __func__); 7613 goto out; 7614 } 7615 } 7616 7617 ret = 0; 7618 out: 7619 srcu_read_unlock(&kvm->irq_srcu, idx); 7620 return ret; 7621 } 7622 7623 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7624 { 7625 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7626 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7627 FEAT_CTL_LMCE_ENABLED; 7628 else 7629 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7630 ~FEAT_CTL_LMCE_ENABLED; 7631 } 7632 7633 static int vmx_smi_allowed(struct kvm_vcpu *vcpu) 7634 { 7635 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7636 if (to_vmx(vcpu)->nested.nested_run_pending) 7637 return 0; 7638 return 1; 7639 } 7640 7641 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7642 { 7643 struct vcpu_vmx *vmx = to_vmx(vcpu); 7644 7645 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7646 if (vmx->nested.smm.guest_mode) 7647 nested_vmx_vmexit(vcpu, -1, 0, 0); 7648 7649 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7650 vmx->nested.vmxon = false; 7651 vmx_clear_hlt(vcpu); 7652 return 0; 7653 } 7654 7655 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) 7656 { 7657 struct vcpu_vmx *vmx = to_vmx(vcpu); 7658 int ret; 7659 7660 if (vmx->nested.smm.vmxon) { 7661 vmx->nested.vmxon = true; 7662 vmx->nested.smm.vmxon = false; 7663 } 7664 7665 if (vmx->nested.smm.guest_mode) { 7666 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7667 if (ret) 7668 return ret; 7669 7670 vmx->nested.smm.guest_mode = false; 7671 } 7672 return 0; 7673 } 7674 7675 static int enable_smi_window(struct kvm_vcpu *vcpu) 7676 { 7677 return 0; 7678 } 7679 7680 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) 7681 { 7682 return false; 7683 } 7684 7685 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 7686 { 7687 return to_vmx(vcpu)->nested.vmxon; 7688 } 7689 7690 static void hardware_unsetup(void) 7691 { 7692 if (nested) 7693 nested_vmx_hardware_unsetup(); 7694 7695 free_kvm_area(); 7696 } 7697 7698 static bool vmx_check_apicv_inhibit_reasons(ulong bit) 7699 { 7700 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) | 7701 BIT(APICV_INHIBIT_REASON_HYPERV); 7702 7703 return supported & BIT(bit); 7704 } 7705 7706 static struct kvm_x86_ops vmx_x86_ops __initdata = { 7707 .hardware_unsetup = hardware_unsetup, 7708 7709 .hardware_enable = hardware_enable, 7710 .hardware_disable = hardware_disable, 7711 .cpu_has_accelerated_tpr = report_flexpriority, 7712 .has_emulated_msr = vmx_has_emulated_msr, 7713 7714 .vm_size = sizeof(struct kvm_vmx), 7715 .vm_init = vmx_vm_init, 7716 7717 .vcpu_create = vmx_create_vcpu, 7718 .vcpu_free = vmx_free_vcpu, 7719 .vcpu_reset = vmx_vcpu_reset, 7720 7721 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7722 .vcpu_load = vmx_vcpu_load, 7723 .vcpu_put = vmx_vcpu_put, 7724 7725 .update_bp_intercept = update_exception_bitmap, 7726 .get_msr_feature = vmx_get_msr_feature, 7727 .get_msr = vmx_get_msr, 7728 .set_msr = vmx_set_msr, 7729 .get_segment_base = vmx_get_segment_base, 7730 .get_segment = vmx_get_segment, 7731 .set_segment = vmx_set_segment, 7732 .get_cpl = vmx_get_cpl, 7733 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7734 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, 7735 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, 7736 .set_cr0 = vmx_set_cr0, 7737 .set_cr4 = vmx_set_cr4, 7738 .set_efer = vmx_set_efer, 7739 .get_idt = vmx_get_idt, 7740 .set_idt = vmx_set_idt, 7741 .get_gdt = vmx_get_gdt, 7742 .set_gdt = vmx_set_gdt, 7743 .get_dr6 = vmx_get_dr6, 7744 .set_dr6 = vmx_set_dr6, 7745 .set_dr7 = vmx_set_dr7, 7746 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7747 .cache_reg = vmx_cache_reg, 7748 .get_rflags = vmx_get_rflags, 7749 .set_rflags = vmx_set_rflags, 7750 7751 .tlb_flush = vmx_flush_tlb, 7752 .tlb_flush_gva = vmx_flush_tlb_gva, 7753 7754 .run = vmx_vcpu_run, 7755 .handle_exit = vmx_handle_exit, 7756 .skip_emulated_instruction = vmx_skip_emulated_instruction, 7757 .update_emulated_instruction = vmx_update_emulated_instruction, 7758 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7759 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7760 .patch_hypercall = vmx_patch_hypercall, 7761 .set_irq = vmx_inject_irq, 7762 .set_nmi = vmx_inject_nmi, 7763 .queue_exception = vmx_queue_exception, 7764 .cancel_injection = vmx_cancel_injection, 7765 .interrupt_allowed = vmx_interrupt_allowed, 7766 .nmi_allowed = vmx_nmi_allowed, 7767 .get_nmi_mask = vmx_get_nmi_mask, 7768 .set_nmi_mask = vmx_set_nmi_mask, 7769 .enable_nmi_window = enable_nmi_window, 7770 .enable_irq_window = enable_irq_window, 7771 .update_cr8_intercept = update_cr8_intercept, 7772 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7773 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7774 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7775 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7776 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7777 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons, 7778 .hwapic_irr_update = vmx_hwapic_irr_update, 7779 .hwapic_isr_update = vmx_hwapic_isr_update, 7780 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7781 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7782 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7783 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, 7784 7785 .set_tss_addr = vmx_set_tss_addr, 7786 .set_identity_map_addr = vmx_set_identity_map_addr, 7787 .get_tdp_level = get_ept_level, 7788 .get_mt_mask = vmx_get_mt_mask, 7789 7790 .get_exit_info = vmx_get_exit_info, 7791 7792 .cpuid_update = vmx_cpuid_update, 7793 7794 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7795 7796 .read_l1_tsc_offset = vmx_read_l1_tsc_offset, 7797 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7798 7799 .load_mmu_pgd = vmx_load_mmu_pgd, 7800 7801 .check_intercept = vmx_check_intercept, 7802 .handle_exit_irqoff = vmx_handle_exit_irqoff, 7803 7804 .request_immediate_exit = vmx_request_immediate_exit, 7805 7806 .sched_in = vmx_sched_in, 7807 7808 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7809 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7810 .flush_log_dirty = vmx_flush_log_dirty, 7811 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7812 .write_log_dirty = vmx_write_pml_buffer, 7813 7814 .pre_block = vmx_pre_block, 7815 .post_block = vmx_post_block, 7816 7817 .pmu_ops = &intel_pmu_ops, 7818 7819 .update_pi_irte = vmx_update_pi_irte, 7820 7821 #ifdef CONFIG_X86_64 7822 .set_hv_timer = vmx_set_hv_timer, 7823 .cancel_hv_timer = vmx_cancel_hv_timer, 7824 #endif 7825 7826 .setup_mce = vmx_setup_mce, 7827 7828 .smi_allowed = vmx_smi_allowed, 7829 .pre_enter_smm = vmx_pre_enter_smm, 7830 .pre_leave_smm = vmx_pre_leave_smm, 7831 .enable_smi_window = enable_smi_window, 7832 7833 .check_nested_events = NULL, 7834 .get_nested_state = NULL, 7835 .set_nested_state = NULL, 7836 .get_vmcs12_pages = NULL, 7837 .nested_enable_evmcs = NULL, 7838 .nested_get_evmcs_version = NULL, 7839 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault, 7840 .apic_init_signal_blocked = vmx_apic_init_signal_blocked, 7841 }; 7842 7843 static __init int hardware_setup(void) 7844 { 7845 unsigned long host_bndcfgs; 7846 struct desc_ptr dt; 7847 int r, i, ept_lpage_level; 7848 7849 store_idt(&dt); 7850 host_idt_base = dt.address; 7851 7852 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) 7853 kvm_define_shared_msr(i, vmx_msr_index[i]); 7854 7855 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7856 return -EIO; 7857 7858 if (boot_cpu_has(X86_FEATURE_NX)) 7859 kvm_enable_efer_bits(EFER_NX); 7860 7861 if (boot_cpu_has(X86_FEATURE_MPX)) { 7862 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7863 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7864 } 7865 7866 if (!cpu_has_vmx_mpx()) 7867 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | 7868 XFEATURE_MASK_BNDCSR); 7869 7870 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 7871 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 7872 enable_vpid = 0; 7873 7874 if (!cpu_has_vmx_ept() || 7875 !cpu_has_vmx_ept_4levels() || 7876 !cpu_has_vmx_ept_mt_wb() || 7877 !cpu_has_vmx_invept_global()) 7878 enable_ept = 0; 7879 7880 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 7881 enable_ept_ad_bits = 0; 7882 7883 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 7884 enable_unrestricted_guest = 0; 7885 7886 if (!cpu_has_vmx_flexpriority()) 7887 flexpriority_enabled = 0; 7888 7889 if (!cpu_has_virtual_nmis()) 7890 enable_vnmi = 0; 7891 7892 /* 7893 * set_apic_access_page_addr() is used to reload apic access 7894 * page upon invalidation. No need to do anything if not 7895 * using the APIC_ACCESS_ADDR VMCS field. 7896 */ 7897 if (!flexpriority_enabled) 7898 vmx_x86_ops.set_apic_access_page_addr = NULL; 7899 7900 if (!cpu_has_vmx_tpr_shadow()) 7901 vmx_x86_ops.update_cr8_intercept = NULL; 7902 7903 #if IS_ENABLED(CONFIG_HYPERV) 7904 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 7905 && enable_ept) { 7906 vmx_x86_ops.tlb_remote_flush = hv_remote_flush_tlb; 7907 vmx_x86_ops.tlb_remote_flush_with_range = 7908 hv_remote_flush_tlb_with_range; 7909 } 7910 #endif 7911 7912 if (!cpu_has_vmx_ple()) { 7913 ple_gap = 0; 7914 ple_window = 0; 7915 ple_window_grow = 0; 7916 ple_window_max = 0; 7917 ple_window_shrink = 0; 7918 } 7919 7920 if (!cpu_has_vmx_apicv()) { 7921 enable_apicv = 0; 7922 vmx_x86_ops.sync_pir_to_irr = NULL; 7923 } 7924 7925 if (cpu_has_vmx_tsc_scaling()) { 7926 kvm_has_tsc_control = true; 7927 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 7928 kvm_tsc_scaling_ratio_frac_bits = 48; 7929 } 7930 7931 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 7932 7933 if (enable_ept) 7934 vmx_enable_tdp(); 7935 7936 if (!enable_ept) 7937 ept_lpage_level = 0; 7938 else if (cpu_has_vmx_ept_1g_page()) 7939 ept_lpage_level = PT_PDPE_LEVEL; 7940 else if (cpu_has_vmx_ept_2m_page()) 7941 ept_lpage_level = PT_DIRECTORY_LEVEL; 7942 else 7943 ept_lpage_level = PT_PAGE_TABLE_LEVEL; 7944 kvm_configure_mmu(enable_ept, ept_lpage_level); 7945 7946 /* 7947 * Only enable PML when hardware supports PML feature, and both EPT 7948 * and EPT A/D bit features are enabled -- PML depends on them to work. 7949 */ 7950 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 7951 enable_pml = 0; 7952 7953 if (!enable_pml) { 7954 vmx_x86_ops.slot_enable_log_dirty = NULL; 7955 vmx_x86_ops.slot_disable_log_dirty = NULL; 7956 vmx_x86_ops.flush_log_dirty = NULL; 7957 vmx_x86_ops.enable_log_dirty_pt_masked = NULL; 7958 } 7959 7960 if (!cpu_has_vmx_preemption_timer()) 7961 enable_preemption_timer = false; 7962 7963 if (enable_preemption_timer) { 7964 u64 use_timer_freq = 5000ULL * 1000 * 1000; 7965 u64 vmx_msr; 7966 7967 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 7968 cpu_preemption_timer_multi = 7969 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 7970 7971 if (tsc_khz) 7972 use_timer_freq = (u64)tsc_khz * 1000; 7973 use_timer_freq >>= cpu_preemption_timer_multi; 7974 7975 /* 7976 * KVM "disables" the preemption timer by setting it to its max 7977 * value. Don't use the timer if it might cause spurious exits 7978 * at a rate faster than 0.1 Hz (of uninterrupted guest time). 7979 */ 7980 if (use_timer_freq > 0xffffffffu / 10) 7981 enable_preemption_timer = false; 7982 } 7983 7984 if (!enable_preemption_timer) { 7985 vmx_x86_ops.set_hv_timer = NULL; 7986 vmx_x86_ops.cancel_hv_timer = NULL; 7987 vmx_x86_ops.request_immediate_exit = __kvm_request_immediate_exit; 7988 } 7989 7990 kvm_set_posted_intr_wakeup_handler(wakeup_handler); 7991 7992 kvm_mce_cap_supported |= MCG_LMCE_P; 7993 7994 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 7995 return -EINVAL; 7996 if (!enable_ept || !cpu_has_vmx_intel_pt()) 7997 pt_mode = PT_MODE_SYSTEM; 7998 7999 if (nested) { 8000 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 8001 vmx_capability.ept); 8002 8003 r = nested_vmx_hardware_setup(&vmx_x86_ops, 8004 kvm_vmx_exit_handlers); 8005 if (r) 8006 return r; 8007 } 8008 8009 vmx_set_cpu_caps(); 8010 8011 r = alloc_kvm_area(); 8012 if (r) 8013 nested_vmx_hardware_unsetup(); 8014 return r; 8015 } 8016 8017 static struct kvm_x86_init_ops vmx_init_ops __initdata = { 8018 .cpu_has_kvm_support = cpu_has_kvm_support, 8019 .disabled_by_bios = vmx_disabled_by_bios, 8020 .check_processor_compatibility = vmx_check_processor_compat, 8021 .hardware_setup = hardware_setup, 8022 8023 .runtime_ops = &vmx_x86_ops, 8024 }; 8025 8026 static void vmx_cleanup_l1d_flush(void) 8027 { 8028 if (vmx_l1d_flush_pages) { 8029 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 8030 vmx_l1d_flush_pages = NULL; 8031 } 8032 /* Restore state so sysfs ignores VMX */ 8033 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 8034 } 8035 8036 static void vmx_exit(void) 8037 { 8038 #ifdef CONFIG_KEXEC_CORE 8039 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 8040 synchronize_rcu(); 8041 #endif 8042 8043 kvm_exit(); 8044 8045 #if IS_ENABLED(CONFIG_HYPERV) 8046 if (static_branch_unlikely(&enable_evmcs)) { 8047 int cpu; 8048 struct hv_vp_assist_page *vp_ap; 8049 /* 8050 * Reset everything to support using non-enlightened VMCS 8051 * access later (e.g. when we reload the module with 8052 * enlightened_vmcs=0) 8053 */ 8054 for_each_online_cpu(cpu) { 8055 vp_ap = hv_get_vp_assist_page(cpu); 8056 8057 if (!vp_ap) 8058 continue; 8059 8060 vp_ap->nested_control.features.directhypercall = 0; 8061 vp_ap->current_nested_vmcs = 0; 8062 vp_ap->enlighten_vmentry = 0; 8063 } 8064 8065 static_branch_disable(&enable_evmcs); 8066 } 8067 #endif 8068 vmx_cleanup_l1d_flush(); 8069 } 8070 module_exit(vmx_exit); 8071 8072 static int __init vmx_init(void) 8073 { 8074 int r, cpu; 8075 8076 #if IS_ENABLED(CONFIG_HYPERV) 8077 /* 8078 * Enlightened VMCS usage should be recommended and the host needs 8079 * to support eVMCS v1 or above. We can also disable eVMCS support 8080 * with module parameter. 8081 */ 8082 if (enlightened_vmcs && 8083 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 8084 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 8085 KVM_EVMCS_VERSION) { 8086 int cpu; 8087 8088 /* Check that we have assist pages on all online CPUs */ 8089 for_each_online_cpu(cpu) { 8090 if (!hv_get_vp_assist_page(cpu)) { 8091 enlightened_vmcs = false; 8092 break; 8093 } 8094 } 8095 8096 if (enlightened_vmcs) { 8097 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 8098 static_branch_enable(&enable_evmcs); 8099 } 8100 8101 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) 8102 vmx_x86_ops.enable_direct_tlbflush 8103 = hv_enable_direct_tlbflush; 8104 8105 } else { 8106 enlightened_vmcs = false; 8107 } 8108 #endif 8109 8110 r = kvm_init(&vmx_init_ops, sizeof(struct vcpu_vmx), 8111 __alignof__(struct vcpu_vmx), THIS_MODULE); 8112 if (r) 8113 return r; 8114 8115 /* 8116 * Must be called after kvm_init() so enable_ept is properly set 8117 * up. Hand the parameter mitigation value in which was stored in 8118 * the pre module init parser. If no parameter was given, it will 8119 * contain 'auto' which will be turned into the default 'cond' 8120 * mitigation mode. 8121 */ 8122 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 8123 if (r) { 8124 vmx_exit(); 8125 return r; 8126 } 8127 8128 for_each_possible_cpu(cpu) { 8129 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 8130 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); 8131 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 8132 } 8133 8134 #ifdef CONFIG_KEXEC_CORE 8135 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 8136 crash_vmclear_local_loaded_vmcss); 8137 #endif 8138 vmx_check_vmcs12_offsets(); 8139 8140 return 0; 8141 } 8142 module_init(vmx_init); 8143