1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/module.h> 47 #include <linux/sched.h> 48 #include <linux/percpu.h> 49 #include <linux/bootmem.h> 50 #include <linux/err.h> 51 #include <linux/nmi.h> 52 #include <linux/tboot.h> 53 #include <linux/stackprotector.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 57 #include <asm/acpi.h> 58 #include <asm/desc.h> 59 #include <asm/nmi.h> 60 #include <asm/irq.h> 61 #include <asm/idle.h> 62 #include <asm/realmode.h> 63 #include <asm/cpu.h> 64 #include <asm/numa.h> 65 #include <asm/pgtable.h> 66 #include <asm/tlbflush.h> 67 #include <asm/mtrr.h> 68 #include <asm/mwait.h> 69 #include <asm/apic.h> 70 #include <asm/io_apic.h> 71 #include <asm/i387.h> 72 #include <asm/fpu-internal.h> 73 #include <asm/setup.h> 74 #include <asm/uv/uv.h> 75 #include <linux/mc146818rtc.h> 76 #include <asm/smpboot_hooks.h> 77 #include <asm/i8259.h> 78 #include <asm/realmode.h> 79 #include <asm/misc.h> 80 81 /* State of each CPU */ 82 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 83 84 /* Number of siblings per CPU package */ 85 int smp_num_siblings = 1; 86 EXPORT_SYMBOL(smp_num_siblings); 87 88 /* Last level cache ID of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 90 91 /* representing HT siblings of each logical CPU */ 92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 94 95 /* representing HT and core siblings of each logical CPU */ 96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 97 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 98 99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 100 101 /* Per CPU bogomips and other parameters */ 102 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 103 EXPORT_PER_CPU_SYMBOL(cpu_info); 104 105 static DEFINE_PER_CPU(struct completion, die_complete); 106 107 atomic_t init_deasserted; 108 109 /* 110 * Report back to the Boot Processor during boot time or to the caller processor 111 * during CPU online. 112 */ 113 static void smp_callin(void) 114 { 115 int cpuid, phys_id; 116 117 /* 118 * If waken up by an INIT in an 82489DX configuration 119 * we may get here before an INIT-deassert IPI reaches 120 * our local APIC. We have to wait for the IPI or we'll 121 * lock up on an APIC access. 122 * 123 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. 124 */ 125 cpuid = smp_processor_id(); 126 if (apic->wait_for_init_deassert && cpuid) 127 while (!atomic_read(&init_deasserted)) 128 cpu_relax(); 129 130 /* 131 * (This works even if the APIC is not enabled.) 132 */ 133 phys_id = read_apic_id(); 134 135 /* 136 * the boot CPU has finished the init stage and is spinning 137 * on callin_map until we finish. We are free to set up this 138 * CPU, first the APIC. (this is probably redundant on most 139 * boards) 140 */ 141 setup_local_APIC(); 142 end_local_APIC_setup(); 143 144 /* 145 * Need to setup vector mappings before we enable interrupts. 146 */ 147 setup_vector_irq(smp_processor_id()); 148 149 /* 150 * Save our processor parameters. Note: this information 151 * is needed for clock calibration. 152 */ 153 smp_store_cpu_info(cpuid); 154 155 /* 156 * Get our bogomips. 157 * Update loops_per_jiffy in cpu_data. Previous call to 158 * smp_store_cpu_info() stored a value that is close but not as 159 * accurate as the value just calculated. 160 */ 161 calibrate_delay(); 162 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 163 pr_debug("Stack at about %p\n", &cpuid); 164 165 /* 166 * This must be done before setting cpu_online_mask 167 * or calling notify_cpu_starting. 168 */ 169 set_cpu_sibling_map(raw_smp_processor_id()); 170 wmb(); 171 172 notify_cpu_starting(cpuid); 173 174 /* 175 * Allow the master to continue. 176 */ 177 cpumask_set_cpu(cpuid, cpu_callin_mask); 178 } 179 180 static int cpu0_logical_apicid; 181 static int enable_start_cpu0; 182 /* 183 * Activate a secondary processor. 184 */ 185 static void notrace start_secondary(void *unused) 186 { 187 /* 188 * Don't put *anything* before cpu_init(), SMP booting is too 189 * fragile that we want to limit the things done here to the 190 * most necessary things. 191 */ 192 cpu_init(); 193 x86_cpuinit.early_percpu_clock_init(); 194 preempt_disable(); 195 smp_callin(); 196 197 enable_start_cpu0 = 0; 198 199 #ifdef CONFIG_X86_32 200 /* switch away from the initial page table */ 201 load_cr3(swapper_pg_dir); 202 __flush_tlb_all(); 203 #endif 204 205 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 206 barrier(); 207 /* 208 * Check TSC synchronization with the BP: 209 */ 210 check_tsc_sync_target(); 211 212 /* 213 * Enable the espfix hack for this CPU 214 */ 215 #ifdef CONFIG_X86_ESPFIX64 216 init_espfix_ap(); 217 #endif 218 219 /* 220 * We need to hold vector_lock so there the set of online cpus 221 * does not change while we are assigning vectors to cpus. Holding 222 * this lock ensures we don't half assign or remove an irq from a cpu. 223 */ 224 lock_vector_lock(); 225 set_cpu_online(smp_processor_id(), true); 226 unlock_vector_lock(); 227 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 228 x86_platform.nmi_init(); 229 230 /* enable local interrupts */ 231 local_irq_enable(); 232 233 /* to prevent fake stack check failure in clock setup */ 234 boot_init_stack_canary(); 235 236 x86_cpuinit.setup_percpu_clockev(); 237 238 wmb(); 239 cpu_startup_entry(CPUHP_ONLINE); 240 } 241 242 void __init smp_store_boot_cpu_info(void) 243 { 244 int id = 0; /* CPU 0 */ 245 struct cpuinfo_x86 *c = &cpu_data(id); 246 247 *c = boot_cpu_data; 248 c->cpu_index = id; 249 } 250 251 /* 252 * The bootstrap kernel entry code has set these up. Save them for 253 * a given CPU 254 */ 255 void smp_store_cpu_info(int id) 256 { 257 struct cpuinfo_x86 *c = &cpu_data(id); 258 259 *c = boot_cpu_data; 260 c->cpu_index = id; 261 /* 262 * During boot time, CPU0 has this setup already. Save the info when 263 * bringing up AP or offlined CPU0. 264 */ 265 identify_secondary_cpu(c); 266 } 267 268 static bool 269 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 270 { 271 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 272 273 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 274 } 275 276 static bool 277 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 278 { 279 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 280 281 return !WARN_ONCE(!topology_same_node(c, o), 282 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 283 "[node: %d != %d]. Ignoring dependency.\n", 284 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 285 } 286 287 #define link_mask(_m, c1, c2) \ 288 do { \ 289 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ 290 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ 291 } while (0) 292 293 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 294 { 295 if (cpu_has_topoext) { 296 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 297 298 if (c->phys_proc_id == o->phys_proc_id && 299 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 300 c->compute_unit_id == o->compute_unit_id) 301 return topology_sane(c, o, "smt"); 302 303 } else if (c->phys_proc_id == o->phys_proc_id && 304 c->cpu_core_id == o->cpu_core_id) { 305 return topology_sane(c, o, "smt"); 306 } 307 308 return false; 309 } 310 311 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 312 { 313 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 314 315 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 316 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 317 return topology_sane(c, o, "llc"); 318 319 return false; 320 } 321 322 /* 323 * Unlike the other levels, we do not enforce keeping a 324 * multicore group inside a NUMA node. If this happens, we will 325 * discard the MC level of the topology later. 326 */ 327 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 328 { 329 if (c->phys_proc_id == o->phys_proc_id) 330 return true; 331 return false; 332 } 333 334 static struct sched_domain_topology_level numa_inside_package_topology[] = { 335 #ifdef CONFIG_SCHED_SMT 336 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, 337 #endif 338 #ifdef CONFIG_SCHED_MC 339 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, 340 #endif 341 { NULL, }, 342 }; 343 /* 344 * set_sched_topology() sets the topology internal to a CPU. The 345 * NUMA topologies are layered on top of it to build the full 346 * system topology. 347 * 348 * If NUMA nodes are observed to occur within a CPU package, this 349 * function should be called. It forces the sched domain code to 350 * only use the SMT level for the CPU portion of the topology. 351 * This essentially falls back to relying on NUMA information 352 * from the SRAT table to describe the entire system topology 353 * (except for hyperthreads). 354 */ 355 static void primarily_use_numa_for_topology(void) 356 { 357 set_sched_topology(numa_inside_package_topology); 358 } 359 360 void set_cpu_sibling_map(int cpu) 361 { 362 bool has_smt = smp_num_siblings > 1; 363 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 364 struct cpuinfo_x86 *c = &cpu_data(cpu); 365 struct cpuinfo_x86 *o; 366 int i; 367 368 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 369 370 if (!has_mp) { 371 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 372 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 373 cpumask_set_cpu(cpu, cpu_core_mask(cpu)); 374 c->booted_cores = 1; 375 return; 376 } 377 378 for_each_cpu(i, cpu_sibling_setup_mask) { 379 o = &cpu_data(i); 380 381 if ((i == cpu) || (has_smt && match_smt(c, o))) 382 link_mask(sibling, cpu, i); 383 384 if ((i == cpu) || (has_mp && match_llc(c, o))) 385 link_mask(llc_shared, cpu, i); 386 387 } 388 389 /* 390 * This needs a separate iteration over the cpus because we rely on all 391 * cpu_sibling_mask links to be set-up. 392 */ 393 for_each_cpu(i, cpu_sibling_setup_mask) { 394 o = &cpu_data(i); 395 396 if ((i == cpu) || (has_mp && match_die(c, o))) { 397 link_mask(core, cpu, i); 398 399 /* 400 * Does this new cpu bringup a new core? 401 */ 402 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 403 /* 404 * for each core in package, increment 405 * the booted_cores for this new cpu 406 */ 407 if (cpumask_first(cpu_sibling_mask(i)) == i) 408 c->booted_cores++; 409 /* 410 * increment the core count for all 411 * the other cpus in this package 412 */ 413 if (i != cpu) 414 cpu_data(i).booted_cores++; 415 } else if (i != cpu && !c->booted_cores) 416 c->booted_cores = cpu_data(i).booted_cores; 417 } 418 if (match_die(c, o) && !topology_same_node(c, o)) 419 primarily_use_numa_for_topology(); 420 } 421 } 422 423 /* maps the cpu to the sched domain representing multi-core */ 424 const struct cpumask *cpu_coregroup_mask(int cpu) 425 { 426 return cpu_llc_shared_mask(cpu); 427 } 428 429 static void impress_friends(void) 430 { 431 int cpu; 432 unsigned long bogosum = 0; 433 /* 434 * Allow the user to impress friends. 435 */ 436 pr_debug("Before bogomips\n"); 437 for_each_possible_cpu(cpu) 438 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 439 bogosum += cpu_data(cpu).loops_per_jiffy; 440 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 441 num_online_cpus(), 442 bogosum/(500000/HZ), 443 (bogosum/(5000/HZ))%100); 444 445 pr_debug("Before bogocount - setting activated=1\n"); 446 } 447 448 void __inquire_remote_apic(int apicid) 449 { 450 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 451 const char * const names[] = { "ID", "VERSION", "SPIV" }; 452 int timeout; 453 u32 status; 454 455 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 456 457 for (i = 0; i < ARRAY_SIZE(regs); i++) { 458 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 459 460 /* 461 * Wait for idle. 462 */ 463 status = safe_apic_wait_icr_idle(); 464 if (status) 465 pr_cont("a previous APIC delivery may have failed\n"); 466 467 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 468 469 timeout = 0; 470 do { 471 udelay(100); 472 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 473 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 474 475 switch (status) { 476 case APIC_ICR_RR_VALID: 477 status = apic_read(APIC_RRR); 478 pr_cont("%08x\n", status); 479 break; 480 default: 481 pr_cont("failed\n"); 482 } 483 } 484 } 485 486 /* 487 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 488 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 489 * won't ... remember to clear down the APIC, etc later. 490 */ 491 int 492 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 493 { 494 unsigned long send_status, accept_status = 0; 495 int maxlvt; 496 497 /* Target chip */ 498 /* Boot on the stack */ 499 /* Kick the second */ 500 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 501 502 pr_debug("Waiting for send to finish...\n"); 503 send_status = safe_apic_wait_icr_idle(); 504 505 /* 506 * Give the other CPU some time to accept the IPI. 507 */ 508 udelay(200); 509 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 510 maxlvt = lapic_get_maxlvt(); 511 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 512 apic_write(APIC_ESR, 0); 513 accept_status = (apic_read(APIC_ESR) & 0xEF); 514 } 515 pr_debug("NMI sent\n"); 516 517 if (send_status) 518 pr_err("APIC never delivered???\n"); 519 if (accept_status) 520 pr_err("APIC delivery error (%lx)\n", accept_status); 521 522 return (send_status | accept_status); 523 } 524 525 static int 526 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 527 { 528 unsigned long send_status, accept_status = 0; 529 int maxlvt, num_starts, j; 530 531 maxlvt = lapic_get_maxlvt(); 532 533 /* 534 * Be paranoid about clearing APIC errors. 535 */ 536 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 537 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 538 apic_write(APIC_ESR, 0); 539 apic_read(APIC_ESR); 540 } 541 542 pr_debug("Asserting INIT\n"); 543 544 /* 545 * Turn INIT on target chip 546 */ 547 /* 548 * Send IPI 549 */ 550 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 551 phys_apicid); 552 553 pr_debug("Waiting for send to finish...\n"); 554 send_status = safe_apic_wait_icr_idle(); 555 556 mdelay(10); 557 558 pr_debug("Deasserting INIT\n"); 559 560 /* Target chip */ 561 /* Send IPI */ 562 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 563 564 pr_debug("Waiting for send to finish...\n"); 565 send_status = safe_apic_wait_icr_idle(); 566 567 mb(); 568 atomic_set(&init_deasserted, 1); 569 570 /* 571 * Should we send STARTUP IPIs ? 572 * 573 * Determine this based on the APIC version. 574 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 575 */ 576 if (APIC_INTEGRATED(apic_version[phys_apicid])) 577 num_starts = 2; 578 else 579 num_starts = 0; 580 581 /* 582 * Paravirt / VMI wants a startup IPI hook here to set up the 583 * target processor state. 584 */ 585 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 586 stack_start); 587 588 /* 589 * Run STARTUP IPI loop. 590 */ 591 pr_debug("#startup loops: %d\n", num_starts); 592 593 for (j = 1; j <= num_starts; j++) { 594 pr_debug("Sending STARTUP #%d\n", j); 595 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 596 apic_write(APIC_ESR, 0); 597 apic_read(APIC_ESR); 598 pr_debug("After apic_write\n"); 599 600 /* 601 * STARTUP IPI 602 */ 603 604 /* Target chip */ 605 /* Boot on the stack */ 606 /* Kick the second */ 607 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 608 phys_apicid); 609 610 /* 611 * Give the other CPU some time to accept the IPI. 612 */ 613 udelay(300); 614 615 pr_debug("Startup point 1\n"); 616 617 pr_debug("Waiting for send to finish...\n"); 618 send_status = safe_apic_wait_icr_idle(); 619 620 /* 621 * Give the other CPU some time to accept the IPI. 622 */ 623 udelay(200); 624 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 625 apic_write(APIC_ESR, 0); 626 accept_status = (apic_read(APIC_ESR) & 0xEF); 627 if (send_status || accept_status) 628 break; 629 } 630 pr_debug("After Startup\n"); 631 632 if (send_status) 633 pr_err("APIC never delivered???\n"); 634 if (accept_status) 635 pr_err("APIC delivery error (%lx)\n", accept_status); 636 637 return (send_status | accept_status); 638 } 639 640 void smp_announce(void) 641 { 642 int num_nodes = num_online_nodes(); 643 644 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", 645 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); 646 } 647 648 /* reduce the number of lines printed when booting a large cpu count system */ 649 static void announce_cpu(int cpu, int apicid) 650 { 651 static int current_node = -1; 652 int node = early_cpu_to_node(cpu); 653 static int width, node_width; 654 655 if (!width) 656 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 657 658 if (!node_width) 659 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 660 661 if (cpu == 1) 662 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 663 664 if (system_state == SYSTEM_BOOTING) { 665 if (node != current_node) { 666 if (current_node > (-1)) 667 pr_cont("\n"); 668 current_node = node; 669 670 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 671 node_width - num_digits(node), " ", node); 672 } 673 674 /* Add padding for the BSP */ 675 if (cpu == 1) 676 pr_cont("%*s", width + 1, " "); 677 678 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 679 680 } else 681 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 682 node, cpu, apicid); 683 } 684 685 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 686 { 687 int cpu; 688 689 cpu = smp_processor_id(); 690 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 691 return NMI_HANDLED; 692 693 return NMI_DONE; 694 } 695 696 /* 697 * Wake up AP by INIT, INIT, STARTUP sequence. 698 * 699 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 700 * boot-strap code which is not a desired behavior for waking up BSP. To 701 * void the boot-strap code, wake up CPU0 by NMI instead. 702 * 703 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 704 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 705 * We'll change this code in the future to wake up hard offlined CPU0 if 706 * real platform and request are available. 707 */ 708 static int 709 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 710 int *cpu0_nmi_registered) 711 { 712 int id; 713 int boot_error; 714 715 preempt_disable(); 716 717 /* 718 * Wake up AP by INIT, INIT, STARTUP sequence. 719 */ 720 if (cpu) { 721 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 722 goto out; 723 } 724 725 /* 726 * Wake up BSP by nmi. 727 * 728 * Register a NMI handler to help wake up CPU0. 729 */ 730 boot_error = register_nmi_handler(NMI_LOCAL, 731 wakeup_cpu0_nmi, 0, "wake_cpu0"); 732 733 if (!boot_error) { 734 enable_start_cpu0 = 1; 735 *cpu0_nmi_registered = 1; 736 if (apic->dest_logical == APIC_DEST_LOGICAL) 737 id = cpu0_logical_apicid; 738 else 739 id = apicid; 740 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 741 } 742 743 out: 744 preempt_enable(); 745 746 return boot_error; 747 } 748 749 /* 750 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 751 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 752 * Returns zero if CPU booted OK, else error code from 753 * ->wakeup_secondary_cpu. 754 */ 755 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 756 { 757 volatile u32 *trampoline_status = 758 (volatile u32 *) __va(real_mode_header->trampoline_status); 759 /* start_ip had better be page-aligned! */ 760 unsigned long start_ip = real_mode_header->trampoline_start; 761 762 unsigned long boot_error = 0; 763 int cpu0_nmi_registered = 0; 764 unsigned long timeout; 765 766 /* Just in case we booted with a single CPU. */ 767 alternatives_enable_smp(); 768 769 idle->thread.sp = (unsigned long) (((struct pt_regs *) 770 (THREAD_SIZE + task_stack_page(idle))) - 1); 771 per_cpu(current_task, cpu) = idle; 772 773 #ifdef CONFIG_X86_32 774 /* Stack for startup_32 can be just as for start_secondary onwards */ 775 irq_ctx_init(cpu); 776 #else 777 clear_tsk_thread_flag(idle, TIF_FORK); 778 initial_gs = per_cpu_offset(cpu); 779 #endif 780 per_cpu(kernel_stack, cpu) = 781 (unsigned long)task_stack_page(idle) - 782 KERNEL_STACK_OFFSET + THREAD_SIZE; 783 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 784 initial_code = (unsigned long)start_secondary; 785 stack_start = idle->thread.sp; 786 787 /* So we see what's up */ 788 announce_cpu(cpu, apicid); 789 790 /* 791 * This grunge runs the startup process for 792 * the targeted processor. 793 */ 794 795 atomic_set(&init_deasserted, 0); 796 797 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 798 799 pr_debug("Setting warm reset code and vector.\n"); 800 801 smpboot_setup_warm_reset_vector(start_ip); 802 /* 803 * Be paranoid about clearing APIC errors. 804 */ 805 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 806 apic_write(APIC_ESR, 0); 807 apic_read(APIC_ESR); 808 } 809 } 810 811 /* 812 * AP might wait on cpu_callout_mask in cpu_init() with 813 * cpu_initialized_mask set if previous attempt to online 814 * it timed-out. Clear cpu_initialized_mask so that after 815 * INIT/SIPI it could start with a clean state. 816 */ 817 cpumask_clear_cpu(cpu, cpu_initialized_mask); 818 smp_mb(); 819 820 /* 821 * Wake up a CPU in difference cases: 822 * - Use the method in the APIC driver if it's defined 823 * Otherwise, 824 * - Use an INIT boot APIC message for APs or NMI for BSP. 825 */ 826 if (apic->wakeup_secondary_cpu) 827 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 828 else 829 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 830 &cpu0_nmi_registered); 831 832 if (!boot_error) { 833 /* 834 * Wait 10s total for a response from AP 835 */ 836 boot_error = -1; 837 timeout = jiffies + 10*HZ; 838 while (time_before(jiffies, timeout)) { 839 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 840 /* 841 * Tell AP to proceed with initialization 842 */ 843 cpumask_set_cpu(cpu, cpu_callout_mask); 844 boot_error = 0; 845 break; 846 } 847 udelay(100); 848 schedule(); 849 } 850 } 851 852 if (!boot_error) { 853 /* 854 * Wait till AP completes initial initialization 855 */ 856 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 857 /* 858 * Allow other tasks to run while we wait for the 859 * AP to come online. This also gives a chance 860 * for the MTRR work(triggered by the AP coming online) 861 * to be completed in the stop machine context. 862 */ 863 udelay(100); 864 schedule(); 865 } 866 } 867 868 /* mark "stuck" area as not stuck */ 869 *trampoline_status = 0; 870 871 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 872 /* 873 * Cleanup possible dangling ends... 874 */ 875 smpboot_restore_warm_reset_vector(); 876 } 877 /* 878 * Clean up the nmi handler. Do this after the callin and callout sync 879 * to avoid impact of possible long unregister time. 880 */ 881 if (cpu0_nmi_registered) 882 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 883 884 return boot_error; 885 } 886 887 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 888 { 889 int apicid = apic->cpu_present_to_apicid(cpu); 890 unsigned long flags; 891 int err; 892 893 WARN_ON(irqs_disabled()); 894 895 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 896 897 if (apicid == BAD_APICID || 898 !physid_isset(apicid, phys_cpu_present_map) || 899 !apic->apic_id_valid(apicid)) { 900 pr_err("%s: bad cpu %d\n", __func__, cpu); 901 return -EINVAL; 902 } 903 904 /* 905 * Already booted CPU? 906 */ 907 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 908 pr_debug("do_boot_cpu %d Already started\n", cpu); 909 return -ENOSYS; 910 } 911 912 /* 913 * Save current MTRR state in case it was changed since early boot 914 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 915 */ 916 mtrr_save_state(); 917 918 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 919 920 /* the FPU context is blank, nobody can own it */ 921 __cpu_disable_lazy_restore(cpu); 922 923 err = do_boot_cpu(apicid, cpu, tidle); 924 if (err) { 925 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 926 return -EIO; 927 } 928 929 /* 930 * Check TSC synchronization with the AP (keep irqs disabled 931 * while doing so): 932 */ 933 local_irq_save(flags); 934 check_tsc_sync_source(cpu); 935 local_irq_restore(flags); 936 937 while (!cpu_online(cpu)) { 938 cpu_relax(); 939 touch_nmi_watchdog(); 940 } 941 942 return 0; 943 } 944 945 /** 946 * arch_disable_smp_support() - disables SMP support for x86 at runtime 947 */ 948 void arch_disable_smp_support(void) 949 { 950 disable_ioapic_support(); 951 } 952 953 /* 954 * Fall back to non SMP mode after errors. 955 * 956 * RED-PEN audit/test this more. I bet there is more state messed up here. 957 */ 958 static __init void disable_smp(void) 959 { 960 init_cpu_present(cpumask_of(0)); 961 init_cpu_possible(cpumask_of(0)); 962 smpboot_clear_io_apic_irqs(); 963 964 if (smp_found_config) 965 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 966 else 967 physid_set_mask_of_physid(0, &phys_cpu_present_map); 968 cpumask_set_cpu(0, cpu_sibling_mask(0)); 969 cpumask_set_cpu(0, cpu_core_mask(0)); 970 } 971 972 /* 973 * Various sanity checks. 974 */ 975 static int __init smp_sanity_check(unsigned max_cpus) 976 { 977 preempt_disable(); 978 979 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 980 if (def_to_bigsmp && nr_cpu_ids > 8) { 981 unsigned int cpu; 982 unsigned nr; 983 984 pr_warn("More than 8 CPUs detected - skipping them\n" 985 "Use CONFIG_X86_BIGSMP\n"); 986 987 nr = 0; 988 for_each_present_cpu(cpu) { 989 if (nr >= 8) 990 set_cpu_present(cpu, false); 991 nr++; 992 } 993 994 nr = 0; 995 for_each_possible_cpu(cpu) { 996 if (nr >= 8) 997 set_cpu_possible(cpu, false); 998 nr++; 999 } 1000 1001 nr_cpu_ids = 8; 1002 } 1003 #endif 1004 1005 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1006 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1007 hard_smp_processor_id()); 1008 1009 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1010 } 1011 1012 /* 1013 * If we couldn't find an SMP configuration at boot time, 1014 * get out of here now! 1015 */ 1016 if (!smp_found_config && !acpi_lapic) { 1017 preempt_enable(); 1018 pr_notice("SMP motherboard not detected\n"); 1019 disable_smp(); 1020 if (APIC_init_uniprocessor()) 1021 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1022 return -1; 1023 } 1024 1025 /* 1026 * Should not be necessary because the MP table should list the boot 1027 * CPU too, but we do it for the sake of robustness anyway. 1028 */ 1029 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1030 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1031 boot_cpu_physical_apicid); 1032 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1033 } 1034 preempt_enable(); 1035 1036 /* 1037 * If we couldn't find a local APIC, then get out of here now! 1038 */ 1039 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1040 !cpu_has_apic) { 1041 if (!disable_apic) { 1042 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1043 boot_cpu_physical_apicid); 1044 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1045 } 1046 smpboot_clear_io_apic(); 1047 disable_ioapic_support(); 1048 return -1; 1049 } 1050 1051 verify_local_APIC(); 1052 1053 /* 1054 * If SMP should be disabled, then really disable it! 1055 */ 1056 if (!max_cpus) { 1057 pr_info("SMP mode deactivated\n"); 1058 smpboot_clear_io_apic(); 1059 1060 connect_bsp_APIC(); 1061 setup_local_APIC(); 1062 bsp_end_local_APIC_setup(); 1063 return -1; 1064 } 1065 1066 return 0; 1067 } 1068 1069 static void __init smp_cpu_index_default(void) 1070 { 1071 int i; 1072 struct cpuinfo_x86 *c; 1073 1074 for_each_possible_cpu(i) { 1075 c = &cpu_data(i); 1076 /* mark all to hotplug */ 1077 c->cpu_index = nr_cpu_ids; 1078 } 1079 } 1080 1081 /* 1082 * Prepare for SMP bootup. The MP table or ACPI has been read 1083 * earlier. Just do some sanity checking here and enable APIC mode. 1084 */ 1085 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1086 { 1087 unsigned int i; 1088 1089 preempt_disable(); 1090 smp_cpu_index_default(); 1091 1092 /* 1093 * Setup boot CPU information 1094 */ 1095 smp_store_boot_cpu_info(); /* Final full version of the data */ 1096 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1097 mb(); 1098 1099 current_thread_info()->cpu = 0; /* needed? */ 1100 for_each_possible_cpu(i) { 1101 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1102 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1103 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1104 } 1105 set_cpu_sibling_map(0); 1106 1107 1108 if (smp_sanity_check(max_cpus) < 0) { 1109 pr_info("SMP disabled\n"); 1110 disable_smp(); 1111 goto out; 1112 } 1113 1114 default_setup_apic_routing(); 1115 1116 preempt_disable(); 1117 if (read_apic_id() != boot_cpu_physical_apicid) { 1118 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1119 read_apic_id(), boot_cpu_physical_apicid); 1120 /* Or can we switch back to PIC here? */ 1121 } 1122 preempt_enable(); 1123 1124 connect_bsp_APIC(); 1125 1126 /* 1127 * Switch from PIC to APIC mode. 1128 */ 1129 setup_local_APIC(); 1130 1131 if (x2apic_mode) 1132 cpu0_logical_apicid = apic_read(APIC_LDR); 1133 else 1134 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1135 1136 /* 1137 * Enable IO APIC before setting up error vector 1138 */ 1139 if (!skip_ioapic_setup && nr_ioapics) 1140 enable_IO_APIC(); 1141 1142 bsp_end_local_APIC_setup(); 1143 smpboot_setup_io_apic(); 1144 /* 1145 * Set up local APIC timer on boot CPU. 1146 */ 1147 1148 pr_info("CPU%d: ", 0); 1149 print_cpu_info(&cpu_data(0)); 1150 x86_init.timers.setup_percpu_clockev(); 1151 1152 if (is_uv_system()) 1153 uv_system_init(); 1154 1155 set_mtrr_aps_delayed_init(); 1156 out: 1157 preempt_enable(); 1158 } 1159 1160 void arch_enable_nonboot_cpus_begin(void) 1161 { 1162 set_mtrr_aps_delayed_init(); 1163 } 1164 1165 void arch_enable_nonboot_cpus_end(void) 1166 { 1167 mtrr_aps_init(); 1168 } 1169 1170 /* 1171 * Early setup to make printk work. 1172 */ 1173 void __init native_smp_prepare_boot_cpu(void) 1174 { 1175 int me = smp_processor_id(); 1176 switch_to_new_gdt(me); 1177 /* already set me in cpu_online_mask in boot_cpu_init() */ 1178 cpumask_set_cpu(me, cpu_callout_mask); 1179 per_cpu(cpu_state, me) = CPU_ONLINE; 1180 } 1181 1182 void __init native_smp_cpus_done(unsigned int max_cpus) 1183 { 1184 pr_debug("Boot done\n"); 1185 1186 nmi_selftest(); 1187 impress_friends(); 1188 #ifdef CONFIG_X86_IO_APIC 1189 setup_ioapic_dest(); 1190 #endif 1191 mtrr_aps_init(); 1192 } 1193 1194 static int __initdata setup_possible_cpus = -1; 1195 static int __init _setup_possible_cpus(char *str) 1196 { 1197 get_option(&str, &setup_possible_cpus); 1198 return 0; 1199 } 1200 early_param("possible_cpus", _setup_possible_cpus); 1201 1202 1203 /* 1204 * cpu_possible_mask should be static, it cannot change as cpu's 1205 * are onlined, or offlined. The reason is per-cpu data-structures 1206 * are allocated by some modules at init time, and dont expect to 1207 * do this dynamically on cpu arrival/departure. 1208 * cpu_present_mask on the other hand can change dynamically. 1209 * In case when cpu_hotplug is not compiled, then we resort to current 1210 * behaviour, which is cpu_possible == cpu_present. 1211 * - Ashok Raj 1212 * 1213 * Three ways to find out the number of additional hotplug CPUs: 1214 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1215 * - The user can overwrite it with possible_cpus=NUM 1216 * - Otherwise don't reserve additional CPUs. 1217 * We do this because additional CPUs waste a lot of memory. 1218 * -AK 1219 */ 1220 __init void prefill_possible_map(void) 1221 { 1222 int i, possible; 1223 1224 /* no processor from mptable or madt */ 1225 if (!num_processors) 1226 num_processors = 1; 1227 1228 i = setup_max_cpus ?: 1; 1229 if (setup_possible_cpus == -1) { 1230 possible = num_processors; 1231 #ifdef CONFIG_HOTPLUG_CPU 1232 if (setup_max_cpus) 1233 possible += disabled_cpus; 1234 #else 1235 if (possible > i) 1236 possible = i; 1237 #endif 1238 } else 1239 possible = setup_possible_cpus; 1240 1241 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1242 1243 /* nr_cpu_ids could be reduced via nr_cpus= */ 1244 if (possible > nr_cpu_ids) { 1245 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", 1246 possible, nr_cpu_ids); 1247 possible = nr_cpu_ids; 1248 } 1249 1250 #ifdef CONFIG_HOTPLUG_CPU 1251 if (!setup_max_cpus) 1252 #endif 1253 if (possible > i) { 1254 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1255 possible, setup_max_cpus); 1256 possible = i; 1257 } 1258 1259 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1260 possible, max_t(int, possible - num_processors, 0)); 1261 1262 for (i = 0; i < possible; i++) 1263 set_cpu_possible(i, true); 1264 for (; i < NR_CPUS; i++) 1265 set_cpu_possible(i, false); 1266 1267 nr_cpu_ids = possible; 1268 } 1269 1270 #ifdef CONFIG_HOTPLUG_CPU 1271 1272 static void remove_siblinginfo(int cpu) 1273 { 1274 int sibling; 1275 struct cpuinfo_x86 *c = &cpu_data(cpu); 1276 1277 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1278 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1279 /*/ 1280 * last thread sibling in this cpu core going down 1281 */ 1282 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1283 cpu_data(sibling).booted_cores--; 1284 } 1285 1286 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1287 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1288 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1289 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1290 cpumask_clear(cpu_llc_shared_mask(cpu)); 1291 cpumask_clear(cpu_sibling_mask(cpu)); 1292 cpumask_clear(cpu_core_mask(cpu)); 1293 c->phys_proc_id = 0; 1294 c->cpu_core_id = 0; 1295 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1296 } 1297 1298 static void __ref remove_cpu_from_maps(int cpu) 1299 { 1300 set_cpu_online(cpu, false); 1301 cpumask_clear_cpu(cpu, cpu_callout_mask); 1302 cpumask_clear_cpu(cpu, cpu_callin_mask); 1303 /* was set by cpu_init() */ 1304 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1305 numa_remove_cpu(cpu); 1306 } 1307 1308 void cpu_disable_common(void) 1309 { 1310 int cpu = smp_processor_id(); 1311 1312 remove_siblinginfo(cpu); 1313 1314 /* It's now safe to remove this processor from the online map */ 1315 lock_vector_lock(); 1316 remove_cpu_from_maps(cpu); 1317 unlock_vector_lock(); 1318 fixup_irqs(); 1319 } 1320 1321 int native_cpu_disable(void) 1322 { 1323 int ret; 1324 1325 ret = check_irq_vectors_for_cpu_disable(); 1326 if (ret) 1327 return ret; 1328 1329 clear_local_APIC(); 1330 init_completion(&per_cpu(die_complete, smp_processor_id())); 1331 cpu_disable_common(); 1332 1333 return 0; 1334 } 1335 1336 void native_cpu_die(unsigned int cpu) 1337 { 1338 /* We don't do anything here: idle task is faking death itself. */ 1339 wait_for_completion_timeout(&per_cpu(die_complete, cpu), HZ); 1340 1341 /* They ack this in play_dead() by setting CPU_DEAD */ 1342 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1343 if (system_state == SYSTEM_RUNNING) 1344 pr_info("CPU %u is now offline\n", cpu); 1345 } else { 1346 pr_err("CPU %u didn't die...\n", cpu); 1347 } 1348 } 1349 1350 void play_dead_common(void) 1351 { 1352 idle_task_exit(); 1353 reset_lazy_tlbstate(); 1354 amd_e400_remove_cpu(raw_smp_processor_id()); 1355 1356 mb(); 1357 /* Ack it */ 1358 __this_cpu_write(cpu_state, CPU_DEAD); 1359 complete(&per_cpu(die_complete, smp_processor_id())); 1360 1361 /* 1362 * With physical CPU hotplug, we should halt the cpu 1363 */ 1364 local_irq_disable(); 1365 } 1366 1367 static bool wakeup_cpu0(void) 1368 { 1369 if (smp_processor_id() == 0 && enable_start_cpu0) 1370 return true; 1371 1372 return false; 1373 } 1374 1375 /* 1376 * We need to flush the caches before going to sleep, lest we have 1377 * dirty data in our caches when we come back up. 1378 */ 1379 static inline void mwait_play_dead(void) 1380 { 1381 unsigned int eax, ebx, ecx, edx; 1382 unsigned int highest_cstate = 0; 1383 unsigned int highest_subcstate = 0; 1384 void *mwait_ptr; 1385 int i; 1386 1387 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1388 return; 1389 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1390 return; 1391 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1392 return; 1393 1394 eax = CPUID_MWAIT_LEAF; 1395 ecx = 0; 1396 native_cpuid(&eax, &ebx, &ecx, &edx); 1397 1398 /* 1399 * eax will be 0 if EDX enumeration is not valid. 1400 * Initialized below to cstate, sub_cstate value when EDX is valid. 1401 */ 1402 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1403 eax = 0; 1404 } else { 1405 edx >>= MWAIT_SUBSTATE_SIZE; 1406 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1407 if (edx & MWAIT_SUBSTATE_MASK) { 1408 highest_cstate = i; 1409 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1410 } 1411 } 1412 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1413 (highest_subcstate - 1); 1414 } 1415 1416 /* 1417 * This should be a memory location in a cache line which is 1418 * unlikely to be touched by other processors. The actual 1419 * content is immaterial as it is not actually modified in any way. 1420 */ 1421 mwait_ptr = ¤t_thread_info()->flags; 1422 1423 wbinvd(); 1424 1425 while (1) { 1426 /* 1427 * The CLFLUSH is a workaround for erratum AAI65 for 1428 * the Xeon 7400 series. It's not clear it is actually 1429 * needed, but it should be harmless in either case. 1430 * The WBINVD is insufficient due to the spurious-wakeup 1431 * case where we return around the loop. 1432 */ 1433 mb(); 1434 clflush(mwait_ptr); 1435 mb(); 1436 __monitor(mwait_ptr, 0, 0); 1437 mb(); 1438 __mwait(eax, 0); 1439 /* 1440 * If NMI wants to wake up CPU0, start CPU0. 1441 */ 1442 if (wakeup_cpu0()) 1443 start_cpu0(); 1444 } 1445 } 1446 1447 static inline void hlt_play_dead(void) 1448 { 1449 if (__this_cpu_read(cpu_info.x86) >= 4) 1450 wbinvd(); 1451 1452 while (1) { 1453 native_halt(); 1454 /* 1455 * If NMI wants to wake up CPU0, start CPU0. 1456 */ 1457 if (wakeup_cpu0()) 1458 start_cpu0(); 1459 } 1460 } 1461 1462 void native_play_dead(void) 1463 { 1464 play_dead_common(); 1465 tboot_shutdown(TB_SHUTDOWN_WFS); 1466 1467 mwait_play_dead(); /* Only returns on failure */ 1468 if (cpuidle_play_dead()) 1469 hlt_play_dead(); 1470 } 1471 1472 #else /* ... !CONFIG_HOTPLUG_CPU */ 1473 int native_cpu_disable(void) 1474 { 1475 return -ENOSYS; 1476 } 1477 1478 void native_cpu_die(unsigned int cpu) 1479 { 1480 /* We said "no" in __cpu_disable */ 1481 BUG(); 1482 } 1483 1484 void native_play_dead(void) 1485 { 1486 BUG(); 1487 } 1488 1489 #endif 1490