1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/export.h> 47 #include <linux/sched.h> 48 #include <linux/percpu.h> 49 #include <linux/bootmem.h> 50 #include <linux/err.h> 51 #include <linux/nmi.h> 52 #include <linux/tboot.h> 53 #include <linux/stackprotector.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 57 #include <asm/acpi.h> 58 #include <asm/desc.h> 59 #include <asm/nmi.h> 60 #include <asm/irq.h> 61 #include <asm/realmode.h> 62 #include <asm/cpu.h> 63 #include <asm/numa.h> 64 #include <asm/pgtable.h> 65 #include <asm/tlbflush.h> 66 #include <asm/mtrr.h> 67 #include <asm/mwait.h> 68 #include <asm/apic.h> 69 #include <asm/io_apic.h> 70 #include <asm/fpu/internal.h> 71 #include <asm/setup.h> 72 #include <asm/uv/uv.h> 73 #include <linux/mc146818rtc.h> 74 #include <asm/i8259.h> 75 #include <asm/realmode.h> 76 #include <asm/misc.h> 77 78 /* Number of siblings per CPU package */ 79 int smp_num_siblings = 1; 80 EXPORT_SYMBOL(smp_num_siblings); 81 82 /* Last level cache ID of each logical CPU */ 83 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 84 85 /* representing HT siblings of each logical CPU */ 86 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 87 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 88 89 /* representing HT and core siblings of each logical CPU */ 90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 91 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 92 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 94 95 /* Per CPU bogomips and other parameters */ 96 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 97 EXPORT_PER_CPU_SYMBOL(cpu_info); 98 99 /* Logical package management. We might want to allocate that dynamically */ 100 static int *physical_to_logical_pkg __read_mostly; 101 static unsigned long *physical_package_map __read_mostly;; 102 static unsigned int max_physical_pkg_id __read_mostly; 103 unsigned int __max_logical_packages __read_mostly; 104 EXPORT_SYMBOL(__max_logical_packages); 105 static unsigned int logical_packages __read_mostly; 106 107 /* Maximum number of SMT threads on any online core */ 108 int __max_smt_threads __read_mostly; 109 110 /* Flag to indicate if a complete sched domain rebuild is required */ 111 bool x86_topology_update; 112 113 int arch_update_cpu_topology(void) 114 { 115 int retval = x86_topology_update; 116 117 x86_topology_update = false; 118 return retval; 119 } 120 121 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 122 { 123 unsigned long flags; 124 125 spin_lock_irqsave(&rtc_lock, flags); 126 CMOS_WRITE(0xa, 0xf); 127 spin_unlock_irqrestore(&rtc_lock, flags); 128 local_flush_tlb(); 129 pr_debug("1.\n"); 130 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 131 start_eip >> 4; 132 pr_debug("2.\n"); 133 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 134 start_eip & 0xf; 135 pr_debug("3.\n"); 136 } 137 138 static inline void smpboot_restore_warm_reset_vector(void) 139 { 140 unsigned long flags; 141 142 /* 143 * Install writable page 0 entry to set BIOS data area. 144 */ 145 local_flush_tlb(); 146 147 /* 148 * Paranoid: Set warm reset code and vector here back 149 * to default values. 150 */ 151 spin_lock_irqsave(&rtc_lock, flags); 152 CMOS_WRITE(0, 0xf); 153 spin_unlock_irqrestore(&rtc_lock, flags); 154 155 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 156 } 157 158 /* 159 * Report back to the Boot Processor during boot time or to the caller processor 160 * during CPU online. 161 */ 162 static void smp_callin(void) 163 { 164 int cpuid, phys_id; 165 166 /* 167 * If waken up by an INIT in an 82489DX configuration 168 * cpu_callout_mask guarantees we don't get here before 169 * an INIT_deassert IPI reaches our local APIC, so it is 170 * now safe to touch our local APIC. 171 */ 172 cpuid = smp_processor_id(); 173 174 /* 175 * (This works even if the APIC is not enabled.) 176 */ 177 phys_id = read_apic_id(); 178 179 /* 180 * the boot CPU has finished the init stage and is spinning 181 * on callin_map until we finish. We are free to set up this 182 * CPU, first the APIC. (this is probably redundant on most 183 * boards) 184 */ 185 apic_ap_setup(); 186 187 /* 188 * Save our processor parameters. Note: this information 189 * is needed for clock calibration. 190 */ 191 smp_store_cpu_info(cpuid); 192 193 /* 194 * Get our bogomips. 195 * Update loops_per_jiffy in cpu_data. Previous call to 196 * smp_store_cpu_info() stored a value that is close but not as 197 * accurate as the value just calculated. 198 */ 199 calibrate_delay(); 200 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 201 pr_debug("Stack at about %p\n", &cpuid); 202 203 /* 204 * This must be done before setting cpu_online_mask 205 * or calling notify_cpu_starting. 206 */ 207 set_cpu_sibling_map(raw_smp_processor_id()); 208 wmb(); 209 210 notify_cpu_starting(cpuid); 211 212 /* 213 * Allow the master to continue. 214 */ 215 cpumask_set_cpu(cpuid, cpu_callin_mask); 216 } 217 218 static int cpu0_logical_apicid; 219 static int enable_start_cpu0; 220 /* 221 * Activate a secondary processor. 222 */ 223 static void notrace start_secondary(void *unused) 224 { 225 /* 226 * Don't put *anything* before cpu_init(), SMP booting is too 227 * fragile that we want to limit the things done here to the 228 * most necessary things. 229 */ 230 cpu_init(); 231 x86_cpuinit.early_percpu_clock_init(); 232 preempt_disable(); 233 smp_callin(); 234 235 enable_start_cpu0 = 0; 236 237 #ifdef CONFIG_X86_32 238 /* switch away from the initial page table */ 239 load_cr3(swapper_pg_dir); 240 __flush_tlb_all(); 241 #endif 242 243 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 244 barrier(); 245 /* 246 * Check TSC synchronization with the BP: 247 */ 248 check_tsc_sync_target(); 249 250 /* 251 * Lock vector_lock and initialize the vectors on this cpu 252 * before setting the cpu online. We must set it online with 253 * vector_lock held to prevent a concurrent setup/teardown 254 * from seeing a half valid vector space. 255 */ 256 lock_vector_lock(); 257 setup_vector_irq(smp_processor_id()); 258 set_cpu_online(smp_processor_id(), true); 259 unlock_vector_lock(); 260 cpu_set_state_online(smp_processor_id()); 261 x86_platform.nmi_init(); 262 263 /* enable local interrupts */ 264 local_irq_enable(); 265 266 /* to prevent fake stack check failure in clock setup */ 267 boot_init_stack_canary(); 268 269 x86_cpuinit.setup_percpu_clockev(); 270 271 wmb(); 272 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 273 } 274 275 /** 276 * topology_update_package_map - Update the physical to logical package map 277 * @pkg: The physical package id as retrieved via CPUID 278 * @cpu: The cpu for which this is updated 279 */ 280 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 281 { 282 unsigned int new; 283 284 /* Called from early boot ? */ 285 if (!physical_package_map) 286 return 0; 287 288 if (pkg >= max_physical_pkg_id) 289 return -EINVAL; 290 291 /* Set the logical package id */ 292 if (test_and_set_bit(pkg, physical_package_map)) 293 goto found; 294 295 if (logical_packages >= __max_logical_packages) { 296 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n", 297 logical_packages, cpu, __max_logical_packages); 298 return -ENOSPC; 299 } 300 301 new = logical_packages++; 302 if (new != pkg) { 303 pr_info("CPU %u Converting physical %u to logical package %u\n", 304 cpu, pkg, new); 305 } 306 physical_to_logical_pkg[pkg] = new; 307 308 found: 309 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; 310 return 0; 311 } 312 313 /** 314 * topology_phys_to_logical_pkg - Map a physical package id to a logical 315 * 316 * Returns logical package id or -1 if not found 317 */ 318 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 319 { 320 if (phys_pkg >= max_physical_pkg_id) 321 return -1; 322 return physical_to_logical_pkg[phys_pkg]; 323 } 324 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 325 326 static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu) 327 { 328 unsigned int ncpus; 329 size_t size; 330 331 /* 332 * Today neither Intel nor AMD support heterogenous systems. That 333 * might change in the future.... 334 * 335 * While ideally we'd want '* smp_num_siblings' in the below @ncpus 336 * computation, this won't actually work since some Intel BIOSes 337 * report inconsistent HT data when they disable HT. 338 * 339 * In particular, they reduce the APIC-IDs to only include the cores, 340 * but leave the CPUID topology to say there are (2) siblings. 341 * This means we don't know how many threads there will be until 342 * after the APIC enumeration. 343 * 344 * By not including this we'll sometimes over-estimate the number of 345 * logical packages by the amount of !present siblings, but this is 346 * still better than MAX_LOCAL_APIC. 347 * 348 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited 349 * on the command line leading to a similar issue as the HT disable 350 * problem because the hyperthreads are usually enumerated after the 351 * primary cores. 352 */ 353 ncpus = boot_cpu_data.x86_max_cores; 354 if (!ncpus) { 355 pr_warn("x86_max_cores == zero !?!?"); 356 ncpus = 1; 357 } 358 359 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 360 logical_packages = 0; 361 362 /* 363 * Possibly larger than what we need as the number of apic ids per 364 * package can be smaller than the actual used apic ids. 365 */ 366 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); 367 size = max_physical_pkg_id * sizeof(unsigned int); 368 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); 369 memset(physical_to_logical_pkg, 0xff, size); 370 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); 371 physical_package_map = kzalloc(size, GFP_KERNEL); 372 373 pr_info("Max logical packages: %u\n", __max_logical_packages); 374 375 topology_update_package_map(c->phys_proc_id, cpu); 376 } 377 378 void __init smp_store_boot_cpu_info(void) 379 { 380 int id = 0; /* CPU 0 */ 381 struct cpuinfo_x86 *c = &cpu_data(id); 382 383 *c = boot_cpu_data; 384 c->cpu_index = id; 385 smp_init_package_map(c, id); 386 } 387 388 /* 389 * The bootstrap kernel entry code has set these up. Save them for 390 * a given CPU 391 */ 392 void smp_store_cpu_info(int id) 393 { 394 struct cpuinfo_x86 *c = &cpu_data(id); 395 396 *c = boot_cpu_data; 397 c->cpu_index = id; 398 /* 399 * During boot time, CPU0 has this setup already. Save the info when 400 * bringing up AP or offlined CPU0. 401 */ 402 identify_secondary_cpu(c); 403 } 404 405 static bool 406 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 407 { 408 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 409 410 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 411 } 412 413 static bool 414 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 415 { 416 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 417 418 return !WARN_ONCE(!topology_same_node(c, o), 419 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 420 "[node: %d != %d]. Ignoring dependency.\n", 421 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 422 } 423 424 #define link_mask(mfunc, c1, c2) \ 425 do { \ 426 cpumask_set_cpu((c1), mfunc(c2)); \ 427 cpumask_set_cpu((c2), mfunc(c1)); \ 428 } while (0) 429 430 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 431 { 432 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 433 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 434 435 if (c->phys_proc_id == o->phys_proc_id && 436 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 437 if (c->cpu_core_id == o->cpu_core_id) 438 return topology_sane(c, o, "smt"); 439 440 if ((c->cu_id != 0xff) && 441 (o->cu_id != 0xff) && 442 (c->cu_id == o->cu_id)) 443 return topology_sane(c, o, "smt"); 444 } 445 446 } else if (c->phys_proc_id == o->phys_proc_id && 447 c->cpu_core_id == o->cpu_core_id) { 448 return topology_sane(c, o, "smt"); 449 } 450 451 return false; 452 } 453 454 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 455 { 456 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 457 458 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 459 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 460 return topology_sane(c, o, "llc"); 461 462 return false; 463 } 464 465 /* 466 * Unlike the other levels, we do not enforce keeping a 467 * multicore group inside a NUMA node. If this happens, we will 468 * discard the MC level of the topology later. 469 */ 470 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 471 { 472 if (c->phys_proc_id == o->phys_proc_id) 473 return true; 474 return false; 475 } 476 477 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 478 static inline int x86_sched_itmt_flags(void) 479 { 480 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 481 } 482 483 #ifdef CONFIG_SCHED_MC 484 static int x86_core_flags(void) 485 { 486 return cpu_core_flags() | x86_sched_itmt_flags(); 487 } 488 #endif 489 #ifdef CONFIG_SCHED_SMT 490 static int x86_smt_flags(void) 491 { 492 return cpu_smt_flags() | x86_sched_itmt_flags(); 493 } 494 #endif 495 #endif 496 497 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 498 #ifdef CONFIG_SCHED_SMT 499 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 500 #endif 501 #ifdef CONFIG_SCHED_MC 502 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 503 #endif 504 { NULL, }, 505 }; 506 507 static struct sched_domain_topology_level x86_topology[] = { 508 #ifdef CONFIG_SCHED_SMT 509 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 510 #endif 511 #ifdef CONFIG_SCHED_MC 512 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 513 #endif 514 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 515 { NULL, }, 516 }; 517 518 /* 519 * Set if a package/die has multiple NUMA nodes inside. 520 * AMD Magny-Cours and Intel Cluster-on-Die have this. 521 */ 522 static bool x86_has_numa_in_package; 523 524 void set_cpu_sibling_map(int cpu) 525 { 526 bool has_smt = smp_num_siblings > 1; 527 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 528 struct cpuinfo_x86 *c = &cpu_data(cpu); 529 struct cpuinfo_x86 *o; 530 int i, threads; 531 532 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 533 534 if (!has_mp) { 535 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 536 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 537 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 538 c->booted_cores = 1; 539 return; 540 } 541 542 for_each_cpu(i, cpu_sibling_setup_mask) { 543 o = &cpu_data(i); 544 545 if ((i == cpu) || (has_smt && match_smt(c, o))) 546 link_mask(topology_sibling_cpumask, cpu, i); 547 548 if ((i == cpu) || (has_mp && match_llc(c, o))) 549 link_mask(cpu_llc_shared_mask, cpu, i); 550 551 } 552 553 /* 554 * This needs a separate iteration over the cpus because we rely on all 555 * topology_sibling_cpumask links to be set-up. 556 */ 557 for_each_cpu(i, cpu_sibling_setup_mask) { 558 o = &cpu_data(i); 559 560 if ((i == cpu) || (has_mp && match_die(c, o))) { 561 link_mask(topology_core_cpumask, cpu, i); 562 563 /* 564 * Does this new cpu bringup a new core? 565 */ 566 if (cpumask_weight( 567 topology_sibling_cpumask(cpu)) == 1) { 568 /* 569 * for each core in package, increment 570 * the booted_cores for this new cpu 571 */ 572 if (cpumask_first( 573 topology_sibling_cpumask(i)) == i) 574 c->booted_cores++; 575 /* 576 * increment the core count for all 577 * the other cpus in this package 578 */ 579 if (i != cpu) 580 cpu_data(i).booted_cores++; 581 } else if (i != cpu && !c->booted_cores) 582 c->booted_cores = cpu_data(i).booted_cores; 583 } 584 if (match_die(c, o) && !topology_same_node(c, o)) 585 x86_has_numa_in_package = true; 586 } 587 588 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 589 if (threads > __max_smt_threads) 590 __max_smt_threads = threads; 591 } 592 593 /* maps the cpu to the sched domain representing multi-core */ 594 const struct cpumask *cpu_coregroup_mask(int cpu) 595 { 596 return cpu_llc_shared_mask(cpu); 597 } 598 599 static void impress_friends(void) 600 { 601 int cpu; 602 unsigned long bogosum = 0; 603 /* 604 * Allow the user to impress friends. 605 */ 606 pr_debug("Before bogomips\n"); 607 for_each_possible_cpu(cpu) 608 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 609 bogosum += cpu_data(cpu).loops_per_jiffy; 610 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 611 num_online_cpus(), 612 bogosum/(500000/HZ), 613 (bogosum/(5000/HZ))%100); 614 615 pr_debug("Before bogocount - setting activated=1\n"); 616 } 617 618 void __inquire_remote_apic(int apicid) 619 { 620 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 621 const char * const names[] = { "ID", "VERSION", "SPIV" }; 622 int timeout; 623 u32 status; 624 625 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 626 627 for (i = 0; i < ARRAY_SIZE(regs); i++) { 628 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 629 630 /* 631 * Wait for idle. 632 */ 633 status = safe_apic_wait_icr_idle(); 634 if (status) 635 pr_cont("a previous APIC delivery may have failed\n"); 636 637 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 638 639 timeout = 0; 640 do { 641 udelay(100); 642 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 643 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 644 645 switch (status) { 646 case APIC_ICR_RR_VALID: 647 status = apic_read(APIC_RRR); 648 pr_cont("%08x\n", status); 649 break; 650 default: 651 pr_cont("failed\n"); 652 } 653 } 654 } 655 656 /* 657 * The Multiprocessor Specification 1.4 (1997) example code suggests 658 * that there should be a 10ms delay between the BSP asserting INIT 659 * and de-asserting INIT, when starting a remote processor. 660 * But that slows boot and resume on modern processors, which include 661 * many cores and don't require that delay. 662 * 663 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 664 * Modern processor families are quirked to remove the delay entirely. 665 */ 666 #define UDELAY_10MS_DEFAULT 10000 667 668 static unsigned int init_udelay = UINT_MAX; 669 670 static int __init cpu_init_udelay(char *str) 671 { 672 get_option(&str, &init_udelay); 673 674 return 0; 675 } 676 early_param("cpu_init_udelay", cpu_init_udelay); 677 678 static void __init smp_quirk_init_udelay(void) 679 { 680 /* if cmdline changed it from default, leave it alone */ 681 if (init_udelay != UINT_MAX) 682 return; 683 684 /* if modern processor, use no delay */ 685 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 686 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 687 init_udelay = 0; 688 return; 689 } 690 /* else, use legacy delay */ 691 init_udelay = UDELAY_10MS_DEFAULT; 692 } 693 694 /* 695 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 696 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 697 * won't ... remember to clear down the APIC, etc later. 698 */ 699 int 700 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 701 { 702 unsigned long send_status, accept_status = 0; 703 int maxlvt; 704 705 /* Target chip */ 706 /* Boot on the stack */ 707 /* Kick the second */ 708 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 709 710 pr_debug("Waiting for send to finish...\n"); 711 send_status = safe_apic_wait_icr_idle(); 712 713 /* 714 * Give the other CPU some time to accept the IPI. 715 */ 716 udelay(200); 717 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 718 maxlvt = lapic_get_maxlvt(); 719 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 720 apic_write(APIC_ESR, 0); 721 accept_status = (apic_read(APIC_ESR) & 0xEF); 722 } 723 pr_debug("NMI sent\n"); 724 725 if (send_status) 726 pr_err("APIC never delivered???\n"); 727 if (accept_status) 728 pr_err("APIC delivery error (%lx)\n", accept_status); 729 730 return (send_status | accept_status); 731 } 732 733 static int 734 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 735 { 736 unsigned long send_status = 0, accept_status = 0; 737 int maxlvt, num_starts, j; 738 739 maxlvt = lapic_get_maxlvt(); 740 741 /* 742 * Be paranoid about clearing APIC errors. 743 */ 744 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 745 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 746 apic_write(APIC_ESR, 0); 747 apic_read(APIC_ESR); 748 } 749 750 pr_debug("Asserting INIT\n"); 751 752 /* 753 * Turn INIT on target chip 754 */ 755 /* 756 * Send IPI 757 */ 758 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 759 phys_apicid); 760 761 pr_debug("Waiting for send to finish...\n"); 762 send_status = safe_apic_wait_icr_idle(); 763 764 udelay(init_udelay); 765 766 pr_debug("Deasserting INIT\n"); 767 768 /* Target chip */ 769 /* Send IPI */ 770 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 771 772 pr_debug("Waiting for send to finish...\n"); 773 send_status = safe_apic_wait_icr_idle(); 774 775 mb(); 776 777 /* 778 * Should we send STARTUP IPIs ? 779 * 780 * Determine this based on the APIC version. 781 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 782 */ 783 if (APIC_INTEGRATED(boot_cpu_apic_version)) 784 num_starts = 2; 785 else 786 num_starts = 0; 787 788 /* 789 * Run STARTUP IPI loop. 790 */ 791 pr_debug("#startup loops: %d\n", num_starts); 792 793 for (j = 1; j <= num_starts; j++) { 794 pr_debug("Sending STARTUP #%d\n", j); 795 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 796 apic_write(APIC_ESR, 0); 797 apic_read(APIC_ESR); 798 pr_debug("After apic_write\n"); 799 800 /* 801 * STARTUP IPI 802 */ 803 804 /* Target chip */ 805 /* Boot on the stack */ 806 /* Kick the second */ 807 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 808 phys_apicid); 809 810 /* 811 * Give the other CPU some time to accept the IPI. 812 */ 813 if (init_udelay == 0) 814 udelay(10); 815 else 816 udelay(300); 817 818 pr_debug("Startup point 1\n"); 819 820 pr_debug("Waiting for send to finish...\n"); 821 send_status = safe_apic_wait_icr_idle(); 822 823 /* 824 * Give the other CPU some time to accept the IPI. 825 */ 826 if (init_udelay == 0) 827 udelay(10); 828 else 829 udelay(200); 830 831 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 832 apic_write(APIC_ESR, 0); 833 accept_status = (apic_read(APIC_ESR) & 0xEF); 834 if (send_status || accept_status) 835 break; 836 } 837 pr_debug("After Startup\n"); 838 839 if (send_status) 840 pr_err("APIC never delivered???\n"); 841 if (accept_status) 842 pr_err("APIC delivery error (%lx)\n", accept_status); 843 844 return (send_status | accept_status); 845 } 846 847 /* reduce the number of lines printed when booting a large cpu count system */ 848 static void announce_cpu(int cpu, int apicid) 849 { 850 static int current_node = -1; 851 int node = early_cpu_to_node(cpu); 852 static int width, node_width; 853 854 if (!width) 855 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 856 857 if (!node_width) 858 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 859 860 if (cpu == 1) 861 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 862 863 if (system_state == SYSTEM_BOOTING) { 864 if (node != current_node) { 865 if (current_node > (-1)) 866 pr_cont("\n"); 867 current_node = node; 868 869 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 870 node_width - num_digits(node), " ", node); 871 } 872 873 /* Add padding for the BSP */ 874 if (cpu == 1) 875 pr_cont("%*s", width + 1, " "); 876 877 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 878 879 } else 880 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 881 node, cpu, apicid); 882 } 883 884 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 885 { 886 int cpu; 887 888 cpu = smp_processor_id(); 889 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 890 return NMI_HANDLED; 891 892 return NMI_DONE; 893 } 894 895 /* 896 * Wake up AP by INIT, INIT, STARTUP sequence. 897 * 898 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 899 * boot-strap code which is not a desired behavior for waking up BSP. To 900 * void the boot-strap code, wake up CPU0 by NMI instead. 901 * 902 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 903 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 904 * We'll change this code in the future to wake up hard offlined CPU0 if 905 * real platform and request are available. 906 */ 907 static int 908 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 909 int *cpu0_nmi_registered) 910 { 911 int id; 912 int boot_error; 913 914 preempt_disable(); 915 916 /* 917 * Wake up AP by INIT, INIT, STARTUP sequence. 918 */ 919 if (cpu) { 920 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 921 goto out; 922 } 923 924 /* 925 * Wake up BSP by nmi. 926 * 927 * Register a NMI handler to help wake up CPU0. 928 */ 929 boot_error = register_nmi_handler(NMI_LOCAL, 930 wakeup_cpu0_nmi, 0, "wake_cpu0"); 931 932 if (!boot_error) { 933 enable_start_cpu0 = 1; 934 *cpu0_nmi_registered = 1; 935 if (apic->dest_logical == APIC_DEST_LOGICAL) 936 id = cpu0_logical_apicid; 937 else 938 id = apicid; 939 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 940 } 941 942 out: 943 preempt_enable(); 944 945 return boot_error; 946 } 947 948 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 949 { 950 /* Just in case we booted with a single CPU. */ 951 alternatives_enable_smp(); 952 953 per_cpu(current_task, cpu) = idle; 954 955 #ifdef CONFIG_X86_32 956 /* Stack for startup_32 can be just as for start_secondary onwards */ 957 irq_ctx_init(cpu); 958 per_cpu(cpu_current_top_of_stack, cpu) = 959 (unsigned long)task_stack_page(idle) + THREAD_SIZE; 960 #else 961 initial_gs = per_cpu_offset(cpu); 962 #endif 963 } 964 965 /* 966 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 967 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 968 * Returns zero if CPU booted OK, else error code from 969 * ->wakeup_secondary_cpu. 970 */ 971 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 972 { 973 volatile u32 *trampoline_status = 974 (volatile u32 *) __va(real_mode_header->trampoline_status); 975 /* start_ip had better be page-aligned! */ 976 unsigned long start_ip = real_mode_header->trampoline_start; 977 978 unsigned long boot_error = 0; 979 int cpu0_nmi_registered = 0; 980 unsigned long timeout; 981 982 idle->thread.sp = (unsigned long)task_pt_regs(idle); 983 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 984 initial_code = (unsigned long)start_secondary; 985 initial_stack = idle->thread.sp; 986 987 /* 988 * Enable the espfix hack for this CPU 989 */ 990 #ifdef CONFIG_X86_ESPFIX64 991 init_espfix_ap(cpu); 992 #endif 993 994 /* So we see what's up */ 995 announce_cpu(cpu, apicid); 996 997 /* 998 * This grunge runs the startup process for 999 * the targeted processor. 1000 */ 1001 1002 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 1003 1004 pr_debug("Setting warm reset code and vector.\n"); 1005 1006 smpboot_setup_warm_reset_vector(start_ip); 1007 /* 1008 * Be paranoid about clearing APIC errors. 1009 */ 1010 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1011 apic_write(APIC_ESR, 0); 1012 apic_read(APIC_ESR); 1013 } 1014 } 1015 1016 /* 1017 * AP might wait on cpu_callout_mask in cpu_init() with 1018 * cpu_initialized_mask set if previous attempt to online 1019 * it timed-out. Clear cpu_initialized_mask so that after 1020 * INIT/SIPI it could start with a clean state. 1021 */ 1022 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1023 smp_mb(); 1024 1025 /* 1026 * Wake up a CPU in difference cases: 1027 * - Use the method in the APIC driver if it's defined 1028 * Otherwise, 1029 * - Use an INIT boot APIC message for APs or NMI for BSP. 1030 */ 1031 if (apic->wakeup_secondary_cpu) 1032 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1033 else 1034 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1035 &cpu0_nmi_registered); 1036 1037 if (!boot_error) { 1038 /* 1039 * Wait 10s total for first sign of life from AP 1040 */ 1041 boot_error = -1; 1042 timeout = jiffies + 10*HZ; 1043 while (time_before(jiffies, timeout)) { 1044 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1045 /* 1046 * Tell AP to proceed with initialization 1047 */ 1048 cpumask_set_cpu(cpu, cpu_callout_mask); 1049 boot_error = 0; 1050 break; 1051 } 1052 schedule(); 1053 } 1054 } 1055 1056 if (!boot_error) { 1057 /* 1058 * Wait till AP completes initial initialization 1059 */ 1060 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1061 /* 1062 * Allow other tasks to run while we wait for the 1063 * AP to come online. This also gives a chance 1064 * for the MTRR work(triggered by the AP coming online) 1065 * to be completed in the stop machine context. 1066 */ 1067 schedule(); 1068 } 1069 } 1070 1071 /* mark "stuck" area as not stuck */ 1072 *trampoline_status = 0; 1073 1074 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 1075 /* 1076 * Cleanup possible dangling ends... 1077 */ 1078 smpboot_restore_warm_reset_vector(); 1079 } 1080 /* 1081 * Clean up the nmi handler. Do this after the callin and callout sync 1082 * to avoid impact of possible long unregister time. 1083 */ 1084 if (cpu0_nmi_registered) 1085 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1086 1087 return boot_error; 1088 } 1089 1090 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1091 { 1092 int apicid = apic->cpu_present_to_apicid(cpu); 1093 unsigned long flags; 1094 int err; 1095 1096 WARN_ON(irqs_disabled()); 1097 1098 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1099 1100 if (apicid == BAD_APICID || 1101 !physid_isset(apicid, phys_cpu_present_map) || 1102 !apic->apic_id_valid(apicid)) { 1103 pr_err("%s: bad cpu %d\n", __func__, cpu); 1104 return -EINVAL; 1105 } 1106 1107 /* 1108 * Already booted CPU? 1109 */ 1110 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1111 pr_debug("do_boot_cpu %d Already started\n", cpu); 1112 return -ENOSYS; 1113 } 1114 1115 /* 1116 * Save current MTRR state in case it was changed since early boot 1117 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1118 */ 1119 mtrr_save_state(); 1120 1121 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1122 err = cpu_check_up_prepare(cpu); 1123 if (err && err != -EBUSY) 1124 return err; 1125 1126 /* the FPU context is blank, nobody can own it */ 1127 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1128 1129 common_cpu_up(cpu, tidle); 1130 1131 err = do_boot_cpu(apicid, cpu, tidle); 1132 if (err) { 1133 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1134 return -EIO; 1135 } 1136 1137 /* 1138 * Check TSC synchronization with the AP (keep irqs disabled 1139 * while doing so): 1140 */ 1141 local_irq_save(flags); 1142 check_tsc_sync_source(cpu); 1143 local_irq_restore(flags); 1144 1145 while (!cpu_online(cpu)) { 1146 cpu_relax(); 1147 touch_nmi_watchdog(); 1148 } 1149 1150 return 0; 1151 } 1152 1153 /** 1154 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1155 */ 1156 void arch_disable_smp_support(void) 1157 { 1158 disable_ioapic_support(); 1159 } 1160 1161 /* 1162 * Fall back to non SMP mode after errors. 1163 * 1164 * RED-PEN audit/test this more. I bet there is more state messed up here. 1165 */ 1166 static __init void disable_smp(void) 1167 { 1168 pr_info("SMP disabled\n"); 1169 1170 disable_ioapic_support(); 1171 1172 init_cpu_present(cpumask_of(0)); 1173 init_cpu_possible(cpumask_of(0)); 1174 1175 if (smp_found_config) 1176 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1177 else 1178 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1179 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1180 cpumask_set_cpu(0, topology_core_cpumask(0)); 1181 } 1182 1183 enum { 1184 SMP_OK, 1185 SMP_NO_CONFIG, 1186 SMP_NO_APIC, 1187 SMP_FORCE_UP, 1188 }; 1189 1190 /* 1191 * Various sanity checks. 1192 */ 1193 static int __init smp_sanity_check(unsigned max_cpus) 1194 { 1195 preempt_disable(); 1196 1197 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1198 if (def_to_bigsmp && nr_cpu_ids > 8) { 1199 unsigned int cpu; 1200 unsigned nr; 1201 1202 pr_warn("More than 8 CPUs detected - skipping them\n" 1203 "Use CONFIG_X86_BIGSMP\n"); 1204 1205 nr = 0; 1206 for_each_present_cpu(cpu) { 1207 if (nr >= 8) 1208 set_cpu_present(cpu, false); 1209 nr++; 1210 } 1211 1212 nr = 0; 1213 for_each_possible_cpu(cpu) { 1214 if (nr >= 8) 1215 set_cpu_possible(cpu, false); 1216 nr++; 1217 } 1218 1219 nr_cpu_ids = 8; 1220 } 1221 #endif 1222 1223 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1224 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1225 hard_smp_processor_id()); 1226 1227 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1228 } 1229 1230 /* 1231 * If we couldn't find an SMP configuration at boot time, 1232 * get out of here now! 1233 */ 1234 if (!smp_found_config && !acpi_lapic) { 1235 preempt_enable(); 1236 pr_notice("SMP motherboard not detected\n"); 1237 return SMP_NO_CONFIG; 1238 } 1239 1240 /* 1241 * Should not be necessary because the MP table should list the boot 1242 * CPU too, but we do it for the sake of robustness anyway. 1243 */ 1244 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1245 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1246 boot_cpu_physical_apicid); 1247 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1248 } 1249 preempt_enable(); 1250 1251 /* 1252 * If we couldn't find a local APIC, then get out of here now! 1253 */ 1254 if (APIC_INTEGRATED(boot_cpu_apic_version) && 1255 !boot_cpu_has(X86_FEATURE_APIC)) { 1256 if (!disable_apic) { 1257 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1258 boot_cpu_physical_apicid); 1259 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1260 } 1261 return SMP_NO_APIC; 1262 } 1263 1264 /* 1265 * If SMP should be disabled, then really disable it! 1266 */ 1267 if (!max_cpus) { 1268 pr_info("SMP mode deactivated\n"); 1269 return SMP_FORCE_UP; 1270 } 1271 1272 return SMP_OK; 1273 } 1274 1275 static void __init smp_cpu_index_default(void) 1276 { 1277 int i; 1278 struct cpuinfo_x86 *c; 1279 1280 for_each_possible_cpu(i) { 1281 c = &cpu_data(i); 1282 /* mark all to hotplug */ 1283 c->cpu_index = nr_cpu_ids; 1284 } 1285 } 1286 1287 /* 1288 * Prepare for SMP bootup. The MP table or ACPI has been read 1289 * earlier. Just do some sanity checking here and enable APIC mode. 1290 */ 1291 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1292 { 1293 unsigned int i; 1294 1295 smp_cpu_index_default(); 1296 1297 /* 1298 * Setup boot CPU information 1299 */ 1300 smp_store_boot_cpu_info(); /* Final full version of the data */ 1301 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1302 mb(); 1303 1304 for_each_possible_cpu(i) { 1305 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1306 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1307 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1308 } 1309 1310 /* 1311 * Set 'default' x86 topology, this matches default_topology() in that 1312 * it has NUMA nodes as a topology level. See also 1313 * native_smp_cpus_done(). 1314 * 1315 * Must be done before set_cpus_sibling_map() is ran. 1316 */ 1317 set_sched_topology(x86_topology); 1318 1319 set_cpu_sibling_map(0); 1320 1321 switch (smp_sanity_check(max_cpus)) { 1322 case SMP_NO_CONFIG: 1323 disable_smp(); 1324 if (APIC_init_uniprocessor()) 1325 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1326 return; 1327 case SMP_NO_APIC: 1328 disable_smp(); 1329 return; 1330 case SMP_FORCE_UP: 1331 disable_smp(); 1332 apic_bsp_setup(false); 1333 return; 1334 case SMP_OK: 1335 break; 1336 } 1337 1338 if (read_apic_id() != boot_cpu_physical_apicid) { 1339 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1340 read_apic_id(), boot_cpu_physical_apicid); 1341 /* Or can we switch back to PIC here? */ 1342 } 1343 1344 default_setup_apic_routing(); 1345 cpu0_logical_apicid = apic_bsp_setup(false); 1346 1347 pr_info("CPU0: "); 1348 print_cpu_info(&cpu_data(0)); 1349 1350 uv_system_init(); 1351 1352 set_mtrr_aps_delayed_init(); 1353 1354 smp_quirk_init_udelay(); 1355 } 1356 1357 void arch_enable_nonboot_cpus_begin(void) 1358 { 1359 set_mtrr_aps_delayed_init(); 1360 } 1361 1362 void arch_enable_nonboot_cpus_end(void) 1363 { 1364 mtrr_aps_init(); 1365 } 1366 1367 /* 1368 * Early setup to make printk work. 1369 */ 1370 void __init native_smp_prepare_boot_cpu(void) 1371 { 1372 int me = smp_processor_id(); 1373 switch_to_new_gdt(me); 1374 /* already set me in cpu_online_mask in boot_cpu_init() */ 1375 cpumask_set_cpu(me, cpu_callout_mask); 1376 cpu_set_state_online(me); 1377 } 1378 1379 void __init native_smp_cpus_done(unsigned int max_cpus) 1380 { 1381 pr_debug("Boot done\n"); 1382 1383 if (x86_has_numa_in_package) 1384 set_sched_topology(x86_numa_in_package_topology); 1385 1386 nmi_selftest(); 1387 impress_friends(); 1388 setup_ioapic_dest(); 1389 mtrr_aps_init(); 1390 } 1391 1392 static int __initdata setup_possible_cpus = -1; 1393 static int __init _setup_possible_cpus(char *str) 1394 { 1395 get_option(&str, &setup_possible_cpus); 1396 return 0; 1397 } 1398 early_param("possible_cpus", _setup_possible_cpus); 1399 1400 1401 /* 1402 * cpu_possible_mask should be static, it cannot change as cpu's 1403 * are onlined, or offlined. The reason is per-cpu data-structures 1404 * are allocated by some modules at init time, and dont expect to 1405 * do this dynamically on cpu arrival/departure. 1406 * cpu_present_mask on the other hand can change dynamically. 1407 * In case when cpu_hotplug is not compiled, then we resort to current 1408 * behaviour, which is cpu_possible == cpu_present. 1409 * - Ashok Raj 1410 * 1411 * Three ways to find out the number of additional hotplug CPUs: 1412 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1413 * - The user can overwrite it with possible_cpus=NUM 1414 * - Otherwise don't reserve additional CPUs. 1415 * We do this because additional CPUs waste a lot of memory. 1416 * -AK 1417 */ 1418 __init void prefill_possible_map(void) 1419 { 1420 int i, possible; 1421 1422 /* No boot processor was found in mptable or ACPI MADT */ 1423 if (!num_processors) { 1424 if (boot_cpu_has(X86_FEATURE_APIC)) { 1425 int apicid = boot_cpu_physical_apicid; 1426 int cpu = hard_smp_processor_id(); 1427 1428 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1429 1430 /* Make sure boot cpu is enumerated */ 1431 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1432 apic->apic_id_valid(apicid)) 1433 generic_processor_info(apicid, boot_cpu_apic_version); 1434 } 1435 1436 if (!num_processors) 1437 num_processors = 1; 1438 } 1439 1440 i = setup_max_cpus ?: 1; 1441 if (setup_possible_cpus == -1) { 1442 possible = num_processors; 1443 #ifdef CONFIG_HOTPLUG_CPU 1444 if (setup_max_cpus) 1445 possible += disabled_cpus; 1446 #else 1447 if (possible > i) 1448 possible = i; 1449 #endif 1450 } else 1451 possible = setup_possible_cpus; 1452 1453 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1454 1455 /* nr_cpu_ids could be reduced via nr_cpus= */ 1456 if (possible > nr_cpu_ids) { 1457 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", 1458 possible, nr_cpu_ids); 1459 possible = nr_cpu_ids; 1460 } 1461 1462 #ifdef CONFIG_HOTPLUG_CPU 1463 if (!setup_max_cpus) 1464 #endif 1465 if (possible > i) { 1466 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1467 possible, setup_max_cpus); 1468 possible = i; 1469 } 1470 1471 nr_cpu_ids = possible; 1472 1473 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1474 possible, max_t(int, possible - num_processors, 0)); 1475 1476 reset_cpu_possible_mask(); 1477 1478 for (i = 0; i < possible; i++) 1479 set_cpu_possible(i, true); 1480 } 1481 1482 #ifdef CONFIG_HOTPLUG_CPU 1483 1484 /* Recompute SMT state for all CPUs on offline */ 1485 static void recompute_smt_state(void) 1486 { 1487 int max_threads, cpu; 1488 1489 max_threads = 0; 1490 for_each_online_cpu (cpu) { 1491 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1492 1493 if (threads > max_threads) 1494 max_threads = threads; 1495 } 1496 __max_smt_threads = max_threads; 1497 } 1498 1499 static void remove_siblinginfo(int cpu) 1500 { 1501 int sibling; 1502 struct cpuinfo_x86 *c = &cpu_data(cpu); 1503 1504 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1505 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1506 /*/ 1507 * last thread sibling in this cpu core going down 1508 */ 1509 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1510 cpu_data(sibling).booted_cores--; 1511 } 1512 1513 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1514 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1515 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1516 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1517 cpumask_clear(cpu_llc_shared_mask(cpu)); 1518 cpumask_clear(topology_sibling_cpumask(cpu)); 1519 cpumask_clear(topology_core_cpumask(cpu)); 1520 c->phys_proc_id = 0; 1521 c->cpu_core_id = 0; 1522 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1523 recompute_smt_state(); 1524 } 1525 1526 static void remove_cpu_from_maps(int cpu) 1527 { 1528 set_cpu_online(cpu, false); 1529 cpumask_clear_cpu(cpu, cpu_callout_mask); 1530 cpumask_clear_cpu(cpu, cpu_callin_mask); 1531 /* was set by cpu_init() */ 1532 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1533 numa_remove_cpu(cpu); 1534 } 1535 1536 void cpu_disable_common(void) 1537 { 1538 int cpu = smp_processor_id(); 1539 1540 remove_siblinginfo(cpu); 1541 1542 /* It's now safe to remove this processor from the online map */ 1543 lock_vector_lock(); 1544 remove_cpu_from_maps(cpu); 1545 unlock_vector_lock(); 1546 fixup_irqs(); 1547 } 1548 1549 int native_cpu_disable(void) 1550 { 1551 int ret; 1552 1553 ret = check_irq_vectors_for_cpu_disable(); 1554 if (ret) 1555 return ret; 1556 1557 clear_local_APIC(); 1558 cpu_disable_common(); 1559 1560 return 0; 1561 } 1562 1563 int common_cpu_die(unsigned int cpu) 1564 { 1565 int ret = 0; 1566 1567 /* We don't do anything here: idle task is faking death itself. */ 1568 1569 /* They ack this in play_dead() by setting CPU_DEAD */ 1570 if (cpu_wait_death(cpu, 5)) { 1571 if (system_state == SYSTEM_RUNNING) 1572 pr_info("CPU %u is now offline\n", cpu); 1573 } else { 1574 pr_err("CPU %u didn't die...\n", cpu); 1575 ret = -1; 1576 } 1577 1578 return ret; 1579 } 1580 1581 void native_cpu_die(unsigned int cpu) 1582 { 1583 common_cpu_die(cpu); 1584 } 1585 1586 void play_dead_common(void) 1587 { 1588 idle_task_exit(); 1589 reset_lazy_tlbstate(); 1590 1591 /* Ack it */ 1592 (void)cpu_report_death(); 1593 1594 /* 1595 * With physical CPU hotplug, we should halt the cpu 1596 */ 1597 local_irq_disable(); 1598 } 1599 1600 static bool wakeup_cpu0(void) 1601 { 1602 if (smp_processor_id() == 0 && enable_start_cpu0) 1603 return true; 1604 1605 return false; 1606 } 1607 1608 /* 1609 * We need to flush the caches before going to sleep, lest we have 1610 * dirty data in our caches when we come back up. 1611 */ 1612 static inline void mwait_play_dead(void) 1613 { 1614 unsigned int eax, ebx, ecx, edx; 1615 unsigned int highest_cstate = 0; 1616 unsigned int highest_subcstate = 0; 1617 void *mwait_ptr; 1618 int i; 1619 1620 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1621 return; 1622 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1623 return; 1624 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1625 return; 1626 1627 eax = CPUID_MWAIT_LEAF; 1628 ecx = 0; 1629 native_cpuid(&eax, &ebx, &ecx, &edx); 1630 1631 /* 1632 * eax will be 0 if EDX enumeration is not valid. 1633 * Initialized below to cstate, sub_cstate value when EDX is valid. 1634 */ 1635 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1636 eax = 0; 1637 } else { 1638 edx >>= MWAIT_SUBSTATE_SIZE; 1639 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1640 if (edx & MWAIT_SUBSTATE_MASK) { 1641 highest_cstate = i; 1642 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1643 } 1644 } 1645 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1646 (highest_subcstate - 1); 1647 } 1648 1649 /* 1650 * This should be a memory location in a cache line which is 1651 * unlikely to be touched by other processors. The actual 1652 * content is immaterial as it is not actually modified in any way. 1653 */ 1654 mwait_ptr = ¤t_thread_info()->flags; 1655 1656 wbinvd(); 1657 1658 while (1) { 1659 /* 1660 * The CLFLUSH is a workaround for erratum AAI65 for 1661 * the Xeon 7400 series. It's not clear it is actually 1662 * needed, but it should be harmless in either case. 1663 * The WBINVD is insufficient due to the spurious-wakeup 1664 * case where we return around the loop. 1665 */ 1666 mb(); 1667 clflush(mwait_ptr); 1668 mb(); 1669 __monitor(mwait_ptr, 0, 0); 1670 mb(); 1671 __mwait(eax, 0); 1672 /* 1673 * If NMI wants to wake up CPU0, start CPU0. 1674 */ 1675 if (wakeup_cpu0()) 1676 start_cpu0(); 1677 } 1678 } 1679 1680 void hlt_play_dead(void) 1681 { 1682 if (__this_cpu_read(cpu_info.x86) >= 4) 1683 wbinvd(); 1684 1685 while (1) { 1686 native_halt(); 1687 /* 1688 * If NMI wants to wake up CPU0, start CPU0. 1689 */ 1690 if (wakeup_cpu0()) 1691 start_cpu0(); 1692 } 1693 } 1694 1695 void native_play_dead(void) 1696 { 1697 play_dead_common(); 1698 tboot_shutdown(TB_SHUTDOWN_WFS); 1699 1700 mwait_play_dead(); /* Only returns on failure */ 1701 if (cpuidle_play_dead()) 1702 hlt_play_dead(); 1703 } 1704 1705 #else /* ... !CONFIG_HOTPLUG_CPU */ 1706 int native_cpu_disable(void) 1707 { 1708 return -ENOSYS; 1709 } 1710 1711 void native_cpu_die(unsigned int cpu) 1712 { 1713 /* We said "no" in __cpu_disable */ 1714 BUG(); 1715 } 1716 1717 void native_play_dead(void) 1718 { 1719 BUG(); 1720 } 1721 1722 #endif 1723