1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/export.h> 47 #include <linux/sched.h> 48 #include <linux/percpu.h> 49 #include <linux/bootmem.h> 50 #include <linux/err.h> 51 #include <linux/nmi.h> 52 #include <linux/tboot.h> 53 #include <linux/stackprotector.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 57 #include <asm/acpi.h> 58 #include <asm/desc.h> 59 #include <asm/nmi.h> 60 #include <asm/irq.h> 61 #include <asm/realmode.h> 62 #include <asm/cpu.h> 63 #include <asm/numa.h> 64 #include <asm/pgtable.h> 65 #include <asm/tlbflush.h> 66 #include <asm/mtrr.h> 67 #include <asm/mwait.h> 68 #include <asm/apic.h> 69 #include <asm/io_apic.h> 70 #include <asm/fpu/internal.h> 71 #include <asm/setup.h> 72 #include <asm/uv/uv.h> 73 #include <linux/mc146818rtc.h> 74 #include <asm/i8259.h> 75 #include <asm/realmode.h> 76 #include <asm/misc.h> 77 78 /* Number of siblings per CPU package */ 79 int smp_num_siblings = 1; 80 EXPORT_SYMBOL(smp_num_siblings); 81 82 /* Last level cache ID of each logical CPU */ 83 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 84 85 /* representing HT siblings of each logical CPU */ 86 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 87 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 88 89 /* representing HT and core siblings of each logical CPU */ 90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 91 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 92 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 94 95 /* Per CPU bogomips and other parameters */ 96 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 97 EXPORT_PER_CPU_SYMBOL(cpu_info); 98 99 /* Logical package management. We might want to allocate that dynamically */ 100 static int *physical_to_logical_pkg __read_mostly; 101 static unsigned long *physical_package_map __read_mostly;; 102 static unsigned int max_physical_pkg_id __read_mostly; 103 unsigned int __max_logical_packages __read_mostly; 104 EXPORT_SYMBOL(__max_logical_packages); 105 static unsigned int logical_packages __read_mostly; 106 static bool logical_packages_frozen __read_mostly; 107 108 /* Maximum number of SMT threads on any online core */ 109 int __max_smt_threads __read_mostly; 110 111 /* Flag to indicate if a complete sched domain rebuild is required */ 112 bool x86_topology_update; 113 114 int arch_update_cpu_topology(void) 115 { 116 int retval = x86_topology_update; 117 118 x86_topology_update = false; 119 return retval; 120 } 121 122 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 123 { 124 unsigned long flags; 125 126 spin_lock_irqsave(&rtc_lock, flags); 127 CMOS_WRITE(0xa, 0xf); 128 spin_unlock_irqrestore(&rtc_lock, flags); 129 local_flush_tlb(); 130 pr_debug("1.\n"); 131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 132 start_eip >> 4; 133 pr_debug("2.\n"); 134 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 135 start_eip & 0xf; 136 pr_debug("3.\n"); 137 } 138 139 static inline void smpboot_restore_warm_reset_vector(void) 140 { 141 unsigned long flags; 142 143 /* 144 * Install writable page 0 entry to set BIOS data area. 145 */ 146 local_flush_tlb(); 147 148 /* 149 * Paranoid: Set warm reset code and vector here back 150 * to default values. 151 */ 152 spin_lock_irqsave(&rtc_lock, flags); 153 CMOS_WRITE(0, 0xf); 154 spin_unlock_irqrestore(&rtc_lock, flags); 155 156 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 157 } 158 159 /* 160 * Report back to the Boot Processor during boot time or to the caller processor 161 * during CPU online. 162 */ 163 static void smp_callin(void) 164 { 165 int cpuid, phys_id; 166 167 /* 168 * If waken up by an INIT in an 82489DX configuration 169 * cpu_callout_mask guarantees we don't get here before 170 * an INIT_deassert IPI reaches our local APIC, so it is 171 * now safe to touch our local APIC. 172 */ 173 cpuid = smp_processor_id(); 174 175 /* 176 * (This works even if the APIC is not enabled.) 177 */ 178 phys_id = read_apic_id(); 179 180 /* 181 * the boot CPU has finished the init stage and is spinning 182 * on callin_map until we finish. We are free to set up this 183 * CPU, first the APIC. (this is probably redundant on most 184 * boards) 185 */ 186 apic_ap_setup(); 187 188 /* 189 * Save our processor parameters. Note: this information 190 * is needed for clock calibration. 191 */ 192 smp_store_cpu_info(cpuid); 193 194 /* 195 * Get our bogomips. 196 * Update loops_per_jiffy in cpu_data. Previous call to 197 * smp_store_cpu_info() stored a value that is close but not as 198 * accurate as the value just calculated. 199 */ 200 calibrate_delay(); 201 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 202 pr_debug("Stack at about %p\n", &cpuid); 203 204 /* 205 * This must be done before setting cpu_online_mask 206 * or calling notify_cpu_starting. 207 */ 208 set_cpu_sibling_map(raw_smp_processor_id()); 209 wmb(); 210 211 notify_cpu_starting(cpuid); 212 213 /* 214 * Allow the master to continue. 215 */ 216 cpumask_set_cpu(cpuid, cpu_callin_mask); 217 } 218 219 static int cpu0_logical_apicid; 220 static int enable_start_cpu0; 221 /* 222 * Activate a secondary processor. 223 */ 224 static void notrace start_secondary(void *unused) 225 { 226 /* 227 * Don't put *anything* before cpu_init(), SMP booting is too 228 * fragile that we want to limit the things done here to the 229 * most necessary things. 230 */ 231 cpu_init(); 232 x86_cpuinit.early_percpu_clock_init(); 233 preempt_disable(); 234 smp_callin(); 235 236 enable_start_cpu0 = 0; 237 238 #ifdef CONFIG_X86_32 239 /* switch away from the initial page table */ 240 load_cr3(swapper_pg_dir); 241 __flush_tlb_all(); 242 #endif 243 244 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 245 barrier(); 246 /* 247 * Check TSC synchronization with the BP: 248 */ 249 check_tsc_sync_target(); 250 251 /* 252 * Lock vector_lock and initialize the vectors on this cpu 253 * before setting the cpu online. We must set it online with 254 * vector_lock held to prevent a concurrent setup/teardown 255 * from seeing a half valid vector space. 256 */ 257 lock_vector_lock(); 258 setup_vector_irq(smp_processor_id()); 259 set_cpu_online(smp_processor_id(), true); 260 unlock_vector_lock(); 261 cpu_set_state_online(smp_processor_id()); 262 x86_platform.nmi_init(); 263 264 /* enable local interrupts */ 265 local_irq_enable(); 266 267 /* to prevent fake stack check failure in clock setup */ 268 boot_init_stack_canary(); 269 270 x86_cpuinit.setup_percpu_clockev(); 271 272 wmb(); 273 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 274 } 275 276 int topology_update_package_map(unsigned int apicid, unsigned int cpu) 277 { 278 unsigned int new, pkg = apicid >> boot_cpu_data.x86_coreid_bits; 279 280 /* Called from early boot ? */ 281 if (!physical_package_map) 282 return 0; 283 284 if (pkg >= max_physical_pkg_id) 285 return -EINVAL; 286 287 /* Set the logical package id */ 288 if (test_and_set_bit(pkg, physical_package_map)) 289 goto found; 290 291 if (logical_packages_frozen) { 292 physical_to_logical_pkg[pkg] = -1; 293 pr_warn("APIC(%x) Package %u exceeds logical package max\n", 294 apicid, pkg); 295 return -ENOSPC; 296 } 297 298 new = logical_packages++; 299 pr_info("APIC(%x) Converting physical %u to logical package %u\n", 300 apicid, pkg, new); 301 physical_to_logical_pkg[pkg] = new; 302 303 found: 304 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; 305 return 0; 306 } 307 308 /** 309 * topology_phys_to_logical_pkg - Map a physical package id to a logical 310 * 311 * Returns logical package id or -1 if not found 312 */ 313 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 314 { 315 if (phys_pkg >= max_physical_pkg_id) 316 return -1; 317 return physical_to_logical_pkg[phys_pkg]; 318 } 319 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 320 321 static void __init smp_init_package_map(void) 322 { 323 unsigned int ncpus, cpu; 324 size_t size; 325 326 /* 327 * Today neither Intel nor AMD support heterogenous systems. That 328 * might change in the future.... 329 * 330 * While ideally we'd want '* smp_num_siblings' in the below @ncpus 331 * computation, this won't actually work since some Intel BIOSes 332 * report inconsistent HT data when they disable HT. 333 * 334 * In particular, they reduce the APIC-IDs to only include the cores, 335 * but leave the CPUID topology to say there are (2) siblings. 336 * This means we don't know how many threads there will be until 337 * after the APIC enumeration. 338 * 339 * By not including this we'll sometimes over-estimate the number of 340 * logical packages by the amount of !present siblings, but this is 341 * still better than MAX_LOCAL_APIC. 342 * 343 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited 344 * on the command line leading to a similar issue as the HT disable 345 * problem because the hyperthreads are usually enumerated after the 346 * primary cores. 347 */ 348 ncpus = boot_cpu_data.x86_max_cores; 349 if (!ncpus) { 350 pr_warn("x86_max_cores == zero !?!?"); 351 ncpus = 1; 352 } 353 354 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 355 logical_packages = 0; 356 357 /* 358 * Possibly larger than what we need as the number of apic ids per 359 * package can be smaller than the actual used apic ids. 360 */ 361 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); 362 size = max_physical_pkg_id * sizeof(unsigned int); 363 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); 364 memset(physical_to_logical_pkg, 0xff, size); 365 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); 366 physical_package_map = kzalloc(size, GFP_KERNEL); 367 368 for_each_present_cpu(cpu) { 369 unsigned int apicid = apic->cpu_present_to_apicid(cpu); 370 371 if (apicid == BAD_APICID || !apic->apic_id_valid(apicid)) 372 continue; 373 if (!topology_update_package_map(apicid, cpu)) 374 continue; 375 pr_warn("CPU %u APICId %x disabled\n", cpu, apicid); 376 per_cpu(x86_bios_cpu_apicid, cpu) = BAD_APICID; 377 set_cpu_possible(cpu, false); 378 set_cpu_present(cpu, false); 379 } 380 381 if (logical_packages > __max_logical_packages) { 382 pr_warn("Detected more packages (%u), then computed by BIOS data (%u).\n", 383 logical_packages, __max_logical_packages); 384 logical_packages_frozen = true; 385 __max_logical_packages = logical_packages; 386 } 387 388 pr_info("Max logical packages: %u\n", __max_logical_packages); 389 } 390 391 void __init smp_store_boot_cpu_info(void) 392 { 393 int id = 0; /* CPU 0 */ 394 struct cpuinfo_x86 *c = &cpu_data(id); 395 396 *c = boot_cpu_data; 397 c->cpu_index = id; 398 smp_init_package_map(); 399 } 400 401 /* 402 * The bootstrap kernel entry code has set these up. Save them for 403 * a given CPU 404 */ 405 void smp_store_cpu_info(int id) 406 { 407 struct cpuinfo_x86 *c = &cpu_data(id); 408 409 *c = boot_cpu_data; 410 c->cpu_index = id; 411 /* 412 * During boot time, CPU0 has this setup already. Save the info when 413 * bringing up AP or offlined CPU0. 414 */ 415 identify_secondary_cpu(c); 416 } 417 418 static bool 419 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 420 { 421 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 422 423 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 424 } 425 426 static bool 427 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 428 { 429 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 430 431 return !WARN_ONCE(!topology_same_node(c, o), 432 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 433 "[node: %d != %d]. Ignoring dependency.\n", 434 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 435 } 436 437 #define link_mask(mfunc, c1, c2) \ 438 do { \ 439 cpumask_set_cpu((c1), mfunc(c2)); \ 440 cpumask_set_cpu((c2), mfunc(c1)); \ 441 } while (0) 442 443 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 444 { 445 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 446 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 447 448 if (c->phys_proc_id == o->phys_proc_id && 449 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 450 c->cpu_core_id == o->cpu_core_id) 451 return topology_sane(c, o, "smt"); 452 453 } else if (c->phys_proc_id == o->phys_proc_id && 454 c->cpu_core_id == o->cpu_core_id) { 455 return topology_sane(c, o, "smt"); 456 } 457 458 return false; 459 } 460 461 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 462 { 463 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 464 465 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 466 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 467 return topology_sane(c, o, "llc"); 468 469 return false; 470 } 471 472 /* 473 * Unlike the other levels, we do not enforce keeping a 474 * multicore group inside a NUMA node. If this happens, we will 475 * discard the MC level of the topology later. 476 */ 477 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 478 { 479 if (c->phys_proc_id == o->phys_proc_id) 480 return true; 481 return false; 482 } 483 484 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 485 static inline int x86_sched_itmt_flags(void) 486 { 487 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 488 } 489 490 #ifdef CONFIG_SCHED_MC 491 static int x86_core_flags(void) 492 { 493 return cpu_core_flags() | x86_sched_itmt_flags(); 494 } 495 #endif 496 #ifdef CONFIG_SCHED_SMT 497 static int x86_smt_flags(void) 498 { 499 return cpu_smt_flags() | x86_sched_itmt_flags(); 500 } 501 #endif 502 #endif 503 504 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 505 #ifdef CONFIG_SCHED_SMT 506 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 507 #endif 508 #ifdef CONFIG_SCHED_MC 509 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 510 #endif 511 { NULL, }, 512 }; 513 514 static struct sched_domain_topology_level x86_topology[] = { 515 #ifdef CONFIG_SCHED_SMT 516 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 517 #endif 518 #ifdef CONFIG_SCHED_MC 519 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 520 #endif 521 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 522 { NULL, }, 523 }; 524 525 /* 526 * Set if a package/die has multiple NUMA nodes inside. 527 * AMD Magny-Cours and Intel Cluster-on-Die have this. 528 */ 529 static bool x86_has_numa_in_package; 530 531 void set_cpu_sibling_map(int cpu) 532 { 533 bool has_smt = smp_num_siblings > 1; 534 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 535 struct cpuinfo_x86 *c = &cpu_data(cpu); 536 struct cpuinfo_x86 *o; 537 int i, threads; 538 539 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 540 541 if (!has_mp) { 542 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 543 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 544 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 545 c->booted_cores = 1; 546 return; 547 } 548 549 for_each_cpu(i, cpu_sibling_setup_mask) { 550 o = &cpu_data(i); 551 552 if ((i == cpu) || (has_smt && match_smt(c, o))) 553 link_mask(topology_sibling_cpumask, cpu, i); 554 555 if ((i == cpu) || (has_mp && match_llc(c, o))) 556 link_mask(cpu_llc_shared_mask, cpu, i); 557 558 } 559 560 /* 561 * This needs a separate iteration over the cpus because we rely on all 562 * topology_sibling_cpumask links to be set-up. 563 */ 564 for_each_cpu(i, cpu_sibling_setup_mask) { 565 o = &cpu_data(i); 566 567 if ((i == cpu) || (has_mp && match_die(c, o))) { 568 link_mask(topology_core_cpumask, cpu, i); 569 570 /* 571 * Does this new cpu bringup a new core? 572 */ 573 if (cpumask_weight( 574 topology_sibling_cpumask(cpu)) == 1) { 575 /* 576 * for each core in package, increment 577 * the booted_cores for this new cpu 578 */ 579 if (cpumask_first( 580 topology_sibling_cpumask(i)) == i) 581 c->booted_cores++; 582 /* 583 * increment the core count for all 584 * the other cpus in this package 585 */ 586 if (i != cpu) 587 cpu_data(i).booted_cores++; 588 } else if (i != cpu && !c->booted_cores) 589 c->booted_cores = cpu_data(i).booted_cores; 590 } 591 if (match_die(c, o) && !topology_same_node(c, o)) 592 x86_has_numa_in_package = true; 593 } 594 595 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 596 if (threads > __max_smt_threads) 597 __max_smt_threads = threads; 598 } 599 600 /* maps the cpu to the sched domain representing multi-core */ 601 const struct cpumask *cpu_coregroup_mask(int cpu) 602 { 603 return cpu_llc_shared_mask(cpu); 604 } 605 606 static void impress_friends(void) 607 { 608 int cpu; 609 unsigned long bogosum = 0; 610 /* 611 * Allow the user to impress friends. 612 */ 613 pr_debug("Before bogomips\n"); 614 for_each_possible_cpu(cpu) 615 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 616 bogosum += cpu_data(cpu).loops_per_jiffy; 617 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 618 num_online_cpus(), 619 bogosum/(500000/HZ), 620 (bogosum/(5000/HZ))%100); 621 622 pr_debug("Before bogocount - setting activated=1\n"); 623 } 624 625 void __inquire_remote_apic(int apicid) 626 { 627 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 628 const char * const names[] = { "ID", "VERSION", "SPIV" }; 629 int timeout; 630 u32 status; 631 632 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 633 634 for (i = 0; i < ARRAY_SIZE(regs); i++) { 635 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 636 637 /* 638 * Wait for idle. 639 */ 640 status = safe_apic_wait_icr_idle(); 641 if (status) 642 pr_cont("a previous APIC delivery may have failed\n"); 643 644 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 645 646 timeout = 0; 647 do { 648 udelay(100); 649 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 650 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 651 652 switch (status) { 653 case APIC_ICR_RR_VALID: 654 status = apic_read(APIC_RRR); 655 pr_cont("%08x\n", status); 656 break; 657 default: 658 pr_cont("failed\n"); 659 } 660 } 661 } 662 663 /* 664 * The Multiprocessor Specification 1.4 (1997) example code suggests 665 * that there should be a 10ms delay between the BSP asserting INIT 666 * and de-asserting INIT, when starting a remote processor. 667 * But that slows boot and resume on modern processors, which include 668 * many cores and don't require that delay. 669 * 670 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 671 * Modern processor families are quirked to remove the delay entirely. 672 */ 673 #define UDELAY_10MS_DEFAULT 10000 674 675 static unsigned int init_udelay = UINT_MAX; 676 677 static int __init cpu_init_udelay(char *str) 678 { 679 get_option(&str, &init_udelay); 680 681 return 0; 682 } 683 early_param("cpu_init_udelay", cpu_init_udelay); 684 685 static void __init smp_quirk_init_udelay(void) 686 { 687 /* if cmdline changed it from default, leave it alone */ 688 if (init_udelay != UINT_MAX) 689 return; 690 691 /* if modern processor, use no delay */ 692 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 693 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 694 init_udelay = 0; 695 return; 696 } 697 /* else, use legacy delay */ 698 init_udelay = UDELAY_10MS_DEFAULT; 699 } 700 701 /* 702 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 703 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 704 * won't ... remember to clear down the APIC, etc later. 705 */ 706 int 707 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 708 { 709 unsigned long send_status, accept_status = 0; 710 int maxlvt; 711 712 /* Target chip */ 713 /* Boot on the stack */ 714 /* Kick the second */ 715 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 716 717 pr_debug("Waiting for send to finish...\n"); 718 send_status = safe_apic_wait_icr_idle(); 719 720 /* 721 * Give the other CPU some time to accept the IPI. 722 */ 723 udelay(200); 724 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 725 maxlvt = lapic_get_maxlvt(); 726 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 727 apic_write(APIC_ESR, 0); 728 accept_status = (apic_read(APIC_ESR) & 0xEF); 729 } 730 pr_debug("NMI sent\n"); 731 732 if (send_status) 733 pr_err("APIC never delivered???\n"); 734 if (accept_status) 735 pr_err("APIC delivery error (%lx)\n", accept_status); 736 737 return (send_status | accept_status); 738 } 739 740 static int 741 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 742 { 743 unsigned long send_status = 0, accept_status = 0; 744 int maxlvt, num_starts, j; 745 746 maxlvt = lapic_get_maxlvt(); 747 748 /* 749 * Be paranoid about clearing APIC errors. 750 */ 751 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 752 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 753 apic_write(APIC_ESR, 0); 754 apic_read(APIC_ESR); 755 } 756 757 pr_debug("Asserting INIT\n"); 758 759 /* 760 * Turn INIT on target chip 761 */ 762 /* 763 * Send IPI 764 */ 765 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 766 phys_apicid); 767 768 pr_debug("Waiting for send to finish...\n"); 769 send_status = safe_apic_wait_icr_idle(); 770 771 udelay(init_udelay); 772 773 pr_debug("Deasserting INIT\n"); 774 775 /* Target chip */ 776 /* Send IPI */ 777 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 778 779 pr_debug("Waiting for send to finish...\n"); 780 send_status = safe_apic_wait_icr_idle(); 781 782 mb(); 783 784 /* 785 * Should we send STARTUP IPIs ? 786 * 787 * Determine this based on the APIC version. 788 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 789 */ 790 if (APIC_INTEGRATED(boot_cpu_apic_version)) 791 num_starts = 2; 792 else 793 num_starts = 0; 794 795 /* 796 * Run STARTUP IPI loop. 797 */ 798 pr_debug("#startup loops: %d\n", num_starts); 799 800 for (j = 1; j <= num_starts; j++) { 801 pr_debug("Sending STARTUP #%d\n", j); 802 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 803 apic_write(APIC_ESR, 0); 804 apic_read(APIC_ESR); 805 pr_debug("After apic_write\n"); 806 807 /* 808 * STARTUP IPI 809 */ 810 811 /* Target chip */ 812 /* Boot on the stack */ 813 /* Kick the second */ 814 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 815 phys_apicid); 816 817 /* 818 * Give the other CPU some time to accept the IPI. 819 */ 820 if (init_udelay == 0) 821 udelay(10); 822 else 823 udelay(300); 824 825 pr_debug("Startup point 1\n"); 826 827 pr_debug("Waiting for send to finish...\n"); 828 send_status = safe_apic_wait_icr_idle(); 829 830 /* 831 * Give the other CPU some time to accept the IPI. 832 */ 833 if (init_udelay == 0) 834 udelay(10); 835 else 836 udelay(200); 837 838 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 839 apic_write(APIC_ESR, 0); 840 accept_status = (apic_read(APIC_ESR) & 0xEF); 841 if (send_status || accept_status) 842 break; 843 } 844 pr_debug("After Startup\n"); 845 846 if (send_status) 847 pr_err("APIC never delivered???\n"); 848 if (accept_status) 849 pr_err("APIC delivery error (%lx)\n", accept_status); 850 851 return (send_status | accept_status); 852 } 853 854 /* reduce the number of lines printed when booting a large cpu count system */ 855 static void announce_cpu(int cpu, int apicid) 856 { 857 static int current_node = -1; 858 int node = early_cpu_to_node(cpu); 859 static int width, node_width; 860 861 if (!width) 862 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 863 864 if (!node_width) 865 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 866 867 if (cpu == 1) 868 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 869 870 if (system_state == SYSTEM_BOOTING) { 871 if (node != current_node) { 872 if (current_node > (-1)) 873 pr_cont("\n"); 874 current_node = node; 875 876 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 877 node_width - num_digits(node), " ", node); 878 } 879 880 /* Add padding for the BSP */ 881 if (cpu == 1) 882 pr_cont("%*s", width + 1, " "); 883 884 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 885 886 } else 887 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 888 node, cpu, apicid); 889 } 890 891 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 892 { 893 int cpu; 894 895 cpu = smp_processor_id(); 896 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 897 return NMI_HANDLED; 898 899 return NMI_DONE; 900 } 901 902 /* 903 * Wake up AP by INIT, INIT, STARTUP sequence. 904 * 905 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 906 * boot-strap code which is not a desired behavior for waking up BSP. To 907 * void the boot-strap code, wake up CPU0 by NMI instead. 908 * 909 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 910 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 911 * We'll change this code in the future to wake up hard offlined CPU0 if 912 * real platform and request are available. 913 */ 914 static int 915 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 916 int *cpu0_nmi_registered) 917 { 918 int id; 919 int boot_error; 920 921 preempt_disable(); 922 923 /* 924 * Wake up AP by INIT, INIT, STARTUP sequence. 925 */ 926 if (cpu) { 927 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 928 goto out; 929 } 930 931 /* 932 * Wake up BSP by nmi. 933 * 934 * Register a NMI handler to help wake up CPU0. 935 */ 936 boot_error = register_nmi_handler(NMI_LOCAL, 937 wakeup_cpu0_nmi, 0, "wake_cpu0"); 938 939 if (!boot_error) { 940 enable_start_cpu0 = 1; 941 *cpu0_nmi_registered = 1; 942 if (apic->dest_logical == APIC_DEST_LOGICAL) 943 id = cpu0_logical_apicid; 944 else 945 id = apicid; 946 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 947 } 948 949 out: 950 preempt_enable(); 951 952 return boot_error; 953 } 954 955 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 956 { 957 /* Just in case we booted with a single CPU. */ 958 alternatives_enable_smp(); 959 960 per_cpu(current_task, cpu) = idle; 961 962 #ifdef CONFIG_X86_32 963 /* Stack for startup_32 can be just as for start_secondary onwards */ 964 irq_ctx_init(cpu); 965 per_cpu(cpu_current_top_of_stack, cpu) = 966 (unsigned long)task_stack_page(idle) + THREAD_SIZE; 967 #else 968 initial_gs = per_cpu_offset(cpu); 969 #endif 970 } 971 972 /* 973 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 974 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 975 * Returns zero if CPU booted OK, else error code from 976 * ->wakeup_secondary_cpu. 977 */ 978 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 979 { 980 volatile u32 *trampoline_status = 981 (volatile u32 *) __va(real_mode_header->trampoline_status); 982 /* start_ip had better be page-aligned! */ 983 unsigned long start_ip = real_mode_header->trampoline_start; 984 985 unsigned long boot_error = 0; 986 int cpu0_nmi_registered = 0; 987 unsigned long timeout; 988 989 idle->thread.sp = (unsigned long)task_pt_regs(idle); 990 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 991 initial_code = (unsigned long)start_secondary; 992 initial_stack = idle->thread.sp; 993 994 /* 995 * Enable the espfix hack for this CPU 996 */ 997 #ifdef CONFIG_X86_ESPFIX64 998 init_espfix_ap(cpu); 999 #endif 1000 1001 /* So we see what's up */ 1002 announce_cpu(cpu, apicid); 1003 1004 /* 1005 * This grunge runs the startup process for 1006 * the targeted processor. 1007 */ 1008 1009 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 1010 1011 pr_debug("Setting warm reset code and vector.\n"); 1012 1013 smpboot_setup_warm_reset_vector(start_ip); 1014 /* 1015 * Be paranoid about clearing APIC errors. 1016 */ 1017 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1018 apic_write(APIC_ESR, 0); 1019 apic_read(APIC_ESR); 1020 } 1021 } 1022 1023 /* 1024 * AP might wait on cpu_callout_mask in cpu_init() with 1025 * cpu_initialized_mask set if previous attempt to online 1026 * it timed-out. Clear cpu_initialized_mask so that after 1027 * INIT/SIPI it could start with a clean state. 1028 */ 1029 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1030 smp_mb(); 1031 1032 /* 1033 * Wake up a CPU in difference cases: 1034 * - Use the method in the APIC driver if it's defined 1035 * Otherwise, 1036 * - Use an INIT boot APIC message for APs or NMI for BSP. 1037 */ 1038 if (apic->wakeup_secondary_cpu) 1039 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1040 else 1041 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1042 &cpu0_nmi_registered); 1043 1044 if (!boot_error) { 1045 /* 1046 * Wait 10s total for first sign of life from AP 1047 */ 1048 boot_error = -1; 1049 timeout = jiffies + 10*HZ; 1050 while (time_before(jiffies, timeout)) { 1051 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1052 /* 1053 * Tell AP to proceed with initialization 1054 */ 1055 cpumask_set_cpu(cpu, cpu_callout_mask); 1056 boot_error = 0; 1057 break; 1058 } 1059 schedule(); 1060 } 1061 } 1062 1063 if (!boot_error) { 1064 /* 1065 * Wait till AP completes initial initialization 1066 */ 1067 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1068 /* 1069 * Allow other tasks to run while we wait for the 1070 * AP to come online. This also gives a chance 1071 * for the MTRR work(triggered by the AP coming online) 1072 * to be completed in the stop machine context. 1073 */ 1074 schedule(); 1075 } 1076 } 1077 1078 /* mark "stuck" area as not stuck */ 1079 *trampoline_status = 0; 1080 1081 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 1082 /* 1083 * Cleanup possible dangling ends... 1084 */ 1085 smpboot_restore_warm_reset_vector(); 1086 } 1087 /* 1088 * Clean up the nmi handler. Do this after the callin and callout sync 1089 * to avoid impact of possible long unregister time. 1090 */ 1091 if (cpu0_nmi_registered) 1092 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1093 1094 return boot_error; 1095 } 1096 1097 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1098 { 1099 int apicid = apic->cpu_present_to_apicid(cpu); 1100 unsigned long flags; 1101 int err; 1102 1103 WARN_ON(irqs_disabled()); 1104 1105 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1106 1107 if (apicid == BAD_APICID || 1108 !physid_isset(apicid, phys_cpu_present_map) || 1109 !apic->apic_id_valid(apicid)) { 1110 pr_err("%s: bad cpu %d\n", __func__, cpu); 1111 return -EINVAL; 1112 } 1113 1114 /* 1115 * Already booted CPU? 1116 */ 1117 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1118 pr_debug("do_boot_cpu %d Already started\n", cpu); 1119 return -ENOSYS; 1120 } 1121 1122 /* 1123 * Save current MTRR state in case it was changed since early boot 1124 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1125 */ 1126 mtrr_save_state(); 1127 1128 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1129 err = cpu_check_up_prepare(cpu); 1130 if (err && err != -EBUSY) 1131 return err; 1132 1133 /* the FPU context is blank, nobody can own it */ 1134 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1135 1136 common_cpu_up(cpu, tidle); 1137 1138 err = do_boot_cpu(apicid, cpu, tidle); 1139 if (err) { 1140 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1141 return -EIO; 1142 } 1143 1144 /* 1145 * Check TSC synchronization with the AP (keep irqs disabled 1146 * while doing so): 1147 */ 1148 local_irq_save(flags); 1149 check_tsc_sync_source(cpu); 1150 local_irq_restore(flags); 1151 1152 while (!cpu_online(cpu)) { 1153 cpu_relax(); 1154 touch_nmi_watchdog(); 1155 } 1156 1157 return 0; 1158 } 1159 1160 /** 1161 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1162 */ 1163 void arch_disable_smp_support(void) 1164 { 1165 disable_ioapic_support(); 1166 } 1167 1168 /* 1169 * Fall back to non SMP mode after errors. 1170 * 1171 * RED-PEN audit/test this more. I bet there is more state messed up here. 1172 */ 1173 static __init void disable_smp(void) 1174 { 1175 pr_info("SMP disabled\n"); 1176 1177 disable_ioapic_support(); 1178 1179 init_cpu_present(cpumask_of(0)); 1180 init_cpu_possible(cpumask_of(0)); 1181 1182 if (smp_found_config) 1183 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1184 else 1185 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1186 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1187 cpumask_set_cpu(0, topology_core_cpumask(0)); 1188 } 1189 1190 enum { 1191 SMP_OK, 1192 SMP_NO_CONFIG, 1193 SMP_NO_APIC, 1194 SMP_FORCE_UP, 1195 }; 1196 1197 /* 1198 * Various sanity checks. 1199 */ 1200 static int __init smp_sanity_check(unsigned max_cpus) 1201 { 1202 preempt_disable(); 1203 1204 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1205 if (def_to_bigsmp && nr_cpu_ids > 8) { 1206 unsigned int cpu; 1207 unsigned nr; 1208 1209 pr_warn("More than 8 CPUs detected - skipping them\n" 1210 "Use CONFIG_X86_BIGSMP\n"); 1211 1212 nr = 0; 1213 for_each_present_cpu(cpu) { 1214 if (nr >= 8) 1215 set_cpu_present(cpu, false); 1216 nr++; 1217 } 1218 1219 nr = 0; 1220 for_each_possible_cpu(cpu) { 1221 if (nr >= 8) 1222 set_cpu_possible(cpu, false); 1223 nr++; 1224 } 1225 1226 nr_cpu_ids = 8; 1227 } 1228 #endif 1229 1230 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1231 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1232 hard_smp_processor_id()); 1233 1234 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1235 } 1236 1237 /* 1238 * If we couldn't find an SMP configuration at boot time, 1239 * get out of here now! 1240 */ 1241 if (!smp_found_config && !acpi_lapic) { 1242 preempt_enable(); 1243 pr_notice("SMP motherboard not detected\n"); 1244 return SMP_NO_CONFIG; 1245 } 1246 1247 /* 1248 * Should not be necessary because the MP table should list the boot 1249 * CPU too, but we do it for the sake of robustness anyway. 1250 */ 1251 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1252 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1253 boot_cpu_physical_apicid); 1254 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1255 } 1256 preempt_enable(); 1257 1258 /* 1259 * If we couldn't find a local APIC, then get out of here now! 1260 */ 1261 if (APIC_INTEGRATED(boot_cpu_apic_version) && 1262 !boot_cpu_has(X86_FEATURE_APIC)) { 1263 if (!disable_apic) { 1264 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1265 boot_cpu_physical_apicid); 1266 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1267 } 1268 return SMP_NO_APIC; 1269 } 1270 1271 /* 1272 * If SMP should be disabled, then really disable it! 1273 */ 1274 if (!max_cpus) { 1275 pr_info("SMP mode deactivated\n"); 1276 return SMP_FORCE_UP; 1277 } 1278 1279 return SMP_OK; 1280 } 1281 1282 static void __init smp_cpu_index_default(void) 1283 { 1284 int i; 1285 struct cpuinfo_x86 *c; 1286 1287 for_each_possible_cpu(i) { 1288 c = &cpu_data(i); 1289 /* mark all to hotplug */ 1290 c->cpu_index = nr_cpu_ids; 1291 } 1292 } 1293 1294 /* 1295 * Prepare for SMP bootup. The MP table or ACPI has been read 1296 * earlier. Just do some sanity checking here and enable APIC mode. 1297 */ 1298 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1299 { 1300 unsigned int i; 1301 1302 smp_cpu_index_default(); 1303 1304 /* 1305 * Setup boot CPU information 1306 */ 1307 smp_store_boot_cpu_info(); /* Final full version of the data */ 1308 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1309 mb(); 1310 1311 for_each_possible_cpu(i) { 1312 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1313 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1314 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1315 } 1316 1317 /* 1318 * Set 'default' x86 topology, this matches default_topology() in that 1319 * it has NUMA nodes as a topology level. See also 1320 * native_smp_cpus_done(). 1321 * 1322 * Must be done before set_cpus_sibling_map() is ran. 1323 */ 1324 set_sched_topology(x86_topology); 1325 1326 set_cpu_sibling_map(0); 1327 1328 switch (smp_sanity_check(max_cpus)) { 1329 case SMP_NO_CONFIG: 1330 disable_smp(); 1331 if (APIC_init_uniprocessor()) 1332 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1333 return; 1334 case SMP_NO_APIC: 1335 disable_smp(); 1336 return; 1337 case SMP_FORCE_UP: 1338 disable_smp(); 1339 apic_bsp_setup(false); 1340 return; 1341 case SMP_OK: 1342 break; 1343 } 1344 1345 if (read_apic_id() != boot_cpu_physical_apicid) { 1346 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1347 read_apic_id(), boot_cpu_physical_apicid); 1348 /* Or can we switch back to PIC here? */ 1349 } 1350 1351 default_setup_apic_routing(); 1352 cpu0_logical_apicid = apic_bsp_setup(false); 1353 1354 pr_info("CPU0: "); 1355 print_cpu_info(&cpu_data(0)); 1356 1357 if (is_uv_system()) 1358 uv_system_init(); 1359 1360 set_mtrr_aps_delayed_init(); 1361 1362 smp_quirk_init_udelay(); 1363 } 1364 1365 void arch_enable_nonboot_cpus_begin(void) 1366 { 1367 set_mtrr_aps_delayed_init(); 1368 } 1369 1370 void arch_enable_nonboot_cpus_end(void) 1371 { 1372 mtrr_aps_init(); 1373 } 1374 1375 /* 1376 * Early setup to make printk work. 1377 */ 1378 void __init native_smp_prepare_boot_cpu(void) 1379 { 1380 int me = smp_processor_id(); 1381 switch_to_new_gdt(me); 1382 /* already set me in cpu_online_mask in boot_cpu_init() */ 1383 cpumask_set_cpu(me, cpu_callout_mask); 1384 cpu_set_state_online(me); 1385 } 1386 1387 void __init native_smp_cpus_done(unsigned int max_cpus) 1388 { 1389 pr_debug("Boot done\n"); 1390 1391 if (x86_has_numa_in_package) 1392 set_sched_topology(x86_numa_in_package_topology); 1393 1394 nmi_selftest(); 1395 impress_friends(); 1396 setup_ioapic_dest(); 1397 mtrr_aps_init(); 1398 } 1399 1400 static int __initdata setup_possible_cpus = -1; 1401 static int __init _setup_possible_cpus(char *str) 1402 { 1403 get_option(&str, &setup_possible_cpus); 1404 return 0; 1405 } 1406 early_param("possible_cpus", _setup_possible_cpus); 1407 1408 1409 /* 1410 * cpu_possible_mask should be static, it cannot change as cpu's 1411 * are onlined, or offlined. The reason is per-cpu data-structures 1412 * are allocated by some modules at init time, and dont expect to 1413 * do this dynamically on cpu arrival/departure. 1414 * cpu_present_mask on the other hand can change dynamically. 1415 * In case when cpu_hotplug is not compiled, then we resort to current 1416 * behaviour, which is cpu_possible == cpu_present. 1417 * - Ashok Raj 1418 * 1419 * Three ways to find out the number of additional hotplug CPUs: 1420 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1421 * - The user can overwrite it with possible_cpus=NUM 1422 * - Otherwise don't reserve additional CPUs. 1423 * We do this because additional CPUs waste a lot of memory. 1424 * -AK 1425 */ 1426 __init void prefill_possible_map(void) 1427 { 1428 int i, possible; 1429 1430 /* No boot processor was found in mptable or ACPI MADT */ 1431 if (!num_processors) { 1432 if (boot_cpu_has(X86_FEATURE_APIC)) { 1433 int apicid = boot_cpu_physical_apicid; 1434 int cpu = hard_smp_processor_id(); 1435 1436 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1437 1438 /* Make sure boot cpu is enumerated */ 1439 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1440 apic->apic_id_valid(apicid)) 1441 generic_processor_info(apicid, boot_cpu_apic_version); 1442 } 1443 1444 if (!num_processors) 1445 num_processors = 1; 1446 } 1447 1448 i = setup_max_cpus ?: 1; 1449 if (setup_possible_cpus == -1) { 1450 possible = num_processors; 1451 #ifdef CONFIG_HOTPLUG_CPU 1452 if (setup_max_cpus) 1453 possible += disabled_cpus; 1454 #else 1455 if (possible > i) 1456 possible = i; 1457 #endif 1458 } else 1459 possible = setup_possible_cpus; 1460 1461 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1462 1463 /* nr_cpu_ids could be reduced via nr_cpus= */ 1464 if (possible > nr_cpu_ids) { 1465 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", 1466 possible, nr_cpu_ids); 1467 possible = nr_cpu_ids; 1468 } 1469 1470 #ifdef CONFIG_HOTPLUG_CPU 1471 if (!setup_max_cpus) 1472 #endif 1473 if (possible > i) { 1474 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1475 possible, setup_max_cpus); 1476 possible = i; 1477 } 1478 1479 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1480 possible, max_t(int, possible - num_processors, 0)); 1481 1482 for (i = 0; i < possible; i++) 1483 set_cpu_possible(i, true); 1484 for (; i < NR_CPUS; i++) 1485 set_cpu_possible(i, false); 1486 1487 nr_cpu_ids = possible; 1488 } 1489 1490 #ifdef CONFIG_HOTPLUG_CPU 1491 1492 /* Recompute SMT state for all CPUs on offline */ 1493 static void recompute_smt_state(void) 1494 { 1495 int max_threads, cpu; 1496 1497 max_threads = 0; 1498 for_each_online_cpu (cpu) { 1499 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1500 1501 if (threads > max_threads) 1502 max_threads = threads; 1503 } 1504 __max_smt_threads = max_threads; 1505 } 1506 1507 static void remove_siblinginfo(int cpu) 1508 { 1509 int sibling; 1510 struct cpuinfo_x86 *c = &cpu_data(cpu); 1511 1512 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1513 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1514 /*/ 1515 * last thread sibling in this cpu core going down 1516 */ 1517 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1518 cpu_data(sibling).booted_cores--; 1519 } 1520 1521 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1522 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1523 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1524 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1525 cpumask_clear(cpu_llc_shared_mask(cpu)); 1526 cpumask_clear(topology_sibling_cpumask(cpu)); 1527 cpumask_clear(topology_core_cpumask(cpu)); 1528 c->phys_proc_id = 0; 1529 c->cpu_core_id = 0; 1530 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1531 recompute_smt_state(); 1532 } 1533 1534 static void remove_cpu_from_maps(int cpu) 1535 { 1536 set_cpu_online(cpu, false); 1537 cpumask_clear_cpu(cpu, cpu_callout_mask); 1538 cpumask_clear_cpu(cpu, cpu_callin_mask); 1539 /* was set by cpu_init() */ 1540 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1541 numa_remove_cpu(cpu); 1542 } 1543 1544 void cpu_disable_common(void) 1545 { 1546 int cpu = smp_processor_id(); 1547 1548 remove_siblinginfo(cpu); 1549 1550 /* It's now safe to remove this processor from the online map */ 1551 lock_vector_lock(); 1552 remove_cpu_from_maps(cpu); 1553 unlock_vector_lock(); 1554 fixup_irqs(); 1555 } 1556 1557 int native_cpu_disable(void) 1558 { 1559 int ret; 1560 1561 ret = check_irq_vectors_for_cpu_disable(); 1562 if (ret) 1563 return ret; 1564 1565 clear_local_APIC(); 1566 cpu_disable_common(); 1567 1568 return 0; 1569 } 1570 1571 int common_cpu_die(unsigned int cpu) 1572 { 1573 int ret = 0; 1574 1575 /* We don't do anything here: idle task is faking death itself. */ 1576 1577 /* They ack this in play_dead() by setting CPU_DEAD */ 1578 if (cpu_wait_death(cpu, 5)) { 1579 if (system_state == SYSTEM_RUNNING) 1580 pr_info("CPU %u is now offline\n", cpu); 1581 } else { 1582 pr_err("CPU %u didn't die...\n", cpu); 1583 ret = -1; 1584 } 1585 1586 return ret; 1587 } 1588 1589 void native_cpu_die(unsigned int cpu) 1590 { 1591 common_cpu_die(cpu); 1592 } 1593 1594 void play_dead_common(void) 1595 { 1596 idle_task_exit(); 1597 reset_lazy_tlbstate(); 1598 1599 /* Ack it */ 1600 (void)cpu_report_death(); 1601 1602 /* 1603 * With physical CPU hotplug, we should halt the cpu 1604 */ 1605 local_irq_disable(); 1606 } 1607 1608 static bool wakeup_cpu0(void) 1609 { 1610 if (smp_processor_id() == 0 && enable_start_cpu0) 1611 return true; 1612 1613 return false; 1614 } 1615 1616 /* 1617 * We need to flush the caches before going to sleep, lest we have 1618 * dirty data in our caches when we come back up. 1619 */ 1620 static inline void mwait_play_dead(void) 1621 { 1622 unsigned int eax, ebx, ecx, edx; 1623 unsigned int highest_cstate = 0; 1624 unsigned int highest_subcstate = 0; 1625 void *mwait_ptr; 1626 int i; 1627 1628 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1629 return; 1630 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1631 return; 1632 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1633 return; 1634 1635 eax = CPUID_MWAIT_LEAF; 1636 ecx = 0; 1637 native_cpuid(&eax, &ebx, &ecx, &edx); 1638 1639 /* 1640 * eax will be 0 if EDX enumeration is not valid. 1641 * Initialized below to cstate, sub_cstate value when EDX is valid. 1642 */ 1643 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1644 eax = 0; 1645 } else { 1646 edx >>= MWAIT_SUBSTATE_SIZE; 1647 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1648 if (edx & MWAIT_SUBSTATE_MASK) { 1649 highest_cstate = i; 1650 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1651 } 1652 } 1653 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1654 (highest_subcstate - 1); 1655 } 1656 1657 /* 1658 * This should be a memory location in a cache line which is 1659 * unlikely to be touched by other processors. The actual 1660 * content is immaterial as it is not actually modified in any way. 1661 */ 1662 mwait_ptr = ¤t_thread_info()->flags; 1663 1664 wbinvd(); 1665 1666 while (1) { 1667 /* 1668 * The CLFLUSH is a workaround for erratum AAI65 for 1669 * the Xeon 7400 series. It's not clear it is actually 1670 * needed, but it should be harmless in either case. 1671 * The WBINVD is insufficient due to the spurious-wakeup 1672 * case where we return around the loop. 1673 */ 1674 mb(); 1675 clflush(mwait_ptr); 1676 mb(); 1677 __monitor(mwait_ptr, 0, 0); 1678 mb(); 1679 __mwait(eax, 0); 1680 /* 1681 * If NMI wants to wake up CPU0, start CPU0. 1682 */ 1683 if (wakeup_cpu0()) 1684 start_cpu0(); 1685 } 1686 } 1687 1688 void hlt_play_dead(void) 1689 { 1690 if (__this_cpu_read(cpu_info.x86) >= 4) 1691 wbinvd(); 1692 1693 while (1) { 1694 native_halt(); 1695 /* 1696 * If NMI wants to wake up CPU0, start CPU0. 1697 */ 1698 if (wakeup_cpu0()) 1699 start_cpu0(); 1700 } 1701 } 1702 1703 void native_play_dead(void) 1704 { 1705 play_dead_common(); 1706 tboot_shutdown(TB_SHUTDOWN_WFS); 1707 1708 mwait_play_dead(); /* Only returns on failure */ 1709 if (cpuidle_play_dead()) 1710 hlt_play_dead(); 1711 } 1712 1713 #else /* ... !CONFIG_HOTPLUG_CPU */ 1714 int native_cpu_disable(void) 1715 { 1716 return -ENOSYS; 1717 } 1718 1719 void native_cpu_die(unsigned int cpu) 1720 { 1721 /* We said "no" in __cpu_disable */ 1722 BUG(); 1723 } 1724 1725 void native_play_dead(void) 1726 { 1727 BUG(); 1728 } 1729 1730 #endif 1731