1 #include <linux/kernel.h> 2 3 #include <linux/string.h> 4 #include <linux/bitops.h> 5 #include <linux/smp.h> 6 #include <linux/sched.h> 7 #include <linux/thread_info.h> 8 #include <linux/init.h> 9 #include <linux/uaccess.h> 10 11 #include <asm/cpufeature.h> 12 #include <asm/pgtable.h> 13 #include <asm/msr.h> 14 #include <asm/bugs.h> 15 #include <asm/cpu.h> 16 #include <asm/intel-family.h> 17 #include <asm/microcode_intel.h> 18 #include <asm/hwcap2.h> 19 #include <asm/elf.h> 20 21 #ifdef CONFIG_X86_64 22 #include <linux/topology.h> 23 #endif 24 25 #include "cpu.h" 26 27 #ifdef CONFIG_X86_LOCAL_APIC 28 #include <asm/mpspec.h> 29 #include <asm/apic.h> 30 #endif 31 32 /* 33 * Just in case our CPU detection goes bad, or you have a weird system, 34 * allow a way to override the automatic disabling of MPX. 35 */ 36 static int forcempx; 37 38 static int __init forcempx_setup(char *__unused) 39 { 40 forcempx = 1; 41 42 return 1; 43 } 44 __setup("intel-skd-046-workaround=disable", forcempx_setup); 45 46 void check_mpx_erratum(struct cpuinfo_x86 *c) 47 { 48 if (forcempx) 49 return; 50 /* 51 * Turn off the MPX feature on CPUs where SMEP is not 52 * available or disabled. 53 * 54 * Works around Intel Erratum SKD046: "Branch Instructions 55 * May Initialize MPX Bound Registers Incorrectly". 56 * 57 * This might falsely disable MPX on systems without 58 * SMEP, like Atom processors without SMEP. But there 59 * is no such hardware known at the moment. 60 */ 61 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) { 62 setup_clear_cpu_cap(X86_FEATURE_MPX); 63 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n"); 64 } 65 } 66 67 static bool ring3mwait_disabled __read_mostly; 68 69 static int __init ring3mwait_disable(char *__unused) 70 { 71 ring3mwait_disabled = true; 72 return 0; 73 } 74 __setup("ring3mwait=disable", ring3mwait_disable); 75 76 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) 77 { 78 /* 79 * Ring 3 MONITOR/MWAIT feature cannot be detected without 80 * cpu model and family comparison. 81 */ 82 if (c->x86 != 6) 83 return; 84 switch (c->x86_model) { 85 case INTEL_FAM6_XEON_PHI_KNL: 86 case INTEL_FAM6_XEON_PHI_KNM: 87 break; 88 default: 89 return; 90 } 91 92 if (ring3mwait_disabled) { 93 msr_clear_bit(MSR_MISC_FEATURE_ENABLES, 94 MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT); 95 return; 96 } 97 98 msr_set_bit(MSR_MISC_FEATURE_ENABLES, 99 MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT); 100 101 set_cpu_cap(c, X86_FEATURE_RING3MWAIT); 102 103 if (c == &boot_cpu_data) 104 ELF_HWCAP2 |= HWCAP2_RING3MWAIT; 105 } 106 107 static void early_init_intel(struct cpuinfo_x86 *c) 108 { 109 u64 misc_enable; 110 111 /* Unmask CPUID levels if masked: */ 112 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 113 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 114 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { 115 c->cpuid_level = cpuid_eax(0); 116 get_cpu_cap(c); 117 } 118 } 119 120 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 121 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 122 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 123 124 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) 125 c->microcode = intel_get_microcode_revision(); 126 127 /* 128 * Atom erratum AAE44/AAF40/AAG38/AAH41: 129 * 130 * A race condition between speculative fetches and invalidating 131 * a large page. This is worked around in microcode, but we 132 * need the microcode to have already been loaded... so if it is 133 * not, recommend a BIOS update and disable large pages. 134 */ 135 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 && 136 c->microcode < 0x20e) { 137 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); 138 clear_cpu_cap(c, X86_FEATURE_PSE); 139 } 140 141 #ifdef CONFIG_X86_64 142 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 143 #else 144 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 145 if (c->x86 == 15 && c->x86_cache_alignment == 64) 146 c->x86_cache_alignment = 128; 147 #endif 148 149 /* CPUID workaround for 0F33/0F34 CPU */ 150 if (c->x86 == 0xF && c->x86_model == 0x3 151 && (c->x86_mask == 0x3 || c->x86_mask == 0x4)) 152 c->x86_phys_bits = 36; 153 154 /* 155 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 156 * with P/T states and does not stop in deep C-states. 157 * 158 * It is also reliable across cores and sockets. (but not across 159 * cabinets - we turn it off in that case explicitly.) 160 */ 161 if (c->x86_power & (1 << 8)) { 162 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 163 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 164 if (check_tsc_unstable()) 165 clear_sched_clock_stable(); 166 } else { 167 clear_sched_clock_stable(); 168 } 169 170 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 171 if (c->x86 == 6) { 172 switch (c->x86_model) { 173 case 0x27: /* Penwell */ 174 case 0x35: /* Cloverview */ 175 case 0x4a: /* Merrifield */ 176 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 177 break; 178 default: 179 break; 180 } 181 } 182 183 /* 184 * There is a known erratum on Pentium III and Core Solo 185 * and Core Duo CPUs. 186 * " Page with PAT set to WC while associated MTRR is UC 187 * may consolidate to UC " 188 * Because of this erratum, it is better to stick with 189 * setting WC in MTRR rather than using PAT on these CPUs. 190 * 191 * Enable PAT WC only on P4, Core 2 or later CPUs. 192 */ 193 if (c->x86 == 6 && c->x86_model < 15) 194 clear_cpu_cap(c, X86_FEATURE_PAT); 195 196 #ifdef CONFIG_KMEMCHECK 197 /* 198 * P4s have a "fast strings" feature which causes single- 199 * stepping REP instructions to only generate a #DB on 200 * cache-line boundaries. 201 * 202 * Ingo Molnar reported a Pentium D (model 6) and a Xeon 203 * (model 2) with the same problem. 204 */ 205 if (c->x86 == 15) 206 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 207 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0) 208 pr_info("kmemcheck: Disabling fast string operations\n"); 209 #endif 210 211 /* 212 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, 213 * clear the fast string and enhanced fast string CPU capabilities. 214 */ 215 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 216 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 217 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { 218 pr_info("Disabled fast string operations\n"); 219 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 220 setup_clear_cpu_cap(X86_FEATURE_ERMS); 221 } 222 } 223 224 /* 225 * Intel Quark Core DevMan_001.pdf section 6.4.11 226 * "The operating system also is required to invalidate (i.e., flush) 227 * the TLB when any changes are made to any of the page table entries. 228 * The operating system must reload CR3 to cause the TLB to be flushed" 229 * 230 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h 231 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE 232 * to be modified. 233 */ 234 if (c->x86 == 5 && c->x86_model == 9) { 235 pr_info("Disabling PGE capability bit\n"); 236 setup_clear_cpu_cap(X86_FEATURE_PGE); 237 } 238 239 if (c->cpuid_level >= 0x00000001) { 240 u32 eax, ebx, ecx, edx; 241 242 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 243 /* 244 * If HTT (EDX[28]) is set EBX[16:23] contain the number of 245 * apicids which are reserved per package. Store the resulting 246 * shift value for the package management code. 247 */ 248 if (edx & (1U << 28)) 249 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); 250 } 251 252 check_mpx_erratum(c); 253 } 254 255 #ifdef CONFIG_X86_32 256 /* 257 * Early probe support logic for ppro memory erratum #50 258 * 259 * This is called before we do cpu ident work 260 */ 261 262 int ppro_with_ram_bug(void) 263 { 264 /* Uses data from early_cpu_detect now */ 265 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 266 boot_cpu_data.x86 == 6 && 267 boot_cpu_data.x86_model == 1 && 268 boot_cpu_data.x86_mask < 8) { 269 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 270 return 1; 271 } 272 return 0; 273 } 274 275 static void intel_smp_check(struct cpuinfo_x86 *c) 276 { 277 /* calling is from identify_secondary_cpu() ? */ 278 if (!c->cpu_index) 279 return; 280 281 /* 282 * Mask B, Pentium, but not Pentium MMX 283 */ 284 if (c->x86 == 5 && 285 c->x86_mask >= 1 && c->x86_mask <= 4 && 286 c->x86_model <= 3) { 287 /* 288 * Remember we have B step Pentia with bugs 289 */ 290 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 291 "with B stepping processors.\n"); 292 } 293 } 294 295 static int forcepae; 296 static int __init forcepae_setup(char *__unused) 297 { 298 forcepae = 1; 299 return 1; 300 } 301 __setup("forcepae", forcepae_setup); 302 303 static void intel_workarounds(struct cpuinfo_x86 *c) 304 { 305 #ifdef CONFIG_X86_F00F_BUG 306 /* 307 * All models of Pentium and Pentium with MMX technology CPUs 308 * have the F0 0F bug, which lets nonprivileged users lock up the 309 * system. Announce that the fault handler will be checking for it. 310 * The Quark is also family 5, but does not have the same bug. 311 */ 312 clear_cpu_bug(c, X86_BUG_F00F); 313 if (c->x86 == 5 && c->x86_model < 9) { 314 static int f00f_workaround_enabled; 315 316 set_cpu_bug(c, X86_BUG_F00F); 317 if (!f00f_workaround_enabled) { 318 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); 319 f00f_workaround_enabled = 1; 320 } 321 } 322 #endif 323 324 /* 325 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 326 * model 3 mask 3 327 */ 328 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) 329 clear_cpu_cap(c, X86_FEATURE_SEP); 330 331 /* 332 * PAE CPUID issue: many Pentium M report no PAE but may have a 333 * functionally usable PAE implementation. 334 * Forcefully enable PAE if kernel parameter "forcepae" is present. 335 */ 336 if (forcepae) { 337 pr_warn("PAE forced!\n"); 338 set_cpu_cap(c, X86_FEATURE_PAE); 339 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 340 } 341 342 /* 343 * P4 Xeon erratum 037 workaround. 344 * Hardware prefetcher may cause stale data to be loaded into the cache. 345 */ 346 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { 347 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 348 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { 349 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 350 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); 351 } 352 } 353 354 /* 355 * See if we have a good local APIC by checking for buggy Pentia, 356 * i.e. all B steppings and the C2 stepping of P54C when using their 357 * integrated APIC (see 11AP erratum in "Pentium Processor 358 * Specification Update"). 359 */ 360 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && 361 (c->x86_mask < 0x6 || c->x86_mask == 0xb)) 362 set_cpu_bug(c, X86_BUG_11AP); 363 364 365 #ifdef CONFIG_X86_INTEL_USERCOPY 366 /* 367 * Set up the preferred alignment for movsl bulk memory moves 368 */ 369 switch (c->x86) { 370 case 4: /* 486: untested */ 371 break; 372 case 5: /* Old Pentia: untested */ 373 break; 374 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 375 movsl_mask.mask = 7; 376 break; 377 case 15: /* P4 is OK down to 8-byte alignment */ 378 movsl_mask.mask = 7; 379 break; 380 } 381 #endif 382 383 intel_smp_check(c); 384 } 385 #else 386 static void intel_workarounds(struct cpuinfo_x86 *c) 387 { 388 } 389 #endif 390 391 static void srat_detect_node(struct cpuinfo_x86 *c) 392 { 393 #ifdef CONFIG_NUMA 394 unsigned node; 395 int cpu = smp_processor_id(); 396 397 /* Don't do the funky fallback heuristics the AMD version employs 398 for now. */ 399 node = numa_cpu_node(cpu); 400 if (node == NUMA_NO_NODE || !node_online(node)) { 401 /* reuse the value from init_cpu_to_node() */ 402 node = cpu_to_node(cpu); 403 } 404 numa_set_node(cpu, node); 405 #endif 406 } 407 408 /* 409 * find out the number of processor cores on the die 410 */ 411 static int intel_num_cpu_cores(struct cpuinfo_x86 *c) 412 { 413 unsigned int eax, ebx, ecx, edx; 414 415 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 416 return 1; 417 418 /* Intel has a non-standard dependency on %ecx for this CPUID level. */ 419 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 420 if (eax & 0x1f) 421 return (eax >> 26) + 1; 422 else 423 return 1; 424 } 425 426 static void detect_vmx_virtcap(struct cpuinfo_x86 *c) 427 { 428 /* Intel VMX MSR indicated features */ 429 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 430 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 431 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 432 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 433 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 434 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 435 436 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; 437 438 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 439 clear_cpu_cap(c, X86_FEATURE_VNMI); 440 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 441 clear_cpu_cap(c, X86_FEATURE_EPT); 442 clear_cpu_cap(c, X86_FEATURE_VPID); 443 444 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); 445 msr_ctl = vmx_msr_high | vmx_msr_low; 446 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) 447 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 448 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) 449 set_cpu_cap(c, X86_FEATURE_VNMI); 450 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { 451 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, 452 vmx_msr_low, vmx_msr_high); 453 msr_ctl2 = vmx_msr_high | vmx_msr_low; 454 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && 455 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) 456 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 457 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) 458 set_cpu_cap(c, X86_FEATURE_EPT); 459 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) 460 set_cpu_cap(c, X86_FEATURE_VPID); 461 } 462 } 463 464 static void init_intel_energy_perf(struct cpuinfo_x86 *c) 465 { 466 u64 epb; 467 468 /* 469 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized. 470 * (x86_energy_perf_policy(8) is available to change it at run-time.) 471 */ 472 if (!cpu_has(c, X86_FEATURE_EPB)) 473 return; 474 475 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 476 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE) 477 return; 478 479 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n"); 480 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n"); 481 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL; 482 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 483 } 484 485 static void intel_bsp_resume(struct cpuinfo_x86 *c) 486 { 487 /* 488 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume, 489 * so reinitialize it properly like during bootup: 490 */ 491 init_intel_energy_perf(c); 492 } 493 494 static void init_intel(struct cpuinfo_x86 *c) 495 { 496 unsigned int l2 = 0; 497 498 early_init_intel(c); 499 500 intel_workarounds(c); 501 502 /* 503 * Detect the extended topology information if available. This 504 * will reinitialise the initial_apicid which will be used 505 * in init_intel_cacheinfo() 506 */ 507 detect_extended_topology(c); 508 509 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { 510 /* 511 * let's use the legacy cpuid vector 0x1 and 0x4 for topology 512 * detection. 513 */ 514 c->x86_max_cores = intel_num_cpu_cores(c); 515 #ifdef CONFIG_X86_32 516 detect_ht(c); 517 #endif 518 } 519 520 l2 = init_intel_cacheinfo(c); 521 522 /* Detect legacy cache sizes if init_intel_cacheinfo did not */ 523 if (l2 == 0) { 524 cpu_detect_cache_sizes(c); 525 l2 = c->x86_cache_size; 526 } 527 528 if (c->cpuid_level > 9) { 529 unsigned eax = cpuid_eax(10); 530 /* Check for version and the number of counters */ 531 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 532 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 533 } 534 535 if (cpu_has(c, X86_FEATURE_XMM2)) 536 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 537 538 if (boot_cpu_has(X86_FEATURE_DS)) { 539 unsigned int l1; 540 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 541 if (!(l1 & (1<<11))) 542 set_cpu_cap(c, X86_FEATURE_BTS); 543 if (!(l1 & (1<<12))) 544 set_cpu_cap(c, X86_FEATURE_PEBS); 545 } 546 547 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && 548 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) 549 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 550 551 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && 552 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) 553 set_cpu_bug(c, X86_BUG_MONITOR); 554 555 #ifdef CONFIG_X86_64 556 if (c->x86 == 15) 557 c->x86_cache_alignment = c->x86_clflush_size * 2; 558 if (c->x86 == 6) 559 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 560 #else 561 /* 562 * Names for the Pentium II/Celeron processors 563 * detectable only by also checking the cache size. 564 * Dixon is NOT a Celeron. 565 */ 566 if (c->x86 == 6) { 567 char *p = NULL; 568 569 switch (c->x86_model) { 570 case 5: 571 if (l2 == 0) 572 p = "Celeron (Covington)"; 573 else if (l2 == 256) 574 p = "Mobile Pentium II (Dixon)"; 575 break; 576 577 case 6: 578 if (l2 == 128) 579 p = "Celeron (Mendocino)"; 580 else if (c->x86_mask == 0 || c->x86_mask == 5) 581 p = "Celeron-A"; 582 break; 583 584 case 8: 585 if (l2 == 128) 586 p = "Celeron (Coppermine)"; 587 break; 588 } 589 590 if (p) 591 strcpy(c->x86_model_id, p); 592 } 593 594 if (c->x86 == 15) 595 set_cpu_cap(c, X86_FEATURE_P4); 596 if (c->x86 == 6) 597 set_cpu_cap(c, X86_FEATURE_P3); 598 #endif 599 600 /* Work around errata */ 601 srat_detect_node(c); 602 603 if (cpu_has(c, X86_FEATURE_VMX)) 604 detect_vmx_virtcap(c); 605 606 init_intel_energy_perf(c); 607 608 probe_xeon_phi_r3mwait(c); 609 } 610 611 #ifdef CONFIG_X86_32 612 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 613 { 614 /* 615 * Intel PIII Tualatin. This comes in two flavours. 616 * One has 256kb of cache, the other 512. We have no way 617 * to determine which, so we use a boottime override 618 * for the 512kb model, and assume 256 otherwise. 619 */ 620 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 621 size = 256; 622 623 /* 624 * Intel Quark SoC X1000 contains a 4-way set associative 625 * 16K cache with a 16 byte cache line and 256 lines per tag 626 */ 627 if ((c->x86 == 5) && (c->x86_model == 9)) 628 size = 16; 629 return size; 630 } 631 #endif 632 633 #define TLB_INST_4K 0x01 634 #define TLB_INST_4M 0x02 635 #define TLB_INST_2M_4M 0x03 636 637 #define TLB_INST_ALL 0x05 638 #define TLB_INST_1G 0x06 639 640 #define TLB_DATA_4K 0x11 641 #define TLB_DATA_4M 0x12 642 #define TLB_DATA_2M_4M 0x13 643 #define TLB_DATA_4K_4M 0x14 644 645 #define TLB_DATA_1G 0x16 646 647 #define TLB_DATA0_4K 0x21 648 #define TLB_DATA0_4M 0x22 649 #define TLB_DATA0_2M_4M 0x23 650 651 #define STLB_4K 0x41 652 #define STLB_4K_2M 0x42 653 654 static const struct _tlb_table intel_tlb_table[] = { 655 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, 656 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, 657 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, 658 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, 659 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, 660 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, 661 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" }, 662 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 663 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 664 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 665 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 666 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, 667 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, 668 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, 669 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, 670 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, 671 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, 672 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, 673 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, 674 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, 675 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 676 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, 677 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, 678 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, 679 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, 680 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, 681 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" }, 682 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" }, 683 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, 684 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, 685 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, 686 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" }, 687 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, 688 { 0x00, 0, 0 } 689 }; 690 691 static void intel_tlb_lookup(const unsigned char desc) 692 { 693 unsigned char k; 694 if (desc == 0) 695 return; 696 697 /* look up this descriptor in the table */ 698 for (k = 0; intel_tlb_table[k].descriptor != desc && \ 699 intel_tlb_table[k].descriptor != 0; k++) 700 ; 701 702 if (intel_tlb_table[k].tlb_type == 0) 703 return; 704 705 switch (intel_tlb_table[k].tlb_type) { 706 case STLB_4K: 707 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 708 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 709 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 710 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 711 break; 712 case STLB_4K_2M: 713 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 714 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 715 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 716 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 717 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 718 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 719 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 720 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 721 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 722 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 723 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 724 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 725 break; 726 case TLB_INST_ALL: 727 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 728 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 729 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 730 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 731 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 732 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 733 break; 734 case TLB_INST_4K: 735 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 736 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 737 break; 738 case TLB_INST_4M: 739 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 740 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 741 break; 742 case TLB_INST_2M_4M: 743 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 744 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 745 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 746 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 747 break; 748 case TLB_DATA_4K: 749 case TLB_DATA0_4K: 750 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 751 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 752 break; 753 case TLB_DATA_4M: 754 case TLB_DATA0_4M: 755 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 756 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 757 break; 758 case TLB_DATA_2M_4M: 759 case TLB_DATA0_2M_4M: 760 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 761 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 762 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 763 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 764 break; 765 case TLB_DATA_4K_4M: 766 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 767 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 768 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 769 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 770 break; 771 case TLB_DATA_1G: 772 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) 773 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; 774 break; 775 } 776 } 777 778 static void intel_detect_tlb(struct cpuinfo_x86 *c) 779 { 780 int i, j, n; 781 unsigned int regs[4]; 782 unsigned char *desc = (unsigned char *)regs; 783 784 if (c->cpuid_level < 2) 785 return; 786 787 /* Number of times to iterate */ 788 n = cpuid_eax(2) & 0xFF; 789 790 for (i = 0 ; i < n ; i++) { 791 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); 792 793 /* If bit 31 is set, this is an unknown format */ 794 for (j = 0 ; j < 3 ; j++) 795 if (regs[j] & (1 << 31)) 796 regs[j] = 0; 797 798 /* Byte 0 is level count, not a descriptor */ 799 for (j = 1 ; j < 16 ; j++) 800 intel_tlb_lookup(desc[j]); 801 } 802 } 803 804 static const struct cpu_dev intel_cpu_dev = { 805 .c_vendor = "Intel", 806 .c_ident = { "GenuineIntel" }, 807 #ifdef CONFIG_X86_32 808 .legacy_models = { 809 { .family = 4, .model_names = 810 { 811 [0] = "486 DX-25/33", 812 [1] = "486 DX-50", 813 [2] = "486 SX", 814 [3] = "486 DX/2", 815 [4] = "486 SL", 816 [5] = "486 SX/2", 817 [7] = "486 DX/2-WB", 818 [8] = "486 DX/4", 819 [9] = "486 DX/4-WB" 820 } 821 }, 822 { .family = 5, .model_names = 823 { 824 [0] = "Pentium 60/66 A-step", 825 [1] = "Pentium 60/66", 826 [2] = "Pentium 75 - 200", 827 [3] = "OverDrive PODP5V83", 828 [4] = "Pentium MMX", 829 [7] = "Mobile Pentium 75 - 200", 830 [8] = "Mobile Pentium MMX", 831 [9] = "Quark SoC X1000", 832 } 833 }, 834 { .family = 6, .model_names = 835 { 836 [0] = "Pentium Pro A-step", 837 [1] = "Pentium Pro", 838 [3] = "Pentium II (Klamath)", 839 [4] = "Pentium II (Deschutes)", 840 [5] = "Pentium II (Deschutes)", 841 [6] = "Mobile Pentium II", 842 [7] = "Pentium III (Katmai)", 843 [8] = "Pentium III (Coppermine)", 844 [10] = "Pentium III (Cascades)", 845 [11] = "Pentium III (Tualatin)", 846 } 847 }, 848 { .family = 15, .model_names = 849 { 850 [0] = "Pentium 4 (Unknown)", 851 [1] = "Pentium 4 (Willamette)", 852 [2] = "Pentium 4 (Northwood)", 853 [4] = "Pentium 4 (Foster)", 854 [5] = "Pentium 4 (Foster)", 855 } 856 }, 857 }, 858 .legacy_cache_size = intel_size_cache, 859 #endif 860 .c_detect_tlb = intel_detect_tlb, 861 .c_early_init = early_init_intel, 862 .c_init = init_intel, 863 .c_bsp_resume = intel_bsp_resume, 864 .c_x86_vendor = X86_VENDOR_INTEL, 865 }; 866 867 cpu_dev_register(intel_cpu_dev); 868 869