1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/export.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/ctype.h> 9 #include <linux/delay.h> 10 #include <linux/sched/mm.h> 11 #include <linux/sched/clock.h> 12 #include <linux/sched/task.h> 13 #include <linux/init.h> 14 #include <linux/kprobes.h> 15 #include <linux/kgdb.h> 16 #include <linux/smp.h> 17 #include <linux/io.h> 18 #include <linux/syscore_ops.h> 19 20 #include <asm/stackprotector.h> 21 #include <asm/perf_event.h> 22 #include <asm/mmu_context.h> 23 #include <asm/archrandom.h> 24 #include <asm/hypervisor.h> 25 #include <asm/processor.h> 26 #include <asm/tlbflush.h> 27 #include <asm/debugreg.h> 28 #include <asm/sections.h> 29 #include <asm/vsyscall.h> 30 #include <linux/topology.h> 31 #include <linux/cpumask.h> 32 #include <asm/pgtable.h> 33 #include <linux/atomic.h> 34 #include <asm/proto.h> 35 #include <asm/setup.h> 36 #include <asm/apic.h> 37 #include <asm/desc.h> 38 #include <asm/fpu/internal.h> 39 #include <asm/mtrr.h> 40 #include <asm/hwcap2.h> 41 #include <linux/numa.h> 42 #include <asm/asm.h> 43 #include <asm/bugs.h> 44 #include <asm/cpu.h> 45 #include <asm/mce.h> 46 #include <asm/msr.h> 47 #include <asm/pat.h> 48 #include <asm/microcode.h> 49 #include <asm/microcode_intel.h> 50 #include <asm/intel-family.h> 51 #include <asm/cpu_device_id.h> 52 53 #ifdef CONFIG_X86_LOCAL_APIC 54 #include <asm/uv/uv.h> 55 #endif 56 57 #include "cpu.h" 58 59 u32 elf_hwcap2 __read_mostly; 60 61 /* all of these masks are initialized in setup_cpu_local_masks() */ 62 cpumask_var_t cpu_initialized_mask; 63 cpumask_var_t cpu_callout_mask; 64 cpumask_var_t cpu_callin_mask; 65 66 /* representing cpus for which sibling maps can be computed */ 67 cpumask_var_t cpu_sibling_setup_mask; 68 69 /* Number of siblings per CPU package */ 70 int smp_num_siblings = 1; 71 EXPORT_SYMBOL(smp_num_siblings); 72 73 /* Last level cache ID of each logical CPU */ 74 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 75 76 /* correctly size the local cpu masks */ 77 void __init setup_cpu_local_masks(void) 78 { 79 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 80 alloc_bootmem_cpumask_var(&cpu_callin_mask); 81 alloc_bootmem_cpumask_var(&cpu_callout_mask); 82 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 83 } 84 85 static void default_init(struct cpuinfo_x86 *c) 86 { 87 #ifdef CONFIG_X86_64 88 cpu_detect_cache_sizes(c); 89 #else 90 /* Not much we can do here... */ 91 /* Check if at least it has cpuid */ 92 if (c->cpuid_level == -1) { 93 /* No cpuid. It must be an ancient CPU */ 94 if (c->x86 == 4) 95 strcpy(c->x86_model_id, "486"); 96 else if (c->x86 == 3) 97 strcpy(c->x86_model_id, "386"); 98 } 99 #endif 100 } 101 102 static const struct cpu_dev default_cpu = { 103 .c_init = default_init, 104 .c_vendor = "Unknown", 105 .c_x86_vendor = X86_VENDOR_UNKNOWN, 106 }; 107 108 static const struct cpu_dev *this_cpu = &default_cpu; 109 110 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 111 #ifdef CONFIG_X86_64 112 /* 113 * We need valid kernel segments for data and code in long mode too 114 * IRET will check the segment types kkeil 2000/10/28 115 * Also sysret mandates a special GDT layout 116 * 117 * TLS descriptors are currently at a different place compared to i386. 118 * Hopefully nobody expects them at a fixed place (Wine?) 119 */ 120 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 121 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 122 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 123 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 124 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 125 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 126 #else 127 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 128 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 129 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 130 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 131 /* 132 * Segments used for calling PnP BIOS have byte granularity. 133 * They code segments and data segments have fixed 64k limits, 134 * the transfer segment sizes are set at run time. 135 */ 136 /* 32-bit code */ 137 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 138 /* 16-bit code */ 139 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 140 /* 16-bit data */ 141 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 142 /* 16-bit data */ 143 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 144 /* 16-bit data */ 145 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 146 /* 147 * The APM segments have byte granularity and their bases 148 * are set at run time. All have 64k limits. 149 */ 150 /* 32-bit code */ 151 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 152 /* 16-bit code */ 153 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 154 /* data */ 155 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 156 157 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 158 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 159 GDT_STACK_CANARY_INIT 160 #endif 161 } }; 162 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 163 164 static int __init x86_mpx_setup(char *s) 165 { 166 /* require an exact match without trailing characters */ 167 if (strlen(s)) 168 return 0; 169 170 /* do not emit a message if the feature is not present */ 171 if (!boot_cpu_has(X86_FEATURE_MPX)) 172 return 1; 173 174 setup_clear_cpu_cap(X86_FEATURE_MPX); 175 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 176 return 1; 177 } 178 __setup("nompx", x86_mpx_setup); 179 180 #ifdef CONFIG_X86_64 181 static int __init x86_nopcid_setup(char *s) 182 { 183 /* nopcid doesn't accept parameters */ 184 if (s) 185 return -EINVAL; 186 187 /* do not emit a message if the feature is not present */ 188 if (!boot_cpu_has(X86_FEATURE_PCID)) 189 return 0; 190 191 setup_clear_cpu_cap(X86_FEATURE_PCID); 192 pr_info("nopcid: PCID feature disabled\n"); 193 return 0; 194 } 195 early_param("nopcid", x86_nopcid_setup); 196 #endif 197 198 static int __init x86_noinvpcid_setup(char *s) 199 { 200 /* noinvpcid doesn't accept parameters */ 201 if (s) 202 return -EINVAL; 203 204 /* do not emit a message if the feature is not present */ 205 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 206 return 0; 207 208 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 209 pr_info("noinvpcid: INVPCID feature disabled\n"); 210 return 0; 211 } 212 early_param("noinvpcid", x86_noinvpcid_setup); 213 214 #ifdef CONFIG_X86_32 215 static int cachesize_override = -1; 216 static int disable_x86_serial_nr = 1; 217 218 static int __init cachesize_setup(char *str) 219 { 220 get_option(&str, &cachesize_override); 221 return 1; 222 } 223 __setup("cachesize=", cachesize_setup); 224 225 static int __init x86_sep_setup(char *s) 226 { 227 setup_clear_cpu_cap(X86_FEATURE_SEP); 228 return 1; 229 } 230 __setup("nosep", x86_sep_setup); 231 232 /* Standard macro to see if a specific flag is changeable */ 233 static inline int flag_is_changeable_p(u32 flag) 234 { 235 u32 f1, f2; 236 237 /* 238 * Cyrix and IDT cpus allow disabling of CPUID 239 * so the code below may return different results 240 * when it is executed before and after enabling 241 * the CPUID. Add "volatile" to not allow gcc to 242 * optimize the subsequent calls to this function. 243 */ 244 asm volatile ("pushfl \n\t" 245 "pushfl \n\t" 246 "popl %0 \n\t" 247 "movl %0, %1 \n\t" 248 "xorl %2, %0 \n\t" 249 "pushl %0 \n\t" 250 "popfl \n\t" 251 "pushfl \n\t" 252 "popl %0 \n\t" 253 "popfl \n\t" 254 255 : "=&r" (f1), "=&r" (f2) 256 : "ir" (flag)); 257 258 return ((f1^f2) & flag) != 0; 259 } 260 261 /* Probe for the CPUID instruction */ 262 int have_cpuid_p(void) 263 { 264 return flag_is_changeable_p(X86_EFLAGS_ID); 265 } 266 267 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 268 { 269 unsigned long lo, hi; 270 271 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 272 return; 273 274 /* Disable processor serial number: */ 275 276 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 277 lo |= 0x200000; 278 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 279 280 pr_notice("CPU serial number disabled.\n"); 281 clear_cpu_cap(c, X86_FEATURE_PN); 282 283 /* Disabling the serial number may affect the cpuid level */ 284 c->cpuid_level = cpuid_eax(0); 285 } 286 287 static int __init x86_serial_nr_setup(char *s) 288 { 289 disable_x86_serial_nr = 0; 290 return 1; 291 } 292 __setup("serialnumber", x86_serial_nr_setup); 293 #else 294 static inline int flag_is_changeable_p(u32 flag) 295 { 296 return 1; 297 } 298 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 299 { 300 } 301 #endif 302 303 static __init int setup_disable_smep(char *arg) 304 { 305 setup_clear_cpu_cap(X86_FEATURE_SMEP); 306 /* Check for things that depend on SMEP being enabled: */ 307 check_mpx_erratum(&boot_cpu_data); 308 return 1; 309 } 310 __setup("nosmep", setup_disable_smep); 311 312 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 313 { 314 if (cpu_has(c, X86_FEATURE_SMEP)) 315 cr4_set_bits(X86_CR4_SMEP); 316 } 317 318 static __init int setup_disable_smap(char *arg) 319 { 320 setup_clear_cpu_cap(X86_FEATURE_SMAP); 321 return 1; 322 } 323 __setup("nosmap", setup_disable_smap); 324 325 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 326 { 327 unsigned long eflags = native_save_fl(); 328 329 /* This should have been cleared long ago */ 330 BUG_ON(eflags & X86_EFLAGS_AC); 331 332 if (cpu_has(c, X86_FEATURE_SMAP)) { 333 #ifdef CONFIG_X86_SMAP 334 cr4_set_bits(X86_CR4_SMAP); 335 #else 336 cr4_clear_bits(X86_CR4_SMAP); 337 #endif 338 } 339 } 340 341 static __always_inline void setup_umip(struct cpuinfo_x86 *c) 342 { 343 /* Check the boot processor, plus build option for UMIP. */ 344 if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 345 goto out; 346 347 /* Check the current processor's cpuid bits. */ 348 if (!cpu_has(c, X86_FEATURE_UMIP)) 349 goto out; 350 351 cr4_set_bits(X86_CR4_UMIP); 352 353 pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n"); 354 355 return; 356 357 out: 358 /* 359 * Make sure UMIP is disabled in case it was enabled in a 360 * previous boot (e.g., via kexec). 361 */ 362 cr4_clear_bits(X86_CR4_UMIP); 363 } 364 365 /* 366 * Protection Keys are not available in 32-bit mode. 367 */ 368 static bool pku_disabled; 369 370 static __always_inline void setup_pku(struct cpuinfo_x86 *c) 371 { 372 /* check the boot processor, plus compile options for PKU: */ 373 if (!cpu_feature_enabled(X86_FEATURE_PKU)) 374 return; 375 /* checks the actual processor's cpuid bits: */ 376 if (!cpu_has(c, X86_FEATURE_PKU)) 377 return; 378 if (pku_disabled) 379 return; 380 381 cr4_set_bits(X86_CR4_PKE); 382 /* 383 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE 384 * cpuid bit to be set. We need to ensure that we 385 * update that bit in this CPU's "cpu_info". 386 */ 387 get_cpu_cap(c); 388 } 389 390 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 391 static __init int setup_disable_pku(char *arg) 392 { 393 /* 394 * Do not clear the X86_FEATURE_PKU bit. All of the 395 * runtime checks are against OSPKE so clearing the 396 * bit does nothing. 397 * 398 * This way, we will see "pku" in cpuinfo, but not 399 * "ospke", which is exactly what we want. It shows 400 * that the CPU has PKU, but the OS has not enabled it. 401 * This happens to be exactly how a system would look 402 * if we disabled the config option. 403 */ 404 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); 405 pku_disabled = true; 406 return 1; 407 } 408 __setup("nopku", setup_disable_pku); 409 #endif /* CONFIG_X86_64 */ 410 411 /* 412 * Some CPU features depend on higher CPUID levels, which may not always 413 * be available due to CPUID level capping or broken virtualization 414 * software. Add those features to this table to auto-disable them. 415 */ 416 struct cpuid_dependent_feature { 417 u32 feature; 418 u32 level; 419 }; 420 421 static const struct cpuid_dependent_feature 422 cpuid_dependent_features[] = { 423 { X86_FEATURE_MWAIT, 0x00000005 }, 424 { X86_FEATURE_DCA, 0x00000009 }, 425 { X86_FEATURE_XSAVE, 0x0000000d }, 426 { 0, 0 } 427 }; 428 429 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 430 { 431 const struct cpuid_dependent_feature *df; 432 433 for (df = cpuid_dependent_features; df->feature; df++) { 434 435 if (!cpu_has(c, df->feature)) 436 continue; 437 /* 438 * Note: cpuid_level is set to -1 if unavailable, but 439 * extended_extended_level is set to 0 if unavailable 440 * and the legitimate extended levels are all negative 441 * when signed; hence the weird messing around with 442 * signs here... 443 */ 444 if (!((s32)df->level < 0 ? 445 (u32)df->level > (u32)c->extended_cpuid_level : 446 (s32)df->level > (s32)c->cpuid_level)) 447 continue; 448 449 clear_cpu_cap(c, df->feature); 450 if (!warn) 451 continue; 452 453 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 454 x86_cap_flag(df->feature), df->level); 455 } 456 } 457 458 /* 459 * Naming convention should be: <Name> [(<Codename>)] 460 * This table only is used unless init_<vendor>() below doesn't set it; 461 * in particular, if CPUID levels 0x80000002..4 are supported, this 462 * isn't used 463 */ 464 465 /* Look up CPU names by table lookup. */ 466 static const char *table_lookup_model(struct cpuinfo_x86 *c) 467 { 468 #ifdef CONFIG_X86_32 469 const struct legacy_cpu_model_info *info; 470 471 if (c->x86_model >= 16) 472 return NULL; /* Range check */ 473 474 if (!this_cpu) 475 return NULL; 476 477 info = this_cpu->legacy_models; 478 479 while (info->family) { 480 if (info->family == c->x86) 481 return info->model_names[c->x86_model]; 482 info++; 483 } 484 #endif 485 return NULL; /* Not found */ 486 } 487 488 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; 489 __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; 490 491 void load_percpu_segment(int cpu) 492 { 493 #ifdef CONFIG_X86_32 494 loadsegment(fs, __KERNEL_PERCPU); 495 #else 496 __loadsegment_simple(gs, 0); 497 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 498 #endif 499 load_stack_canary_segment(); 500 } 501 502 #ifdef CONFIG_X86_32 503 /* The 32-bit entry code needs to find cpu_entry_area. */ 504 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); 505 #endif 506 507 #ifdef CONFIG_X86_64 508 /* 509 * Special IST stacks which the CPU switches to when it calls 510 * an IST-marked descriptor entry. Up to 7 stacks (hardware 511 * limit), all of them are 4K, except the debug stack which 512 * is 8K. 513 */ 514 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 515 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 516 [DEBUG_STACK - 1] = DEBUG_STKSZ 517 }; 518 #endif 519 520 /* Load the original GDT from the per-cpu structure */ 521 void load_direct_gdt(int cpu) 522 { 523 struct desc_ptr gdt_descr; 524 525 gdt_descr.address = (long)get_cpu_gdt_rw(cpu); 526 gdt_descr.size = GDT_SIZE - 1; 527 load_gdt(&gdt_descr); 528 } 529 EXPORT_SYMBOL_GPL(load_direct_gdt); 530 531 /* Load a fixmap remapping of the per-cpu GDT */ 532 void load_fixmap_gdt(int cpu) 533 { 534 struct desc_ptr gdt_descr; 535 536 gdt_descr.address = (long)get_cpu_gdt_ro(cpu); 537 gdt_descr.size = GDT_SIZE - 1; 538 load_gdt(&gdt_descr); 539 } 540 EXPORT_SYMBOL_GPL(load_fixmap_gdt); 541 542 /* 543 * Current gdt points %fs at the "master" per-cpu area: after this, 544 * it's on the real one. 545 */ 546 void switch_to_new_gdt(int cpu) 547 { 548 /* Load the original GDT */ 549 load_direct_gdt(cpu); 550 /* Reload the per-cpu base */ 551 load_percpu_segment(cpu); 552 } 553 554 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 555 556 static void get_model_name(struct cpuinfo_x86 *c) 557 { 558 unsigned int *v; 559 char *p, *q, *s; 560 561 if (c->extended_cpuid_level < 0x80000004) 562 return; 563 564 v = (unsigned int *)c->x86_model_id; 565 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 566 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 567 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 568 c->x86_model_id[48] = 0; 569 570 /* Trim whitespace */ 571 p = q = s = &c->x86_model_id[0]; 572 573 while (*p == ' ') 574 p++; 575 576 while (*p) { 577 /* Note the last non-whitespace index */ 578 if (!isspace(*p)) 579 s = q; 580 581 *q++ = *p++; 582 } 583 584 *(s + 1) = '\0'; 585 } 586 587 void detect_num_cpu_cores(struct cpuinfo_x86 *c) 588 { 589 unsigned int eax, ebx, ecx, edx; 590 591 c->x86_max_cores = 1; 592 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) 593 return; 594 595 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 596 if (eax & 0x1f) 597 c->x86_max_cores = (eax >> 26) + 1; 598 } 599 600 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 601 { 602 unsigned int n, dummy, ebx, ecx, edx, l2size; 603 604 n = c->extended_cpuid_level; 605 606 if (n >= 0x80000005) { 607 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 608 c->x86_cache_size = (ecx>>24) + (edx>>24); 609 #ifdef CONFIG_X86_64 610 /* On K8 L1 TLB is inclusive, so don't count it */ 611 c->x86_tlbsize = 0; 612 #endif 613 } 614 615 if (n < 0x80000006) /* Some chips just has a large L1. */ 616 return; 617 618 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 619 l2size = ecx >> 16; 620 621 #ifdef CONFIG_X86_64 622 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 623 #else 624 /* do processor-specific cache resizing */ 625 if (this_cpu->legacy_cache_size) 626 l2size = this_cpu->legacy_cache_size(c, l2size); 627 628 /* Allow user to override all this if necessary. */ 629 if (cachesize_override != -1) 630 l2size = cachesize_override; 631 632 if (l2size == 0) 633 return; /* Again, no L2 cache is possible */ 634 #endif 635 636 c->x86_cache_size = l2size; 637 } 638 639 u16 __read_mostly tlb_lli_4k[NR_INFO]; 640 u16 __read_mostly tlb_lli_2m[NR_INFO]; 641 u16 __read_mostly tlb_lli_4m[NR_INFO]; 642 u16 __read_mostly tlb_lld_4k[NR_INFO]; 643 u16 __read_mostly tlb_lld_2m[NR_INFO]; 644 u16 __read_mostly tlb_lld_4m[NR_INFO]; 645 u16 __read_mostly tlb_lld_1g[NR_INFO]; 646 647 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 648 { 649 if (this_cpu->c_detect_tlb) 650 this_cpu->c_detect_tlb(c); 651 652 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 653 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 654 tlb_lli_4m[ENTRIES]); 655 656 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 657 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 658 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 659 } 660 661 void detect_ht(struct cpuinfo_x86 *c) 662 { 663 #ifdef CONFIG_SMP 664 u32 eax, ebx, ecx, edx; 665 int index_msb, core_bits; 666 static bool printed; 667 668 if (!cpu_has(c, X86_FEATURE_HT)) 669 return; 670 671 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 672 goto out; 673 674 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 675 return; 676 677 cpuid(1, &eax, &ebx, &ecx, &edx); 678 679 smp_num_siblings = (ebx & 0xff0000) >> 16; 680 681 if (smp_num_siblings == 1) { 682 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 683 goto out; 684 } 685 686 if (smp_num_siblings <= 1) 687 goto out; 688 689 index_msb = get_count_order(smp_num_siblings); 690 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 691 692 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 693 694 index_msb = get_count_order(smp_num_siblings); 695 696 core_bits = get_count_order(c->x86_max_cores); 697 698 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 699 ((1 << core_bits) - 1); 700 701 out: 702 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 703 pr_info("CPU: Physical Processor ID: %d\n", 704 c->phys_proc_id); 705 pr_info("CPU: Processor Core ID: %d\n", 706 c->cpu_core_id); 707 printed = 1; 708 } 709 #endif 710 } 711 712 static void get_cpu_vendor(struct cpuinfo_x86 *c) 713 { 714 char *v = c->x86_vendor_id; 715 int i; 716 717 for (i = 0; i < X86_VENDOR_NUM; i++) { 718 if (!cpu_devs[i]) 719 break; 720 721 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 722 (cpu_devs[i]->c_ident[1] && 723 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 724 725 this_cpu = cpu_devs[i]; 726 c->x86_vendor = this_cpu->c_x86_vendor; 727 return; 728 } 729 } 730 731 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 732 "CPU: Your system may be unstable.\n", v); 733 734 c->x86_vendor = X86_VENDOR_UNKNOWN; 735 this_cpu = &default_cpu; 736 } 737 738 void cpu_detect(struct cpuinfo_x86 *c) 739 { 740 /* Get vendor name */ 741 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 742 (unsigned int *)&c->x86_vendor_id[0], 743 (unsigned int *)&c->x86_vendor_id[8], 744 (unsigned int *)&c->x86_vendor_id[4]); 745 746 c->x86 = 4; 747 /* Intel-defined flags: level 0x00000001 */ 748 if (c->cpuid_level >= 0x00000001) { 749 u32 junk, tfms, cap0, misc; 750 751 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 752 c->x86 = x86_family(tfms); 753 c->x86_model = x86_model(tfms); 754 c->x86_stepping = x86_stepping(tfms); 755 756 if (cap0 & (1<<19)) { 757 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 758 c->x86_cache_alignment = c->x86_clflush_size; 759 } 760 } 761 } 762 763 static void apply_forced_caps(struct cpuinfo_x86 *c) 764 { 765 int i; 766 767 for (i = 0; i < NCAPINTS + NBUGINTS; i++) { 768 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 769 c->x86_capability[i] |= cpu_caps_set[i]; 770 } 771 } 772 773 static void init_speculation_control(struct cpuinfo_x86 *c) 774 { 775 /* 776 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, 777 * and they also have a different bit for STIBP support. Also, 778 * a hypervisor might have set the individual AMD bits even on 779 * Intel CPUs, for finer-grained selection of what's available. 780 */ 781 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { 782 set_cpu_cap(c, X86_FEATURE_IBRS); 783 set_cpu_cap(c, X86_FEATURE_IBPB); 784 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 785 } 786 787 if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) 788 set_cpu_cap(c, X86_FEATURE_STIBP); 789 790 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || 791 cpu_has(c, X86_FEATURE_VIRT_SSBD)) 792 set_cpu_cap(c, X86_FEATURE_SSBD); 793 794 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { 795 set_cpu_cap(c, X86_FEATURE_IBRS); 796 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 797 } 798 799 if (cpu_has(c, X86_FEATURE_AMD_IBPB)) 800 set_cpu_cap(c, X86_FEATURE_IBPB); 801 802 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { 803 set_cpu_cap(c, X86_FEATURE_STIBP); 804 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); 805 } 806 } 807 808 void get_cpu_cap(struct cpuinfo_x86 *c) 809 { 810 u32 eax, ebx, ecx, edx; 811 812 /* Intel-defined flags: level 0x00000001 */ 813 if (c->cpuid_level >= 0x00000001) { 814 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 815 816 c->x86_capability[CPUID_1_ECX] = ecx; 817 c->x86_capability[CPUID_1_EDX] = edx; 818 } 819 820 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ 821 if (c->cpuid_level >= 0x00000006) 822 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 823 824 /* Additional Intel-defined flags: level 0x00000007 */ 825 if (c->cpuid_level >= 0x00000007) { 826 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 827 c->x86_capability[CPUID_7_0_EBX] = ebx; 828 c->x86_capability[CPUID_7_ECX] = ecx; 829 c->x86_capability[CPUID_7_EDX] = edx; 830 } 831 832 /* Extended state features: level 0x0000000d */ 833 if (c->cpuid_level >= 0x0000000d) { 834 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 835 836 c->x86_capability[CPUID_D_1_EAX] = eax; 837 } 838 839 /* Additional Intel-defined flags: level 0x0000000F */ 840 if (c->cpuid_level >= 0x0000000F) { 841 842 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 843 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 844 c->x86_capability[CPUID_F_0_EDX] = edx; 845 846 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 847 /* will be overridden if occupancy monitoring exists */ 848 c->x86_cache_max_rmid = ebx; 849 850 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 851 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 852 c->x86_capability[CPUID_F_1_EDX] = edx; 853 854 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || 855 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || 856 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { 857 c->x86_cache_max_rmid = ecx; 858 c->x86_cache_occ_scale = ebx; 859 } 860 } else { 861 c->x86_cache_max_rmid = -1; 862 c->x86_cache_occ_scale = -1; 863 } 864 } 865 866 /* AMD-defined flags: level 0x80000001 */ 867 eax = cpuid_eax(0x80000000); 868 c->extended_cpuid_level = eax; 869 870 if ((eax & 0xffff0000) == 0x80000000) { 871 if (eax >= 0x80000001) { 872 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 873 874 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 875 c->x86_capability[CPUID_8000_0001_EDX] = edx; 876 } 877 } 878 879 if (c->extended_cpuid_level >= 0x80000007) { 880 cpuid(0x80000007, &eax, &ebx, &ecx, &edx); 881 882 c->x86_capability[CPUID_8000_0007_EBX] = ebx; 883 c->x86_power = edx; 884 } 885 886 if (c->extended_cpuid_level >= 0x80000008) { 887 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 888 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 889 } 890 891 if (c->extended_cpuid_level >= 0x8000000a) 892 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 893 894 init_scattered_cpuid_features(c); 895 init_speculation_control(c); 896 897 /* 898 * Clear/Set all flags overridden by options, after probe. 899 * This needs to happen each time we re-probe, which may happen 900 * several times during CPU initialization. 901 */ 902 apply_forced_caps(c); 903 } 904 905 static void get_cpu_address_sizes(struct cpuinfo_x86 *c) 906 { 907 u32 eax, ebx, ecx, edx; 908 909 if (c->extended_cpuid_level >= 0x80000008) { 910 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 911 912 c->x86_virt_bits = (eax >> 8) & 0xff; 913 c->x86_phys_bits = eax & 0xff; 914 } 915 #ifdef CONFIG_X86_32 916 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 917 c->x86_phys_bits = 36; 918 #endif 919 } 920 921 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 922 { 923 #ifdef CONFIG_X86_32 924 int i; 925 926 /* 927 * First of all, decide if this is a 486 or higher 928 * It's a 486 if we can modify the AC flag 929 */ 930 if (flag_is_changeable_p(X86_EFLAGS_AC)) 931 c->x86 = 4; 932 else 933 c->x86 = 3; 934 935 for (i = 0; i < X86_VENDOR_NUM; i++) 936 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 937 c->x86_vendor_id[0] = 0; 938 cpu_devs[i]->c_identify(c); 939 if (c->x86_vendor_id[0]) { 940 get_cpu_vendor(c); 941 break; 942 } 943 } 944 #endif 945 } 946 947 static const __initconst struct x86_cpu_id cpu_no_speculation[] = { 948 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY }, 949 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY }, 950 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY }, 951 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY }, 952 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY }, 953 { X86_VENDOR_CENTAUR, 5 }, 954 { X86_VENDOR_INTEL, 5 }, 955 { X86_VENDOR_NSC, 5 }, 956 { X86_VENDOR_ANY, 4 }, 957 {} 958 }; 959 960 static const __initconst struct x86_cpu_id cpu_no_meltdown[] = { 961 { X86_VENDOR_AMD }, 962 {} 963 }; 964 965 /* Only list CPUs which speculate but are non susceptible to SSB */ 966 static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = { 967 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 }, 968 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT }, 969 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 }, 970 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD }, 971 { X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH }, 972 { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL }, 973 { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM }, 974 { X86_VENDOR_AMD, 0x12, }, 975 { X86_VENDOR_AMD, 0x11, }, 976 { X86_VENDOR_AMD, 0x10, }, 977 { X86_VENDOR_AMD, 0xf, }, 978 {} 979 }; 980 981 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) 982 { 983 u64 ia32_cap = 0; 984 985 if (x86_match_cpu(cpu_no_speculation)) 986 return; 987 988 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 989 setup_force_cpu_bug(X86_BUG_SPECTRE_V2); 990 991 if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) 992 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); 993 994 if (!x86_match_cpu(cpu_no_spec_store_bypass) && 995 !(ia32_cap & ARCH_CAP_SSB_NO)) 996 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); 997 998 if (x86_match_cpu(cpu_no_meltdown)) 999 return; 1000 1001 /* Rogue Data Cache Load? No! */ 1002 if (ia32_cap & ARCH_CAP_RDCL_NO) 1003 return; 1004 1005 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); 1006 } 1007 1008 /* 1009 * Do minimum CPU detection early. 1010 * Fields really needed: vendor, cpuid_level, family, model, mask, 1011 * cache alignment. 1012 * The others are not touched to avoid unwanted side effects. 1013 * 1014 * WARNING: this function is only called on the boot CPU. Don't add code 1015 * here that is supposed to run on all CPUs. 1016 */ 1017 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 1018 { 1019 #ifdef CONFIG_X86_64 1020 c->x86_clflush_size = 64; 1021 c->x86_phys_bits = 36; 1022 c->x86_virt_bits = 48; 1023 #else 1024 c->x86_clflush_size = 32; 1025 c->x86_phys_bits = 32; 1026 c->x86_virt_bits = 32; 1027 #endif 1028 c->x86_cache_alignment = c->x86_clflush_size; 1029 1030 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1031 c->extended_cpuid_level = 0; 1032 1033 /* cyrix could have cpuid enabled via c_identify()*/ 1034 if (have_cpuid_p()) { 1035 cpu_detect(c); 1036 get_cpu_vendor(c); 1037 get_cpu_cap(c); 1038 get_cpu_address_sizes(c); 1039 setup_force_cpu_cap(X86_FEATURE_CPUID); 1040 1041 if (this_cpu->c_early_init) 1042 this_cpu->c_early_init(c); 1043 1044 c->cpu_index = 0; 1045 filter_cpuid_features(c, false); 1046 1047 if (this_cpu->c_bsp_init) 1048 this_cpu->c_bsp_init(c); 1049 } else { 1050 identify_cpu_without_cpuid(c); 1051 setup_clear_cpu_cap(X86_FEATURE_CPUID); 1052 } 1053 1054 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 1055 1056 cpu_set_bug_bits(c); 1057 1058 fpu__init_system(c); 1059 1060 #ifdef CONFIG_X86_32 1061 /* 1062 * Regardless of whether PCID is enumerated, the SDM says 1063 * that it can't be enabled in 32-bit mode. 1064 */ 1065 setup_clear_cpu_cap(X86_FEATURE_PCID); 1066 #endif 1067 1068 /* 1069 * Later in the boot process pgtable_l5_enabled() relies on 1070 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not 1071 * enabled by this point we need to clear the feature bit to avoid 1072 * false-positives at the later stage. 1073 * 1074 * pgtable_l5_enabled() can be false here for several reasons: 1075 * - 5-level paging is disabled compile-time; 1076 * - it's 32-bit kernel; 1077 * - machine doesn't support 5-level paging; 1078 * - user specified 'no5lvl' in kernel command line. 1079 */ 1080 if (!pgtable_l5_enabled()) 1081 setup_clear_cpu_cap(X86_FEATURE_LA57); 1082 } 1083 1084 void __init early_cpu_init(void) 1085 { 1086 const struct cpu_dev *const *cdev; 1087 int count = 0; 1088 1089 #ifdef CONFIG_PROCESSOR_SELECT 1090 pr_info("KERNEL supported cpus:\n"); 1091 #endif 1092 1093 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 1094 const struct cpu_dev *cpudev = *cdev; 1095 1096 if (count >= X86_VENDOR_NUM) 1097 break; 1098 cpu_devs[count] = cpudev; 1099 count++; 1100 1101 #ifdef CONFIG_PROCESSOR_SELECT 1102 { 1103 unsigned int j; 1104 1105 for (j = 0; j < 2; j++) { 1106 if (!cpudev->c_ident[j]) 1107 continue; 1108 pr_info(" %s %s\n", cpudev->c_vendor, 1109 cpudev->c_ident[j]); 1110 } 1111 } 1112 #endif 1113 } 1114 early_identify_cpu(&boot_cpu_data); 1115 } 1116 1117 /* 1118 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 1119 * unfortunately, that's not true in practice because of early VIA 1120 * chips and (more importantly) broken virtualizers that are not easy 1121 * to detect. In the latter case it doesn't even *fail* reliably, so 1122 * probing for it doesn't even work. Disable it completely on 32-bit 1123 * unless we can find a reliable way to detect all the broken cases. 1124 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 1125 */ 1126 static void detect_nopl(struct cpuinfo_x86 *c) 1127 { 1128 #ifdef CONFIG_X86_32 1129 clear_cpu_cap(c, X86_FEATURE_NOPL); 1130 #else 1131 set_cpu_cap(c, X86_FEATURE_NOPL); 1132 #endif 1133 } 1134 1135 static void detect_null_seg_behavior(struct cpuinfo_x86 *c) 1136 { 1137 #ifdef CONFIG_X86_64 1138 /* 1139 * Empirically, writing zero to a segment selector on AMD does 1140 * not clear the base, whereas writing zero to a segment 1141 * selector on Intel does clear the base. Intel's behavior 1142 * allows slightly faster context switches in the common case 1143 * where GS is unused by the prev and next threads. 1144 * 1145 * Since neither vendor documents this anywhere that I can see, 1146 * detect it directly instead of hardcoding the choice by 1147 * vendor. 1148 * 1149 * I've designated AMD's behavior as the "bug" because it's 1150 * counterintuitive and less friendly. 1151 */ 1152 1153 unsigned long old_base, tmp; 1154 rdmsrl(MSR_FS_BASE, old_base); 1155 wrmsrl(MSR_FS_BASE, 1); 1156 loadsegment(fs, 0); 1157 rdmsrl(MSR_FS_BASE, tmp); 1158 if (tmp != 0) 1159 set_cpu_bug(c, X86_BUG_NULL_SEG); 1160 wrmsrl(MSR_FS_BASE, old_base); 1161 #endif 1162 } 1163 1164 static void generic_identify(struct cpuinfo_x86 *c) 1165 { 1166 c->extended_cpuid_level = 0; 1167 1168 if (!have_cpuid_p()) 1169 identify_cpu_without_cpuid(c); 1170 1171 /* cyrix could have cpuid enabled via c_identify()*/ 1172 if (!have_cpuid_p()) 1173 return; 1174 1175 cpu_detect(c); 1176 1177 get_cpu_vendor(c); 1178 1179 get_cpu_cap(c); 1180 1181 get_cpu_address_sizes(c); 1182 1183 if (c->cpuid_level >= 0x00000001) { 1184 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 1185 #ifdef CONFIG_X86_32 1186 # ifdef CONFIG_SMP 1187 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1188 # else 1189 c->apicid = c->initial_apicid; 1190 # endif 1191 #endif 1192 c->phys_proc_id = c->initial_apicid; 1193 } 1194 1195 get_model_name(c); /* Default name */ 1196 1197 detect_nopl(c); 1198 1199 detect_null_seg_behavior(c); 1200 1201 /* 1202 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 1203 * systems that run Linux at CPL > 0 may or may not have the 1204 * issue, but, even if they have the issue, there's absolutely 1205 * nothing we can do about it because we can't use the real IRET 1206 * instruction. 1207 * 1208 * NB: For the time being, only 32-bit kernels support 1209 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 1210 * whether to apply espfix using paravirt hooks. If any 1211 * non-paravirt system ever shows up that does *not* have the 1212 * ESPFIX issue, we can change this. 1213 */ 1214 #ifdef CONFIG_X86_32 1215 # ifdef CONFIG_PARAVIRT 1216 do { 1217 extern void native_iret(void); 1218 if (pv_cpu_ops.iret == native_iret) 1219 set_cpu_bug(c, X86_BUG_ESPFIX); 1220 } while (0); 1221 # else 1222 set_cpu_bug(c, X86_BUG_ESPFIX); 1223 # endif 1224 #endif 1225 } 1226 1227 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 1228 { 1229 /* 1230 * The heavy lifting of max_rmid and cache_occ_scale are handled 1231 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 1232 * in case CQM bits really aren't there in this CPU. 1233 */ 1234 if (c != &boot_cpu_data) { 1235 boot_cpu_data.x86_cache_max_rmid = 1236 min(boot_cpu_data.x86_cache_max_rmid, 1237 c->x86_cache_max_rmid); 1238 } 1239 } 1240 1241 /* 1242 * Validate that ACPI/mptables have the same information about the 1243 * effective APIC id and update the package map. 1244 */ 1245 static void validate_apic_and_package_id(struct cpuinfo_x86 *c) 1246 { 1247 #ifdef CONFIG_SMP 1248 unsigned int apicid, cpu = smp_processor_id(); 1249 1250 apicid = apic->cpu_present_to_apicid(cpu); 1251 1252 if (apicid != c->apicid) { 1253 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", 1254 cpu, apicid, c->initial_apicid); 1255 } 1256 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); 1257 #else 1258 c->logical_proc_id = 0; 1259 #endif 1260 } 1261 1262 /* 1263 * This does the hard work of actually picking apart the CPU stuff... 1264 */ 1265 static void identify_cpu(struct cpuinfo_x86 *c) 1266 { 1267 int i; 1268 1269 c->loops_per_jiffy = loops_per_jiffy; 1270 c->x86_cache_size = 0; 1271 c->x86_vendor = X86_VENDOR_UNKNOWN; 1272 c->x86_model = c->x86_stepping = 0; /* So far unknown... */ 1273 c->x86_vendor_id[0] = '\0'; /* Unset */ 1274 c->x86_model_id[0] = '\0'; /* Unset */ 1275 c->x86_max_cores = 1; 1276 c->x86_coreid_bits = 0; 1277 c->cu_id = 0xff; 1278 #ifdef CONFIG_X86_64 1279 c->x86_clflush_size = 64; 1280 c->x86_phys_bits = 36; 1281 c->x86_virt_bits = 48; 1282 #else 1283 c->cpuid_level = -1; /* CPUID not detected */ 1284 c->x86_clflush_size = 32; 1285 c->x86_phys_bits = 32; 1286 c->x86_virt_bits = 32; 1287 #endif 1288 c->x86_cache_alignment = c->x86_clflush_size; 1289 memset(&c->x86_capability, 0, sizeof c->x86_capability); 1290 1291 generic_identify(c); 1292 1293 if (this_cpu->c_identify) 1294 this_cpu->c_identify(c); 1295 1296 /* Clear/Set all flags overridden by options, after probe */ 1297 apply_forced_caps(c); 1298 1299 #ifdef CONFIG_X86_64 1300 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 1301 #endif 1302 1303 /* 1304 * Vendor-specific initialization. In this section we 1305 * canonicalize the feature flags, meaning if there are 1306 * features a certain CPU supports which CPUID doesn't 1307 * tell us, CPUID claiming incorrect flags, or other bugs, 1308 * we handle them here. 1309 * 1310 * At the end of this section, c->x86_capability better 1311 * indicate the features this CPU genuinely supports! 1312 */ 1313 if (this_cpu->c_init) 1314 this_cpu->c_init(c); 1315 1316 /* Disable the PN if appropriate */ 1317 squash_the_stupid_serial_number(c); 1318 1319 /* Set up SMEP/SMAP/UMIP */ 1320 setup_smep(c); 1321 setup_smap(c); 1322 setup_umip(c); 1323 1324 /* 1325 * The vendor-specific functions might have changed features. 1326 * Now we do "generic changes." 1327 */ 1328 1329 /* Filter out anything that depends on CPUID levels we don't have */ 1330 filter_cpuid_features(c, true); 1331 1332 /* If the model name is still unset, do table lookup. */ 1333 if (!c->x86_model_id[0]) { 1334 const char *p; 1335 p = table_lookup_model(c); 1336 if (p) 1337 strcpy(c->x86_model_id, p); 1338 else 1339 /* Last resort... */ 1340 sprintf(c->x86_model_id, "%02x/%02x", 1341 c->x86, c->x86_model); 1342 } 1343 1344 #ifdef CONFIG_X86_64 1345 detect_ht(c); 1346 #endif 1347 1348 x86_init_rdrand(c); 1349 x86_init_cache_qos(c); 1350 setup_pku(c); 1351 1352 /* 1353 * Clear/Set all flags overridden by options, need do it 1354 * before following smp all cpus cap AND. 1355 */ 1356 apply_forced_caps(c); 1357 1358 /* 1359 * On SMP, boot_cpu_data holds the common feature set between 1360 * all CPUs; so make sure that we indicate which features are 1361 * common between the CPUs. The first time this routine gets 1362 * executed, c == &boot_cpu_data. 1363 */ 1364 if (c != &boot_cpu_data) { 1365 /* AND the already accumulated flags with these */ 1366 for (i = 0; i < NCAPINTS; i++) 1367 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1368 1369 /* OR, i.e. replicate the bug flags */ 1370 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1371 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1372 } 1373 1374 /* Init Machine Check Exception if available. */ 1375 mcheck_cpu_init(c); 1376 1377 select_idle_routine(c); 1378 1379 #ifdef CONFIG_NUMA 1380 numa_add_cpu(smp_processor_id()); 1381 #endif 1382 } 1383 1384 /* 1385 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1386 * on 32-bit kernels: 1387 */ 1388 #ifdef CONFIG_X86_32 1389 void enable_sep_cpu(void) 1390 { 1391 struct tss_struct *tss; 1392 int cpu; 1393 1394 if (!boot_cpu_has(X86_FEATURE_SEP)) 1395 return; 1396 1397 cpu = get_cpu(); 1398 tss = &per_cpu(cpu_tss_rw, cpu); 1399 1400 /* 1401 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1402 * see the big comment in struct x86_hw_tss's definition. 1403 */ 1404 1405 tss->x86_tss.ss1 = __KERNEL_CS; 1406 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1407 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 1408 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1409 1410 put_cpu(); 1411 } 1412 #endif 1413 1414 void __init identify_boot_cpu(void) 1415 { 1416 identify_cpu(&boot_cpu_data); 1417 #ifdef CONFIG_X86_32 1418 sysenter_setup(); 1419 enable_sep_cpu(); 1420 #endif 1421 cpu_detect_tlb(&boot_cpu_data); 1422 } 1423 1424 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1425 { 1426 BUG_ON(c == &boot_cpu_data); 1427 identify_cpu(c); 1428 #ifdef CONFIG_X86_32 1429 enable_sep_cpu(); 1430 #endif 1431 mtrr_ap_init(); 1432 validate_apic_and_package_id(c); 1433 x86_spec_ctrl_setup_ap(); 1434 } 1435 1436 static __init int setup_noclflush(char *arg) 1437 { 1438 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1439 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1440 return 1; 1441 } 1442 __setup("noclflush", setup_noclflush); 1443 1444 void print_cpu_info(struct cpuinfo_x86 *c) 1445 { 1446 const char *vendor = NULL; 1447 1448 if (c->x86_vendor < X86_VENDOR_NUM) { 1449 vendor = this_cpu->c_vendor; 1450 } else { 1451 if (c->cpuid_level >= 0) 1452 vendor = c->x86_vendor_id; 1453 } 1454 1455 if (vendor && !strstr(c->x86_model_id, vendor)) 1456 pr_cont("%s ", vendor); 1457 1458 if (c->x86_model_id[0]) 1459 pr_cont("%s", c->x86_model_id); 1460 else 1461 pr_cont("%d86", c->x86); 1462 1463 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1464 1465 if (c->x86_stepping || c->cpuid_level >= 0) 1466 pr_cont(", stepping: 0x%x)\n", c->x86_stepping); 1467 else 1468 pr_cont(")\n"); 1469 } 1470 1471 /* 1472 * clearcpuid= was already parsed in fpu__init_parse_early_param. 1473 * But we need to keep a dummy __setup around otherwise it would 1474 * show up as an environment variable for init. 1475 */ 1476 static __init int setup_clearcpuid(char *arg) 1477 { 1478 return 1; 1479 } 1480 __setup("clearcpuid=", setup_clearcpuid); 1481 1482 #ifdef CONFIG_X86_64 1483 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1484 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1485 EXPORT_PER_CPU_SYMBOL_GPL(irq_stack_union); 1486 1487 /* 1488 * The following percpu variables are hot. Align current_task to 1489 * cacheline size such that they fall in the same cacheline. 1490 */ 1491 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1492 &init_task; 1493 EXPORT_PER_CPU_SYMBOL(current_task); 1494 1495 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1496 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; 1497 1498 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1499 1500 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1501 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1502 1503 /* May not be marked __init: used by software suspend */ 1504 void syscall_init(void) 1505 { 1506 extern char _entry_trampoline[]; 1507 extern char entry_SYSCALL_64_trampoline[]; 1508 1509 int cpu = smp_processor_id(); 1510 unsigned long SYSCALL64_entry_trampoline = 1511 (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline + 1512 (entry_SYSCALL_64_trampoline - _entry_trampoline); 1513 1514 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1515 if (static_cpu_has(X86_FEATURE_PTI)) 1516 wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline); 1517 else 1518 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1519 1520 #ifdef CONFIG_IA32_EMULATION 1521 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1522 /* 1523 * This only works on Intel CPUs. 1524 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1525 * This does not cause SYSENTER to jump to the wrong location, because 1526 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1527 */ 1528 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1529 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); 1530 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1531 #else 1532 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1533 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1534 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1535 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1536 #endif 1537 1538 /* Flags to clear on syscall */ 1539 wrmsrl(MSR_SYSCALL_MASK, 1540 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1541 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1542 } 1543 1544 /* 1545 * Copies of the original ist values from the tss are only accessed during 1546 * debugging, no special alignment required. 1547 */ 1548 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1549 1550 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1551 DEFINE_PER_CPU(int, debug_stack_usage); 1552 1553 int is_debug_stack(unsigned long addr) 1554 { 1555 return __this_cpu_read(debug_stack_usage) || 1556 (addr <= __this_cpu_read(debug_stack_addr) && 1557 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1558 } 1559 NOKPROBE_SYMBOL(is_debug_stack); 1560 1561 DEFINE_PER_CPU(u32, debug_idt_ctr); 1562 1563 void debug_stack_set_zero(void) 1564 { 1565 this_cpu_inc(debug_idt_ctr); 1566 load_current_idt(); 1567 } 1568 NOKPROBE_SYMBOL(debug_stack_set_zero); 1569 1570 void debug_stack_reset(void) 1571 { 1572 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1573 return; 1574 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1575 load_current_idt(); 1576 } 1577 NOKPROBE_SYMBOL(debug_stack_reset); 1578 1579 #else /* CONFIG_X86_64 */ 1580 1581 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1582 EXPORT_PER_CPU_SYMBOL(current_task); 1583 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1584 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1585 1586 /* 1587 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1588 * the top of the kernel stack. Use an extra percpu variable to track the 1589 * top of the kernel stack directly. 1590 */ 1591 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1592 (unsigned long)&init_thread_union + THREAD_SIZE; 1593 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1594 1595 #ifdef CONFIG_CC_STACKPROTECTOR 1596 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1597 #endif 1598 1599 #endif /* CONFIG_X86_64 */ 1600 1601 /* 1602 * Clear all 6 debug registers: 1603 */ 1604 static void clear_all_debug_regs(void) 1605 { 1606 int i; 1607 1608 for (i = 0; i < 8; i++) { 1609 /* Ignore db4, db5 */ 1610 if ((i == 4) || (i == 5)) 1611 continue; 1612 1613 set_debugreg(0, i); 1614 } 1615 } 1616 1617 #ifdef CONFIG_KGDB 1618 /* 1619 * Restore debug regs if using kgdbwait and you have a kernel debugger 1620 * connection established. 1621 */ 1622 static void dbg_restore_debug_regs(void) 1623 { 1624 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1625 arch_kgdb_ops.correct_hw_break(); 1626 } 1627 #else /* ! CONFIG_KGDB */ 1628 #define dbg_restore_debug_regs() 1629 #endif /* ! CONFIG_KGDB */ 1630 1631 static void wait_for_master_cpu(int cpu) 1632 { 1633 #ifdef CONFIG_SMP 1634 /* 1635 * wait for ACK from master CPU before continuing 1636 * with AP initialization 1637 */ 1638 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1639 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1640 cpu_relax(); 1641 #endif 1642 } 1643 1644 /* 1645 * cpu_init() initializes state that is per-CPU. Some data is already 1646 * initialized (naturally) in the bootstrap process, such as the GDT 1647 * and IDT. We reload them nevertheless, this function acts as a 1648 * 'CPU state barrier', nothing should get across. 1649 * A lot of state is already set up in PDA init for 64 bit 1650 */ 1651 #ifdef CONFIG_X86_64 1652 1653 void cpu_init(void) 1654 { 1655 struct orig_ist *oist; 1656 struct task_struct *me; 1657 struct tss_struct *t; 1658 unsigned long v; 1659 int cpu = raw_smp_processor_id(); 1660 int i; 1661 1662 wait_for_master_cpu(cpu); 1663 1664 /* 1665 * Initialize the CR4 shadow before doing anything that could 1666 * try to read it. 1667 */ 1668 cr4_init_shadow(); 1669 1670 if (cpu) 1671 load_ucode_ap(); 1672 1673 t = &per_cpu(cpu_tss_rw, cpu); 1674 oist = &per_cpu(orig_ist, cpu); 1675 1676 #ifdef CONFIG_NUMA 1677 if (this_cpu_read(numa_node) == 0 && 1678 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1679 set_numa_node(early_cpu_to_node(cpu)); 1680 #endif 1681 1682 me = current; 1683 1684 pr_debug("Initializing CPU#%d\n", cpu); 1685 1686 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1687 1688 /* 1689 * Initialize the per-CPU GDT with the boot GDT, 1690 * and set up the GDT descriptor: 1691 */ 1692 1693 switch_to_new_gdt(cpu); 1694 loadsegment(fs, 0); 1695 1696 load_current_idt(); 1697 1698 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1699 syscall_init(); 1700 1701 wrmsrl(MSR_FS_BASE, 0); 1702 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1703 barrier(); 1704 1705 x86_configure_nx(); 1706 x2apic_setup(); 1707 1708 /* 1709 * set up and load the per-CPU TSS 1710 */ 1711 if (!oist->ist[0]) { 1712 char *estacks = get_cpu_entry_area(cpu)->exception_stacks; 1713 1714 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1715 estacks += exception_stack_sizes[v]; 1716 oist->ist[v] = t->x86_tss.ist[v] = 1717 (unsigned long)estacks; 1718 if (v == DEBUG_STACK-1) 1719 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1720 } 1721 } 1722 1723 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1724 1725 /* 1726 * <= is required because the CPU will access up to 1727 * 8 bits beyond the end of the IO permission bitmap. 1728 */ 1729 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1730 t->io_bitmap[i] = ~0UL; 1731 1732 mmgrab(&init_mm); 1733 me->active_mm = &init_mm; 1734 BUG_ON(me->mm); 1735 initialize_tlbstate_and_flush(); 1736 enter_lazy_tlb(&init_mm, me); 1737 1738 /* 1739 * Initialize the TSS. sp0 points to the entry trampoline stack 1740 * regardless of what task is running. 1741 */ 1742 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1743 load_TR_desc(); 1744 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); 1745 1746 load_mm_ldt(&init_mm); 1747 1748 clear_all_debug_regs(); 1749 dbg_restore_debug_regs(); 1750 1751 fpu__init_cpu(); 1752 1753 if (is_uv_system()) 1754 uv_cpu_init(); 1755 1756 load_fixmap_gdt(cpu); 1757 } 1758 1759 #else 1760 1761 void cpu_init(void) 1762 { 1763 int cpu = smp_processor_id(); 1764 struct task_struct *curr = current; 1765 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); 1766 1767 wait_for_master_cpu(cpu); 1768 1769 /* 1770 * Initialize the CR4 shadow before doing anything that could 1771 * try to read it. 1772 */ 1773 cr4_init_shadow(); 1774 1775 show_ucode_info_early(); 1776 1777 pr_info("Initializing CPU#%d\n", cpu); 1778 1779 if (cpu_feature_enabled(X86_FEATURE_VME) || 1780 boot_cpu_has(X86_FEATURE_TSC) || 1781 boot_cpu_has(X86_FEATURE_DE)) 1782 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1783 1784 load_current_idt(); 1785 switch_to_new_gdt(cpu); 1786 1787 /* 1788 * Set up and load the per-CPU TSS and LDT 1789 */ 1790 mmgrab(&init_mm); 1791 curr->active_mm = &init_mm; 1792 BUG_ON(curr->mm); 1793 initialize_tlbstate_and_flush(); 1794 enter_lazy_tlb(&init_mm, curr); 1795 1796 /* 1797 * Initialize the TSS. Don't bother initializing sp0, as the initial 1798 * task never enters user mode. 1799 */ 1800 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 1801 load_TR_desc(); 1802 1803 load_mm_ldt(&init_mm); 1804 1805 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; 1806 1807 #ifdef CONFIG_DOUBLEFAULT 1808 /* Set up doublefault TSS pointer in the GDT */ 1809 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1810 #endif 1811 1812 clear_all_debug_regs(); 1813 dbg_restore_debug_regs(); 1814 1815 fpu__init_cpu(); 1816 1817 load_fixmap_gdt(cpu); 1818 } 1819 #endif 1820 1821 static void bsp_resume(void) 1822 { 1823 if (this_cpu->c_bsp_resume) 1824 this_cpu->c_bsp_resume(&boot_cpu_data); 1825 } 1826 1827 static struct syscore_ops cpu_syscore_ops = { 1828 .resume = bsp_resume, 1829 }; 1830 1831 static int __init init_cpu_syscore(void) 1832 { 1833 register_syscore_ops(&cpu_syscore_ops); 1834 return 0; 1835 } 1836 core_initcall(init_cpu_syscore); 1837 1838 /* 1839 * The microcode loader calls this upon late microcode load to recheck features, 1840 * only when microcode has been updated. Caller holds microcode_mutex and CPU 1841 * hotplug lock. 1842 */ 1843 void microcode_check(void) 1844 { 1845 struct cpuinfo_x86 info; 1846 1847 perf_check_microcode(); 1848 1849 /* Reload CPUID max function as it might've changed. */ 1850 info.cpuid_level = cpuid_eax(0); 1851 1852 /* 1853 * Copy all capability leafs to pick up the synthetic ones so that 1854 * memcmp() below doesn't fail on that. The ones coming from CPUID will 1855 * get overwritten in get_cpu_cap(). 1856 */ 1857 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); 1858 1859 get_cpu_cap(&info); 1860 1861 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) 1862 return; 1863 1864 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); 1865 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); 1866 } 1867