1 #include <linux/bootmem.h> 2 #include <linux/linkage.h> 3 #include <linux/bitops.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/percpu.h> 7 #include <linux/string.h> 8 #include <linux/ctype.h> 9 #include <linux/delay.h> 10 #include <linux/sched.h> 11 #include <linux/init.h> 12 #include <linux/kprobes.h> 13 #include <linux/kgdb.h> 14 #include <linux/smp.h> 15 #include <linux/io.h> 16 #include <linux/syscore_ops.h> 17 18 #include <asm/stackprotector.h> 19 #include <asm/perf_event.h> 20 #include <asm/mmu_context.h> 21 #include <asm/archrandom.h> 22 #include <asm/hypervisor.h> 23 #include <asm/processor.h> 24 #include <asm/tlbflush.h> 25 #include <asm/debugreg.h> 26 #include <asm/sections.h> 27 #include <asm/vsyscall.h> 28 #include <linux/topology.h> 29 #include <linux/cpumask.h> 30 #include <asm/pgtable.h> 31 #include <linux/atomic.h> 32 #include <asm/proto.h> 33 #include <asm/setup.h> 34 #include <asm/apic.h> 35 #include <asm/desc.h> 36 #include <asm/fpu/internal.h> 37 #include <asm/mtrr.h> 38 #include <linux/numa.h> 39 #include <asm/asm.h> 40 #include <asm/cpu.h> 41 #include <asm/mce.h> 42 #include <asm/msr.h> 43 #include <asm/pat.h> 44 #include <asm/microcode.h> 45 #include <asm/microcode_intel.h> 46 47 #ifdef CONFIG_X86_LOCAL_APIC 48 #include <asm/uv/uv.h> 49 #endif 50 51 #include "cpu.h" 52 53 /* all of these masks are initialized in setup_cpu_local_masks() */ 54 cpumask_var_t cpu_initialized_mask; 55 cpumask_var_t cpu_callout_mask; 56 cpumask_var_t cpu_callin_mask; 57 58 /* representing cpus for which sibling maps can be computed */ 59 cpumask_var_t cpu_sibling_setup_mask; 60 61 /* correctly size the local cpu masks */ 62 void __init setup_cpu_local_masks(void) 63 { 64 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 65 alloc_bootmem_cpumask_var(&cpu_callin_mask); 66 alloc_bootmem_cpumask_var(&cpu_callout_mask); 67 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 68 } 69 70 static void default_init(struct cpuinfo_x86 *c) 71 { 72 #ifdef CONFIG_X86_64 73 cpu_detect_cache_sizes(c); 74 #else 75 /* Not much we can do here... */ 76 /* Check if at least it has cpuid */ 77 if (c->cpuid_level == -1) { 78 /* No cpuid. It must be an ancient CPU */ 79 if (c->x86 == 4) 80 strcpy(c->x86_model_id, "486"); 81 else if (c->x86 == 3) 82 strcpy(c->x86_model_id, "386"); 83 } 84 #endif 85 } 86 87 static const struct cpu_dev default_cpu = { 88 .c_init = default_init, 89 .c_vendor = "Unknown", 90 .c_x86_vendor = X86_VENDOR_UNKNOWN, 91 }; 92 93 static const struct cpu_dev *this_cpu = &default_cpu; 94 95 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { 96 #ifdef CONFIG_X86_64 97 /* 98 * We need valid kernel segments for data and code in long mode too 99 * IRET will check the segment types kkeil 2000/10/28 100 * Also sysret mandates a special GDT layout 101 * 102 * TLS descriptors are currently at a different place compared to i386. 103 * Hopefully nobody expects them at a fixed place (Wine?) 104 */ 105 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 106 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 107 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 108 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), 109 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), 110 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), 111 #else 112 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), 113 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 114 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), 115 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), 116 /* 117 * Segments used for calling PnP BIOS have byte granularity. 118 * They code segments and data segments have fixed 64k limits, 119 * the transfer segment sizes are set at run time. 120 */ 121 /* 32-bit code */ 122 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 123 /* 16-bit code */ 124 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 125 /* 16-bit data */ 126 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), 127 /* 16-bit data */ 128 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), 129 /* 16-bit data */ 130 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), 131 /* 132 * The APM segments have byte granularity and their bases 133 * are set at run time. All have 64k limits. 134 */ 135 /* 32-bit code */ 136 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), 137 /* 16-bit code */ 138 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), 139 /* data */ 140 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), 141 142 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 143 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), 144 GDT_STACK_CANARY_INIT 145 #endif 146 } }; 147 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); 148 149 static int __init x86_mpx_setup(char *s) 150 { 151 /* require an exact match without trailing characters */ 152 if (strlen(s)) 153 return 0; 154 155 /* do not emit a message if the feature is not present */ 156 if (!boot_cpu_has(X86_FEATURE_MPX)) 157 return 1; 158 159 setup_clear_cpu_cap(X86_FEATURE_MPX); 160 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); 161 return 1; 162 } 163 __setup("nompx", x86_mpx_setup); 164 165 static int __init x86_noinvpcid_setup(char *s) 166 { 167 /* noinvpcid doesn't accept parameters */ 168 if (s) 169 return -EINVAL; 170 171 /* do not emit a message if the feature is not present */ 172 if (!boot_cpu_has(X86_FEATURE_INVPCID)) 173 return 0; 174 175 setup_clear_cpu_cap(X86_FEATURE_INVPCID); 176 pr_info("noinvpcid: INVPCID feature disabled\n"); 177 return 0; 178 } 179 early_param("noinvpcid", x86_noinvpcid_setup); 180 181 #ifdef CONFIG_X86_32 182 static int cachesize_override = -1; 183 static int disable_x86_serial_nr = 1; 184 185 static int __init cachesize_setup(char *str) 186 { 187 get_option(&str, &cachesize_override); 188 return 1; 189 } 190 __setup("cachesize=", cachesize_setup); 191 192 static int __init x86_sep_setup(char *s) 193 { 194 setup_clear_cpu_cap(X86_FEATURE_SEP); 195 return 1; 196 } 197 __setup("nosep", x86_sep_setup); 198 199 /* Standard macro to see if a specific flag is changeable */ 200 static inline int flag_is_changeable_p(u32 flag) 201 { 202 u32 f1, f2; 203 204 /* 205 * Cyrix and IDT cpus allow disabling of CPUID 206 * so the code below may return different results 207 * when it is executed before and after enabling 208 * the CPUID. Add "volatile" to not allow gcc to 209 * optimize the subsequent calls to this function. 210 */ 211 asm volatile ("pushfl \n\t" 212 "pushfl \n\t" 213 "popl %0 \n\t" 214 "movl %0, %1 \n\t" 215 "xorl %2, %0 \n\t" 216 "pushl %0 \n\t" 217 "popfl \n\t" 218 "pushfl \n\t" 219 "popl %0 \n\t" 220 "popfl \n\t" 221 222 : "=&r" (f1), "=&r" (f2) 223 : "ir" (flag)); 224 225 return ((f1^f2) & flag) != 0; 226 } 227 228 /* Probe for the CPUID instruction */ 229 int have_cpuid_p(void) 230 { 231 return flag_is_changeable_p(X86_EFLAGS_ID); 232 } 233 234 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 235 { 236 unsigned long lo, hi; 237 238 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) 239 return; 240 241 /* Disable processor serial number: */ 242 243 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 244 lo |= 0x200000; 245 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); 246 247 pr_notice("CPU serial number disabled.\n"); 248 clear_cpu_cap(c, X86_FEATURE_PN); 249 250 /* Disabling the serial number may affect the cpuid level */ 251 c->cpuid_level = cpuid_eax(0); 252 } 253 254 static int __init x86_serial_nr_setup(char *s) 255 { 256 disable_x86_serial_nr = 0; 257 return 1; 258 } 259 __setup("serialnumber", x86_serial_nr_setup); 260 #else 261 static inline int flag_is_changeable_p(u32 flag) 262 { 263 return 1; 264 } 265 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) 266 { 267 } 268 #endif 269 270 static __init int setup_disable_smep(char *arg) 271 { 272 setup_clear_cpu_cap(X86_FEATURE_SMEP); 273 return 1; 274 } 275 __setup("nosmep", setup_disable_smep); 276 277 static __always_inline void setup_smep(struct cpuinfo_x86 *c) 278 { 279 if (cpu_has(c, X86_FEATURE_SMEP)) 280 cr4_set_bits(X86_CR4_SMEP); 281 } 282 283 static __init int setup_disable_smap(char *arg) 284 { 285 setup_clear_cpu_cap(X86_FEATURE_SMAP); 286 return 1; 287 } 288 __setup("nosmap", setup_disable_smap); 289 290 static __always_inline void setup_smap(struct cpuinfo_x86 *c) 291 { 292 unsigned long eflags = native_save_fl(); 293 294 /* This should have been cleared long ago */ 295 BUG_ON(eflags & X86_EFLAGS_AC); 296 297 if (cpu_has(c, X86_FEATURE_SMAP)) { 298 #ifdef CONFIG_X86_SMAP 299 cr4_set_bits(X86_CR4_SMAP); 300 #else 301 cr4_clear_bits(X86_CR4_SMAP); 302 #endif 303 } 304 } 305 306 /* 307 * Some CPU features depend on higher CPUID levels, which may not always 308 * be available due to CPUID level capping or broken virtualization 309 * software. Add those features to this table to auto-disable them. 310 */ 311 struct cpuid_dependent_feature { 312 u32 feature; 313 u32 level; 314 }; 315 316 static const struct cpuid_dependent_feature 317 cpuid_dependent_features[] = { 318 { X86_FEATURE_MWAIT, 0x00000005 }, 319 { X86_FEATURE_DCA, 0x00000009 }, 320 { X86_FEATURE_XSAVE, 0x0000000d }, 321 { 0, 0 } 322 }; 323 324 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) 325 { 326 const struct cpuid_dependent_feature *df; 327 328 for (df = cpuid_dependent_features; df->feature; df++) { 329 330 if (!cpu_has(c, df->feature)) 331 continue; 332 /* 333 * Note: cpuid_level is set to -1 if unavailable, but 334 * extended_extended_level is set to 0 if unavailable 335 * and the legitimate extended levels are all negative 336 * when signed; hence the weird messing around with 337 * signs here... 338 */ 339 if (!((s32)df->level < 0 ? 340 (u32)df->level > (u32)c->extended_cpuid_level : 341 (s32)df->level > (s32)c->cpuid_level)) 342 continue; 343 344 clear_cpu_cap(c, df->feature); 345 if (!warn) 346 continue; 347 348 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", 349 x86_cap_flag(df->feature), df->level); 350 } 351 } 352 353 /* 354 * Naming convention should be: <Name> [(<Codename>)] 355 * This table only is used unless init_<vendor>() below doesn't set it; 356 * in particular, if CPUID levels 0x80000002..4 are supported, this 357 * isn't used 358 */ 359 360 /* Look up CPU names by table lookup. */ 361 static const char *table_lookup_model(struct cpuinfo_x86 *c) 362 { 363 #ifdef CONFIG_X86_32 364 const struct legacy_cpu_model_info *info; 365 366 if (c->x86_model >= 16) 367 return NULL; /* Range check */ 368 369 if (!this_cpu) 370 return NULL; 371 372 info = this_cpu->legacy_models; 373 374 while (info->family) { 375 if (info->family == c->x86) 376 return info->model_names[c->x86_model]; 377 info++; 378 } 379 #endif 380 return NULL; /* Not found */ 381 } 382 383 __u32 cpu_caps_cleared[NCAPINTS]; 384 __u32 cpu_caps_set[NCAPINTS]; 385 386 void load_percpu_segment(int cpu) 387 { 388 #ifdef CONFIG_X86_32 389 loadsegment(fs, __KERNEL_PERCPU); 390 #else 391 loadsegment(gs, 0); 392 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); 393 #endif 394 load_stack_canary_segment(); 395 } 396 397 /* 398 * Current gdt points %fs at the "master" per-cpu area: after this, 399 * it's on the real one. 400 */ 401 void switch_to_new_gdt(int cpu) 402 { 403 struct desc_ptr gdt_descr; 404 405 gdt_descr.address = (long)get_cpu_gdt_table(cpu); 406 gdt_descr.size = GDT_SIZE - 1; 407 load_gdt(&gdt_descr); 408 /* Reload the per-cpu base */ 409 410 load_percpu_segment(cpu); 411 } 412 413 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; 414 415 static void get_model_name(struct cpuinfo_x86 *c) 416 { 417 unsigned int *v; 418 char *p, *q, *s; 419 420 if (c->extended_cpuid_level < 0x80000004) 421 return; 422 423 v = (unsigned int *)c->x86_model_id; 424 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); 425 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); 426 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); 427 c->x86_model_id[48] = 0; 428 429 /* Trim whitespace */ 430 p = q = s = &c->x86_model_id[0]; 431 432 while (*p == ' ') 433 p++; 434 435 while (*p) { 436 /* Note the last non-whitespace index */ 437 if (!isspace(*p)) 438 s = q; 439 440 *q++ = *p++; 441 } 442 443 *(s + 1) = '\0'; 444 } 445 446 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) 447 { 448 unsigned int n, dummy, ebx, ecx, edx, l2size; 449 450 n = c->extended_cpuid_level; 451 452 if (n >= 0x80000005) { 453 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); 454 c->x86_cache_size = (ecx>>24) + (edx>>24); 455 #ifdef CONFIG_X86_64 456 /* On K8 L1 TLB is inclusive, so don't count it */ 457 c->x86_tlbsize = 0; 458 #endif 459 } 460 461 if (n < 0x80000006) /* Some chips just has a large L1. */ 462 return; 463 464 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); 465 l2size = ecx >> 16; 466 467 #ifdef CONFIG_X86_64 468 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); 469 #else 470 /* do processor-specific cache resizing */ 471 if (this_cpu->legacy_cache_size) 472 l2size = this_cpu->legacy_cache_size(c, l2size); 473 474 /* Allow user to override all this if necessary. */ 475 if (cachesize_override != -1) 476 l2size = cachesize_override; 477 478 if (l2size == 0) 479 return; /* Again, no L2 cache is possible */ 480 #endif 481 482 c->x86_cache_size = l2size; 483 } 484 485 u16 __read_mostly tlb_lli_4k[NR_INFO]; 486 u16 __read_mostly tlb_lli_2m[NR_INFO]; 487 u16 __read_mostly tlb_lli_4m[NR_INFO]; 488 u16 __read_mostly tlb_lld_4k[NR_INFO]; 489 u16 __read_mostly tlb_lld_2m[NR_INFO]; 490 u16 __read_mostly tlb_lld_4m[NR_INFO]; 491 u16 __read_mostly tlb_lld_1g[NR_INFO]; 492 493 static void cpu_detect_tlb(struct cpuinfo_x86 *c) 494 { 495 if (this_cpu->c_detect_tlb) 496 this_cpu->c_detect_tlb(c); 497 498 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", 499 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], 500 tlb_lli_4m[ENTRIES]); 501 502 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", 503 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], 504 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); 505 } 506 507 void detect_ht(struct cpuinfo_x86 *c) 508 { 509 #ifdef CONFIG_SMP 510 u32 eax, ebx, ecx, edx; 511 int index_msb, core_bits; 512 static bool printed; 513 514 if (!cpu_has(c, X86_FEATURE_HT)) 515 return; 516 517 if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) 518 goto out; 519 520 if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) 521 return; 522 523 cpuid(1, &eax, &ebx, &ecx, &edx); 524 525 smp_num_siblings = (ebx & 0xff0000) >> 16; 526 527 if (smp_num_siblings == 1) { 528 pr_info_once("CPU0: Hyper-Threading is disabled\n"); 529 goto out; 530 } 531 532 if (smp_num_siblings <= 1) 533 goto out; 534 535 index_msb = get_count_order(smp_num_siblings); 536 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); 537 538 smp_num_siblings = smp_num_siblings / c->x86_max_cores; 539 540 index_msb = get_count_order(smp_num_siblings); 541 542 core_bits = get_count_order(c->x86_max_cores); 543 544 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & 545 ((1 << core_bits) - 1); 546 547 out: 548 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { 549 pr_info("CPU: Physical Processor ID: %d\n", 550 c->phys_proc_id); 551 pr_info("CPU: Processor Core ID: %d\n", 552 c->cpu_core_id); 553 printed = 1; 554 } 555 #endif 556 } 557 558 static void get_cpu_vendor(struct cpuinfo_x86 *c) 559 { 560 char *v = c->x86_vendor_id; 561 int i; 562 563 for (i = 0; i < X86_VENDOR_NUM; i++) { 564 if (!cpu_devs[i]) 565 break; 566 567 if (!strcmp(v, cpu_devs[i]->c_ident[0]) || 568 (cpu_devs[i]->c_ident[1] && 569 !strcmp(v, cpu_devs[i]->c_ident[1]))) { 570 571 this_cpu = cpu_devs[i]; 572 c->x86_vendor = this_cpu->c_x86_vendor; 573 return; 574 } 575 } 576 577 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ 578 "CPU: Your system may be unstable.\n", v); 579 580 c->x86_vendor = X86_VENDOR_UNKNOWN; 581 this_cpu = &default_cpu; 582 } 583 584 void cpu_detect(struct cpuinfo_x86 *c) 585 { 586 /* Get vendor name */ 587 cpuid(0x00000000, (unsigned int *)&c->cpuid_level, 588 (unsigned int *)&c->x86_vendor_id[0], 589 (unsigned int *)&c->x86_vendor_id[8], 590 (unsigned int *)&c->x86_vendor_id[4]); 591 592 c->x86 = 4; 593 /* Intel-defined flags: level 0x00000001 */ 594 if (c->cpuid_level >= 0x00000001) { 595 u32 junk, tfms, cap0, misc; 596 597 cpuid(0x00000001, &tfms, &misc, &junk, &cap0); 598 c->x86 = x86_family(tfms); 599 c->x86_model = x86_model(tfms); 600 c->x86_mask = x86_stepping(tfms); 601 602 if (cap0 & (1<<19)) { 603 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; 604 c->x86_cache_alignment = c->x86_clflush_size; 605 } 606 } 607 } 608 609 void get_cpu_cap(struct cpuinfo_x86 *c) 610 { 611 u32 eax, ebx, ecx, edx; 612 613 /* Intel-defined flags: level 0x00000001 */ 614 if (c->cpuid_level >= 0x00000001) { 615 cpuid(0x00000001, &eax, &ebx, &ecx, &edx); 616 617 c->x86_capability[CPUID_1_ECX] = ecx; 618 c->x86_capability[CPUID_1_EDX] = edx; 619 } 620 621 /* Additional Intel-defined flags: level 0x00000007 */ 622 if (c->cpuid_level >= 0x00000007) { 623 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); 624 625 c->x86_capability[CPUID_7_0_EBX] = ebx; 626 627 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); 628 } 629 630 /* Extended state features: level 0x0000000d */ 631 if (c->cpuid_level >= 0x0000000d) { 632 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); 633 634 c->x86_capability[CPUID_D_1_EAX] = eax; 635 } 636 637 /* Additional Intel-defined flags: level 0x0000000F */ 638 if (c->cpuid_level >= 0x0000000F) { 639 640 /* QoS sub-leaf, EAX=0Fh, ECX=0 */ 641 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); 642 c->x86_capability[CPUID_F_0_EDX] = edx; 643 644 if (cpu_has(c, X86_FEATURE_CQM_LLC)) { 645 /* will be overridden if occupancy monitoring exists */ 646 c->x86_cache_max_rmid = ebx; 647 648 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 649 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); 650 c->x86_capability[CPUID_F_1_EDX] = edx; 651 652 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) { 653 c->x86_cache_max_rmid = ecx; 654 c->x86_cache_occ_scale = ebx; 655 } 656 } else { 657 c->x86_cache_max_rmid = -1; 658 c->x86_cache_occ_scale = -1; 659 } 660 } 661 662 /* AMD-defined flags: level 0x80000001 */ 663 eax = cpuid_eax(0x80000000); 664 c->extended_cpuid_level = eax; 665 666 if ((eax & 0xffff0000) == 0x80000000) { 667 if (eax >= 0x80000001) { 668 cpuid(0x80000001, &eax, &ebx, &ecx, &edx); 669 670 c->x86_capability[CPUID_8000_0001_ECX] = ecx; 671 c->x86_capability[CPUID_8000_0001_EDX] = edx; 672 } 673 } 674 675 if (c->extended_cpuid_level >= 0x80000008) { 676 cpuid(0x80000008, &eax, &ebx, &ecx, &edx); 677 678 c->x86_virt_bits = (eax >> 8) & 0xff; 679 c->x86_phys_bits = eax & 0xff; 680 c->x86_capability[CPUID_8000_0008_EBX] = ebx; 681 } 682 #ifdef CONFIG_X86_32 683 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) 684 c->x86_phys_bits = 36; 685 #endif 686 687 if (c->extended_cpuid_level >= 0x80000007) 688 c->x86_power = cpuid_edx(0x80000007); 689 690 if (c->extended_cpuid_level >= 0x8000000a) 691 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); 692 693 init_scattered_cpuid_features(c); 694 } 695 696 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 697 { 698 #ifdef CONFIG_X86_32 699 int i; 700 701 /* 702 * First of all, decide if this is a 486 or higher 703 * It's a 486 if we can modify the AC flag 704 */ 705 if (flag_is_changeable_p(X86_EFLAGS_AC)) 706 c->x86 = 4; 707 else 708 c->x86 = 3; 709 710 for (i = 0; i < X86_VENDOR_NUM; i++) 711 if (cpu_devs[i] && cpu_devs[i]->c_identify) { 712 c->x86_vendor_id[0] = 0; 713 cpu_devs[i]->c_identify(c); 714 if (c->x86_vendor_id[0]) { 715 get_cpu_vendor(c); 716 break; 717 } 718 } 719 #endif 720 } 721 722 /* 723 * Do minimum CPU detection early. 724 * Fields really needed: vendor, cpuid_level, family, model, mask, 725 * cache alignment. 726 * The others are not touched to avoid unwanted side effects. 727 * 728 * WARNING: this function is only called on the BP. Don't add code here 729 * that is supposed to run on all CPUs. 730 */ 731 static void __init early_identify_cpu(struct cpuinfo_x86 *c) 732 { 733 #ifdef CONFIG_X86_64 734 c->x86_clflush_size = 64; 735 c->x86_phys_bits = 36; 736 c->x86_virt_bits = 48; 737 #else 738 c->x86_clflush_size = 32; 739 c->x86_phys_bits = 32; 740 c->x86_virt_bits = 32; 741 #endif 742 c->x86_cache_alignment = c->x86_clflush_size; 743 744 memset(&c->x86_capability, 0, sizeof c->x86_capability); 745 c->extended_cpuid_level = 0; 746 747 if (!have_cpuid_p()) 748 identify_cpu_without_cpuid(c); 749 750 /* cyrix could have cpuid enabled via c_identify()*/ 751 if (!have_cpuid_p()) 752 return; 753 754 cpu_detect(c); 755 get_cpu_vendor(c); 756 get_cpu_cap(c); 757 758 if (this_cpu->c_early_init) 759 this_cpu->c_early_init(c); 760 761 c->cpu_index = 0; 762 filter_cpuid_features(c, false); 763 764 if (this_cpu->c_bsp_init) 765 this_cpu->c_bsp_init(c); 766 767 setup_force_cpu_cap(X86_FEATURE_ALWAYS); 768 fpu__init_system(c); 769 } 770 771 void __init early_cpu_init(void) 772 { 773 const struct cpu_dev *const *cdev; 774 int count = 0; 775 776 #ifdef CONFIG_PROCESSOR_SELECT 777 pr_info("KERNEL supported cpus:\n"); 778 #endif 779 780 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { 781 const struct cpu_dev *cpudev = *cdev; 782 783 if (count >= X86_VENDOR_NUM) 784 break; 785 cpu_devs[count] = cpudev; 786 count++; 787 788 #ifdef CONFIG_PROCESSOR_SELECT 789 { 790 unsigned int j; 791 792 for (j = 0; j < 2; j++) { 793 if (!cpudev->c_ident[j]) 794 continue; 795 pr_info(" %s %s\n", cpudev->c_vendor, 796 cpudev->c_ident[j]); 797 } 798 } 799 #endif 800 } 801 early_identify_cpu(&boot_cpu_data); 802 } 803 804 /* 805 * The NOPL instruction is supposed to exist on all CPUs of family >= 6; 806 * unfortunately, that's not true in practice because of early VIA 807 * chips and (more importantly) broken virtualizers that are not easy 808 * to detect. In the latter case it doesn't even *fail* reliably, so 809 * probing for it doesn't even work. Disable it completely on 32-bit 810 * unless we can find a reliable way to detect all the broken cases. 811 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). 812 */ 813 static void detect_nopl(struct cpuinfo_x86 *c) 814 { 815 #ifdef CONFIG_X86_32 816 clear_cpu_cap(c, X86_FEATURE_NOPL); 817 #else 818 set_cpu_cap(c, X86_FEATURE_NOPL); 819 #endif 820 821 /* 822 * ESPFIX is a strange bug. All real CPUs have it. Paravirt 823 * systems that run Linux at CPL > 0 may or may not have the 824 * issue, but, even if they have the issue, there's absolutely 825 * nothing we can do about it because we can't use the real IRET 826 * instruction. 827 * 828 * NB: For the time being, only 32-bit kernels support 829 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose 830 * whether to apply espfix using paravirt hooks. If any 831 * non-paravirt system ever shows up that does *not* have the 832 * ESPFIX issue, we can change this. 833 */ 834 #ifdef CONFIG_X86_32 835 #ifdef CONFIG_PARAVIRT 836 do { 837 extern void native_iret(void); 838 if (pv_cpu_ops.iret == native_iret) 839 set_cpu_bug(c, X86_BUG_ESPFIX); 840 } while (0); 841 #else 842 set_cpu_bug(c, X86_BUG_ESPFIX); 843 #endif 844 #endif 845 } 846 847 static void generic_identify(struct cpuinfo_x86 *c) 848 { 849 c->extended_cpuid_level = 0; 850 851 if (!have_cpuid_p()) 852 identify_cpu_without_cpuid(c); 853 854 /* cyrix could have cpuid enabled via c_identify()*/ 855 if (!have_cpuid_p()) 856 return; 857 858 cpu_detect(c); 859 860 get_cpu_vendor(c); 861 862 get_cpu_cap(c); 863 864 if (c->cpuid_level >= 0x00000001) { 865 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; 866 #ifdef CONFIG_X86_32 867 # ifdef CONFIG_SMP 868 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 869 # else 870 c->apicid = c->initial_apicid; 871 # endif 872 #endif 873 c->phys_proc_id = c->initial_apicid; 874 } 875 876 get_model_name(c); /* Default name */ 877 878 detect_nopl(c); 879 } 880 881 static void x86_init_cache_qos(struct cpuinfo_x86 *c) 882 { 883 /* 884 * The heavy lifting of max_rmid and cache_occ_scale are handled 885 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu 886 * in case CQM bits really aren't there in this CPU. 887 */ 888 if (c != &boot_cpu_data) { 889 boot_cpu_data.x86_cache_max_rmid = 890 min(boot_cpu_data.x86_cache_max_rmid, 891 c->x86_cache_max_rmid); 892 } 893 } 894 895 /* 896 * This does the hard work of actually picking apart the CPU stuff... 897 */ 898 static void identify_cpu(struct cpuinfo_x86 *c) 899 { 900 int i; 901 902 c->loops_per_jiffy = loops_per_jiffy; 903 c->x86_cache_size = -1; 904 c->x86_vendor = X86_VENDOR_UNKNOWN; 905 c->x86_model = c->x86_mask = 0; /* So far unknown... */ 906 c->x86_vendor_id[0] = '\0'; /* Unset */ 907 c->x86_model_id[0] = '\0'; /* Unset */ 908 c->x86_max_cores = 1; 909 c->x86_coreid_bits = 0; 910 #ifdef CONFIG_X86_64 911 c->x86_clflush_size = 64; 912 c->x86_phys_bits = 36; 913 c->x86_virt_bits = 48; 914 #else 915 c->cpuid_level = -1; /* CPUID not detected */ 916 c->x86_clflush_size = 32; 917 c->x86_phys_bits = 32; 918 c->x86_virt_bits = 32; 919 #endif 920 c->x86_cache_alignment = c->x86_clflush_size; 921 memset(&c->x86_capability, 0, sizeof c->x86_capability); 922 923 generic_identify(c); 924 925 if (this_cpu->c_identify) 926 this_cpu->c_identify(c); 927 928 /* Clear/Set all flags overriden by options, after probe */ 929 for (i = 0; i < NCAPINTS; i++) { 930 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 931 c->x86_capability[i] |= cpu_caps_set[i]; 932 } 933 934 #ifdef CONFIG_X86_64 935 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); 936 #endif 937 938 /* 939 * Vendor-specific initialization. In this section we 940 * canonicalize the feature flags, meaning if there are 941 * features a certain CPU supports which CPUID doesn't 942 * tell us, CPUID claiming incorrect flags, or other bugs, 943 * we handle them here. 944 * 945 * At the end of this section, c->x86_capability better 946 * indicate the features this CPU genuinely supports! 947 */ 948 if (this_cpu->c_init) 949 this_cpu->c_init(c); 950 951 /* Disable the PN if appropriate */ 952 squash_the_stupid_serial_number(c); 953 954 /* Set up SMEP/SMAP */ 955 setup_smep(c); 956 setup_smap(c); 957 958 /* 959 * The vendor-specific functions might have changed features. 960 * Now we do "generic changes." 961 */ 962 963 /* Filter out anything that depends on CPUID levels we don't have */ 964 filter_cpuid_features(c, true); 965 966 /* If the model name is still unset, do table lookup. */ 967 if (!c->x86_model_id[0]) { 968 const char *p; 969 p = table_lookup_model(c); 970 if (p) 971 strcpy(c->x86_model_id, p); 972 else 973 /* Last resort... */ 974 sprintf(c->x86_model_id, "%02x/%02x", 975 c->x86, c->x86_model); 976 } 977 978 #ifdef CONFIG_X86_64 979 detect_ht(c); 980 #endif 981 982 init_hypervisor(c); 983 x86_init_rdrand(c); 984 x86_init_cache_qos(c); 985 986 /* 987 * Clear/Set all flags overriden by options, need do it 988 * before following smp all cpus cap AND. 989 */ 990 for (i = 0; i < NCAPINTS; i++) { 991 c->x86_capability[i] &= ~cpu_caps_cleared[i]; 992 c->x86_capability[i] |= cpu_caps_set[i]; 993 } 994 995 /* 996 * On SMP, boot_cpu_data holds the common feature set between 997 * all CPUs; so make sure that we indicate which features are 998 * common between the CPUs. The first time this routine gets 999 * executed, c == &boot_cpu_data. 1000 */ 1001 if (c != &boot_cpu_data) { 1002 /* AND the already accumulated flags with these */ 1003 for (i = 0; i < NCAPINTS; i++) 1004 boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; 1005 1006 /* OR, i.e. replicate the bug flags */ 1007 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) 1008 c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; 1009 } 1010 1011 /* Init Machine Check Exception if available. */ 1012 mcheck_cpu_init(c); 1013 1014 select_idle_routine(c); 1015 1016 #ifdef CONFIG_NUMA 1017 numa_add_cpu(smp_processor_id()); 1018 #endif 1019 /* The boot/hotplug time assigment got cleared, restore it */ 1020 c->logical_proc_id = topology_phys_to_logical_pkg(c->phys_proc_id); 1021 } 1022 1023 /* 1024 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions 1025 * on 32-bit kernels: 1026 */ 1027 #ifdef CONFIG_X86_32 1028 void enable_sep_cpu(void) 1029 { 1030 struct tss_struct *tss; 1031 int cpu; 1032 1033 cpu = get_cpu(); 1034 tss = &per_cpu(cpu_tss, cpu); 1035 1036 if (!boot_cpu_has(X86_FEATURE_SEP)) 1037 goto out; 1038 1039 /* 1040 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- 1041 * see the big comment in struct x86_hw_tss's definition. 1042 */ 1043 1044 tss->x86_tss.ss1 = __KERNEL_CS; 1045 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 1046 1047 wrmsr(MSR_IA32_SYSENTER_ESP, 1048 (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack), 1049 0); 1050 1051 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 1052 1053 out: 1054 put_cpu(); 1055 } 1056 #endif 1057 1058 void __init identify_boot_cpu(void) 1059 { 1060 identify_cpu(&boot_cpu_data); 1061 init_amd_e400_c1e_mask(); 1062 #ifdef CONFIG_X86_32 1063 sysenter_setup(); 1064 enable_sep_cpu(); 1065 #endif 1066 cpu_detect_tlb(&boot_cpu_data); 1067 } 1068 1069 void identify_secondary_cpu(struct cpuinfo_x86 *c) 1070 { 1071 BUG_ON(c == &boot_cpu_data); 1072 identify_cpu(c); 1073 #ifdef CONFIG_X86_32 1074 enable_sep_cpu(); 1075 #endif 1076 mtrr_ap_init(); 1077 } 1078 1079 struct msr_range { 1080 unsigned min; 1081 unsigned max; 1082 }; 1083 1084 static const struct msr_range msr_range_array[] = { 1085 { 0x00000000, 0x00000418}, 1086 { 0xc0000000, 0xc000040b}, 1087 { 0xc0010000, 0xc0010142}, 1088 { 0xc0011000, 0xc001103b}, 1089 }; 1090 1091 static void __print_cpu_msr(void) 1092 { 1093 unsigned index_min, index_max; 1094 unsigned index; 1095 u64 val; 1096 int i; 1097 1098 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { 1099 index_min = msr_range_array[i].min; 1100 index_max = msr_range_array[i].max; 1101 1102 for (index = index_min; index < index_max; index++) { 1103 if (rdmsrl_safe(index, &val)) 1104 continue; 1105 pr_info(" MSR%08x: %016llx\n", index, val); 1106 } 1107 } 1108 } 1109 1110 static int show_msr; 1111 1112 static __init int setup_show_msr(char *arg) 1113 { 1114 int num; 1115 1116 get_option(&arg, &num); 1117 1118 if (num > 0) 1119 show_msr = num; 1120 return 1; 1121 } 1122 __setup("show_msr=", setup_show_msr); 1123 1124 static __init int setup_noclflush(char *arg) 1125 { 1126 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); 1127 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); 1128 return 1; 1129 } 1130 __setup("noclflush", setup_noclflush); 1131 1132 void print_cpu_info(struct cpuinfo_x86 *c) 1133 { 1134 const char *vendor = NULL; 1135 1136 if (c->x86_vendor < X86_VENDOR_NUM) { 1137 vendor = this_cpu->c_vendor; 1138 } else { 1139 if (c->cpuid_level >= 0) 1140 vendor = c->x86_vendor_id; 1141 } 1142 1143 if (vendor && !strstr(c->x86_model_id, vendor)) 1144 pr_cont("%s ", vendor); 1145 1146 if (c->x86_model_id[0]) 1147 pr_cont("%s", c->x86_model_id); 1148 else 1149 pr_cont("%d86", c->x86); 1150 1151 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); 1152 1153 if (c->x86_mask || c->cpuid_level >= 0) 1154 pr_cont(", stepping: 0x%x)\n", c->x86_mask); 1155 else 1156 pr_cont(")\n"); 1157 1158 print_cpu_msr(c); 1159 } 1160 1161 void print_cpu_msr(struct cpuinfo_x86 *c) 1162 { 1163 if (c->cpu_index < show_msr) 1164 __print_cpu_msr(); 1165 } 1166 1167 static __init int setup_disablecpuid(char *arg) 1168 { 1169 int bit; 1170 1171 if (get_option(&arg, &bit) && bit < NCAPINTS*32) 1172 setup_clear_cpu_cap(bit); 1173 else 1174 return 0; 1175 1176 return 1; 1177 } 1178 __setup("clearcpuid=", setup_disablecpuid); 1179 1180 #ifdef CONFIG_X86_64 1181 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; 1182 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, 1183 (unsigned long) debug_idt_table }; 1184 1185 DEFINE_PER_CPU_FIRST(union irq_stack_union, 1186 irq_stack_union) __aligned(PAGE_SIZE) __visible; 1187 1188 /* 1189 * The following percpu variables are hot. Align current_task to 1190 * cacheline size such that they fall in the same cacheline. 1191 */ 1192 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = 1193 &init_task; 1194 EXPORT_PER_CPU_SYMBOL(current_task); 1195 1196 DEFINE_PER_CPU(char *, irq_stack_ptr) = 1197 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; 1198 1199 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; 1200 1201 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1202 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1203 1204 /* 1205 * Special IST stacks which the CPU switches to when it calls 1206 * an IST-marked descriptor entry. Up to 7 stacks (hardware 1207 * limit), all of them are 4K, except the debug stack which 1208 * is 8K. 1209 */ 1210 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { 1211 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, 1212 [DEBUG_STACK - 1] = DEBUG_STKSZ 1213 }; 1214 1215 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks 1216 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); 1217 1218 /* May not be marked __init: used by software suspend */ 1219 void syscall_init(void) 1220 { 1221 /* 1222 * LSTAR and STAR live in a bit strange symbiosis. 1223 * They both write to the same internal register. STAR allows to 1224 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. 1225 */ 1226 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); 1227 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 1228 1229 #ifdef CONFIG_IA32_EMULATION 1230 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); 1231 /* 1232 * This only works on Intel CPUs. 1233 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 1234 * This does not cause SYSENTER to jump to the wrong location, because 1235 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 1236 */ 1237 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 1238 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1239 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 1240 #else 1241 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); 1242 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 1243 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 1244 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 1245 #endif 1246 1247 /* Flags to clear on syscall */ 1248 wrmsrl(MSR_SYSCALL_MASK, 1249 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| 1250 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); 1251 } 1252 1253 /* 1254 * Copies of the original ist values from the tss are only accessed during 1255 * debugging, no special alignment required. 1256 */ 1257 DEFINE_PER_CPU(struct orig_ist, orig_ist); 1258 1259 static DEFINE_PER_CPU(unsigned long, debug_stack_addr); 1260 DEFINE_PER_CPU(int, debug_stack_usage); 1261 1262 int is_debug_stack(unsigned long addr) 1263 { 1264 return __this_cpu_read(debug_stack_usage) || 1265 (addr <= __this_cpu_read(debug_stack_addr) && 1266 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); 1267 } 1268 NOKPROBE_SYMBOL(is_debug_stack); 1269 1270 DEFINE_PER_CPU(u32, debug_idt_ctr); 1271 1272 void debug_stack_set_zero(void) 1273 { 1274 this_cpu_inc(debug_idt_ctr); 1275 load_current_idt(); 1276 } 1277 NOKPROBE_SYMBOL(debug_stack_set_zero); 1278 1279 void debug_stack_reset(void) 1280 { 1281 if (WARN_ON(!this_cpu_read(debug_idt_ctr))) 1282 return; 1283 if (this_cpu_dec_return(debug_idt_ctr) == 0) 1284 load_current_idt(); 1285 } 1286 NOKPROBE_SYMBOL(debug_stack_reset); 1287 1288 #else /* CONFIG_X86_64 */ 1289 1290 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; 1291 EXPORT_PER_CPU_SYMBOL(current_task); 1292 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; 1293 EXPORT_PER_CPU_SYMBOL(__preempt_count); 1294 1295 /* 1296 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find 1297 * the top of the kernel stack. Use an extra percpu variable to track the 1298 * top of the kernel stack directly. 1299 */ 1300 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = 1301 (unsigned long)&init_thread_union + THREAD_SIZE; 1302 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); 1303 1304 #ifdef CONFIG_CC_STACKPROTECTOR 1305 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 1306 #endif 1307 1308 #endif /* CONFIG_X86_64 */ 1309 1310 /* 1311 * Clear all 6 debug registers: 1312 */ 1313 static void clear_all_debug_regs(void) 1314 { 1315 int i; 1316 1317 for (i = 0; i < 8; i++) { 1318 /* Ignore db4, db5 */ 1319 if ((i == 4) || (i == 5)) 1320 continue; 1321 1322 set_debugreg(0, i); 1323 } 1324 } 1325 1326 #ifdef CONFIG_KGDB 1327 /* 1328 * Restore debug regs if using kgdbwait and you have a kernel debugger 1329 * connection established. 1330 */ 1331 static void dbg_restore_debug_regs(void) 1332 { 1333 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) 1334 arch_kgdb_ops.correct_hw_break(); 1335 } 1336 #else /* ! CONFIG_KGDB */ 1337 #define dbg_restore_debug_regs() 1338 #endif /* ! CONFIG_KGDB */ 1339 1340 static void wait_for_master_cpu(int cpu) 1341 { 1342 #ifdef CONFIG_SMP 1343 /* 1344 * wait for ACK from master CPU before continuing 1345 * with AP initialization 1346 */ 1347 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 1348 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 1349 cpu_relax(); 1350 #endif 1351 } 1352 1353 /* 1354 * cpu_init() initializes state that is per-CPU. Some data is already 1355 * initialized (naturally) in the bootstrap process, such as the GDT 1356 * and IDT. We reload them nevertheless, this function acts as a 1357 * 'CPU state barrier', nothing should get across. 1358 * A lot of state is already set up in PDA init for 64 bit 1359 */ 1360 #ifdef CONFIG_X86_64 1361 1362 void cpu_init(void) 1363 { 1364 struct orig_ist *oist; 1365 struct task_struct *me; 1366 struct tss_struct *t; 1367 unsigned long v; 1368 int cpu = stack_smp_processor_id(); 1369 int i; 1370 1371 wait_for_master_cpu(cpu); 1372 1373 /* 1374 * Initialize the CR4 shadow before doing anything that could 1375 * try to read it. 1376 */ 1377 cr4_init_shadow(); 1378 1379 /* 1380 * Load microcode on this cpu if a valid microcode is available. 1381 * This is early microcode loading procedure. 1382 */ 1383 load_ucode_ap(); 1384 1385 t = &per_cpu(cpu_tss, cpu); 1386 oist = &per_cpu(orig_ist, cpu); 1387 1388 #ifdef CONFIG_NUMA 1389 if (this_cpu_read(numa_node) == 0 && 1390 early_cpu_to_node(cpu) != NUMA_NO_NODE) 1391 set_numa_node(early_cpu_to_node(cpu)); 1392 #endif 1393 1394 me = current; 1395 1396 pr_debug("Initializing CPU#%d\n", cpu); 1397 1398 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1399 1400 /* 1401 * Initialize the per-CPU GDT with the boot GDT, 1402 * and set up the GDT descriptor: 1403 */ 1404 1405 switch_to_new_gdt(cpu); 1406 loadsegment(fs, 0); 1407 1408 load_current_idt(); 1409 1410 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 1411 syscall_init(); 1412 1413 wrmsrl(MSR_FS_BASE, 0); 1414 wrmsrl(MSR_KERNEL_GS_BASE, 0); 1415 barrier(); 1416 1417 x86_configure_nx(); 1418 x2apic_setup(); 1419 1420 /* 1421 * set up and load the per-CPU TSS 1422 */ 1423 if (!oist->ist[0]) { 1424 char *estacks = per_cpu(exception_stacks, cpu); 1425 1426 for (v = 0; v < N_EXCEPTION_STACKS; v++) { 1427 estacks += exception_stack_sizes[v]; 1428 oist->ist[v] = t->x86_tss.ist[v] = 1429 (unsigned long)estacks; 1430 if (v == DEBUG_STACK-1) 1431 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; 1432 } 1433 } 1434 1435 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1436 1437 /* 1438 * <= is required because the CPU will access up to 1439 * 8 bits beyond the end of the IO permission bitmap. 1440 */ 1441 for (i = 0; i <= IO_BITMAP_LONGS; i++) 1442 t->io_bitmap[i] = ~0UL; 1443 1444 atomic_inc(&init_mm.mm_count); 1445 me->active_mm = &init_mm; 1446 BUG_ON(me->mm); 1447 enter_lazy_tlb(&init_mm, me); 1448 1449 load_sp0(t, ¤t->thread); 1450 set_tss_desc(cpu, t); 1451 load_TR_desc(); 1452 load_mm_ldt(&init_mm); 1453 1454 clear_all_debug_regs(); 1455 dbg_restore_debug_regs(); 1456 1457 fpu__init_cpu(); 1458 1459 if (is_uv_system()) 1460 uv_cpu_init(); 1461 } 1462 1463 #else 1464 1465 void cpu_init(void) 1466 { 1467 int cpu = smp_processor_id(); 1468 struct task_struct *curr = current; 1469 struct tss_struct *t = &per_cpu(cpu_tss, cpu); 1470 struct thread_struct *thread = &curr->thread; 1471 1472 wait_for_master_cpu(cpu); 1473 1474 /* 1475 * Initialize the CR4 shadow before doing anything that could 1476 * try to read it. 1477 */ 1478 cr4_init_shadow(); 1479 1480 show_ucode_info_early(); 1481 1482 pr_info("Initializing CPU#%d\n", cpu); 1483 1484 if (cpu_feature_enabled(X86_FEATURE_VME) || 1485 cpu_has_tsc || 1486 boot_cpu_has(X86_FEATURE_DE)) 1487 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); 1488 1489 load_current_idt(); 1490 switch_to_new_gdt(cpu); 1491 1492 /* 1493 * Set up and load the per-CPU TSS and LDT 1494 */ 1495 atomic_inc(&init_mm.mm_count); 1496 curr->active_mm = &init_mm; 1497 BUG_ON(curr->mm); 1498 enter_lazy_tlb(&init_mm, curr); 1499 1500 load_sp0(t, thread); 1501 set_tss_desc(cpu, t); 1502 load_TR_desc(); 1503 load_mm_ldt(&init_mm); 1504 1505 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 1506 1507 #ifdef CONFIG_DOUBLEFAULT 1508 /* Set up doublefault TSS pointer in the GDT */ 1509 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); 1510 #endif 1511 1512 clear_all_debug_regs(); 1513 dbg_restore_debug_regs(); 1514 1515 fpu__init_cpu(); 1516 } 1517 #endif 1518 1519 static void bsp_resume(void) 1520 { 1521 if (this_cpu->c_bsp_resume) 1522 this_cpu->c_bsp_resume(&boot_cpu_data); 1523 } 1524 1525 static struct syscore_ops cpu_syscore_ops = { 1526 .resume = bsp_resume, 1527 }; 1528 1529 static int __init init_cpu_syscore(void) 1530 { 1531 register_syscore_ops(&cpu_syscore_ops); 1532 return 0; 1533 } 1534 core_initcall(init_cpu_syscore); 1535