1 #ifndef _ASM_X86_PROCESSOR_H 2 #define _ASM_X86_PROCESSOR_H 3 4 #include <asm/processor-flags.h> 5 6 /* Forward declaration, a strange C thing */ 7 struct task_struct; 8 struct mm_struct; 9 struct vm86; 10 11 #include <asm/math_emu.h> 12 #include <asm/segment.h> 13 #include <asm/types.h> 14 #include <uapi/asm/sigcontext.h> 15 #include <asm/current.h> 16 #include <asm/cpufeatures.h> 17 #include <asm/page.h> 18 #include <asm/pgtable_types.h> 19 #include <asm/percpu.h> 20 #include <asm/msr.h> 21 #include <asm/desc_defs.h> 22 #include <asm/nops.h> 23 #include <asm/special_insns.h> 24 #include <asm/fpu/types.h> 25 26 #include <linux/personality.h> 27 #include <linux/cache.h> 28 #include <linux/threads.h> 29 #include <linux/math64.h> 30 #include <linux/err.h> 31 #include <linux/irqflags.h> 32 33 /* 34 * We handle most unaligned accesses in hardware. On the other hand 35 * unaligned DMA can be quite expensive on some Nehalem processors. 36 * 37 * Based on this we disable the IP header alignment in network drivers. 38 */ 39 #define NET_IP_ALIGN 0 40 41 #define HBP_NUM 4 42 /* 43 * Default implementation of macro that returns current 44 * instruction pointer ("program counter"). 45 */ 46 static inline void *current_text_addr(void) 47 { 48 void *pc; 49 50 asm volatile("mov $1f, %0; 1:":"=r" (pc)); 51 52 return pc; 53 } 54 55 /* 56 * These alignment constraints are for performance in the vSMP case, 57 * but in the task_struct case we must also meet hardware imposed 58 * alignment requirements of the FPU state: 59 */ 60 #ifdef CONFIG_X86_VSMP 61 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) 62 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) 63 #else 64 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) 65 # define ARCH_MIN_MMSTRUCT_ALIGN 0 66 #endif 67 68 enum tlb_infos { 69 ENTRIES, 70 NR_INFO 71 }; 72 73 extern u16 __read_mostly tlb_lli_4k[NR_INFO]; 74 extern u16 __read_mostly tlb_lli_2m[NR_INFO]; 75 extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 76 extern u16 __read_mostly tlb_lld_4k[NR_INFO]; 77 extern u16 __read_mostly tlb_lld_2m[NR_INFO]; 78 extern u16 __read_mostly tlb_lld_4m[NR_INFO]; 79 extern u16 __read_mostly tlb_lld_1g[NR_INFO]; 80 81 /* 82 * CPU type and hardware bug flags. Kept separately for each CPU. 83 * Members of this structure are referenced in head.S, so think twice 84 * before touching them. [mj] 85 */ 86 87 struct cpuinfo_x86 { 88 __u8 x86; /* CPU family */ 89 __u8 x86_vendor; /* CPU vendor */ 90 __u8 x86_model; 91 __u8 x86_mask; 92 #ifdef CONFIG_X86_32 93 char wp_works_ok; /* It doesn't on 386's */ 94 95 /* Problems on some 486Dx4's and old 386's: */ 96 char rfu; 97 char pad0; 98 char pad1; 99 #else 100 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 101 int x86_tlbsize; 102 #endif 103 __u8 x86_virt_bits; 104 __u8 x86_phys_bits; 105 /* CPUID returned core id bits: */ 106 __u8 x86_coreid_bits; 107 /* Max extended CPUID function supported: */ 108 __u32 extended_cpuid_level; 109 /* Maximum supported CPUID level, -1=no CPUID: */ 110 int cpuid_level; 111 __u32 x86_capability[NCAPINTS + NBUGINTS]; 112 char x86_vendor_id[16]; 113 char x86_model_id[64]; 114 /* in KB - valid for CPUS which support this call: */ 115 int x86_cache_size; 116 int x86_cache_alignment; /* In bytes */ 117 /* Cache QoS architectural values: */ 118 int x86_cache_max_rmid; /* max index */ 119 int x86_cache_occ_scale; /* scale to bytes */ 120 int x86_power; 121 unsigned long loops_per_jiffy; 122 /* cpuid returned max cores value: */ 123 u16 x86_max_cores; 124 u16 apicid; 125 u16 initial_apicid; 126 u16 x86_clflush_size; 127 /* number of cores as seen by the OS: */ 128 u16 booted_cores; 129 /* Physical processor id: */ 130 u16 phys_proc_id; 131 /* Logical processor id: */ 132 u16 logical_proc_id; 133 /* Core id: */ 134 u16 cpu_core_id; 135 /* Compute unit id */ 136 u8 compute_unit_id; 137 /* Index into per_cpu list: */ 138 u16 cpu_index; 139 u32 microcode; 140 }; 141 142 #define X86_VENDOR_INTEL 0 143 #define X86_VENDOR_CYRIX 1 144 #define X86_VENDOR_AMD 2 145 #define X86_VENDOR_UMC 3 146 #define X86_VENDOR_CENTAUR 5 147 #define X86_VENDOR_TRANSMETA 7 148 #define X86_VENDOR_NSC 8 149 #define X86_VENDOR_NUM 9 150 151 #define X86_VENDOR_UNKNOWN 0xff 152 153 /* 154 * capabilities of CPUs 155 */ 156 extern struct cpuinfo_x86 boot_cpu_data; 157 extern struct cpuinfo_x86 new_cpu_data; 158 159 extern struct tss_struct doublefault_tss; 160 extern __u32 cpu_caps_cleared[NCAPINTS]; 161 extern __u32 cpu_caps_set[NCAPINTS]; 162 163 #ifdef CONFIG_SMP 164 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 165 #define cpu_data(cpu) per_cpu(cpu_info, cpu) 166 #else 167 #define cpu_info boot_cpu_data 168 #define cpu_data(cpu) boot_cpu_data 169 #endif 170 171 extern const struct seq_operations cpuinfo_op; 172 173 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) 174 175 extern void cpu_detect(struct cpuinfo_x86 *c); 176 177 extern void early_cpu_init(void); 178 extern void identify_boot_cpu(void); 179 extern void identify_secondary_cpu(struct cpuinfo_x86 *); 180 extern void print_cpu_info(struct cpuinfo_x86 *); 181 void print_cpu_msr(struct cpuinfo_x86 *); 182 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); 183 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); 184 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); 185 186 extern void detect_extended_topology(struct cpuinfo_x86 *c); 187 extern void detect_ht(struct cpuinfo_x86 *c); 188 189 #ifdef CONFIG_X86_32 190 extern int have_cpuid_p(void); 191 #else 192 static inline int have_cpuid_p(void) 193 { 194 return 1; 195 } 196 #endif 197 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, 198 unsigned int *ecx, unsigned int *edx) 199 { 200 /* ecx is often an input as well as an output. */ 201 asm volatile("cpuid" 202 : "=a" (*eax), 203 "=b" (*ebx), 204 "=c" (*ecx), 205 "=d" (*edx) 206 : "0" (*eax), "2" (*ecx) 207 : "memory"); 208 } 209 210 static inline void load_cr3(pgd_t *pgdir) 211 { 212 write_cr3(__pa(pgdir)); 213 } 214 215 #ifdef CONFIG_X86_32 216 /* This is the TSS defined by the hardware. */ 217 struct x86_hw_tss { 218 unsigned short back_link, __blh; 219 unsigned long sp0; 220 unsigned short ss0, __ss0h; 221 unsigned long sp1; 222 223 /* 224 * We don't use ring 1, so ss1 is a convenient scratch space in 225 * the same cacheline as sp0. We use ss1 to cache the value in 226 * MSR_IA32_SYSENTER_CS. When we context switch 227 * MSR_IA32_SYSENTER_CS, we first check if the new value being 228 * written matches ss1, and, if it's not, then we wrmsr the new 229 * value and update ss1. 230 * 231 * The only reason we context switch MSR_IA32_SYSENTER_CS is 232 * that we set it to zero in vm86 tasks to avoid corrupting the 233 * stack if we were to go through the sysenter path from vm86 234 * mode. 235 */ 236 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ 237 238 unsigned short __ss1h; 239 unsigned long sp2; 240 unsigned short ss2, __ss2h; 241 unsigned long __cr3; 242 unsigned long ip; 243 unsigned long flags; 244 unsigned long ax; 245 unsigned long cx; 246 unsigned long dx; 247 unsigned long bx; 248 unsigned long sp; 249 unsigned long bp; 250 unsigned long si; 251 unsigned long di; 252 unsigned short es, __esh; 253 unsigned short cs, __csh; 254 unsigned short ss, __ssh; 255 unsigned short ds, __dsh; 256 unsigned short fs, __fsh; 257 unsigned short gs, __gsh; 258 unsigned short ldt, __ldth; 259 unsigned short trace; 260 unsigned short io_bitmap_base; 261 262 } __attribute__((packed)); 263 #else 264 struct x86_hw_tss { 265 u32 reserved1; 266 u64 sp0; 267 u64 sp1; 268 u64 sp2; 269 u64 reserved2; 270 u64 ist[7]; 271 u32 reserved3; 272 u32 reserved4; 273 u16 reserved5; 274 u16 io_bitmap_base; 275 276 } __attribute__((packed)) ____cacheline_aligned; 277 #endif 278 279 /* 280 * IO-bitmap sizes: 281 */ 282 #define IO_BITMAP_BITS 65536 283 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) 284 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) 285 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) 286 #define INVALID_IO_BITMAP_OFFSET 0x8000 287 288 struct tss_struct { 289 /* 290 * The hardware state: 291 */ 292 struct x86_hw_tss x86_tss; 293 294 /* 295 * The extra 1 is there because the CPU will access an 296 * additional byte beyond the end of the IO permission 297 * bitmap. The extra byte must be all 1 bits, and must 298 * be within the limit. 299 */ 300 unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; 301 302 #ifdef CONFIG_X86_32 303 /* 304 * Space for the temporary SYSENTER stack. 305 */ 306 unsigned long SYSENTER_stack_canary; 307 unsigned long SYSENTER_stack[64]; 308 #endif 309 310 } ____cacheline_aligned; 311 312 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); 313 314 #ifdef CONFIG_X86_32 315 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); 316 #endif 317 318 /* 319 * Save the original ist values for checking stack pointers during debugging 320 */ 321 struct orig_ist { 322 unsigned long ist[7]; 323 }; 324 325 #ifdef CONFIG_X86_64 326 DECLARE_PER_CPU(struct orig_ist, orig_ist); 327 328 union irq_stack_union { 329 char irq_stack[IRQ_STACK_SIZE]; 330 /* 331 * GCC hardcodes the stack canary as %gs:40. Since the 332 * irq_stack is the object at %gs:0, we reserve the bottom 333 * 48 bytes of the irq stack for the canary. 334 */ 335 struct { 336 char gs_base[40]; 337 unsigned long stack_canary; 338 }; 339 }; 340 341 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; 342 DECLARE_INIT_PER_CPU(irq_stack_union); 343 344 DECLARE_PER_CPU(char *, irq_stack_ptr); 345 DECLARE_PER_CPU(unsigned int, irq_count); 346 extern asmlinkage void ignore_sysret(void); 347 #else /* X86_64 */ 348 #ifdef CONFIG_CC_STACKPROTECTOR 349 /* 350 * Make sure stack canary segment base is cached-aligned: 351 * "For Intel Atom processors, avoid non zero segment base address 352 * that is not aligned to cache line boundary at all cost." 353 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) 354 */ 355 struct stack_canary { 356 char __pad[20]; /* canary at %gs:20 */ 357 unsigned long canary; 358 }; 359 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); 360 #endif 361 /* 362 * per-CPU IRQ handling stacks 363 */ 364 struct irq_stack { 365 u32 stack[THREAD_SIZE/sizeof(u32)]; 366 } __aligned(THREAD_SIZE); 367 368 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); 369 DECLARE_PER_CPU(struct irq_stack *, softirq_stack); 370 #endif /* X86_64 */ 371 372 extern unsigned int xstate_size; 373 374 struct perf_event; 375 376 struct thread_struct { 377 /* Cached TLS descriptors: */ 378 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; 379 unsigned long sp0; 380 unsigned long sp; 381 #ifdef CONFIG_X86_32 382 unsigned long sysenter_cs; 383 #else 384 unsigned short es; 385 unsigned short ds; 386 unsigned short fsindex; 387 unsigned short gsindex; 388 #endif 389 #ifdef CONFIG_X86_32 390 unsigned long ip; 391 #endif 392 #ifdef CONFIG_X86_64 393 unsigned long fs; 394 #endif 395 unsigned long gs; 396 397 /* Save middle states of ptrace breakpoints */ 398 struct perf_event *ptrace_bps[HBP_NUM]; 399 /* Debug status used for traps, single steps, etc... */ 400 unsigned long debugreg6; 401 /* Keep track of the exact dr7 value set by the user */ 402 unsigned long ptrace_dr7; 403 /* Fault info: */ 404 unsigned long cr2; 405 unsigned long trap_nr; 406 unsigned long error_code; 407 #ifdef CONFIG_VM86 408 /* Virtual 86 mode info */ 409 struct vm86 *vm86; 410 #endif 411 /* IO permissions: */ 412 unsigned long *io_bitmap_ptr; 413 unsigned long iopl; 414 /* Max allowed port in the bitmap, in bytes: */ 415 unsigned io_bitmap_max; 416 417 /* Floating point and extended processor state */ 418 struct fpu fpu; 419 /* 420 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at 421 * the end. 422 */ 423 }; 424 425 /* 426 * Set IOPL bits in EFLAGS from given mask 427 */ 428 static inline void native_set_iopl_mask(unsigned mask) 429 { 430 #ifdef CONFIG_X86_32 431 unsigned int reg; 432 433 asm volatile ("pushfl;" 434 "popl %0;" 435 "andl %1, %0;" 436 "orl %2, %0;" 437 "pushl %0;" 438 "popfl" 439 : "=&r" (reg) 440 : "i" (~X86_EFLAGS_IOPL), "r" (mask)); 441 #endif 442 } 443 444 static inline void 445 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) 446 { 447 tss->x86_tss.sp0 = thread->sp0; 448 #ifdef CONFIG_X86_32 449 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ 450 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { 451 tss->x86_tss.ss1 = thread->sysenter_cs; 452 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 453 } 454 #endif 455 } 456 457 static inline void native_swapgs(void) 458 { 459 #ifdef CONFIG_X86_64 460 asm volatile("swapgs" ::: "memory"); 461 #endif 462 } 463 464 static inline unsigned long current_top_of_stack(void) 465 { 466 #ifdef CONFIG_X86_64 467 return this_cpu_read_stable(cpu_tss.x86_tss.sp0); 468 #else 469 /* sp0 on x86_32 is special in and around vm86 mode. */ 470 return this_cpu_read_stable(cpu_current_top_of_stack); 471 #endif 472 } 473 474 #ifdef CONFIG_PARAVIRT 475 #include <asm/paravirt.h> 476 #else 477 #define __cpuid native_cpuid 478 #define paravirt_enabled() 0 479 #define paravirt_has(x) 0 480 481 static inline void load_sp0(struct tss_struct *tss, 482 struct thread_struct *thread) 483 { 484 native_load_sp0(tss, thread); 485 } 486 487 #define set_iopl_mask native_set_iopl_mask 488 #endif /* CONFIG_PARAVIRT */ 489 490 typedef struct { 491 unsigned long seg; 492 } mm_segment_t; 493 494 495 /* Free all resources held by a thread. */ 496 extern void release_thread(struct task_struct *); 497 498 unsigned long get_wchan(struct task_struct *p); 499 500 /* 501 * Generic CPUID function 502 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx 503 * resulting in stale register contents being returned. 504 */ 505 static inline void cpuid(unsigned int op, 506 unsigned int *eax, unsigned int *ebx, 507 unsigned int *ecx, unsigned int *edx) 508 { 509 *eax = op; 510 *ecx = 0; 511 __cpuid(eax, ebx, ecx, edx); 512 } 513 514 /* Some CPUID calls want 'count' to be placed in ecx */ 515 static inline void cpuid_count(unsigned int op, int count, 516 unsigned int *eax, unsigned int *ebx, 517 unsigned int *ecx, unsigned int *edx) 518 { 519 *eax = op; 520 *ecx = count; 521 __cpuid(eax, ebx, ecx, edx); 522 } 523 524 /* 525 * CPUID functions returning a single datum 526 */ 527 static inline unsigned int cpuid_eax(unsigned int op) 528 { 529 unsigned int eax, ebx, ecx, edx; 530 531 cpuid(op, &eax, &ebx, &ecx, &edx); 532 533 return eax; 534 } 535 536 static inline unsigned int cpuid_ebx(unsigned int op) 537 { 538 unsigned int eax, ebx, ecx, edx; 539 540 cpuid(op, &eax, &ebx, &ecx, &edx); 541 542 return ebx; 543 } 544 545 static inline unsigned int cpuid_ecx(unsigned int op) 546 { 547 unsigned int eax, ebx, ecx, edx; 548 549 cpuid(op, &eax, &ebx, &ecx, &edx); 550 551 return ecx; 552 } 553 554 static inline unsigned int cpuid_edx(unsigned int op) 555 { 556 unsigned int eax, ebx, ecx, edx; 557 558 cpuid(op, &eax, &ebx, &ecx, &edx); 559 560 return edx; 561 } 562 563 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ 564 static __always_inline void rep_nop(void) 565 { 566 asm volatile("rep; nop" ::: "memory"); 567 } 568 569 static __always_inline void cpu_relax(void) 570 { 571 rep_nop(); 572 } 573 574 #define cpu_relax_lowlatency() cpu_relax() 575 576 /* Stop speculative execution and prefetching of modified code. */ 577 static inline void sync_core(void) 578 { 579 int tmp; 580 581 #ifdef CONFIG_M486 582 /* 583 * Do a CPUID if available, otherwise do a jump. The jump 584 * can conveniently enough be the jump around CPUID. 585 */ 586 asm volatile("cmpl %2,%1\n\t" 587 "jl 1f\n\t" 588 "cpuid\n" 589 "1:" 590 : "=a" (tmp) 591 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) 592 : "ebx", "ecx", "edx", "memory"); 593 #else 594 /* 595 * CPUID is a barrier to speculative execution. 596 * Prefetched instructions are automatically 597 * invalidated when modified. 598 */ 599 asm volatile("cpuid" 600 : "=a" (tmp) 601 : "0" (1) 602 : "ebx", "ecx", "edx", "memory"); 603 #endif 604 } 605 606 extern void select_idle_routine(const struct cpuinfo_x86 *c); 607 extern void init_amd_e400_c1e_mask(void); 608 609 extern unsigned long boot_option_idle_override; 610 extern bool amd_e400_c1e_detected; 611 612 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, 613 IDLE_POLL}; 614 615 extern void enable_sep_cpu(void); 616 extern int sysenter_setup(void); 617 618 extern void early_trap_init(void); 619 void early_trap_pf_init(void); 620 621 /* Defined in head.S */ 622 extern struct desc_ptr early_gdt_descr; 623 624 extern void cpu_set_gdt(int); 625 extern void switch_to_new_gdt(int); 626 extern void load_percpu_segment(int); 627 extern void cpu_init(void); 628 629 static inline unsigned long get_debugctlmsr(void) 630 { 631 unsigned long debugctlmsr = 0; 632 633 #ifndef CONFIG_X86_DEBUGCTLMSR 634 if (boot_cpu_data.x86 < 6) 635 return 0; 636 #endif 637 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 638 639 return debugctlmsr; 640 } 641 642 static inline void update_debugctlmsr(unsigned long debugctlmsr) 643 { 644 #ifndef CONFIG_X86_DEBUGCTLMSR 645 if (boot_cpu_data.x86 < 6) 646 return; 647 #endif 648 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 649 } 650 651 extern void set_task_blockstep(struct task_struct *task, bool on); 652 653 /* Boot loader type from the setup header: */ 654 extern int bootloader_type; 655 extern int bootloader_version; 656 657 extern char ignore_fpu_irq; 658 659 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 660 #define ARCH_HAS_PREFETCHW 661 #define ARCH_HAS_SPINLOCK_PREFETCH 662 663 #ifdef CONFIG_X86_32 664 # define BASE_PREFETCH "" 665 # define ARCH_HAS_PREFETCH 666 #else 667 # define BASE_PREFETCH "prefetcht0 %P1" 668 #endif 669 670 /* 671 * Prefetch instructions for Pentium III (+) and AMD Athlon (+) 672 * 673 * It's not worth to care about 3dnow prefetches for the K6 674 * because they are microcoded there and very slow. 675 */ 676 static inline void prefetch(const void *x) 677 { 678 alternative_input(BASE_PREFETCH, "prefetchnta %P1", 679 X86_FEATURE_XMM, 680 "m" (*(const char *)x)); 681 } 682 683 /* 684 * 3dnow prefetch to get an exclusive cache line. 685 * Useful for spinlocks to avoid one state transition in the 686 * cache coherency protocol: 687 */ 688 static inline void prefetchw(const void *x) 689 { 690 alternative_input(BASE_PREFETCH, "prefetchw %P1", 691 X86_FEATURE_3DNOWPREFETCH, 692 "m" (*(const char *)x)); 693 } 694 695 static inline void spin_lock_prefetch(const void *x) 696 { 697 prefetchw(x); 698 } 699 700 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ 701 TOP_OF_KERNEL_STACK_PADDING) 702 703 #ifdef CONFIG_X86_32 704 /* 705 * User space process size: 3GB (default). 706 */ 707 #define TASK_SIZE PAGE_OFFSET 708 #define TASK_SIZE_MAX TASK_SIZE 709 #define STACK_TOP TASK_SIZE 710 #define STACK_TOP_MAX STACK_TOP 711 712 #define INIT_THREAD { \ 713 .sp0 = TOP_OF_INIT_STACK, \ 714 .sysenter_cs = __KERNEL_CS, \ 715 .io_bitmap_ptr = NULL, \ 716 } 717 718 extern unsigned long thread_saved_pc(struct task_struct *tsk); 719 720 /* 721 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack. 722 * This is necessary to guarantee that the entire "struct pt_regs" 723 * is accessible even if the CPU haven't stored the SS/ESP registers 724 * on the stack (interrupt gate does not save these registers 725 * when switching to the same priv ring). 726 * Therefore beware: accessing the ss/esp fields of the 727 * "struct pt_regs" is possible, but they may contain the 728 * completely wrong values. 729 */ 730 #define task_pt_regs(task) \ 731 ({ \ 732 unsigned long __ptr = (unsigned long)task_stack_page(task); \ 733 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ 734 ((struct pt_regs *)__ptr) - 1; \ 735 }) 736 737 #define KSTK_ESP(task) (task_pt_regs(task)->sp) 738 739 #else 740 /* 741 * User space process size. 47bits minus one guard page. The guard 742 * page is necessary on Intel CPUs: if a SYSCALL instruction is at 743 * the highest possible canonical userspace address, then that 744 * syscall will enter the kernel with a non-canonical return 745 * address, and SYSRET will explode dangerously. We avoid this 746 * particular problem by preventing anything from being mapped 747 * at the maximum canonical address. 748 */ 749 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) 750 751 /* This decides where the kernel will search for a free chunk of vm 752 * space during mmap's. 753 */ 754 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ 755 0xc0000000 : 0xFFFFe000) 756 757 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ 758 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 759 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ 760 IA32_PAGE_OFFSET : TASK_SIZE_MAX) 761 762 #define STACK_TOP TASK_SIZE 763 #define STACK_TOP_MAX TASK_SIZE_MAX 764 765 #define INIT_THREAD { \ 766 .sp0 = TOP_OF_INIT_STACK \ 767 } 768 769 /* 770 * Return saved PC of a blocked thread. 771 * What is this good for? it will be always the scheduler or ret_from_fork. 772 */ 773 #define thread_saved_pc(t) READ_ONCE_NOCHECK(*(unsigned long *)((t)->thread.sp - 8)) 774 775 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) 776 extern unsigned long KSTK_ESP(struct task_struct *task); 777 778 #endif /* CONFIG_X86_64 */ 779 780 extern void start_thread(struct pt_regs *regs, unsigned long new_ip, 781 unsigned long new_sp); 782 783 /* 784 * This decides where the kernel will search for a free chunk of vm 785 * space during mmap's. 786 */ 787 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 788 789 #define KSTK_EIP(task) (task_pt_regs(task)->ip) 790 791 /* Get/set a process' ability to use the timestamp counter instruction */ 792 #define GET_TSC_CTL(adr) get_tsc_mode((adr)) 793 #define SET_TSC_CTL(val) set_tsc_mode((val)) 794 795 extern int get_tsc_mode(unsigned long adr); 796 extern int set_tsc_mode(unsigned int val); 797 798 /* Register/unregister a process' MPX related resource */ 799 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() 800 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() 801 802 #ifdef CONFIG_X86_INTEL_MPX 803 extern int mpx_enable_management(void); 804 extern int mpx_disable_management(void); 805 #else 806 static inline int mpx_enable_management(void) 807 { 808 return -EINVAL; 809 } 810 static inline int mpx_disable_management(void) 811 { 812 return -EINVAL; 813 } 814 #endif /* CONFIG_X86_INTEL_MPX */ 815 816 extern u16 amd_get_nb_id(int cpu); 817 extern u32 amd_get_nodes_per_socket(void); 818 819 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) 820 { 821 uint32_t base, eax, signature[3]; 822 823 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 824 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); 825 826 if (!memcmp(sig, signature, 12) && 827 (leaves == 0 || ((eax - base) >= leaves))) 828 return base; 829 } 830 831 return 0; 832 } 833 834 extern unsigned long arch_align_stack(unsigned long sp); 835 extern void free_init_pages(char *what, unsigned long begin, unsigned long end); 836 837 void default_idle(void); 838 #ifdef CONFIG_XEN 839 bool xen_set_default_idle(void); 840 #else 841 #define xen_set_default_idle 0 842 #endif 843 844 void stop_this_cpu(void *dummy); 845 void df_debug(struct pt_regs *regs, long error_code); 846 #endif /* _ASM_X86_PROCESSOR_H */ 847