xref: /linux/arch/x86/include/asm/fpu/xstate.h (revision 59024954a1e7e26b62680e1f2b5725249a6c09f7)
1 #ifndef __ASM_X86_XSAVE_H
2 #define __ASM_X86_XSAVE_H
3 
4 #include <linux/types.h>
5 #include <asm/processor.h>
6 #include <linux/uaccess.h>
7 
8 /* Bit 63 of XCR0 is reserved for future expansion */
9 #define XFEATURE_MASK_EXTEND	(~(XFEATURE_MASK_FPSSE | (1ULL << 63)))
10 
11 #define XSTATE_CPUID		0x0000000d
12 
13 #define FXSAVE_SIZE	512
14 
15 #define XSAVE_HDR_SIZE	    64
16 #define XSAVE_HDR_OFFSET    FXSAVE_SIZE
17 
18 #define XSAVE_YMM_SIZE	    256
19 #define XSAVE_YMM_OFFSET    (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)
20 
21 /* Supervisor features */
22 #define XFEATURE_MASK_SUPERVISOR (XFEATURE_MASK_PT)
23 
24 /* Supported features which support lazy state saving */
25 #define XFEATURE_MASK_LAZY	(XFEATURE_MASK_FP | \
26 				 XFEATURE_MASK_SSE | \
27 				 XFEATURE_MASK_YMM | \
28 				 XFEATURE_MASK_OPMASK | \
29 				 XFEATURE_MASK_ZMM_Hi256 | \
30 				 XFEATURE_MASK_Hi16_ZMM	 | \
31 				 XFEATURE_MASK_PKRU)
32 
33 /* Supported features which require eager state saving */
34 #define XFEATURE_MASK_EAGER	(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR)
35 
36 /* All currently supported features */
37 #define XCNTXT_MASK	(XFEATURE_MASK_LAZY | XFEATURE_MASK_EAGER)
38 
39 #ifdef CONFIG_X86_64
40 #define REX_PREFIX	"0x48, "
41 #else
42 #define REX_PREFIX
43 #endif
44 
45 extern u64 xfeatures_mask;
46 extern u64 xstate_fx_sw_bytes[USER_XSTATE_FX_SW_WORDS];
47 
48 extern void __init update_regset_xstate_info(unsigned int size,
49 					     u64 xstate_mask);
50 
51 void fpu__xstate_clear_all_cpu_caps(void);
52 void *get_xsave_addr(struct xregs_state *xsave, int xstate);
53 const void *get_xsave_field_ptr(int xstate_field);
54 int using_compacted_format(void);
55 int copyout_from_xsaves(unsigned int pos, unsigned int count, void *kbuf,
56 			void __user *ubuf, struct xregs_state *xsave);
57 int copyin_to_xsaves(const void *kbuf, const void __user *ubuf,
58 		     struct xregs_state *xsave);
59 #endif
60